In-memory computing circuit, multi-logic in-memory operation circuit and chip thereof

Abstract

The present application relates to the technical field of in-memory computing, and particularly relates to an in-memory computing circuit, a multi-logic in-memory operation circuit and a chip thereof. The in-memory computing circuit is composed of a storage array of a plurality of storage units; two adjacent storage units in the storage array are reversely placed in RRAM structure; each column of storage units is connected to four bit lines SL, BL, BLOBIN and BLBOUT; the source and drain of NMOS tube K1 are connected to BLOBIN and BLBOUT respectively; the source of NMOS tube M8 is connected to BL; the drain of NMOS tube M9 is connected to BLOBIN; the drain of M8 and the source of M9 are grounded; four adjacent storage units RRAM0-RRAM3 in each column constitute a basic storage and computing unit; the storage and computing unit further comprises eight NMOS tubes M0-M7; the gate of each NMOS tube is connected to a word line. The present application solves the resistance cross problem of existing RRAM in in-memory operation.

Description

Technical Field

[0001] This invention relates to the field of in-memory computing technology, and in particular to in-memory computing circuits, multi-logic in-memory arithmetic circuits, and their chips. Background Technology

[0002] In recent years, Moore's Law has been driving the expansion of CMOS technology in logic and memory applications. However, increasing non-ideal effects are limiting the expansion of CMOS, such as subthreshold leakage current which increases static and standby power consumption. Meanwhile, the traditional von Neumann architecture suffers from bottlenecks in data communication due to the separation of processing units and memory storage.

[0003] To improve energy efficiency and overcome existing limitations, researchers have proposed the concept of in-memory computing, where some computations are performed within memory. By performing partial computations inside the memory, power consumption and latency associated with data migration can be effectively reduced. Residual RAM (RRAM) is a type of memory that stores data based on temperature and voltage dependence, offering advantages such as high stacking capability, simple structure, low power consumption, and fast read / write speeds. Furthermore, RRAM is compatible with traditional CMOS processes, thus possessing excellent potential for in-memory computing.

[0004] However, existing RRAM requires more RRAM and clock cycles to perform logic operations such as "OR" and "XOR", which increases power consumption and latency. Furthermore, the overlapping of discharge paths for different logic operations can lead to resistance crossing problems, affecting the accuracy of the calculation. Summary of the Invention

[0005] Therefore, it is necessary to provide an in-memory computing circuit, a multi-logic in-memory computing circuit, and its chip to address the resistance crossover problem that existing RRAM in-memory computing circuits cannot overcome during in-memory operations.

[0006] To achieve the above objectives, the present invention adopts the following technical solution:

[0007] An in-memory computing circuit includes a memory array consisting of multiple memory cells. Adjacent memory cells in the memory array are arranged in reverse order (RRAM). Each column of memory cells is connected to four bit lines SL, BL, BLBIN, and BLBOUT. The source and drain of NMOS transistor K1 are connected to BLBIN and BLBOUT, respectively. The source of NMOS transistor M8 is connected to BL, and the drain of NMOS transistor M9 is connected to BLBIN. The drain of M8 and the source of M9 are grounded.

[0008] Four adjacent memory cells RRAM0 to RRAM3 in each column constitute a basic memory cell. The memory cell also includes eight NMOS transistors M0 to M7. The gate of each NMOS transistor is connected to a word line. The sources of M0, M2, M4, and M6 are connected to SL; the sources of M1, M3, M5, and M7 are connected to BL; the drains of M0 and M1 are connected to the bottom electrode of RRAM0; the drains of M2 and M3 are connected to the top electrode of RRAM1; the drains of M4 and M5 are connected to the bottom electrode of RRAM2; the drains of M6 and M7 are connected to the top electrode of RRAM3; the top electrodes of RRAM0 and RRAM2 are connected to BLBIN; and the bottom electrodes of RRAM1 and RRAM3 are connected to BLBOUT.

[0009] Furthermore, the in-memory unit performs an AND operation as follows: RRAM0 and RRAM2 are connected in series by opening M0, M5, M8, and K1. When RRAM0 and RRAM2 are in a low-resistance state, SL discharges. When RRAM0 and RRAM2 are in a high-resistance state, SL does not discharge. The discharge path of SL is M0, RRAM0, K1, RRAM2, M5, M8.

[0010] Furthermore, the in-memory unit performs the OR logic operation as follows: RRAM0 and RRAM2 are connected in parallel by opening M0, M4, M9, and K1. When RRAM0 and / or RRAM2 are in a low-resistance state, SL discharges. When RRAM0 and RRAM2 are in a high-resistance state, SL does not discharge. The discharge path of SL is M0, RRAM0, K1, M9, or M4, RRAM2, M9.

[0011] Furthermore, the storage unit performs the "XOR" logic operation as follows: RRAM0 and RRAM1 are connected in series by opening M0, M3, and M8; RRAM2 and RRAM3 are connected in series by opening M4 and M7; and RRAM0 and RRAM1 are connected in parallel with RRAM2 and RRAM3. When RRAM0, RRAM1 and / or RRAM2 and RRAM3 are in a low-resistance state, SL discharges. The discharge path of SL is M0, RRAM0, RRAM1, M3, M8, or M4, RRAM2, RRAM3, M7, M8.

[0012] Furthermore, the connection methods between storage cells within the in-memory unit include top-to-bottom connection, bottom-to-bottom connection, and top-to-top connection. The resistance state of the storage cells is used to represent the results of different logical operations.

[0013] Furthermore, the top-bottom connection operation of the memory cells within the in-memory unit is as follows: RRAM0 and RRAM3 are connected by opening K1, M0, and M7, with BL grounded. SL is connected to the bottom electrode of RRAM0, and the top electrode of RRAM3 is grounded through M7. The resistance states of RRAM0 and RRAM3 represent different logic operation results. Alternatively, RRAM1 and RRAM2 are connected by opening K1, M2, and M5, with BL grounded. SL is connected to the top electrode of RRAM1, and the bottom electrode of RRAM2 is grounded through M5. The resistance states of RRAM1 and RRAM2 represent different logic operation results.

[0014] Furthermore, the bottom-to-bottom connection operation of the memory cells within the in-memory unit is as follows: RRAM1 and RRAM3 are connected by opening K1, M2, and M7, and BL is grounded. SL is connected to the top electrode of RRAM1, and the top electrode of RRAM3 is grounded through M7. The resistance states of RRAM1 and RRAM3 indicate the results of different logic operations.

[0015] Furthermore, the top-to-top connection operation of the memory cells within the in-memory unit is as follows: RRAM0 and RRAM2 are connected by opening K1, M0, and M5, and BL is grounded. SL is connected to the bottom electrode of RRAM0, and the bottom electrode of RRAM2 is grounded through M5. The resistance states of RRAM0 and RRAM2 indicate the results of different logic operations.

[0016] The present invention also relates to a multi-logic in-memory operation circuit, which includes a memory array, a bit line group, an NMOS transistor K1, a transistor group, a word line WL, a word line CTRLR, a word line CTRLR, a word line driver module, a decoder, a function switching circuit, a pre-charge circuit, a timing control circuit, a switching circuit, a sensitive amplifier, and an output circuit.

[0017] The storage array consists of 4NM storage units arranged in a 4N×M array. Here, N represents the number of rows in the storage array, and M represents the number of columns in the storage array.

[0018] The bit line group includes M groups SL, BL, BLBIN, and BLBOUT. Each memory cell in each column is connected to the same group of bit lines SL, BL, BLBIN, and BLBOUT.

[0019] There are M NMOS transistors K1, and the source and drain of each column of K1 are connected to the same group BLBIN and BLBOUT.

[0020] The transistor group consists of M NMOS transistors M8 and M9. The bit lines BL and BLBIN of each column are connected to the same group of M8 and M9.

[0021] The number of word lines (WL) is 8N, which are used to control the turning on and off of the NMOS transistors in each memory cell of the memory array.

[0022] The word line CTRLR is used to control the on and off states of each transistor M9 in the transistor group.

[0023] The word line CTRLLL is used to control the on and off states of individual transistors M8 in the transistor group.

[0024] The word line driver module is used to control the high and low levels of the word lines of each memory unit in the memory array.

[0025] The decoder is used to select the appropriate word line to enable based on the input address.

[0026] The function switching circuit is used to control the switching of each in-memory computing unit in the storage array between read / write operations, overwrite operations, and in-memory operations, so as to adjust the different working modes of the circuit.

[0027] The precharge circuit is used to precharge the bit lines SL, BL, BLBIN, and BLBOUT connected to each column of computing cells in the memory array.

[0028] The timing control circuit is used to generate the clock signals required by each functional module.

[0029] Switching circuits are used to control the opening or closing of bit lines connected to each memory cell in the memory array.

[0030] The number of sensitive amplifiers is M, which are used to compare the voltage on the bit line SL with a preset reference voltage Vref, thereby obtaining the stored data or logic calculation results of the memory cell in any column.

[0031] The output circuit is used to output the stored data or logical calculation results of the storage unit in any column.

[0032] Specifically, any in-memory computing unit, K1, and transistor group in the memory array constitute the in-memory computing circuit as described above, and can realize the complete function of the basic circuit.

[0033] This invention also relates to a multi-logic in-memory arithmetic chip, which is packaged from the aforementioned multi-logic in-memory arithmetic circuit. The interface of the multi-logic in-memory arithmetic chip includes at least a power interface VDD, a ground interface VSS, a row select interface A, an input signal interface IN, a control signal interface CEN, a read / write enable signal WEN, a switching signal KN, a clock signal interface CLK, and an output signal interface OUT.

[0034] The power interface VDD is used to connect to a power source.

[0035] The grounding interface VSS is used for grounding.

[0036] The row strobe interface A is used to input row strobe signals to the circuit. The row strobe signals are used to adjust the access status of each memory unit on each word line.

[0037] The input signal interface IN is used to input the corresponding input signals to each memory unit.

[0038] The control signal interface CEN is used to input control signals that adjust the operating status of each memory unit.

[0039] The read / write enable signal WEN is used to input and adjust the enable signal for read / write operations of each memory unit.

[0040] The switching signal KN is used to input a switching signal into the circuit. The switching signal is used to adjust the switching of each memory unit in the memory array between read / write operations, overwrite operations, and in-memory operations, so as to adjust the different working modes of the circuit.

[0041] The clock signal interface CLK is used to input an external clock signal into the circuit. The clock signal is used to provide the clock frequency required for the operation of each memory unit in the memory array.

[0042] The output signal interface OUT is used to read the stored data or logical operation results of each memory unit.

[0043] The technical solution provided by this invention has the following beneficial effects:

[0044] This invention reduces the number of RRAMs and clock cycles required to perform in-memory operations by reversing the RRAM settings, thereby effectively reducing power consumption and latency. Furthermore, by controlling the access NMOS transistors, different discharge paths can be formed for different logic operations, thus solving the resistance crossover problem. Logic operations can be easily performed by adjusting the input voltage pulse and storing the results in the RRAM, using less RRAM and clock cycles, resulting in better spatial and temporal complexity for the overall circuit. Attached Figure Description

[0045] Figure 1 This is a circuit schematic diagram of an in-memory computing circuit according to Embodiment 1 of the present invention;

[0046] Figure 2 Based on Figure 1 The read / write operation waveforms of RRAM0 performing set, reset, and read operations;

[0047] Figure 3 Based on Figure 1 Waveforms of AND, OR, and XOR operations;

[0048] Figure 4 Based on Figure 1A schematic diagram of the structure connecting the top and bottom of the RRAM;

[0049] Figure 5 Based on Figure 1 A schematic diagram of the structure connecting the bottom of the RRAM;

[0050] Figure 6 Based on Figure 1 A schematic diagram of the top-to-top connection structure of the RRAM;

[0051] Figure 7 Based on Figure 1 A schematic diagram of the RRAM connection structure for implementing XOR and XNOR in two cycles;

[0052] Figure 8 Based on Figure 7 Waveform diagrams of XOR and XNOR operations implemented over two cycles;

[0053] Figure 9 This is a circuit schematic diagram of a multi-logic-in-memory arithmetic circuit according to Embodiment 2;

[0054] Figure 10 This is the existing reconnaissance logic circuit diagram;

[0055] Figure 11 This is a simulation diagram comparing the computational accuracy of existing detection logic circuits with that of the in-memory computing circuit of this invention. Detailed Implementation

[0056] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0057] Example 1

[0058] Please participate Figure 1 This embodiment introduces an in-memory computing circuit, which includes a memory array composed of multiple memory cells. Adjacent memory cells in the memory array are arranged in reverse order (RRAM). Each column of memory cells is connected to four bit lines SL, BL, BLBIN, and BLBOUT. The source and drain of NMOS transistor K1 are connected to BLBIN and BLBOUT, respectively. The source of NMOS transistor M8 is connected to BL, and the drain of NMOS transistor M9 is connected to BLBIN. The drain of M8 and the source of M9 are grounded.

[0059] Four adjacent memory cells RRAM0 to RRAM3 in each column constitute a basic memory cell. The memory cell also includes eight NMOS transistors M0 to M7. The gate of each NMOS transistor is connected to a word line. The sources of M0, M2, M4, and M6 are connected to SL; the sources of M1, M3, M5, and M7 are connected to BL; the drains of M0 and M1 are connected to the bottom electrode of RRAM0; the drains of M2 and M3 are connected to the top electrode of RRAM1; the drains of M4 and M5 are connected to the bottom electrode of RRAM2; the drains of M6 and M7 are connected to the top electrode of RRAM3; the top electrodes of RRAM0 and RRAM2 are connected to BLBIN; and the bottom electrodes of RRAM1 and RRAM3 are connected to BLBOUT.

[0060] Connect SL and SA. Read the voltage on the SL line through SA and compare it with a reference voltage Vref to obtain the logic operation result of the circuit. The reference voltage Vref is input through SA. A basic memory-in-memory unit has four RRAM cells and eight NMOS transistors, with the four cells placed adjacent and opposite to each other. Therefore, the basic memory-in-memory unit can be divided into upper and lower parts. Since each part has two RRAM cells and four NMOS transistors, it can be simply referred to as 4T2R. Thus, a basic memory-in-memory unit is composed of two 4T2R cross-coupled units.

[0061] Based on the above in-memory computing circuit structure, the following is a detailed description of the resistor-resistant crossover logic operation.

[0062] Taking an in-memory computing circuit composed of any column of storage units as an example, such as Figure 1 As shown, taking RRAM0 as an example, this illustrates how to read and write RRAM. Figure 1 The three lines shown represent the discharge paths for the three logic operations: AND, OR, and XOR. RRAM0 and RRAM2 are placed in the same way, with the bottom electrode on the left and the top electrode on the right, encoded as "0" in the high-resistivity state (HRS) and "1" in the low-resistivity state (LRS), which is called forward encoding. RRAM1 and RRAM3 are placed in the same way, with the top electrode on the left and the bottom electrode on the right, encoded as "0" in LRS and "1" in HRS, which is called reverse encoding. Figure 2 The display shows the read / write operation waveforms of RRAM0 performing set, reset, and read operations. For a forward-encoded RRAM0 read, the data is read from the positive terminal of SA. For a reverse-encoded RRAM1 read, the data is read from the negative terminal of SA.

[0063] 1) AND Operation: RRAM0 and RRAM2 can be connected in series by turning on M0, M5, M8, and K1. The discharge path will only discharge rapidly (SL) when both RRAMs are LRS (Local Range Receivers). Figure 1As shown. Once HRS appears in the circuit, SL will hardly discharge, thus overcoming the resistance crossover problem that may occur between one unit in LRS and one unit in HRS(1L1H) and two units in LRS(2L), and realizing error-free logic and operation functions.

[0064] like Figure 1 As shown, the discharge path of SL during AND operation is M0, RRAM0, K1, RRAM2, M5, M8.

[0065] 2) OR Operation: Unlike the AND operation, RRAM0 and RRAM2 are connected in parallel by opening M0, M4, M9, and K1. SL will discharge as long as LRS is present in both RRAMs. If both batteries in HRS(2H) are present in the circuit, SL will hardly discharge. Figure 1 As shown, during OR operation, the discharge path of SL is M0, RRAM0, K1, M9, or M4, RRAM2, M9.

[0066] The IMP operation can also be implemented through reverse encoding. If RRAM0 and RRAM1 are selected for the OR operation, and data P is written to RRAM0 and data Q is written to RRAM1, then the result read from the positive end of SA after the OR operation will be... This achieves Q→P.

[0067] 3) XOR operation: RRAM0 and RRAM1 are connected in series by opening M0 and M3. RRAM2 and RRAM3 are connected in series by opening M4 and M7. The two series lines are then connected in parallel. RRAM0 and RRAM3 are written with the same data P, and RRAM1 and RRAM2 are written with the same data Q. Since RRAM1 and RRAM3 use reverse encoding, the corresponding logic is as follows: Read from the positive terminal of SA. SL will discharge as long as two RRAMs are connected in series with LRS. For example... Figure 1 As shown, the discharge path of SL during XOR operation is M0, RRAM0, RRAM1, M3, M8, or M4, RRAM2, RRAM3, M7, M8.

[0068] Figure 3The waveforms for three logic operations are shown. The first cycle precharges the SL line, the second cycle discharges the SL by controlling the transistor, and the last cycle compares the voltage on the SL with Vref on the SA. Due to the presence of RRAM in the discharge path at HRS, the AND operation reads "0" through the SA. Alternatively, due to the presence of LRS in the discharge path, the SA reads the operation as "1". Finally, for the XOR operation, since there is a set of RRAMs both in the LRS, the final result "1" can be obtained on the SA. In this method, data is input into the memory cell, and then logic operations can be performed. All of the above logic operations are resistively cross-connected, which guarantees the correctness of the logic operations.

[0069] In addition to supporting the above formats, where the result is represented as a voltage and read by the SA, the result can also be represented as the RRAM resistor state. We can control the access transistors to implement top-to-bottom, bottom-to-bottom, and top-to-top connections of the RRAM. The following details the logic operations represented as RRAM resistor states:

[0070] 1. P' = P * Q, Q' = P + Q: Connect RRAM0 and RRAM3 by opening K1, M0, and M7. Then ground BL. RRAM0 stores P, RRAM3 stores Q, SL is connected to the bottom electrode of P, and the top electrode of Q is grounded through M7. The equivalent circuit is as follows. Figure 4 As shown. P is forward encoding, Q is reverse encoding. Make the voltage on SL greater than twice |V. RESET |,V RESET The reset voltage for the RRAM is shown in Table 1, and the results after the operation are shown in Table 1.

[0071] Table 1: Truth table for P' = P * Q, Q' = P + Q

[0072]

[0073] When the resistance states of the two RRAMs are the same (P=1, Q=0 or P=0, Q=1), the voltage on SL will be evenly distributed across P and Q. Since the resistances are the same, both RRAMs will be reset to HRS, i.e., P=0, Q=1, because P is the forward encoding and Q is the reverse encoding. If P is LRS and Q is HRS, then most of the voltage is applied to Q. Since Q is HRS, there will be no resistance change in the RRAM.

[0074] The same applies when P=0 and Q=0; there is no change in resistance. The resistance states of P and Q represent the results of different logical operations.

[0075] 2. P' = Q IMP P, Q' = Q NIMP P: (e.g.) Figure 4As shown. If P is forward encoding and Q is reverse encoding, when the voltage of SL is between (V SET 2V SET When V is between ) SET The set voltage of the RRAM is given, and the results of the calculation are shown in Table 2.

[0076] Table 2: Truth table of P' = Q IMP P, Q' = Q NIMP P

[0077]

[0078] When the resistance states of the two RRAMs are the same, i.e., P = 1, Q = 0 or P = 0, Q = 1, the voltage across SL will be uniformly distributed across P and Q, and the voltage at point M will be between (V) SET / 2,V SET The voltage drop across the RRAM is insufficient to set the RRAM, therefore there will be no change in resistance within the RRAM. If P is HRS and Q is LRS, most of the voltage is applied to P. P will be set to LRS, and Q will remain unchanged. Similarly, when P is LRS and Q is HRS, Q will be set to LRS, and P will remain unchanged. After the operation, the resistance states of P and Q represent the results of different logic operations.

[0079] 3. P' = 0, Q' = P IMP Q: Equivalent circuit as follows Figure 5 As shown, RRAM1 and RRAM3 are connected by opening K1, M2, and M7, and BL is grounded. SL is connected to the top electrode of RRAM1, and the top electrode of RRAM3 is grounded through M7. RRAM1 stores P, and RRAM3 stores Q. Assume the voltage across SL is greater than V. SET Twice the resistance of the RRAM. When the resistance states of the two RRAMs are the same (P=0, Q=0 or P=1, Q=1), the voltage on SL will be evenly distributed across P and Q, which is sufficient for P to perform a setting operation and Q to perform a reset operation. After the operation, P'=0, Q'=1. If P is HRS and Q is LRS, most of the voltage is applied to P, so P will be set to LRS and Q will remain unchanged. If P is LRS and Q is HRS, most of the voltage is applied to Q, and since Q is HRS, there will be no resistance change in the RRAM. The results are shown in Table 3.

[0080] Table 3: Truth table for P' = 0, Q' = P IMP Q

[0081]

[0082] 4. P' = P * Q, Q' = P * IMP Q: Let the voltage range on SL be (V) SET 2V SETWhen the resistance states of the two RRAMs are the same (P=0, Q=0 or P=1, Q=1), the voltage across SL will be uniformly distributed across P and Q, and the voltage at point M will be (V). SET / 2,V SET The voltage drop across the RRAM is insufficient to initiate the RRAM setup operation, but a reset operation can be performed. If P = Q = 0, then after the operation P' = 0, Q' = 1. If P = Q = 1, there will be no change in resistance in the RRAM. If P is LRS and Q is HRS, most of the voltage is applied to Q, and because Q is HRS, there will be no change in resistance in the RRAM. If P is HRS and Q is LRS, most of the voltage is applied to P, P will be set to LRS, and Q will remain unchanged. The results are shown in Table 4.

[0083] Table 4: Truth table of P' = P * Q, Q' = P IMP Q

[0084]

[0085] 5. P' = P, Q' = P IMP Q: Assume the voltage range on SL is (2V) RESET V SET When the resistance states of the two RRAMs are the same (P=0, Q=0 or P=1, Q=1), the voltage across SL will be uniformly distributed across the upper and lower RRAMs, and the voltage at point M will be (V). RESET V SET / 2) The voltage drop across the RRAM is insufficient to set the RRAM, but a reset operation can be performed. Therefore, the analysis method and results are the same as before for the voltage case. If P is LRS and Q is HRS, most of the voltage is applied to Q, and because Q is HRS, there is no resistance change in the RRAM. The same applies when P is HRS and Q is LRS; there is no resistance change. The results are shown in Table 5.

[0086] Table 5: Truth Table of P' = P, Q' = P IMP Q

[0087]

[0088] By opening K1, M0, and M5, RRAM0 and RRAM2 are connected, and BL is grounded. SL is connected to the bottom electrode of RRAM0, and the bottom electrode of RRAM2 is grounded through M5, as follows: Figure 6 The connection to RRAM is shown, with RRAM0 storing P and RRAM2 storing Q. The implemented operations also include set to 0, set to 1, hold, "IMP", "NIMP", and "OR", with results shown in Tables 6-8 below.

[0089] Table 6: Truth Table of P' = Q IMP P, Q' = 0

[0090]

[0091] Table 7: Truth Table of P' = Q IMP P, Q' = P * Q

[0092]

[0093] Table 8: Truth Table of P' = Q IMP P, Q' = Q

[0094]

[0095] 6. This structure can also store the results of XOR and XNOR operations, requiring only two RRAMs and two loops. First, configure the RRAMs as follows: Figure 7 The connection is shown in the form shown, where P is encoded using forward encoding and Q using reverse encoding. If P0 = A and Q0 = B, then after the operation P1 = AB and Q1 = A + B, the transistor can then be controlled as follows: Figure 7 The configuration shown consists of two RRAMs, with the upper RRAM containing the previously inverted Q and the lower RRAM containing the forward-encoded P. When the appropriate voltages are set as shown in Table 9, the state of the lower RRAM is as follows: The upper-level RRAM represents the XOR result.

[0096] Table 9: Truth Table for Two-Period XOR and XNOR Realization

[0097]

[0098] Specifically: First, store P in RRAM0 and Q in RRAM3. Then, enable M0, M7, and K1, connecting the two RRAMs at the top and bottom, and ensuring that the voltage of SL is greater than twice V. RESET At this point, the result stored in RRAM1 after the operation is A*B, and the result stored in RRAM3 is A+B. In the second cycle, M1, M6, and K1 are turned on, and the voltage range on SL is set to be greater than V. SET Less than 2V SET After the calculation, the data stored in RRAM0 is P⊙Q, and the data stored in RRAM3 is... It achieves XOR and XNOR operations using two RRAMs in two cycles. Figure 8 The waveforms show the results of XOR and XNOR operations performed using two RRAMs over two cycles.

[0099] Example 2

[0100] Please see Figure 9This embodiment, based on Embodiment 1, provides an in-memory computing circuit with an array distribution as described in Embodiment 1.

[0101] Specifically, this embodiment introduces a multi-logic in-memory operation circuit, which includes a memory array, bit line group, NMOS transistor K1, transistor group, word line WL, word line CTRLR, word line CTRLR, word line driver module, decoder, function switching circuit, precharge circuit, timing control circuit, switching circuit, sensitive amplifier, and output circuit.

[0102] The storage array consists of 4NM storage units arranged in a 4N×M array. Here, N represents the number of rows in the storage array, and M represents the number of columns in the storage array.

[0103] The bit line group includes M groups SL, BL, BLBIN, and BLBOUT. Each memory cell in each column is connected to the same group of bit lines SL, BL, BLBIN, and BLBOUT.

[0104] There are M NMOS transistors K1, and the source and drain of each column of K1 are connected to the same group BLBIN and BLBOUT.

[0105] The transistor group consists of M NMOS transistors M8 and M9. The bit lines BL and BLBIN of each column are connected to the same group of M8 and M9.

[0106] There are 8N word lines (WL), used to control the switching on and off of the NMOS transistors in each memory cell of the memory array. Word line CTRLR is used to control the switching on and off of each transistor M9 in the transistor group. Word line CTRLL is used to control the switching on and off of each transistor M8 in the transistor group. The word line driver module is used to control the high and low levels of the word lines in each memory cell of the memory array.

[0107] The decoder is used to select the appropriate word line to enable based on the input address.

[0108] The function switching circuit is used to control the switching of each in-memory computing unit in the storage array between read / write operations, overwrite operations, and in-memory operations, so as to adjust the different working modes of the circuit.

[0109] The precharge circuit is used to precharge the bit lines SL, BL, BLBIN, and BLBOUT connected to each column of computing cells in the memory array.

[0110] The timing control circuit is used to generate the clock signals required by each functional module.

[0111] Switching circuits are used to control the opening or closing of bit lines connected to each memory cell in the memory array.

[0112] The number of sensitive amplifiers is M, which are used to compare the voltage on the bit line SL with a preset reference voltage Vref, thereby obtaining the stored data or logic calculation results of the memory cell in any column.

[0113] The output circuit is used to output the stored data or logical calculation results of the storage unit in any column.

[0114] Specifically, any in-memory computing unit, K1, and transistor group in the memory array constitute the in-memory computing circuit as described above, and can realize the complete function of the basic circuit.

[0115] The difference between this embodiment and Embodiment 1 is that this embodiment uses an array to form a large-scale in-memory arithmetic circuit, which, in conjunction with other circuits, constitutes a complete multi-logic in-memory arithmetic circuit. Therefore, this embodiment can implement the logical operations and other functions described in Embodiment 1.

[0116] The following is based on Figure 9 The solution of this embodiment will be described in detail using an example.

[0117] Figure 9 The array distribution of the memory computing units is 64×64. Since this embodiment uses adjacent memory computing units in the same column to form a basic memory computing unit, the final storage array is actually distributed in a 64×32 pattern. The basic memory computing unit, formed by the cross-coupling of the original adjacent memory computing units in the same column, can completely resist cross-logic operations. In the final storage array, every row and column includes a basic memory computing unit composed of two original memory computing units.

[0118] refer to Figure 9 The original memory cell shared four word lines per row and four bit lines per column, and each column shared one transistor M8 and M9. A switching transistor K1 was connected between the bit lines BILIN and BLBOUT in the same column. K1 is a NOMS transistor. For the transistors used in this embodiment, all are NOMS transistors. In each column, the odd-numbered rows are connected to the bit line BILIN, and the even-numbered rows are connected to the bit line BLBOUT.

[0119] Specifically, the 4T2R mentioned in Example 1 is... Figure 9 The original storage unit in China, according to Figure 9 The original array of memory cells is explained below, taking the first and second rows as examples. In the first row, transistors M0 to M3 in 4T2R are connected to word lines WL. <0> ~WL <3> In the second row, transistors M4 to M7 in 4T2R are connected to word lines WL respectively. <4> ~WL <7> Each word line connects to the transistors in the same row and can control the transistors to turn on and off.

[0120] Based on this, the storage function is implemented in the same way as the original RRAM, but through the cooperation between RRAMs, logical operations such as "AND", "OR", and "XOR" are implemented, and the time cycle requirement is reduced.

[0121] It should be noted that 4T2R, 64×64 storage arrays, etc., are examples listed in this embodiment to illustrate the solution, and are not intended to limit the scope of this case. In other embodiments, based on the same technical concept, other types of storage units can be used to construct other storage arrays of larger scale to obtain the required "storage array".

[0122] Example 3

[0123] This embodiment introduces a multi-logic in-memory arithmetic chip, which is packaged from the aforementioned multi-logic in-memory arithmetic circuit. The interfaces of the multi-logic in-memory arithmetic chip include at least a power interface VDD, a ground interface VSS, a row select interface A, an input signal interface IN, a control signal interface CEN, a read / write enable signal WEN, a switching signal KN, a clock signal interface CLK, and an output signal interface OUT.

[0124] The power interface VDD is used to connect to the power supply. The ground interface VSS is used for grounding. The row strobe interface A is used to input row strobe signals to the circuit, which are used to adjust the access status of each memory-in-memory unit on each word line. The input signal interface IN is used to input corresponding input signals to each memory-in-memory unit. The control signal interface CEN is used to input control signals to adjust the operating status of each memory-in-memory unit. The read / write enable signal WEN is used to input enable signals to adjust the read / write operations of each memory-in-memory unit. The switching signal KN is used to input a switching signal to the circuit, which is used to adjust the switching between read / write operations, overwrite operations, and in-memory operations of each memory-in-memory unit in the memory array, so as to adjust the different operating modes of the circuit. The clock signal interface CLK is used to input an external clock signal to the circuit, which is used to provide the clock frequency required for the operation of each memory-in-memory unit in the memory array. The output signal interface OUT is used to read the stored data or logical operation results of each memory-in-memory unit.

[0125] Performance testing

[0126] To verify the computational accuracy of the memory computing unit designed in this invention, the memory computing circuit in the embodiment of this invention and, as shown in the example... Figure 10 The existing reconnaissance logic circuit shown is compared to test the accuracy of the operation. For example... Figure 11 As shown, taking the "AND operation" as an example, a simulation experiment is conducted as follows:

[0127] 1. Simulation Conditions: Process corner TT is used, and the temperature is 27℃. It should be noted that the performance range provided to designers is usually only applicable to digital circuits and is given in the form of a "process corner." The idea is to limit the speed fluctuation range of NMOS and PMOS transistors within a rectangle defined by four corners. These four corners are: fast NFET and fast PFET, slow NFET and slow PFET, fast NFET and slow PFET, and slow NFET and fast PFET. When extracting the device model corresponding to each corner from the wafer, the on-chip NMOS and PMOS test structures show different gate delays, and the actual selection of these corners is to obtain an acceptable yield. Simulating the circuit under various process corners and extreme temperature conditions is the basis for determining the yield. Therefore, SS, TT, and FF refer to the lower left corner, the center corner, and the upper right corner, respectively. From a measurement perspective, T indicates that the transistor drive current is an average value, F indicates that the drive current is its maximum value, and S indicates that the drive current is its minimum value. The measured results of a single device follow a normal distribution, with the mean at TT and the minimum and maximum limits at SS and FF.

[0128] 2. Number of simulations: 5000 Monte Carlo simulations were set up. Multiple experiments were conducted to obtain stable experimental results. Therefore, 5000 experiments are more valuable for evaluating the operational accuracy of this circuit.

[0129] 3. Simulation Results: Analysis Figure 11 It can be seen that when the resistance change is less than 2σ, the operation accuracy of the circuit of the present invention and the existing detection logic circuit are both 100%. When the resistance change is between 2σ and 3σ, the operation accuracy of the existing detection logic circuit begins to decrease. When the resistance change is greater than 3σ, the operation accuracy of the existing detection logic circuit decreases significantly, but the accuracy of the circuit of the present invention does not decrease significantly.

[0130] In summary, this invention utilizes a 4T2R architecture to perform various logic operations. The robustness of the underlying scheme stems from the use of different discharge paths depending on the operation, preventing resistor crossover issues. Furthermore, multiple connections to the RRAM can be configured by controlling the transistors, and logic operations can be easily performed by adjusting the input voltage pulses and storing the results in the RRAM. Reverse encoding allows for the execution of OR, XOR, and XNOR operations, which would require more cycles in other devices, using fewer RRAM and clock cycles. Therefore, the designed circuit exhibits better spatial and temporal complexity.

[0131] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0132] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this invention patent should be determined by the appended claims.

Claims

1. An in-memory computing circuit, characterized in that, It includes a memory array consisting of multiple memory cells; two adjacent memory cells in the memory array are placed in reverse RRAM structure; each column of memory cells is connected to four bit lines SL, BL, BLBIN, and BLBOUT; the source and drain of NMOS transistor K1 are connected to BLBIN and BLBOUT respectively; the source of NMOS transistor M8 is connected to BL; the drain of NMOS transistor M9 is connected to BLBIN; and the drain of M8 and the source of M9 are grounded. Four adjacent memory cells RRAM0~RRAM3 in each column constitute a basic memory cell; the memory cell also includes eight NMOS transistors M0~M7; the gate of each NMOS transistor is connected to a word line; the source of M0, M2, M4, and M6 is connected to SL, the source of M1, M3, M5, and M7 is connected to BL, the drain of M0 and M1 is connected to the bottom electrode of RRAM0, the drain of M2 and M3 is connected to the top electrode of RRAM1, the drain of M4 and M5 is connected to the bottom electrode of RRAM2, the drain of M6 and M7 is connected to the top electrode of RRAM3, the top electrode of RRAM0 and RRAM2 is connected to BLBIN, and the bottom electrode of RRAM1 and RRAM3 is connected to BLBOUT.

2. The in-memory computing circuit according to claim 1, characterized in that, The storage unit performs the "AND" logical operation as follows: By opening M0, M5, M8 and K1, RRAM0 and RRAM2 are connected in series; when RRAM0 and RRAM2 are in a low resistance state, SL discharges; when RRAM0 and RRAM2 are in a high resistance state, SL does not discharge; the discharge path of SL is M0, RRAM0, K1, RRAM2, M5, M8.

3. The in-memory computing circuit according to claim 1, characterized in that, The storage unit performs the "OR" logical operation as follows: RRAM0 and RRAM2 are connected in parallel by opening M0, M4, M9 and K1; SL discharges when RRAM0 and / or RRAM2 are in a low resistance state; SL does not discharge when RRAM0 and RRAM2 are in a high resistance state. The discharge path of SL is M0, RRAM0, K1, M9; Or M4, RRAM2, M9.

4. The in-memory computing circuit according to claim 1, characterized in that, The storage unit performs the "XOR" logical operation as follows: By opening M0, M3, and M8, RRAM0 and RRAM1 are connected in series; by opening M4 and M7, RRAM2 and RRAM3 are connected in series, and RRAM0 and RRAM1 are connected in parallel with RRAM2 and RRAM3; when RRAM0, RRAM1 and / or RRAM2 and RRAM3 are in a low-resistance state, SL discharges. The discharge path of SL is M0, RRAM0, RRAM1, M3, M8; Or M4, RRAM2, RRAM3, M7, M8.

5. The in-memory computing circuit according to claim 1, characterized in that, The connection methods between storage units within the in-memory computing unit include top-bottom connection, bottom-bottom connection, and top-top connection; the resistance state of the storage units is used to represent the results of different logical operations.

6. The in-memory computing circuit according to claim 5, characterized in that, The top-to-bottom connection operation of the storage units within the in-memory unit is as follows: RRAM0 and RRAM3 are connected by opening K1, M0 and M7, BL is grounded; SL is connected to the bottom electrode of RRAM0, and the top electrode of RRAM3 is grounded through M7; the resistance states of RRAM0 and RRAM3 indicate the results of different logic operations. or RRAM1 and RRAM2 are connected by opening K1, M2 and M5, BL is grounded; SL is connected to the top electrode of RRAM1, and the bottom electrode of RRAM2 is grounded through M5; the resistance states of RRAM1 and RRAM2 indicate the results of different logic operations.

7. The in-memory computing circuit according to claim 5, characterized in that, The bottom-to-bottom connection operation of the storage units within the in-memory unit is as follows: RRAM1 and RRAM3 are connected by opening K1, M2, and M7, and BL is grounded; SL is connected to the top electrode of RRAM1, and the top electrode of RRAM3 is grounded through M7; the resistance states of RRAM1 and RRAM3 indicate the results of different logic operations.

8. The in-memory computing circuit according to claim 5, characterized in that, The top-to-top connection operation of the storage units within the in-memory unit is as follows: RRAM0 and RRAM2 are connected by opening K1, M0 and M5, BL is grounded; SL is connected to the bottom electrode of RRAM0, and the bottom electrode of RRAM2 is grounded through M5; the resistance states of RRAM0 and RRAM2 indicate the results of different logic operations.

9. A multi-logic-in-memory arithmetic circuit, characterized in that, It includes: The storage array consists of 4NM storage units arranged in a 4N×M array; where N represents the number of rows in the storage array and M represents the number of columns in the storage array. The bit line group includes M groups SL, BL, BLBIN, and BLBOUT; each memory cell in each column is connected to the same group of bit lines SL, BL, BLBIN, and BLBOUT. There are M NMOS transistors K1, and the source and drain of each column of K1 are connected to the same group BLBIN and BLBOUT. A transistor group, comprising M transistors M8 and M9; the bit lines BL and BLBIN of each column are connected to the same group of M8 and M9. The word lines WL, numbering 8N, are used to control the on / off state of the NMOS transistors in each memory cell of the memory array; The word line CTRLR is used to control the on and off states of each transistor M9 in the transistor group; The word line CTRLLL is used to control the on and off states of individual transistors M8 in the transistor group; Word line driver module, which is used to control the high and low levels of word lines of each memory unit in the memory array; A decoder, used to select the activation of the corresponding word line based on the input address; The function switching circuit is used to control the switching of each storage unit in the storage array between read / write operations, overwrite operations, and in-memory operations, so as to adjust the different working modes of the circuit. The pre-charge circuit is used to pre-charge the bit lines SL, BL, BLBIN, and BLBOUT connected to each column of computing cells in the memory array. Timing control circuit, which is used to generate the clock signals required by each functional module; A switching circuit, used to control the opening or closing of the bit lines connected to each memory unit in the memory array; M sensitive amplifiers are used to compare the voltage on the bit line SL with a reference voltage Vref, thereby obtaining the stored data or logic calculation results of the memory cell in any column; Output circuit, which is used to output the stored data or logical calculation results of the storage unit in any column; In this configuration, any in-memory computing unit, K1, and transistor group in the memory array constitute the in-memory computing circuit as described in any one of claims 1-8, and can realize the complete function of the in-memory computing circuit.

10. A multi-logic-in-memory arithmetic chip, characterized in that, It is packaged from the multi-logic in-memory arithmetic circuit described in claim 9; the interface of the multi-logic in-memory arithmetic chip includes at least: The power interface VDD is used to connect to the power supply. The grounding interface VSS is used for grounding. Row strobe interface A is used to input row strobe signals to the circuit, and the row strobe signals are used to adjust the access status of each memory unit on each word line; The input signal interface IN is used to input corresponding input signals to each memory unit. The control signal interface (CEN) is used to input control signals that adjust the operating status of each memory unit. The read / write enable signal WEN is used to input and adjust the enable signal for read / write operations of each memory unit; The switching signal KN is used to input a switching signal into the circuit. The switching signal is used to adjust the switching of each storage unit in the storage array between read / write operations, overwrite operations, and in-memory operations, so as to adjust the different working modes of the circuit. The clock signal interface CLK is used to input an external clock signal into the circuit, which provides the clock frequency required for the operation of each memory computing unit in the memory array. The output signal interface OUT is used to read the stored data or logical operation results of each memory unit.

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