Method of manufacturing a memory device using a mask pattern

Abstract

A method of manufacturing a memory device using a mask pattern is provided. A method of manufacturing a memory device is provided. The method includes the steps of forming a mask layer on an etch target layer; forming a compensation layer having a second impurity on the mask layer, the compensation layer being chemically bonded to the mask layer having a first impurity; performing a first etch process that patterns the compensation layer and the mask layer to form a mask pattern; and performing a second etch process that etches the etch target layer exposed through an opening of the mask pattern.

Description

TECHNICAL FIELD

[0001] The disclosure relates generally to a mask pattern, and more particularly, to a method of manufacturing a memory device including a mask pattern for forming a trench or a contact hole with a narrow distance between patterns. BACKGROUND

[0002] A memory device can be configured to store data and erase or output the stored data. For example, the memory device can include a memory block storing data and a peripheral circuit configured to program data in the memory block or erase or output the programmed data.

[0003] The memory block and the peripheral circuit include a plurality of transistors and a plurality of lines. As the integration of the memory device gradually increases, the size and distance of the plurality of transistors and the plurality of lines gradually decrease. Accordingly, in a manufacturing process of the memory device, a defect such as a bridge can occur between adjacent elements. SUMMARY

[0004] According to one aspect of the disclosure, there is provided a method of manufacturing a memory device, the method including the steps of: forming a mask layer on an etching target layer; forming a compensation layer having a second impurity on the mask layer, the compensation layer being chemically bonded to the mask layer having a first impurity; performing a first etching process that patterns the compensation layer and the mask layer to form a mask pattern; and performing a second etching process that etches the etching target layer exposed through an opening of the mask pattern.

[0005] According to another aspect of the disclosure, there is provided a method of manufacturing a memory device, the method including the steps of: alternately forming a plurality of mask layers and a plurality of compensation layers on an etching target layer, the plurality of compensation layers being chemically bonded to the mask layers; forming a mask pattern having an opening exposing a portion of the etching target layer by patterning the mask layers and the compensation layers; and performing an etching process that forms a contact hole in the etching target layer by removing the portion of the etching target layer exposed through the opening. BRIEF DESCRIPTION OF DRAWINGS

[0006] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings; however, these embodiments can be implemented in different forms and should not be construed as limited to the implementations set forth herein. Rather, these embodiments are provided as illustrative examples so as to convey the principles of the present disclosure to those skilled in the art and to fully disclose the best mode of practicing the example embodiments.

[0007] In the drawings, the size of some of the elements can be exaggerated and not drawn on scale for illustrative purposes. It should be understood that when an element is referred to as being "between" two elements, it can be the only element between the two elements or one or more intervening elements can also be present. Like reference numerals refer to like elements throughout.

[0008] Figures 1A-1C is a view illustrating a defect that can occur in a manufacturing process of a memory device.

[0009] Figures 2A-2D is a view illustrating a method of forming a mask according to an embodiment of the disclosure.

[0010] Figure 3 is a view illustrating a structure in which ions of a mask and a compensation layer are bonded to each other.

[0011] Figure 4 is a view illustrating a method of forming a mask according to another embodiment of the disclosure.

[0012] Figures 5A-5F is a view illustrating a manufacturing method of a memory device according to an embodiment of the disclosure.

[0013] Figures 6A-6F is a view illustrating a manufacturing method of a memory device according to another embodiment of the disclosure.

[0014] Figure 7 is a block diagram of a memory card system to which a manufactured memory device according to an embodiment of the disclosure is applied.

[0015] Figure 8 is a block diagram of a solid state drive (SSD) to which a manufactured memory device according to an embodiment of the disclosure is applied. DETAILED DESCRIPTION

[0016] The specific structural or functional descriptions disclosed herein are only illustrative for the purpose of describing embodiments according to the concept of the disclosure. Embodiments according to the concept of the disclosure can be implemented in various forms, and should not be interpreted as being limited to the embodiments set forth herein.

[0017] Embodiments provide a manufacturing method of a memory device capable of preventing a bridge from occurring between adjacent elements.

[0018] Figures 1A-1C is a view illustrating a defect that can occur in a manufacturing process of a memory device.

[0019] REFERENCE Figure 1AA mask pattern 110 can be formed on top of an etching target layer 100. Although not shown in the drawing, a lower structure such as a substrate or a peripheral circuit can be formed below the etching target layer 100. The etching target layer 100 can be an interlayer insulating layer. For example, the etching target layer 100 can be formed of silicon oxide. In order to form a trench TC or a contact hole in the etching target layer 100, the mask pattern 110 in which an opening is formed in an etching target region can be formed on top of the etching target layer 100. The mask pattern 110 can be formed of carbon. For example, the mask pattern 110 can be formed of amorphous carbon. The mask pattern 110 can include an opening that exposes a portion of the etching target layer 100. Although the mask pattern 110 in which an opening in a linear shape is formed is shown in Figure 1A , the opening can be implemented in various shapes such as a circular shape and a polygonal shape.

[0020] When an etching process using the mask pattern 110 as an etching mask is performed, as the etching target layer 100 exposed through the opening of the mask pattern 110 is etched, a trench TC can be formed. The etching process can be performed by using a plasma via a dry etching process. The etching process can be performed by using a gas having a high etching selectivity with respect to the etching target layer 100 as an etching gas ETC. For example, when the etching target layer 100 formed of silicon oxide is etched by using the mask pattern 110 containing carbon as an etching mask, the etching process can be performed by using a fluorine-containing etching gas ETC. For example, a CF4 or CHF3 gas can be used as the etching gas ETC.

[0021] When the etching process using the fluorine-containing etching gas ETC is performed, fluorine contained in the etching gas ETC can be ionized by a plasma, and fluorine (F) ions can be introduced into the etching target layer 100 through the mask pattern 110. Since fluorine has a high etching selectivity with respect to the etching target layer 100, a defect DF caused by fluorine can occur outside a region in which the trench TC is formed. For example, when the defect DF occurs in a region in which etching of the etching target layer 100 is inhibited, a portion of the etching target layer 100 can be etched due to the defect DF.

[0022] Referring to Figure 1B , the defect DF occurring in the etching target layer 100 can occur in the etching process using the etching gas ETC, and can remain after the mask pattern 110 is removed. Even in a cleaning process performed after the etching process is performed, the region in which the defect DF occurs can be further removed.

[0023] Referring to Figure 1CWhen the trench TC is filled with the conductive layer 120 in a state in which the defect DF occurs in the etching target layer 100, the conductive layer 120 can spill into the area in which the defect DF occurs. Thus, although a polishing process that allows the conductive layer 120 to remain only in the trench TC is performed, the conductive layer 120 that spills into the area in which the defect DF occurs can also remain, thereby possibly forming a bridge BG. For example, the bridge BG can be formed between a line that can be formed in the trench TC and an adjacent line that is to be electrically isolated from the line. When the bridge BG is formed between lines that are to be electrically isolated from each other, a malfunction can occur in the operation of the memory device, and thus, the reliability of the memory device can deteriorate.

[0024] Figures 2A-2D FIG. 1 is a view illustrating a method of forming a mask according to one embodiment of the present disclosure.

[0025] Referring to Figure 2A A first mask layer 210a and a compensation layer 220 can be formed on top of an etching target layer 200. Although not shown in the drawing, a lower structure such as a substrate or a peripheral circuit can be formed on a bottom of the etching target layer 200.

[0026] The etching target layer 200 can be formed of an insulating material. For example, the etching target layer 200 can be formed of an oxide or silicon oxide. The first mask layer 210a can be formed on top of the etching target layer 200, and the compensation layer 220 can be formed on top of the first mask layer 210a. The first mask layer 210a can be used as a mask pattern in an etching process of the etching target layer 200, and can be formed of carbon. For example, the first mask layer 210a can be formed of amorphous carbon.

[0027] The compensation layer 220 can be formed to prevent a defect from occurring in the etching target layer 200 during an etching process. For example, the compensation layer 220 can be formed to prevent a bridge from being formed in the etching target layer 200 that can occur due to the first mask layer 210a. To this end, the compensation layer 220 can be formed of a material that is easily chemically bonded to the first mask layer 210a. When the first mask layer 210a is formed of a carbon (C)-containing material, the compensation layer 220 can be formed of a material that contains hydrogen (H) that is easily ion-bonded to carbon (C). For example, the compensation layer 220 can be formed as a layer having a high hydrogen (H) density.

[0028] Referring to Figure 2BThe second mask layer 210b, the barrier layer 240, and the photoresist pattern 250 can be sequentially formed on top of the compensation layer 220. The barrier layer 240 can be formed of silicon oxide. The second mask layer 210b can be formed on top of the compensation layer 220, the barrier layer 240 can be formed on top of the second mask layer 210b, and the photoresist pattern 250 can be formed on top of the barrier layer 240. The first mask layer 210a, the compensation layer 220, and the second mask layer 210b can serve as a mask pattern MP.

[0029] The photoresist pattern 250 and the barrier layer 240 can serve as a pattern used in a process of patterning the second mask layer 210b, the compensation layer 220, and the first mask layer 210a, and the first mask layer 210a, the compensation layer 220, and the second mask layer 210b can serve as a mask pattern MP used in a process of etching the etching target layer. Accordingly, layers or patterns formed on top of the mask pattern MP are not limited to the barrier layer 240 and the photoresist pattern 250, and various layers or patterns can be formed.

[0030] The first mask layer 210a, the compensation layer 220, and the second mask layer 210b included in the mask pattern MP can be formed by using an in-situ method of changing a gas in the same chamber or by using an ex-situ method of using different gases in different chambers.

[0031] Referring to Figure 2C The barrier layer 240, the second mask layer 210b, the compensation layer 220, and the first mask layer 210a exposed through the opening of the photoresist pattern 250 are sequentially etched by an etching process, and thus an opening OP exposing a portion of the etching target layer 200 can be formed.

[0032] Referring to Figure 2D An etching process for etching a portion of the etching target layer 200 exposed through the opening of the mask pattern MP can be performed. The etching process can be performed by using plasma via a dry etching process.

[0033] The etching process can be performed by using an etching gas ETC having an etching selectivity higher than that of the mask pattern MP with respect to the etching target layer 200. For example, the etching process can be performed by using fluorine gas or a fluorine-containing gas as the etching gas ETC. For example, CF4or CHF3gas can be used as the etching gas ETC.

[0034] The photoresist pattern (250) and the barrier layer (240) formed on top of the mask pattern MP shown in FIG. 2A can be removed by using a photoresist stripping process. Figure 2C Figure 2C ​Both of the illustrated 240) can be removed while the etching process is performed. Therefore, the top surface of the mask pattern MP can be exposed by the etching process using the etching gas ETC. Although the etching speed of the etching target layer 200 is faster than the etching speed of the mask pattern MP, the mask pattern MP can also be etched little by little while the etching process is performed.

[0035] When the etching process is performed, fluorine included in the etching gas ETC can be ionized into fluorine (F) ions due to plasma, and the fluorine (F) ions can penetrate into the second mask layer 210b included in the mask pattern MP.

[0036] In this embodiment, since the compensation layer 220 is located between the first mask layer 210a and the second mask layer 210b, chemical bonding of impurities can occur between the compensation layer 220 and the first mask layer 210a and the second mask layer 210b. For example, covalent bonding in which hydrogen (H) atoms and carbon (C) atoms share electron pairs with each other can occur between the compensation layer 220 and the first mask layer 210a and the second mask layer 210b, and ionic bonding in which fluorine (F) ions and hydrogen (H) ions are bonded to each other can occur between the compensation layer 220 and the first mask layer 210a and the second mask layer 210b. Due to the covalent bonding of hydrogen (H) and carbon (C), a compensation crystal structure 300 can be formed in a boundary region between the compensation layer 220 and the first mask layer 210a and the second mask layer 210b, or in the first mask layer 210a. The compensation crystal structure 300 is a crystal structure formed due to the covalent bonding of hydrogen (H) and carbon (C), and can serve to increase the density of the compensation layer 220 and the first mask layer 210a. Therefore, although fluorine ions F penetrate into the mask pattern MP in the etching process, the penetration can be inhibited by the compensation crystal structure 300. Thus, the number of fluorine ions F that penetrate into the first mask layer 210a can be reduced, and defects that can occur in the etching target layer 200 due to the etching gas ETC can be reduced.

[0037] Further, to further inhibit the penetration of fluorine ions F, the first mask layer 210a and the second mask layer 210b can be formed at a temperature higher than a normal temperature. Assuming that the normal temperature at which the first mask layer 210a and the second mask layer 210b are formed is a reference temperature, when the first mask layer 210a and the second mask layer 210b are formed at a temperature higher than the reference temperature, the density of the first mask layer 210a and the second mask layer 210b can be increased. When the density of the first mask layer 210a and the second mask layer 210b is increased, the number and the penetration speed of fluorine ions F can be further reduced, and thus the probability of defects that can occur in the etching process of forming the trench TR can be reduced.

[0038] Figure 3 is a view illustrating a structure in which ions of a mask and a compensation layer are bonded to each other.

[0039] Referring to Figure 3 and Figure 2D , carbon (C) ions of the first mask layer 210a and hydrogen (H) ions of the compensation layer 220 can be bonded to each other in various structures. For example, a compensation crystal structure 300 of carbon (C) and hydrogen (H) can be generated as a structure of at least one of CH, CH2, HC, and H2C.

[0040] Figure 4 is a view illustrating a method of forming a mask according to another embodiment of the disclosure.

[0041] Referring to Figure 4 , a plurality of mask layers 210a through 210g and a plurality of compensation layers 220a through 220f can be alternately stacked on top of the etching target layer 200. For example, after the first mask layer 210a is formed on top of the etching target layer 200, the first compensation layer 220a can be formed on top of the first mask layer 210a. The second mask layer 210b can be formed on top of the first compensation layer 220a, and the second compensation layer 220b can be formed on top of the second mask layer 210b. In this way, the plurality of compensation layers 220a through 220f can be alternately disposed between the plurality of mask layers 210a through 210g. The number of the first mask layer 210a through the seventh mask layer 210g and the first compensation layer 220a through the sixth compensation layer 220f that are alternately stacked is not limited to that shown in the drawing.

[0042] When the plurality of mask layers 210a through 210g and the plurality of compensation layers 220a through 220f are included in the mask pattern MP, even when fluorine ions F penetrate downward while penetrating the compensation crystal structure 300 from top of the mask pattern MP, the number of the fluorine ions F that penetrate downward can be reduced by the compensation crystal structure 300 shown. Thus, a phenomenon in which defects occur when the fluorine ions F even penetrate into the etching target layer 200 can be prevented. Figure 3

[0043] The above-described embodiments can be used for various etching processes for forming trenches or contact holes adjacent to each other during a manufacturing process of a memory device. In one example, a manufacturing process of forming a contact plug in a memory cell array will be described below.

[0044] Figures 5A-5F is a view illustrating a method of manufacturing a memory device according to one embodiment of the disclosure.

[0045] Referring to Figure 5A ​The first to third mask layers 520a to 520c and the first and second compensation layers 530a and 530b used as the mask pattern MP can be alternately stacked on top of the first interlayer insulating layer 500. The barrier layer 540 and the photoresist pattern 550 can be sequentially stacked on top of the mask pattern MP. Although not shown in the drawing, a lower structure such as a substrate or a peripheral circuit can be formed below the first interlayer insulating layer 500 which is an etching target layer.

[0046] The first interlayer insulating layer 500 can be formed of silicon oxide. A plurality of gate lines 510 used as word lines can be formed in the first interlayer insulating layer 500. The gate lines 510 can be stacked to be spaced apart from each other in a vertical direction of the substrate, and can be formed in a stepped shape. The gate lines 510 can be formed of a conductive material, and can be formed of, for example, tungsten.

[0047] The first to third mask layers 520a to 520c can be formed of carbon. For example, the first to third mask layers 520a to 520c can be formed of amorphous carbon.

[0048] The first and second compensation layers 530a and 530b can be formed between the first to third mask layers 520a to 520c to prevent a bridge from being formed in the first interlayer insulating layer 500 in a subsequent etching process. The first and second compensation layers 530a and 530b can be formed of a material containing hydrogen (H) that is easily chemically bonded to carbon (C) contained in the first to third mask layers 520a to 520c. For example, the first and second compensation layers 530a and 530b can be hard mask layers having a high hydrogen (H) density.

[0049] The photoresist pattern 550 and the barrier layer 540 can be used as an etching mask pattern in a process of patterning the first to third mask layers 520a to 520c and the first and second compensation layers 530a and 530b. The barrier layer 540 can be formed of silicon oxide. The photoresist pattern 550 can include an opening OP exposing a portion of the barrier layer 540.

[0050] Reference Figure 5BA first etching process can be performed to form openings OP in the barrier layer 540, the first mask layers 520a to the third mask layers 520c, and the first compensation layers 530a and the second compensation layers 530b. The first etching process can be a dry etching process and can be performed using a first etching gas 1ETC. For example, the first etching gas 1ETC may include a gas with higher etch selectivity for the barrier layer 540, the first mask layers 520a to the third mask layers 520c, and the first compensation layers 530a and the second compensation layers 530b than for the photoresist pattern 550. The first etching process can be performed until the first interlayer insulating layer 500 is exposed through the openings OP of the mask pattern MP.

[0051] Reference Figure 5C When the first interlayer insulating layer 500 is exposed through the opening OP of the mask pattern MP, a second etching process for forming contact holes Hc in the first interlayer insulating layer 500 exposed through the opening OP can be performed. The second etching process can be performed using a dry etching process. For example, the second etching process can be performed using a second etching gas 2ETC that has a higher etch selectivity for the first interlayer insulating layer 500 than that for the mask pattern MP. The second etching gas 2ETC may include a fluorinated gas. For example, CF4 or CHF3 gas can be used as the second etching gas 2ETC.

[0052] Because plasma is used in the dry etching process, fluoride ions ionized by the plasma in the second etching gas 2ETC can be introduced into the mask pattern MP. The atoms of the first mask layers 520a to 520c, the first compensation layer 530a, and the second compensation layer 530b included in the mask pattern MP can be chemically bonded to each other, thereby creating a compensation crystal structure. Due to the compensation crystal structure, fluoride ions cannot penetrate into the first interlayer insulating layer 500. Therefore, defects caused by fluoride ions in the boundary region BR where the first interlayer insulating layer 500 and the first mask layer 520a are in contact with each other can be prevented. A second etching process can be performed until the gate line 510 is exposed through the contact hole Hc.

[0053] Reference Figure 5D It can perform operations to remove mask patterns. Figure 5C The cleaning process for the MP shown is described. The cleaning process can be performed as a wet etching process and can be performed using an etchant with higher etch selectivity for the mask pattern MP than for the first interlayer insulating layer 500 and the gate line 510.

[0054] Reference Figure 5EThe conductive layer 560 can be formed throughout the structure to fill the contact holes Hc. The conductive layer 560 can be formed of polysilicon or tungsten. To completely fill the contact holes Hc, the conductive layer 560 can be formed such that the top of the first interlayer insulating layer 500 is completely covered by the conductive layer 560.

[0055] Referring to Figure 5F A polishing process can be performed to allow the conductive layers 560 filling the contact holes Hc to be electrically isolated from each other. The polishing process can be a chemical mechanical polishing process, and can be performed until the top of the first interlayer insulating layer 500 is exposed. Since no bridge is formed in the exposed first interlayer insulating layer 500 in the boundary region BR, the contact plugs CP formed in different contact holes Hc can be electrically isolated from each other.

[0056] In the drawings described with reference to Figures 5A-5F The manufacturing method of the contact plug CP formed in the memory cell array has been illustrated as an embodiment. However, the manufacturing method using the hard mask of the compensation layer can also be applied to a manufacturing process of forming trenches or channels adjacent to each other in addition to the contact plug CP.

[0057] Figures 6A-6F is a view illustrating a manufacturing method of a memory device according to another embodiment of the disclosure.

[0058] Referring to Figure 6A , a vertical channel layer VCH can be formed in a stacked structure in which the first interlayer insulating layer 500 and the gate line 510 are alternately stacked. The gate line 510 can be formed of a conductive material. For example, the gate line 510 can be formed of, for example, tungsten. Although not shown in the drawing, a lower structure such as a substrate or a peripheral circuit can be formed below the vertical channel layer VCH. The vertical channel layer VCH can include a memory layer constituting a memory cell. A second interlayer insulating layer 611 and a bit line 612 can be formed throughout the structure including the vertical channel layer VCH. The second interlayer insulating layer 611 can be formed of an oxide or silicon oxide, and the bit line 612 can be formed of a conductive material. The bit line 612 can be formed on the top of the vertical channel layer VCH. A third interlayer insulating layer 613 can be formed on the top of the second interlayer insulating layer 611 and the bit line 612. The third interlayer insulating layer 613 can be formed of silicon oxide.

[0059] The first to third mask layers 620a to 620c serving as the mask pattern MP and the first and second compensation layers 630a and 630b can be alternately stacked on the top of the third interlayer insulating layer 613. The barrier layer 640 and the photoresist pattern 650 can be sequentially stacked on the top of the mask pattern MP. The mask pattern MP can be formed of a material having a different etching selectivity than the first to third mask layers 620a to 620c and the first and second compensation layers 630a and 630b. Figure 5AThe mask patterns MP shown are formed of the same material. For example, the first to third mask layers 620a to 620c can be formed of amorphous carbon.

[0060] A first compensation layer 630a and a second compensation layer 630b can be formed between the first to third mask layers 620a to 620c, the first compensation layer 630a and the second compensation layer 630b preventing a bridge from being formed in the third interlayer insulating layer 613 in a subsequent etching process. The first compensation layer 630a and the second compensation layer 630b can be formed of a material containing hydrogen (H) that is easily chemically bonded to carbon (C) contained in the first to third mask layers 620a to 620c. For example, the first compensation layer 630a and the second compensation layer 630b can be a hard mask layer having a high hydrogen (H) density.

[0061] The resist pattern 650 and the barrier layer 640 can serve as an etching mask pattern in a patterning process on the first to third mask layers 620a to 620c and the first and second compensation layers 630a and 630b. The barrier layer 640 can be formed of silicon oxide. The resist pattern 650 can include an opening OP exposing a portion of the barrier layer 640.

[0062] Referring to Figure 6B A first etching process for forming the opening OP in the barrier layer 640, the first to third mask layers 620a to 620c, and the first and second compensation layers 630a and 630b can be performed. The first etching process can be a dry etching process and can be performed by using a first etching gas 1ETC. For example, the first etching gas 1ETC can include a gas having a higher etching selectivity with respect to the barrier layer 640, the first to third mask layers 620a to 620c, and the first and second compensation layers 630a and 630b than the etching selectivity of the resist pattern 650. The first etching process can be performed until the third interlayer insulating layer 613 is exposed through the opening OP of the mask pattern MP.

[0063] Referring to Figure 6C When the third interlayer insulating layer 613 is exposed through the opening OP of the mask pattern MP, a second etching process for forming a via Hv in the third interlayer insulating layer 613 exposed through the opening OP can be performed. The second etching process can be performed by a dry etching process. For example, the second etching process can be performed by using a second etching gas 2ETC having a higher etching selectivity with respect to the third interlayer insulating layer 613 than the etching selectivity of the mask pattern MP. The second etching gas 2ETC can include a fluorine-containing gas. For example, a CF4or CHF3gas can be used as the second etching gas 2ETC.

[0064] Because plasma is used in the dry etching process, fluoride ions ionized by the plasma in the second etching gas 2ETC can be introduced into the mask pattern MP. The atoms of the first mask layers 620a to 620c, the first compensation layer 630a, and the second compensation layer 630b included in the mask pattern MP can be chemically bonded to each other, thereby creating a compensation crystal structure. Due to the compensation crystal structure, fluoride ions cannot penetrate into the third interlayer insulating layer 613. Therefore, defects caused by fluoride ions in the boundary region BR where the third interlayer insulating layer 613 and the first mask layer 620a contact each other can be prevented. The second etching process can be performed until the bit line 612 is exposed through the via Hv.

[0065] Reference Figure 6D It can perform operations to remove mask patterns. Figure 6C The cleaning process for the MP shown is described. The cleaning process can be performed as a wet etching process and can be performed using an etchant with higher etch selectivity for the mask pattern MP than for the third interlayer insulating layer 613 and bit line 612.

[0066] Reference Figure 6E A conductive layer 660 can be formed over the entire structure to fill the via Hv. The conductive layer 660 can be formed of polysilicon or tungsten. To completely fill the via Hv, the conductive layer 660 can be formed such that the top of the third interlayer insulating layer 613 is completely covered by the conductive layer 660.

[0067] Reference Figure 6F A polishing process can be performed to allow the conductive layers 660 filling the vias Hv to be electrically isolated from each other. The polishing process can be a chemical mechanical polishing process and can be performed until the top of the third interlayer insulating layer 613 is exposed. Since no bridging is formed in the third interlayer insulating layer 613 exposed in the boundary region BR, the contact plugs 660c formed in the different vias Hv can be electrically isolated from each other.

[0068] Figure 7 This is a block diagram illustrating a memory card system of a memory device manufactured according to an embodiment of the present disclosure.

[0069] Reference Figure 7 The memory card system 3000 may include a controller 3100, a memory device 3200, and a connector 3300.

[0070] The controller 3100 can be connected to the memory device 3200. The controller 3100 can access the memory device 3200. For example, the controller 3100 can control a program operation, a read operation, or an erase operation, or can control a background operation of the memory device 3200. The controller 3100 can provide an interface between the memory device 3200 and a host. The controller 3100 can drive firmware for controlling the memory device 3200. To this end, the controller 3100 can include components such as a random access memory (RAM), a processing unit, a host interface, a memory interface, and an error corrector.

[0071] The controller 3100 can communicate with an external device through the connector 3300. The controller 3100 can communicate with an external device (e.g., a host) according to a specific communication protocol. Exemplarily, the controller 3100 can communicate with an external device through at least one of various communication protocols, such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), a fast PCI (PCIe), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), FireWire, universal flash storage (UFS), Wi-Fi, Bluetooth, and NVMe. For example, the connector 3300 can be defined through at least one of the above-described various communication protocols.

[0072] The memory device 3200 can be manufactured according to the above-described embodiments of the disclosure, and can be implemented with various nonvolatile memory devices, such as an electrically erasable programmable ROM (EEPROM), a NAND flash memory, a NOR flash memory, a phase-change RAM (PRAM), a resistive RAM (ReRAM), a ferroelectric RAM (FRAM), and a spin-torque transfer magnetic RAM (STT-MRAM).

[0073] The controller 3100 and the memory device 3200 can be integrated into a single semiconductor device to constitute a memory card. For example, the controller 3100 and the memory device 3200 can constitute a memory card, such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), a compact flash (CF) card, a smart media card (SM and SMC), a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro, and eMMC), an SD card (SD, miniSD, micro, and SDHC), and a universal flash storage (UFS).

[0074] Figure 8is a block diagram illustrating a solid state drive (SDD) of a memory device manufactured by applying the application according to one embodiment of the present disclosure.

[0075] Referring to Figure 8 The SSD system 4000 can include a host 4100 and an SSD 4200. The SSD 4200 can exchange a signal SIG with the host 4100 through a signal connector 4001 and receive power PWR through a power connector 4002. The SSD 4200 can include a controller 4210, a plurality of flash memories 4221 to 422n, an auxiliary power supply 4230, and a buffer memory 4240.

[0076] The controller 4210 can control the plurality of flash memories 4221 to 422n in response to a signal received from the host 4100. Exemplarily, the signal can be a signal defined based on an interface between the host 4100 and the SSD 4200. For example, the signal can be a signal defined through at least one of interfaces such as a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), a fast PCI (PCIe), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), FireWire, universal flash storage (UFS), WI-FI, Bluetooth, and NVMe.

[0077] The auxiliary power supply 4230 can be connected to the host 4100 through the power connector 4002. The auxiliary power supply 4230 can receive power PWR input from the host 4100 and charge the power PWR. When the power supply from the host 4100 is not smooth, the auxiliary power supply 4230 can supply power to the SSD 4200. Exemplarily, the auxiliary power supply 4230 can be located in the SSD 4200 or located outside the SSD 4200. For example, the auxiliary power supply 4230 can be located on a main board and can supply auxiliary power to the SSD 4200.

[0078] The buffer memory 4240 can operate as a buffer memory of the SSD 4200. For example, the buffer memory 4240 can temporarily store data received from the host 4100 or data received from the plurality of flash memories 4221 to 422n, or temporarily store metadata (e.g., a mapping table) of the flash memories 4221 to 422n. The buffer memory 4240 can include a volatile memory (e.g., DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM) or a non-volatile memory (e.g., FRAM, ReRAM, STT-MRAM, and PRAM).

[0079] According to the above-described embodiments of the disclosure, the mask pattern can be used in a process of manufacturing the buffer memory 4240 and the plurality of flash memories 4221 to 422n.

[0080] According to the disclosure, it is possible to reduce and prevent defects that can occur in the holes or trenches in the etching process using the mask pattern. Accordingly, it is possible to prevent the occurrence of bridging between adjacent elements.

[0081] While the disclosure has been shown and described with reference to certain exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details can be made therein without departing from the spirit and scope of the disclosure as defined by the appended claims and their equivalents. Accordingly, the scope of the disclosure should not be limited to the above-described exemplary embodiments but should be determined by the appended claims only and their equivalents.

[0082] In the above-described embodiments, all steps can be selectively performed or part of the steps can be omitted. In each embodiment, the steps are not necessarily performed in the order described and can be rearranged. The embodiments disclosed in the specification and drawings are only examples to help understanding of the disclosure, and the disclosure is not limited thereto. That is, it is obvious to those skilled in the art that various modifications can be made based on the technical scope of the disclosure.

[0083] Meanwhile, the exemplary embodiments of the disclosure have been described in the drawings and the specification. Although specific terms are used herein, these terms are used only for the purpose of explaining the embodiments of the disclosure. Therefore, the disclosure is not limited to the above-described embodiments, and many changes can be made within the spirit and scope of the disclosure. It is obvious to those skilled in the art that, in addition to the embodiments disclosed herein, various modifications can be made based on the technical scope of the disclosure.

[0084] Cross Reference to Related Applications

[0085] This application claims priority to Korean Patent Application No. 10-2021-0087387, filed on July 2, 2021, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.

Claims

1. A method of fabricating a memory device, the method comprising the steps of: forming a mask layer on an etch target layer; forming a compensation layer having a second impurity on the mask layer, the compensation layer being chemically bonded to the mask layer having a first impurity; performing a first etch process that patterns the compensation layer and the mask layer to form a mask pattern; and performing a second etch process that etches the etch target layer exposed through openings of the mask pattern, wherein the second impurity comprises hydrogen.

2. The method of claim 1, wherein, The etch target layer is formed of an oxide.

3. The method of claim 2, wherein, The etch target layer is formed of silicon oxide.

4. The method of claim 1, wherein, The first impurity is carbon.

5. The method of claim 1, wherein, The mask layer is formed of amorphous carbon.

6. The method of claim 1, wherein, The mask layer is formed at a temperature higher than a reference temperature at which the mask layer is normally formed.

7. The method of claim 1, wherein, The compensation layer is formed as a layer having the second impurity.

8. The method of claim 1, wherein, The compensation layer is formed as a layer having a high density of the second impurity.

9. The method of claim 1, wherein, The mask layer and the compensation layer are formed by using an in-situ method in the same chamber.

10. The method of claim 1, wherein, The mask layer and the compensation layer are formed by using an ex-situ method in different chambers.

11. The method of claim 1, further comprising the step of: Before performing the first etch process, a barrier layer and a photoresist pattern are sequentially formed on the compensation layer.

12. The method of claim 11, wherein, The photoresist pattern includes openings that expose a portion of the barrier layer, and wherein the openings have a circular shape or a polygonal shape.

13. The method of claim 1, wherein, The second etch process is performed by using a dry etch process using plasma.

14. The method of claim 1, wherein, The second etch process is performed by using an etch gas having a higher etch selectivity to the etch target layer than the mask pattern.

15. The method of claim 14, wherein, The etch gas comprises fluorine gas or a fluorine-containing gas.

16. The method of claim 14, wherein, The etch gas is CF4 or CHF3 gas.

17. A method of fabricating a memory device, the method comprising the steps of: alternately forming a plurality of mask layers and a plurality of compensation layers on an etch target layer, the plurality of compensation layers being chemically bonded to the mask layers and comprising hydrogen; forming a mask pattern having openings that expose a portion of the etch target layer by patterning the mask layers and the compensation layers; and performing an etch process that forms a contact hole in the etch target layer by removing the portion of the etch target layer exposed through the openings.

18. The method of claim 17, wherein, The plurality of mask layers are formed of carbon.

19. The method of claim 17, wherein, The plurality of compensation layers are formed of a high density of hydrogen.

20. The method of claim 17, wherein, The etch process is performed by using fluorine gas or a fluorine-containing etch gas.

21. The method of claim 17, further comprising the step of: After forming the contact hole, the mask pattern is removed; a conductive layer is formed on the entire structure including the contact hole; and a polishing process is performed to expose a top portion of the etch target layer.

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