Semiconductor structure manufacturing method and semiconductor structure
By forming and etching the dielectric layer in the opening of the conductive layer, a larger size air gap is formed, the problem of increasing parasitic capacitance between adjacent conductive structures is solved, the capacitance resistance delay is reduced, and the performance of the semiconductor structure is improved.
Patent Information
- Application Number
- CN202211350754.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-10-31
- Publication Date
- 2025-09-05
- Estimated Expiration
- 2042-10-31
AI Technical Summary
In the prior art, the increase in parasitic capacitance between adjacent conductive structures results in an increase in capacitance resistance delay, affecting the overall performance of semiconductor devices.
A first dielectric layer is formed in the opening of the conductive layer, and a larger size air gap is formed by etching to reduce parasitic capacitance.
By forming a larger size air gap, the capacitance resistance delay of the semiconductor structure is effectively reduced and the performance of the semiconductor structure is improved.
Smart Images
Figure CN115565946B_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor manufacturing, and in particular to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Art
[0002] With the advancement of semiconductor manufacturing technology, semiconductors are moving towards higher integration to achieve greater data storage capacity, faster computing speeds, and more functionality. This has increased the density of semiconductor devices, but at the same time, has reduced the size and spacing between components within the devices, leading to other problems. For example, for any two adjacent conductive structures, reducing the distance between them will increase parasitic capacitance. This increased parasitic capacitance will lead to increased power consumption and capacitance-resistance delay (RC delay), negatively impacting the overall performance of the semiconductor device.
[0003] Therefore, how to reduce the capacitance and resistance delay of the conductive structure has become one of the research hotspots for those skilled in the art. Summary of the Invention
[0004] The embodiments of the present disclosure provide a method for manufacturing a semiconductor structure and a semiconductor structure, which are at least beneficial for increasing the size of the formed air gap, thereby reducing the capacitance and resistance delay of the formed semiconductor structure.
[0005] According to some embodiments of the present disclosure, on one hand, an embodiment of the present application provides a method for manufacturing a semiconductor structure, comprising: providing a substrate and a conductive layer located on the substrate, wherein the conductive layer has a first opening penetrating the conductive layer; forming a first dielectric layer, wherein the first dielectric layer covers the bottom and side surfaces of the first opening and is also located on the top surface of the conductive layer, wherein the first dielectric layer located in the first opening forms a second initial opening, and the width of the top of the second initial opening is smaller than the width of the middle of the second initial opening; etching to thin the first dielectric layer located in the first opening, wherein the remaining first dielectric layer located in the first opening forms a second opening, and the width of the top of the second opening is smaller than the width of the middle of the second opening; forming a second dielectric layer, wherein the second dielectric layer covers the remaining first dielectric layer and also blocks the top of the second opening, and the second dielectric layer located in the second opening and the second dielectric layer located at the top of the second opening form an air gap.
[0006] In some embodiments, before etching to thin the first dielectric layer located in the first opening, the method further includes: forming a sacrificial layer on the surface of the first dielectric layer, wherein the sacrificial layer located on the top surface of the conductive layer has a first thickness, the sacrificial layer located on the side of the second initial opening has a second thickness, and the sacrificial layer located at the bottom of the second initial opening has a third thickness, the first thickness is greater than the second thickness, and the first thickness is also greater than the third thickness; before etching to thin the first dielectric layer located in the first opening, the sacrificial layer is further etched.
[0007] In some embodiments, the step of etching to thin the first dielectric layer in the first opening further includes: stopping etching the first dielectric layer in the first opening in response to the sacrificial layer on the top surface of the conductive layer being completely etched away.
[0008] In some embodiments, the process of forming the sacrificial layer includes physical vapor deposition or chemical vapor deposition.
[0009] In some embodiments, the material of the sacrificial layer includes Ti or TiN.
[0010] In some embodiments, in the same process step, a wet etching process is used to etch the sacrificial layer and the first dielectric layer located in the first opening.
[0011] In some embodiments, before etching to thin the first dielectric layer within the first opening, the first dielectric layer formed on the top surface of the conductive layer has a fourth thickness, the first dielectric layer formed on the top of the first opening has a fifth thickness, the first dielectric layer formed in the middle of the first opening has a sixth thickness, and the first dielectric layer formed on the bottom surface of the first opening has a seventh thickness, wherein the fifth thickness is greater than the fourth thickness, the fifth thickness is greater than the sixth thickness, and the fifth thickness is greater than the seventh thickness.
[0012] In some embodiments, after etching to thin the first dielectric layer within the first opening, the first dielectric layer on the side surfaces of the first opening is thinned, and the first dielectric layer on the bottom surface of the first opening is removed.
[0013] In some embodiments, a bottom surface of the second opening is formed to be lower than a bottom surface of the conductive layer.
[0014] In some embodiments, a process for forming the first dielectric layer is the same as a process for forming the second dielectric layer.
[0015] In some embodiments, a bottom of the air gap is formed lower than a bottom surface of the conductive layer, and a top of the air gap is formed higher than a top surface of the conductive layer.
[0016] According to some embodiments of the present disclosure, on the other hand, the embodiments of the present application further provide a semiconductor structure, including: a substrate; a conductive layer, the metal layer is located on the substrate, and the conductive layer has a first opening passing through the conductive layer; a first dielectric layer, the first dielectric layer covers the side surfaces of the first opening and is also located on the top surface of the conductive layer; a second dielectric layer, the second dielectric layer covers the first dielectric layer and the top surface of the substrate, and the second dielectric layer also blocks the top of the first opening, the second dielectric layer located in the first opening and the second dielectric layer located on the top of the first opening form an air gap, wherein the bottom of the air gap is lower than the bottom surface of the conductive layer.
[0017] In some embodiments, a top of the air gap is higher than a top surface of the conductive layer.
[0018] In some embodiments, the base includes a substrate and a third dielectric layer, the third dielectric layer is located between the conductive layer and the substrate, wherein a top surface of a portion of the third dielectric layer facing the bottom of the first opening is lower than a bottom surface of the conductive layer.
[0019] In some embodiments, the material of the first dielectric layer is the same as the material of the second dielectric layer.
[0020] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:
[0021] The present invention provides a method for manufacturing a semiconductor structure, wherein a first dielectric layer is formed in a first opening penetrating a conductive layer, the first dielectric layer covering the bottom and side surfaces of the first opening, and the first dielectric layer encloses a second initial opening, wherein the width of the top of the second initial opening is less than the width of the middle of the second initial opening, thereby providing a basis for quickly blocking the second opening in the subsequent formation of an air gap. The first dielectric layer is also thinned by etching, and the remaining first dielectric layer located in the first opening encloses a second opening, wherein the width of the top of the second opening is less than the width of the middle of the second opening, thereby providing a basis for subsequently forming an air gap with a larger width. In addition, a second dielectric layer is formed on the thinned first dielectric layer, and the second dielectric layer can block the top of the second opening, so that the second dielectric layer located in the second opening and the second dielectric layer located at the top of the second opening can enclose an air gap. With this arrangement, the air gap formed in the present invention has a larger width, which is beneficial for reducing the capacitance and resistance delay of the formed semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present application or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0023] Figures 1 to 5 A schematic structural diagram corresponding to each step of a method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure;
[0024] Figure 6 A schematic structural diagram of a semiconductor structure provided in another embodiment of the present disclosure. DETAILED DESCRIPTION
[0025] As known from the background art, there is currently a problem that the parasitic capacitance between adjacent conductive structures increases, resulting in an increase in capacitance, resistance and delay.
[0026] The magnitude of parasitic capacitance is related to the dielectric constant of the associated structure. To reduce the parasitic capacitance between adjacent conductive structures, the dielectric constant of the insulating layer disposed between the adjacent conductive structures can be reduced. Currently, the insulating layer formed has an air gap, and the relative dielectric constant of the insulating layer with an air gap is relatively small. However, the size of the air gap within the insulating layer produced by the current manufacturing method is relatively small, making the ability to reduce RC delay by providing an air gap ineffective. To this end, there is an urgent need to provide a new manufacturing method to form an air gap with a larger size, thereby effectively reducing RC delay.
[0027] The present disclosure provides a method for manufacturing a semiconductor structure, wherein a first dielectric layer is formed in a first opening within a conductive layer, the first opening penetrating the conductive layer. The first dielectric layer covers the top surface of the conductive layer and the bottom and side surfaces of the first opening. The first dielectric layer within the first opening forms a second initial opening, the width of the top of the second initial opening being less than the width of the middle of the second initial opening, thereby facilitating subsequent rapid sealing of the top of the second opening. The first dielectric layer within the first opening is etched to reduce the thickness of the first dielectric layer within the first opening. After the thinning, the remaining first dielectric layer within the first opening forms a second opening, the width of the top of the second opening being less than the width of the middle of the second opening, thereby facilitating subsequent rapid sealing of the top of the second opening. A second dielectric layer is formed on the thinned first dielectric layer, the second dielectric layer sealing the top of the second opening, thereby forming an air gap between the second dielectric layer within the second opening and the second dielectric layer at the top of the second opening. Thus, the formed air gap is larger in size, which is beneficial for improving the performance of the semiconductor structure.
[0028] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to facilitate a better understanding of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented.
[0029] Figures 1 to 5 A schematic structural diagram corresponding to each step of a method for manufacturing a semiconductor structure provided in one embodiment of the present disclosure.
[0030] refer to Figure 1 , providing a substrate 101 and a conductive layer 102 located on the substrate 101 , wherein the conductive layer 102 has a first opening 103 penetrating the conductive layer 102 .
[0031] In some embodiments, the base 101 may include a substrate 104 and a third dielectric layer 105, wherein the third dielectric layer 105 is located between the conductive layer 102 and the substrate 104. It is understood that in some embodiments, during the process of etching the conductive layer 102 to form the first opening 103, over-etching may be performed, that is, the third dielectric layer 105 may be partially etched so that the top surface of the third dielectric layer 105 at the bottom of the first opening 103 is lower than the bottom surface of the conductive layer 102.
[0032] The substrate 104 may be made of at least one of silicon, germanium, silicon germanium, or silicon carbide. In other embodiments, the substrate 104 may also be silicon-on-insulator (SOI) or germanium-on-insulator (GOI).
[0033] The material of the third dielectric layer 105 can be any one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxynitride (SiON), or silicon carboxynitride (SICON).
[0034] The conductive layer 102 may include a plurality of stacked conductive layers 102 . The first opening 103 penetrating the conductive layer 102 divides the conductive layer 102 into two parts. The two parts respectively constitute two conductive structures. Parasitic capacitance can be generated between the two conductive structures.
[0035] In some embodiments, the conductive layer 102 may include a first conductive layer 106, a second conductive layer 107, and a third conductive layer 108 stacked in sequence, wherein the first conductive layer 106 is located between the third dielectric layer 105 and the second conductive layer 107, and the second conductive layer 107 may be located between the first conductive layer 106 and the third conductive layer 108.
[0036] The first conductive layer 106 may be any one or more conductive materials such as titanium, titanium nitride, tantalum, or tantalum nitride. The second conductive layer 107 may be any one or more conductive materials such as copper, tungsten, aluminum, titanium, molybdenum, cobalt, titanium nitride, tantalum, or tantalum nitride. The third conductive layer 108 may be any one or more conductive materials such as titanium nitride, tantalum, or tantalum nitride. In some embodiments, the material of the first conductive layer 106 may be different from the material of the second conductive layer 107. For example, the material of the first conductive layer 106 may be titanium nitride, and the material of the second conductive layer 107 may be aluminum.
[0037] In some embodiments, the material of the second conductive layer 107 may be different from the material of the third conductive layer 108 . For example, the material of the second conductive layer 107 may be aluminum, and the material of the third conductive layer 108 may be titanium nitride.
[0038] In some embodiments, the material of the first conductive layer 106 can be the same as the material of the third conductive layer 108. For example, the material of the first conductive layer 106 can be titanium, and the material of the third conductive layer 108 can be titanium. In other embodiments, the material of the first conductive layer 106 can also be different from the material of the third conductive layer 108. For example, the material of the first conductive layer 106 can be titanium, and the material of the third conductive layer 108 can be titanium nitride.
[0039] In some embodiments, the first conductive layer 106 and the third conductive layer 108 may serve as diffusion barriers for the second conductive layer 107. It is understood that in other embodiments, the conductive layer 102 may also be a single-layer structure or a double-layer structure.
[0040] The width of the first opening 103 may be 100 nm to 500 nm, for example, 100 nm, 300 nm, or 500 nm, etc. The embodiment of the present disclosure does not impose any specific limitation on the width of the first opening 103 .
[0041] refer to Figure 2 , forming a first dielectric layer 109, the first dielectric layer 109 can cover the first opening 103 (refer to Figure 1 ), and may also be located on the top surface of the conductive layer 102, wherein the first dielectric layer 109 located in the first opening 103 surrounds the second initial opening 110, and the width of the top of the second initial opening 110 (the width of the narrowest part of the top of the second initial opening 110 is used as the width of the top) may be smaller than the width of the middle part of the second initial opening 110.
[0042] For example, the first dielectric layer 109 may include a portion formed on the top surface of the conductive layer 102, i.e., a portion located on the top surface of the third conductive layer 108, a portion formed on the sidewall of the conductive layer 102 on the side of the first opening 103, and a portion formed on the top surface of the third dielectric layer 105 on the bottom surface of the first opening 103.
[0043] The first dielectric layer 109 formed on the top of the conductive layer 102 may have a fourth thickness L4, and the first dielectric layer 109 formed on the top of the first opening 103 may have a fifth thickness L5 (the thickness of the first dielectric layer 109 at the narrowest point at the top of the second initial opening 110 is defined as the fifth thickness L5). The top of the first opening 103 may include the portion of the first opening 103 located on the side of the third conductive layer 108 and the portion of the first opening 103 located on the side of the second conductive layer 107 adjacent to the third conductive layer 108. The fifth thickness L5 may be greater than the fourth thickness L4. The first dielectric layer 109 formed in the middle of the first opening 103 may have a sixth thickness L6. The middle of the first opening 103 may include the portion of the first opening 103 located on the side of the second conductive layer 107. The fifth thickness L5 may be greater than the sixth thickness L6. With this configuration, the second initial opening 110, enclosed by the first dielectric layer 109, is narrow at the top and wide at the bottom, providing a foundation for forming a larger air gap in subsequent steps.
[0044] In some embodiments, the first dielectric layer 109 formed on the bottom surface of the first opening 103 may have a seventh thickness L7, and the fifth thickness L5 is greater than the seventh thickness L7. In this way, the first dielectric layer 109 formed on the bottom surface of the first opening 103 is thinner, which is beneficial for completely removing the first dielectric layer 109 located on the bottom surface of the first opening 103 in the subsequent step of thinning the first dielectric layer 109, so that the air gap formed in the subsequent step has a larger depth.
[0045] In some embodiments, the seventh thickness L7 may also be smaller than the sixth thickness L6. Thus, in the subsequent step of thinning the first dielectric layer 109, after completely removing the first dielectric layer 109 at the bottom of the first opening 103, the side of the first opening 103 still has a partial thickness of the first dielectric layer 109 to form an air gap.
[0046] For example, the sixth thickness L6 may be in the range of 30 nm to 100 nm; for example, the sixth thickness L6 may be 30 nm, 50 nm, or 100 nm, etc. For example, the seventh thickness L7 may be in the range of 20 nm to 60 nm, for example, the seventh thickness L7 may be 20 nm, 40 nm, or 60 nm, etc.
[0047] In some embodiments, the formed second initial opening 110 may have side surfaces and a bottom surface. In the first dielectric layer 109 surrounding the second initial opening 110, the thickness of the first dielectric layer 109 located at the bottom of the sidewall of the first opening 103 may be less than the sixth thickness L3. The bottom of the sidewall of the first opening 103 may be a portion of the first opening 103 region located on the sidewall of the first conductive layer 106 and a portion of the first opening 103 region located on the sidewall of the second conductive layer 107 adjacent to the first conductive layer 106.
[0048] In some embodiments, the first dielectric layer 109 can be formed by physical vapor deposition or chemical vapor deposition. During the formation of the first dielectric layer 109, relevant process parameters can be controlled to control the thickness of the generated first dielectric layer 109, so that the thickness of the first dielectric layer 109 formed on the top surface of the third conductive layer 108 is greater than the thickness of the first dielectric layer 109 formed on the sidewalls of the conductive layer 102 on the side of the first opening 103, the thickness of the first dielectric layer 109 formed on the sidewalls of the conductive layer 102 on the side of the first opening 103 is greater than the thickness of the first dielectric layer 109 formed on the top surface of the third dielectric layer 105, and the thickness of the first dielectric layer 109 formed on the top of the first opening 103 is greater than the thickness of the first dielectric layer 109 formed in the middle of the first opening 103, that is, the second initial opening 110 is narrow at the top and wide at the bottom.
[0049] For example, the source material for forming the first dielectric layer 109 may include SiH 4 . The reaction formula for forming the first dielectric layer 109 using SiH 4 as the source material and physical vapor deposition or chemical vapor deposition is:
[0050] SiH4+2O2→SiO2+2H2O (1)
[0051] The material of the first dielectric layer 109 can be silicon oxide.
[0052] In some embodiments, SiH4 is used as a source material and the first dielectric layer 109 is formed by chemical vapor deposition or physical vapor deposition at a rate greater than or equal to 10 nm / s. For example, the rate of forming the first dielectric layer 109 can be 10 nm / s, 12 nm / s, or 15 nm / s. In this way, the rate of forming the first dielectric layer 109 is relatively fast, which can reduce process time.
[0053] In other examples, the first dielectric layer 109 may be formed by atomic vapor deposition or plasma vapor deposition.
[0054] In other embodiments, the material of the first dielectric layer 109 may also be any one or more of silicon nitride or silicon oxynitride.
[0055] In some embodiments, the material of the first dielectric layer 109 can be the same as the material of the third dielectric layer 105. For example, the material of the first dielectric layer 109 can be silicon oxide, and the material of the third dielectric layer 105 can also be silicon oxide. In this way, in the subsequent step of etching the first dielectric layer 109 located in the first opening 103, the portion of the third dielectric layer 105 located at the bottom surface of the first opening 103 is also etched, so that the bottom surface of the formed second opening 111 is lower than the bottom surface of the conductive layer 102.
[0056] Subsequent steps may further include etching to thin the first dielectric layer 109 within the first opening 103 , and before etching to thin the first dielectric layer 109 within the first opening 103 , a sacrificial layer may be formed on the first dielectric layer 109 .
[0057] refer to Figure 3 , etching to thin the first opening 103 (reference Figure 1 ), before etching the first dielectric layer 109 in the first opening 103, the method may further include: forming a sacrificial layer 112 on the surface of the first dielectric layer 109. In this way, before etching to thin the first dielectric layer 109 located in the first opening 103, it is necessary to first etch and remove a portion of the sacrificial layer 112. Therefore, the sacrificial layer 112 can be formed by using a material different from the material of the first dielectric layer 109. Therefore, during the etching process, the etching rate of the sacrificial layer 112 is different from the etching rate of the first dielectric layer 109, so that it is possible to confirm whether the etching object is the sacrificial layer 112 or the first dielectric layer 109 by monitoring the etching rate.
[0058] The sacrificial layer 112 on the top surface of the conductive layer 102 may have a first thickness L1 and be located at the second initial opening 110 (refer to Figure 2) The sacrificial layer 112 on the side may have a second thickness L2, the sacrificial layer 112 at the bottom of the second initial opening 110 may have a third thickness L3, the first thickness L1 may be greater than the second thickness L2, and the first thickness L1 may also be greater than the third thickness L3. In this way, during the etching process, after the sacrificial layer 112 located in the first opening 103 is completely removed, the first dielectric layer 109 located in the first opening 103 is exposed, and the remaining sacrificial layer 112 located on the top surface of the conductive layer 102 still has a partial thickness. During the process of continuing to etch the remaining sacrificial layer 112 located on the top surface of the conductive layer 102, the first dielectric layer 109 located in the first opening 103 begins to be etched. By monitoring the etching status of the remaining sacrificial layer 112 located on the top surface of the conductive layer 102, the etching status of the first dielectric layer 109 located in the first opening 103 can be reflected. On the other hand, after the remaining sacrificial layer 112 located on the top surface of the conductive layer 102 is completely etched, before the first dielectric layer 109 on the top surface of the conductive layer 102 is etched, because the etching rate of the sacrificial layer 112 is different from the etching rate of the first dielectric layer 109, by monitoring the etching rate, it is determined whether the etching target is the sacrificial layer or the first dielectric layer 109, and further, whether to stop etching.
[0059] In order to make the first thickness L1 greater than the second thickness L2, and the first thickness L1 greater than the third thickness L3, in some embodiments, the sacrificial layer 112 can be formed by physical vapor deposition or chemical vapor deposition. At the same time, relevant process parameters can be controlled in the step of forming the sacrificial layer 112 to control the thickness of the formed sacrificial layer 112, so that the thickness of the sacrificial layer 112 located in different areas can be different.
[0060] In some embodiments, the material of the sacrificial layer 112 may include Ti or TiN.
[0061] refer to Figure 4 , etch to thin the first opening 103 (refer to Figure 1 ), wherein the remaining first dielectric layer 109 located in the first opening 103 can surround a second opening 111, and the width of the top of the second opening 111 can be smaller than the width of the middle of the second opening 111. In this way, by thinning the thickness of the first dielectric layer 109 in the first opening 103, the second opening 111 formed has a larger width, providing a basis for forming a larger air gap in the second opening 111 in the subsequent step.
[0062] For example, the top of the second opening 111 may include a region of the partial second opening 111 located on the side of the third conductive layer 108 and a region of the partial second opening 111 located on the side of the partial second conductive layer 107 adjacent to the third conductive layer 108. The middle of the second opening 111 may include a region of the partial second opening 111 located on the side of the second conductive layer 107. That is, the shape of the second opening 111 can be narrow at the top and wide at the bottom, providing a basis for quickly sealing the top of the second opening 111 in the subsequent steps of forming an air gap.
[0063] In some embodiments, after etching to thin the first dielectric layer 109 within the first opening 103 , the first dielectric layer 109 on the side of the first opening 103 may be thinned, and the first dielectric layer 109 on the bottom surface of the first opening 103 may be removed.
[0064] After etching to thin the first dielectric layer 109 within the first opening 103 , the width L9 of the remaining first dielectric layer 109 in the middle of the first opening 103 may be less than 30 nm. For example, the width L9 of the remaining first dielectric layer 109 may be 20 nm, 25 nm, or 28 nm.
[0065] In some embodiments, a sacrificial layer 112 may be formed on the surface of the first dielectric layer 109. The step of etching to thin the first dielectric layer 109 within the first opening 103 may further include: in response to the sacrificial layer 112 located on the top surface of the conductive layer 102 (i.e., the sacrificial layer 112 on the top surface of the first dielectric layer 109) being completely etched away, stopping the etching of the first dielectric layer 109 within the first opening 103. In this way, by controlling the thickness of the formed sacrificial layer 112 and the etching rates of the sacrificial layer 112 and the first dielectric layer 109, the thickness of the remaining first dielectric layer 109 can be precisely controlled.
[0066] In some embodiments, in the same process step, a wet etching process can be used to etch the sacrificial layer 112 and the first dielectric layer 109 located in the first opening 103, wherein the etching rate of the etching solution on the first dielectric layer 109 and the etching rate of the sacrificial layer 112 can be different. Therefore, by monitoring the wet etching rate, it can be confirmed whether the etching object is the first dielectric layer 109 or the sacrificial layer 112, and thus determine whether to stop etching.
[0067] It can be understood that, in some embodiments, the fifth thickness L5 may be greater than the sixth thickness L6. During the etching process, the etching rate of the etching solution on the first dielectric layer 109 located in different areas is the same. Therefore, after etching, in the remaining first dielectric layer 109 located on the first opening 103, the thickness L8 of the first dielectric layer 109 located at the top of the first opening 103 is still greater than the thickness L9 of the first dielectric layer 109 located in the middle of the first opening 103, that is, the width of the top of the enclosed second opening 111 is smaller than the width of the middle.
[0068] In some embodiments, the etchant used in the wet etching process can be any one of a DHF (dilute hydrofluoric acid) etchant, an SPM etchant, an SC-1 etchant, and an SC-2 etchant. For example, when the etching rate of the etchant on the sacrificial layer 112 is lower than the etching rate on the first dielectric layer 109, the etching can be stopped when the first dielectric layer 109 on the top surface of the conductive layer 102 is exposed (i.e., the sacrificial layer 112 on the top surface of the first dielectric layer 109 is completely etched and removed); at this point, it can be determined that the first dielectric layer 109 located within the first opening 103 has been thinned.
[0069] In other embodiments, the etching rate of the etching solution used for the sacrificial layer 112 may also be greater than the etching rate of the first dielectric layer 109 .
[0070] In some embodiments, the material of the first dielectric layer 109 can be the same as the material of the third dielectric layer 105. The process of etching to thin the first dielectric layer 109 located within the first opening 103 may further include etching to thin the thickness of the portion of the third dielectric layer 105 located directly below the first opening 103. That is, the bottom surface of the formed second opening 111 is lower than the bottom surface of the conductive layer 102, providing a basis for the subsequent formation of a deeper air gap.
[0071] It is also understandable that, in some other examples, after etching to thin the first dielectric layer 109 within the first opening 103 , a partial thickness of the first dielectric layer 109 may still exist at the bottom surface of the first opening 103 .
[0072] refer to Figure 5 , forming a second dielectric layer 113, the second dielectric layer 113 covers the remaining first dielectric layer 109 and also blocks the second opening 111 (refer to Figure 4 ), the second dielectric layer 113 located in the second opening 111 and the second dielectric layer 113 located on the top of the second opening 111 form an air gap 114. In this way, the second dielectric layer 113 located on the top surface of the conductive layer 102 can extend and form on the top of the second opening 111 to block the top of the second opening 111 to form a closed space, namely the air gap 114.
[0073] Among them, the minimum thickness L10 of the second dielectric layer 113 formed on the top of the second opening 111 can be greater than the thickness L11 of the second dielectric layer 113 formed in the middle of the second opening 111. This is conducive to forming an air gap 114 with better sealing performance at the top, and the formed air gap 114 has a larger width.
[0074] In some embodiments, a thickness L11 of the second dielectric layer 113 in the middle portion of the second opening 111 is greater than a thickness L12 of the second dielectric layer 113 formed on the bottom surface of the second opening 111. The second dielectric layer 113 may be formed by physical vapor deposition, chemical vapor deposition, atomic vapor deposition, or plasma vapor deposition, and the source material used to form the second dielectric layer 113 may be SiH 4 , but is not limited thereto.
[0075] In some embodiments, the process for forming the first dielectric layer 109 can be the same as the process for forming the second dielectric layer 113, and the source material liquid used to form the first dielectric layer 109 can be the same as the source material used to form the second dielectric layer 113. In this way, the adsorption force between the first dielectric layer 109 and the second dielectric layer 113 is better, and the formed air gap 114 has better sealing performance.
[0076] In some embodiments, SiH4 is used as a source material and chemical vapor deposition or physical vapor deposition is used to form the second dielectric layer 113 at a rate greater than or equal to 10 nm / s. For example, the rate of forming the second dielectric layer 113 can be 10 nm / s, 12 nm / s, or 15 nm / s. Thus, the thickness of the second dielectric layer 113 deposited on the top surface of the third conductive layer 108 is greater than the thickness of the second dielectric layer 113 deposited within the second opening 111. Furthermore, due to the higher rate of forming the second dielectric layer 113, the second dielectric layer 113 deposited on the top of the second opening 111 can quickly block the top of the second opening 111, thereby reducing the amount of second dielectric layer 113 deposited within the second opening 111 and resulting in a larger air gap 114.
[0077] In some embodiments, the bottom of the formed air gap 114 can be lower than the bottom surface of the conductive layer 102, and the top of the formed air gap 114 can be higher than the top surface of the conductive layer 102. In this way, the height of the formed air gap 114 is higher, which is beneficial to reducing the capacitance and resistance delay of the formed semiconductor structure.
[0078] It can be understood that, in the process of forming the second dielectric layer 113, since no film layer is formed on the top of the second opening 111, the second dielectric layer 113 can first be deposited on the top of the first dielectric layer 109 located on the side of the second opening 111, on the top surface of the conductive layer 102, and in the second opening 111. After the second dielectric layer 113 formed on the conductive layer 102 has a partial thickness, the portion of the second dielectric layer 113 begins to extend and deposit toward the top of the second opening 111, so that the top of the formed air gap 114 can extend out of the top of the second opening 111, and the second dielectric layer 113 deposited on the top of the second opening 111 may have a portion of the second dielectric layer 113 adjacent to the top of the second opening 111. 13 falls into the second opening 111, so that the top of the formed air gap 114 can be higher than the top surface of the conductive layer 102; because the bottom surface of the second opening 111 can be lower than the bottom surface of the conductive layer 102, and in the process of forming the second dielectric layer 113, the second dielectric layer 113 formed on the top of the second opening 111 can quickly block the top of the second opening 111, so that after the second dielectric layer 113 formed on the top of the second opening 111 blocks the second opening 111, the second dielectric layer 113 located in the second opening 111 stops depositing, thereby resulting in less second dielectric layer 113 deposited in the second opening 111, so that the bottom of the formed air gap 114 can be lower than the top of the conductive layer 102.
[0079] In some embodiments, the width d1 of the formed air gap 114 can be less than 500 nm. For example, the width d1 of the air gap 114 can be 200 nm, 300 nm, or 400 nm. It can be understood that the width of the formed air gap 114 is related to the width of the first opening 103, the thickness of the first dielectric layer 109, and the thickness of the second dielectric layer 113.
[0080] In some embodiments, the height h1 of the formed air gap 114 may be in a range of 100 nm to 900 nm. For example, the height h1 of the air gap 114 may be 100 nm, 500 nm, or 900 nm.
[0081] The manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure forms a first dielectric layer 109 in the first opening 103 penetrating the conductive layer 102. The first dielectric layer 109 covers the bottom and side surfaces of the first opening 103, and the first dielectric layer 109 surrounds the second initial opening 110. The first dielectric layer 109 formed at the top of the first opening 103 can have a fifth thickness L5, and the first dielectric layer 109 formed in the middle of the first opening 103 can have a sixth thickness L6. The fifth thickness L5 is greater than the sixth thickness L6. This provides a basis for quickly blocking the second opening 111 in the subsequent process of forming the air gap 114. The first dielectric layer 109 is etched and thinned so that the first dielectric layer 109 at the bottom surface of the first opening 103 is removed. , and thinning the thickness of the first dielectric layer 109 located on the side of the first opening 103. In this way, the air gap 114 formed subsequently can have a larger width and depth. After etching to thin the first dielectric layer 109, the thickness of the first dielectric layer 109 located at the top of the first opening 103 is still greater than the thickness of the first dielectric layer 109 located in the middle of the first opening 103, which is conducive to quickly blocking the top of the second opening 111 during the subsequent formation of the air gap 114. In addition, a second dielectric layer 113 is also formed on the thinned first dielectric layer 109. The second dielectric layer 113 can block the top of the second opening 111, so that the second dielectric layer 113 located in the second opening 111 and the second dielectric layer 113 located at the top of the second opening 111 can enclose the air gap 114. With this arrangement, the air gap 114 formed in the embodiment of the present disclosure has a larger width and depth, which is conducive to reducing the capacitance and resistance delay of the formed semiconductor structure.
[0082] Accordingly, another embodiment of the present disclosure further provides a semiconductor structure, which is manufactured using the semiconductor structure manufacturing method provided by the aforementioned embodiment. The semiconductor structure provided by another embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. For parts that are identical or corresponding to the aforementioned embodiment, reference can be made to the corresponding description of the aforementioned embodiment and will not be repeated in detail below. Figure 6 A schematic structural diagram of a semiconductor structure provided in another embodiment of the present disclosure.
[0083] refer to Figure 6The semiconductor structure includes: a substrate 101; a conductive layer 102, the conductive layer 102 being located on the substrate 101 and having a first opening 103 penetrating the conductive layer 102; a first dielectric layer 109, the first dielectric layer 109 covering the side surfaces of the first opening 103 and also being located on the top surface of the conductive layer 102; and a second dielectric layer 113, the second dielectric layer 113 covering the first dielectric layer 109 and the top surface of the substrate 101 and further blocking the top of the first opening 103. The second dielectric layer 113 located within the first opening 103 and the second dielectric layer 113 located on top of the first opening 103 form an air gap 114, wherein the bottom of the air gap 114 is lower than the bottom surface of the conductive layer 102.
[0084] The base 101 may include a substrate 104 and a third dielectric layer 105, wherein the third dielectric layer 105 is located between the conductive layer 102 and the substrate 104. In some embodiments, the top surface of the portion of the third dielectric layer 105 facing the bottom of the first opening 103 may be lower than the bottom surface of the conductive layer 102.
[0085] The conductive layer 102 may include a plurality of stacked conductive layers 102 . The first opening 103 penetrating the conductive layer 102 divides the conductive layer 102 into two parts, and the two parts respectively constitute two conductive structures.
[0086] In some embodiments, the conductive layer 102 may include a stacked first conductive layer 106 , a second conductive layer 107 , and a third conductive layer 108 , wherein the first conductive layer 106 is located between the third dielectric layer 105 and the second conductive layer 107 , and the second conductive layer 107 may be located between the first conductive layer 106 and the third conductive layer 108 .
[0087] In some embodiments, the thickness L4 of the first dielectric layer 109 located on the top surface of the conductive layer 102 may be greater than the thickness L8 of the first dielectric layer 109 located at the top of the first opening 103, and may also be greater than the thickness L9 of the first dielectric layer 109 located in the middle of the first opening 103. The top of the first opening 103 may include a portion of the first opening 103 located on the side of the third conductive layer 108 and a portion of the first opening 103 located on the side of the second conductive layer 107 adjacent to the third conductive layer 108. The middle of the first opening 103 may be a portion of the first opening 103 located on the side of the second conductive layer 107.
[0088] The thickness L9 of the first dielectric layer 109 located in the middle of the first opening 103 may be less than 30 nm. For example, the width L9 of the remaining first dielectric layer 109 may be 20 nm, 25 nm, or 28 nm.
[0089] In some embodiments, the minimum thickness L10 of the second dielectric layer 113 located at the top of the first opening 103 may be greater than the thickness L11 of the second dielectric layer 113 located in the middle of the first opening 103, and the thickness L11 of the second dielectric layer 113 in the middle of the first opening 103 is greater than the thickness L12 of the second dielectric layer 113 formed on the bottom surface of the first opening 103.
[0090] The material of the first dielectric layer 109 can be any one or more of SiO 2 , silicon nitride, or silicon oxynitride.
[0091] The material of the second dielectric layer 113 can be any one or more of SiO 2 , silicon nitride, or silicon oxynitride.
[0092] The material of the first dielectric layer 109 and the material of the second dielectric layer 113 can be the same. For example, the material of the first dielectric layer 109 and the material of the second dielectric layer 113 can both be SiO 2 .
[0093] The width d1 of the air gap 114 may be less than 500 nm. For example, the width d1 of the air gap 114 may be 200 nm, 300 nm, or 400 nm.
[0094] In some embodiments, the top of the air gap 114 may be higher than the top surface of the conductive layer 102 .
[0095] The height h1 of the air gap 114 may be in the range of 100 nm to 900 nm. For example, the depth h1 of the air gap 114 may be 100 nm, 500 nm, or 900 nm.
[0096] In the semiconductor structure provided by the embodiment of the present disclosure, the conductive layer 102 has a first opening 103 that penetrates the conductive layer 102, so that the conductive layer 102 is divided into two parts, and the two parts respectively constitute two conductive structures. To reduce the parasitic capacitance between the two conductive structures, the embodiment of the present disclosure is provided with a stacked first dielectric layer 109 and a second dielectric layer 113 within the first opening 103. The second dielectric layer 113 also blocks the top of the first opening 103, so that the second dielectric layer 113 located within the first opening 103 encloses an air gap 114, and the air gap 114 has a large width and depth. In this way, the parasitic capacitance between the two conductive structures can be effectively reduced, thereby reducing the capacitance and resistance delay of the semiconductor structure, which is beneficial to improving the performance of the semiconductor structure.
[0097] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present disclosure, and that in actual applications, various changes in form and detail may be made thereto without departing from the spirit and scope of the present disclosure. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be subject to the scope defined in the claims.
Claims
1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate and a conductive layer on the substrate, wherein the conductive layer has a first opening penetrating the conductive layer; forming a first dielectric layer, wherein the first dielectric layer covers the bottom and side surfaces of the first opening and is also located on the top surface of the conductive layer, wherein the first dielectric layer located within the first opening encloses a second initial opening, and the width of the top of the second initial opening is smaller than the width of the middle portion of the second initial opening; Etching to thin the first dielectric layer within the first opening, wherein the remaining first dielectric layer within the first opening forms a second opening, and a width of a top portion of the second opening is smaller than a width of a middle portion of the second opening; A second dielectric layer is formed, which covers the remaining first dielectric layer and blocks the top of the second opening. The second dielectric layer in the second opening and the second dielectric layer on the top of the second opening form an air gap.
2. The method for manufacturing a semiconductor structure according to claim 1, wherein: Before etching to thin the first dielectric layer located in the first opening, the method further includes: forming a sacrificial layer on the surface of the first dielectric layer, wherein the sacrificial layer located on the top surface of the conductive layer has a first thickness, the sacrificial layer located on the side of the second initial opening has a second thickness, and the sacrificial layer located at the bottom of the second initial opening has a third thickness, wherein the first thickness is greater than the second thickness, and the first thickness is further greater than the third thickness; Before etching to thin the first dielectric layer in the first opening, the sacrificial layer is further etched.
3. The method for manufacturing a semiconductor structure according to claim 2, wherein: The step of etching to thin the first dielectric layer located in the first opening further includes: In response to the sacrificial layer on the top surface of the conductive layer being completely etched and removed, etching of the first dielectric layer in the first opening is stopped.
4. The method for manufacturing a semiconductor structure according to claim 2, wherein: The process of forming the sacrificial layer includes physical vapor deposition or chemical vapor deposition.
5. The method for manufacturing a semiconductor structure according to claim 2, wherein: The material of the sacrificial layer includes Ti or TiN.
6. The method for manufacturing a semiconductor structure according to claim 2, wherein: In the same process step, a wet etching process is used to etch the sacrificial layer and the first dielectric layer located in the first opening.
7. The method for manufacturing a semiconductor structure according to claim 1, wherein: Before etching to thin the first dielectric layer within the first opening, the first dielectric layer formed on the top surface of the conductive layer has a fourth thickness, the first dielectric layer formed at the top of the first opening has a fifth thickness, the first dielectric layer formed in the middle of the first opening has a sixth thickness, and the first dielectric layer formed on the bottom surface of the first opening has a seventh thickness, wherein the fifth thickness is greater than the fourth thickness, the fifth thickness is greater than the sixth thickness, and the fifth thickness is greater than the seventh thickness.
8. The method for manufacturing a semiconductor structure according to claim 1, wherein: After etching to thin the first dielectric layer in the first opening, the first dielectric layer on the side surface of the first opening is thinned, and the first dielectric layer on the bottom surface of the first opening is removed.
9. The method for manufacturing a semiconductor structure according to claim 1, wherein: The bottom surface of the formed second opening is lower than the bottom surface of the conductive layer.
10. The method for manufacturing a semiconductor structure according to claim 1, wherein: The process of forming the first dielectric layer is the same as the process of forming the second dielectric layer.
11. The method for manufacturing a semiconductor structure according to claim 1, wherein: The bottom of the formed air gap is lower than the bottom surface of the conductive layer, and the top of the formed air gap is higher than the top surface of the conductive layer.
Citation Information
Patent Citations
Interconnection line structure and forming method thereof
CN103077921A
Method of Preventing a Pattern Collapse
US20140252625A1