Super junction device and manufacturing method thereof

Abstract

The present invention discloses a superjunction device comprising: an N-type redundant epitaxial layer and an N-type buffer layer sequentially formed on an N-type semiconductor substrate; a trench-filled superjunction structure formed on the N-type buffer layer; a backside structure comprising a drain region and a patterned backside P-type impurity region; the N-type semiconductor substrate is removed in a backside thinning process, and the N-type redundant epitaxial layer is completely or partially removed in the backside thinning process; the resistivity of the N-type semiconductor substrate is 0.1 to 10 times that of the top epitaxial layer, the resistivity of the N-type redundant epitaxial layer is 0.1 to 10 times that of the N-type semiconductor substrate, and the resistivity of the N-type redundant epitaxial layer is lower than that of the N-type buffer layer. The present invention also discloses a method for manufacturing the superjunction device. The present invention eliminates the adverse effects of impurity diffusion from a high-concentration substrate, thereby enabling the superjunction structure to achieve an ultra-low specific on-resistance structure. It also ensures good ohmic contact on the backside, improving the device's body diode characteristics.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a super junction device; the present invention also relates to a method for manufacturing the super junction device. Background Art

[0002] A superjunction structure consists of alternating N-type and P-type columns, or PN columns. If a superjunction structure replaces the N-type drift region in a vertical double-diffused metal-oxide-semiconductor (VDMOS) transistor (VDMOS), it provides a conductive path in the on state (only the N-type column provides the path, not the P-type column) and withstands reverse bias voltage in the off state (both the PN columns bear the burden), thus forming a superjunction metal-oxide-semiconductor field-effect transistor (MOSFET). Superjunction MOSFETs can significantly reduce the on-resistance of the device by using a low-resistivity epitaxial layer, while maintaining the same reverse breakdown voltage as traditional VDMOS devices.

[0003] By forming trenches in the N-type epitaxial layer and filling the trenches with P-type epitaxial layers, alternating PN columns are formed. This is a superjunction manufacturing method that can be mass-produced.

[0004] If it is necessary to manufacture devices with higher reverse breakdown voltage or lower specific on-resistance, the PN column step size (pitch) must be smaller, or the PN depth of the device must be increased. When using a trench-filled P-type epitaxial process, these requirements will cause the following problems: the high aspect ratio of the P-type trench makes trench etching a problem, especially after etching, the etching residue at the bottom of the trench cannot be cleaned, causing device failure; second, the high aspect ratio of the P-type trench makes epitaxial filling of the device more difficult, resulting in epitaxial voids or excessively long epitaxial filling time, which increases manufacturing costs. Therefore, in these cases, one method is to divide the formation of the P-type column into multiple or two times, reducing the aspect ratio of each P-type column, making the trench etching, cleaning, and filling processes feasible and cost-effective.

[0005] Existing technical solutions all utilize a high-concentration substrate (e.g., a resistivity of 0.001-0.003 ohm.cm, or even a substrate with even lower resistivity to reduce Rdson). This is two orders of magnitude lower than the resistivity of the 0.5-5 ohm.cm N epitaxial layer deposited thereon. Consequently, during the process, outdiffusion of substrate impurities can affect device performance uniformity. To mitigate this outdiffusion, the high-concentration substrate must be protected from the backside with an oxide film and polysilicon film, increasing costs. Furthermore, because the wafer edge of the high-concentration substrate (assuming the backside is already protected) is exposed during processing, special management is required during cleaning and other processes. For example, the high-concentration substrate can be processed only before the cleaning solution is changed, reducing production efficiency, or the high-concentration substrate must be immediately changed after cleaning for use in other processes, further increasing costs.

[0006] Furthermore, because the PN contact surface of trench-filled superjunction MOSFETs is completely smooth, unlike multi-epitaxial superjunction MOSFETs, where the portion following the PN column is formed through ion implantation followed by annealing and diffusion, the ion concentration distribution is not completely uniform. Consequently, localized charge imbalances often exist at the PN contact interface. These localized charge imbalances improve the softness of the body diode's reverse recovery characteristics. Consequently, the body diode softness of existing trench-filled superjunction MOSFETs is not as good as that of multi-epitaxial devices. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide a superjunction device that eliminates the adverse effects of impurity diffusion from a high-concentration substrate on the superjunction structure, thereby enabling the superjunction structure to achieve an ultra-low specific on-resistance structure while also ensuring good ohmic contact on the back side and improving the characteristics of the device's body diode. To this end, the present invention also provides a method for manufacturing the superjunction device.

[0008] In order to solve the above technical problems, the present invention provides a super junction device comprising:

[0009] An N-type redundant epitaxial layer and an N-type buffer layer are sequentially formed on an N-type semiconductor substrate.

[0010] A superjunction structure is formed on the N-type buffer layer, and the superjunction structure is composed of P-type columns and N-type columns arranged alternately. The P-type columns are composed of a P-type semiconductor layer filled in a trench, and the trench is formed in the top epitaxial layer. The N-type columns are composed of the top epitaxial layer filled between the P-type columns.

[0011] The back structure of the super junction device includes a drain region and a patterned back P-type impurity region.

[0012] The drain region is formed by performing a full back surface N-type ion implantation after the back surface thinning process.

[0013] The back P-type impurity region is selected by a photolithography process and includes P-type impurities formed by back P-type ion implantation in the selected region.

[0014] The injection peak position of the back P-type ion implantation is greater than the injection peak position of the back N-type ion implantation; and there is a gap between the back P-type impurity region and the bottom surface of the P-type column.

[0015] The N-type semiconductor substrate is removed in a backside thinning process, the N-type redundant epitaxial layer is completely or partially removed in the backside thinning process, and the thickness of the N-type buffer layer is completely retained after the backside thinning process.

[0016] The resistivity of the N-type semiconductor substrate is 0.1 to 10 times that of the top epitaxial layer, so as to ensure that the diffusion of dopant impurities in the N-type semiconductor substrate does not affect the performance of the super junction structure.

[0017] The resistivity of the N-type redundant epitaxial layer is 0.1 to 10 times the resistivity of the N-type semiconductor substrate, and the resistivity of the N-type redundant epitaxial layer is lower than the resistivity of the N-type buffer layer. The N-type redundant epitaxial layer is used to ensure that the back thinning process can completely remove the N-type semiconductor substrate without affecting the N-type buffer layer and ensure that the drain region can reach the required doping concentration.

[0018] A further improvement is that the resistivity of the N-type buffer layer is 0.5 to 2 times the resistivity of the top epitaxial layer.

[0019] A further improvement is that the resistivity of the N-type buffer layer is equal to the resistivity of the top epitaxial layer.

[0020] A further improvement is that the resistivity of the N-type redundant epitaxial layer is less than 0.2 times the resistivity of the top epitaxial layer.

[0021] A further improvement is that the resistivity of the N-type redundant epitaxial layer is 0.1 times the resistivity of the top epitaxial layer.

[0022] A further improvement is that the impurities implanted into the back N-type ions include phosphorus or arsenic, and the implantation dose is 5E12cm -2 ~1E15cm -2 .

[0023] The impurities of the back P-type ion implantation include B or BF2, and the implantation dose is 1E11cm -2 ~5E12cm -2 , the injection energy is 50keV~400keV.

[0024] A further improvement is that the dimension of at least one direction of each selected region of the back P-type impurity region is greater than or equal to 5 microns; and the thickness of the photoresist in the photolithography process is greater than or equal to 4 microns.

[0025] A further improvement is that the back P-type impurity region has a P-type net doping, and the highest concentration of the P-type net doping in the back P-type impurity region is less than or equal to the lowest concentration of the P-type column.

[0026] A further improvement is that the back P-type impurity region has a P-type net doping, and the highest concentration of the P-type net doping in the back P-type impurity region is less than or equal to 1 / 2 of the lowest concentration of the P-type column.

[0027] A further improvement is that the back P-type impurity region has N-type net doping, and the concentration of the N-type net doping in the back P-type impurity region is 1 / 5 to 1 / 100 of the N-type impurity concentration when no P-type impurities are injected.

[0028] A further improvement is that the drain region and the back P-type impurity region are both subjected to laser annealing, and the depth range of the back P-type impurity region is less than or equal to the depth of the laser annealing.

[0029] A further improvement is that the area of ​​the back surface P-type impurity region is 5% to 30% of the area of ​​the entire drain region.

[0030] A further improvement is that the super junction structure is formed by stacking multiple layers of super junction substructures, and each layer of the super junction substructure is formed by alternating P-type sub-pillars and N-type sub-pillars of the corresponding layer. The P-type sub-pillars of each layer are stacked longitudinally to form the P-type columns, and the N-type sub-pillars of each layer are stacked longitudinally to form the N-type columns.

[0031] The number of layers of the super junction substructure included in the super junction structure is 2 or 3 or more.

[0032] The opening width of each of the P-type sub-columns is equal to the opening width of the N-type sub-columns in the same layer.

[0033] Alternatively, the opening width of each of the P-type sub-columns is not equal to the opening width of the N-type sub-columns in the same layer.

[0034] The charge balance structure in each layer of the superjunction substructure is set so that the deviation of the total amount of impurities of the P-type sub-column and the N-type sub-column is less than 5% of the total amount of impurities of any one of the P-type sub-column and the N-type sub-column.

[0035] The thickness of the N-type sub-columns in each layer above the second layer is set to ensure that the alignment mark and overlay precision mark at the bottom can be identified after the N-type top epitaxial sub-layer corresponding to the N-type sub-columns are deposited.

[0036] A further improvement is that the first layer of superjunction structure is located at the bottom, and the second layer of superjunction structure is superimposed on the first layer of superjunction structure.

[0037] In the second-layer super junction substructure, the top opening width of the second-layer P-type sub-pillar is larger than the bottom opening width, and the optimal charge balance is achieved between the second-layer P-type sub-pillar and the second-layer N-type sub-pillar at the bottom of the second-layer P-type sub-pillar; in the first-layer super junction substructure, the top opening width of the first-layer P-type sub-pillar is larger than the bottom opening width, and the optimal charge balance is achieved between the first-layer P-type sub-pillar and the first-layer N-type sub-pillar at the top of the first-layer P-type sub-pillar.

[0038] Alternatively, the grooves of the first layer of P-type sub-pillars in the first layer of the super junction substructure are inclined grooves, and the grooves of the second layer of P-type sub-pillars in the second layer of the super junction substructure are vertical grooves; the depth of the first layer of P-type sub-pillars is more than 10 microns greater than the depth of the second layer of P-type sub-pillars; in the second layer of the super junction substructure, charge balance is achieved between the second layer of P-type sub-pillars and the second layer of N-type sub-pillars at all longitudinal positions.

[0039] Alternatively, the grooves of the first layer of P-type sub-pillars in the first layer of the super junction substructure are vertical grooves, and the grooves of the second layer of P-type sub-pillars in the second layer of the super junction substructure are inclined grooves; the depth of the first layer of P-type sub-pillars is more than 10 microns greater than the depth of the second layer of P-type sub-pillars; in the first layer of the super junction substructure, charge balance is achieved between the first layer of P-type sub-pillars and the first layer of N-type sub-pillars at all longitudinal positions.

[0040] To solve the above technical problems, the present invention provides a method for manufacturing a super junction device, comprising the following steps:

[0041] Step 1: forming an N-type redundant epitaxial layer and an N-type buffer layer in sequence on an N-type semiconductor substrate.

[0042] The resistivity of the N-type semiconductor substrate is 0.1 to 10 times that of the subsequent top epitaxial layer, so as to ensure that the diffusion of dopant impurities in the N-type semiconductor substrate does not affect the performance of the super junction structure.

[0043] The resistivity of the N-type redundant epitaxial layer is 0.1 to 10 times the resistivity of the N-type semiconductor substrate, and the resistivity of the N-type redundant epitaxial layer is lower than the resistivity of the N-type buffer layer.

[0044] Step 2: A super junction structure is formed on the surface of the N-type buffer layer through a trench filling process, wherein the super junction structure is composed of P-type columns and N-type columns arranged alternately, the P-type columns are composed of a P-type semiconductor layer filled in the trench, the trench is formed in the top epitaxial layer, and the N-type columns are composed of the top epitaxial layer filled between the P-type columns.

[0045] Step 3: After completing the front process, proceed to the back process as follows:

[0046] Step 31 : performing a backside thinning process, wherein the backside thinning process removes the N-type semiconductor substrate, the N-type redundant epitaxial layer is completely or partially removed in the backside thinning process, and the thickness of the N-type buffer layer is completely retained after the backside thinning process.

[0047] In the backside thinning process, the N-type redundant epitaxial layer is used to ensure that the backside thinning process can completely remove the N-type semiconductor substrate without affecting the N-type buffer layer.

[0048] Step 32: Use a photolithography process to form a back-side photoresist pattern, wherein the back-side photoresist pattern opens the back-side P-type impurity region, and then performs back-side P-type ion implantation to implant P-type impurities in a selected region to form the back-side P-type impurity region, wherein the injection peak position of the back-side P-type ion implantation is greater than the injection peak position of the subsequent back-side N-type ion implantation; and there is a gap between the back-side P-type impurity region and the bottom surface of the P-type column.

[0049] Step 33: Perform back-side N-type ion implantation to form a drain region. The N-type redundant epitaxial layer also ensures that the drain region can reach the required doping concentration.

[0050] A further improvement is that the resistivity of the N-type buffer layer is 0.5 to 2 times the resistivity of the top epitaxial layer.

[0051] The resistivity of the N-type redundant epitaxial layer is less than 0.2 times the resistivity of the top epitaxial layer.

[0052] A further improvement is that the dimension of at least one direction of each selected region of the back P-type impurity region is greater than or equal to 5 microns; and the thickness of the photoresist in the photolithography process is greater than or equal to 4 microns.

[0053] A further improvement is that the back P-type impurity region has a P-type net doping, and the highest concentration of the P-type net doping in the back P-type impurity region is less than or equal to the lowest concentration of the P-type column.

[0054] Alternatively, the back surface P-type impurity region has a net N-type doping, and the concentration of the net N-type doping in the back surface P-type impurity region is 1 / 5 to 1 / 100 of the N-type impurity concentration when no P-type impurities are injected.

[0055] A further improvement is that the drain region and the back P-type impurity region are both subjected to laser annealing, and the depth range of the back P-type impurity region is less than or equal to the depth of the laser annealing.

[0056] A further improvement is that the area of ​​the back surface P-type impurity region is 5% to 30% of the area of ​​the entire drain region.

[0057] The present invention makes a special arrangement for the impurity concentration relationship between the N-type semiconductor substrate and the top epitaxial layer corresponding to the superjunction structure. This arrangement can ensure that the N-type semiconductor substrate does not form impurity diffusion that affects the doping distribution of the superjunction structure. Therefore, the present invention can eliminate the adverse effects of impurity diffusion of a high-concentration substrate on the superjunction structure. This enables the superjunction structure to achieve an ultra-low specific on-resistance structure. For example, the stepping energy of the PN column of the superjunction structure can be smaller and the depth can be deeper, thereby reducing the specific on-resistance of the device.

[0058] Since the present invention does not reduce the device's specific on-resistance by increasing the doping concentration of the N-type semiconductor substrate, the N-type semiconductor substrate will be completely removed in the backside thinning process to eliminate the adverse effects of the N-type semiconductor substrate on the device's specific on-resistance.

[0059] In order to completely remove the N-type semiconductor substrate without affecting the N-type buffer layer, the present invention adds an N-type redundant epitaxial layer. The N-type redundant epitaxial layer can increase the process window of the back thinning process, so that the N-type semiconductor substrate can be completely removed without affecting the N-type buffer layer.

[0060] The present invention also sets the relationship between the doping concentrations of the N-type redundant epitaxial layer and the N-type semiconductor substrate, and between the N-type redundant epitaxial layer and the N-type buffer layer, thereby preventing adverse effects caused by excessively high doping concentrations of the N-type redundant epitaxial layer, such as fluctuations in the resistivity of the epitaxial layer in the transition region. At the same time, the present invention can combine back-side N-type ion implantation to form a drain region with a higher doping concentration and form a good ohmic contact with the back-side metal layer, thereby reducing the ratio of the back-side contact resistance to the total on-resistance to less than 1%.

[0061] Since the present invention does not require the use of a high-concentration N-type semiconductor substrate, it is possible to perform local photolithographic P-type impurity implantation on the back side to form a P-type impurity region on the back side, thereby changing the carrier distribution of the device when the body diode is turned on. In particular, it increases the carriers between the PN column, i.e., the superjunction structure, and the drain region. Since these carriers are not located in the PN column, they are not depleted when the PN column occurs and is completely depleted during the reverse recovery process. Instead, they are extracted as Vds further increases. Finally, the reverse recovery time is increased, thereby improving the reverse recovery softness of the body diode. Therefore, the present invention improves the characteristics of the device's body diode, including the reverse recovery peak current (Irrm) and the reverse recovery softness. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0063] Figure 1 1 is a schematic structural diagram of a super junction device according to an embodiment of the present invention;

[0064] Figure 2-Figure 9 It is a schematic diagram of the device structure in each step of the manufacturing method of the super junction device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0065] like Figure 1 FIG. 1 is a schematic diagram of the structure of a super junction device according to an embodiment of the present invention. The super junction device according to an embodiment of the present invention includes:

[0066] Sequentially formed on an N-type semiconductor substrate 1 (please refer to Figure 2 As shown) on the N-type redundant epitaxial layer 201 (please refer to Figure 2 as shown) and an N-type buffer layer 202.

[0067] A superjunction structure is formed on the N-type buffer layer 202, and the superjunction structure is composed of P-type columns and N-type columns arranged alternately. The P-type columns are composed of a P-type semiconductor layer filled in a trench, and the trench is formed in the top epitaxial layer. The N-type columns are composed of the top epitaxial layer filled between the P-type columns.

[0068] The backside structure of the super junction device includes a drain region 211 and a patterned backside P-type impurity region 212 .

[0069] The drain region 211 is formed by performing full backside N-type ion implantation after the backside thinning process.

[0070] The back P-type impurity region 212 is patterned by a photoresist 213 formed by a photolithography process and includes P-type impurities formed by back P-type ion implantation in the selected region.

[0071] The injection peak position of the back P-type ion implantation is greater than the injection peak position of the back N-type ion implantation; and there is a gap between the back P-type impurity region 212 and the bottom surface of the P-type column.

[0072] The N-type semiconductor substrate 1 is removed during the backside thinning process.

[0073] The N-type redundant epitaxial layer 201 is partially removed during the backside thinning process. In other embodiments, the N-type redundant epitaxial layer 201 can also be completely removed during the backside thinning process.

[0074] After the backside thinning process, the thickness of the N-type buffer layer 202 is completely retained.

[0075] The resistivity of the N-type semiconductor substrate 1 is 0.1 to 10 times that of the top epitaxial layer, so as to ensure that the diffusion of dopant impurities in the N-type semiconductor substrate 1 does not affect the performance of the superjunction structure.

[0076] The resistivity of the N-type redundant epitaxial layer 201 is 0.1 to 10 times the resistivity of the N-type semiconductor substrate 1. The resistivity of the N-type redundant epitaxial layer 201 is lower than the resistivity of the N-type buffer layer 202. The N-type redundant epitaxial layer 201 is used to ensure that the back thinning process can completely remove the N-type semiconductor substrate 1 without affecting the N-type buffer layer 202 and to ensure that the drain region 211 can reach the required doping concentration.

[0077] The resistivity of the N-type buffer layer 202 is 0.5 to 2 times the resistivity of the top epitaxial layer. Preferably, the resistivity of the N-type buffer layer 202 is equal to the resistivity of the top epitaxial layer.

[0078] The resistivity of the N-type redundant epitaxial layer 201 is less than 0.2 times the resistivity of the top epitaxial layer. Preferably, the resistivity of the N-type redundant epitaxial layer 201 is 0.1 times the resistivity of the top epitaxial layer.

[0079] The impurities of the back N-type ion implantation include phosphorus or arsenic, and the implantation dose is 5E12cm -2 ~1E15cm -2 .

[0080] The impurities of the back P-type ion implantation include B or BF2, and the implantation dose is 1E11cm -2 ~5E12cm -2 , the injection energy is 50keV~400keV.

[0081] The dimension of at least one direction of each selected region of the back P-type impurity region 212 is greater than or equal to 5 micrometers; the thickness of the photoresist 213 of the photolithography process is greater than or equal to 4 micrometers.

[0082] The back P-type impurity region 212 has a net P-type doping, and the maximum concentration of the P-type net doping in the back P-type impurity region 212 is less than or equal to the minimum concentration of the P-type pillars. More preferably, the back P-type impurity region 212 has a net P-type doping, and the maximum concentration of the P-type net doping in the back P-type impurity region 212 is less than or equal to 1 / 2 of the minimum concentration of the P-type pillars.

[0083] Alternatively, the back surface P-type impurity region 212 has N-type net doping, and the concentration of the N-type net doping in the back surface P-type impurity region 212 is 1 / 5 to 1 / 100 of the N-type impurity concentration when no P-type impurities are injected.

[0084] The drain region 211 and the back P-type impurity region 212 are both laser annealed, and the depth range of the back P-type impurity region 212 is less than or equal to the depth of the laser annealing. For example, when the depth of the laser annealing is 4 microns, the depth of the back P-type impurity region 212 is less than 4 microns.

[0085] The area of ​​the backside P-type impurity region 212 is 5% to 30% of the area of ​​the entire drain region 211 .

[0086] The super junction structure is formed by stacking multiple layers of super junction substructures, and each layer of the super junction substructure is formed by alternating P-type sub-pillars and N-type sub-pillars of the corresponding layer. The P-type sub-pillars of each layer are stacked longitudinally to form the P-type columns, and the N-type sub-pillars of each layer are stacked longitudinally to form the N-type columns.

[0087] In an embodiment of the present invention, the number of layers of the super junction substructure included in the super junction structure is 2. In other embodiments, the number of layers of the super junction substructure included in the super junction structure may be 3 or more.

[0088] Figure 1 In the figure, the first layer of super junction structure is between line A1A2 and line B1B2, which is composed of the first layer of P-type sub-pillars 301 and the first layer of N-type sub-pillars 203 arranged alternately; the second layer of super junction structure is between line B1B2 and line C1C2, which is composed of the second layer of P-type sub-pillars 302 and the second layer of N-type sub-pillars 204 arranged alternately.

[0089] The opening width of each P-type sub-column is greater than the opening width of the N-type sub-column in the same layer. For example, for a super-junction structure with a step size of 9 microns, the top width of each P-type sub-column can be set to 5 microns, and the top width of each N-type sub-column can be set to 4 microns. For a super-junction structure with a step size of 5 microns, the top width of each P-type sub-column can be set to 3 microns, and the top width of each N-type sub-column can be set to 2 microns.

[0090] The charge balance structure in each layer of the superjunction substructure is set so that the deviation of the total amount of impurities of the P-type sub-column and the N-type sub-column is less than 5% of the total amount of impurities of any one of the P-type sub-column and the N-type sub-column.

[0091] The thickness of the N-type sub-pillars in each layer above the second layer is set to ensure that the alignment marks and overlay accuracy marks at the bottom of the N-type top epitaxial sub-layer corresponding to the N-type sub-pillars can be identified after deposition. For example, the thickness of the N-type sub-pillars in each layer above the second layer is set to 20 microns to 25 microns.

[0092] The first layer of superjunction structure is located at the bottom, and the second layer of superjunction structure is superimposed on the first layer of superjunction structure.

[0093] In an embodiment of the present invention, in the second-layer super junction structure, the top opening width of the second-layer P-type sub-pillar 302 is greater than the bottom opening width, and the optimal charge balance is achieved between the second-layer P-type sub-pillar 302 and the second-layer N-type sub-pillar 204 at the bottom of the second-layer P-type sub-pillar 302.

[0094] In the first-layer super junction structure, the top opening width of the first-layer P-type sub-pillar 301 is larger than the bottom opening width, and the optimal charge balance is achieved between the first-layer P-type sub-pillar 301 and the first-layer N-type sub-pillar 203 at the top of the first-layer P-type sub-pillar 301.

[0095] Thus, the optimal charge balance of the superjunction structure is located at line B1B2. The benefits of this arrangement are:

[0096] The upper portion of the second-layer P-type sub-pillars 302 contains more P-type impurities than N-type impurities, while the lower portion of the first-layer P-type sub-pillars 301 contains more N-type impurities than P-type impurities. During device operation, when Vds increases and the PN pillars breakdown, the breakdown occurs around the tops of the first-layer P-type sub-pillars 301, which is also around the bottoms of the second-layer P-type sub-pillars 302. This improves the device's current surge resistance, particularly the consistency of its surge resistance.

[0097] Through such a setting, when the impurity concentration of the P-type column caused by the process deviates, the highest value of the electric field strength in the entire P-type column is located at a position around the center of the first layer of P-type sub-columns 301, which has a certain stability. When avalanche breakdown occurs at this position, the holes (with positive charge) in the generated electron-hole pairs flow to the upper part of the first layer of P-type sub-columns 301 under the action of the vertical electric field, which better improves the charge balance in the upper area (this area has more P than N, and after depletion, the negative charge in the P-type column is more than the positive charge in the N-type column; therefore, the increase in positive charge improves the charge balance); the electrons (with negative charge) in the generated electron-hole pairs flow to the bottom of the first layer of P-type sub-columns 301 under the action of the vertical electric field, which better improves the charge balance in the first layer of P-type sub-columns 301 (this area has less P than N, and after depletion, the negative charge in the P-type column is less than the positive charge in the N-type column; therefore, the increase in negative charge improves the charge balance), thereby increasing the breakdown voltage of the device and improving the avalanche withstand capability of the device.

[0098] In other embodiments, the grooves of the first-layer P-type sub-pillars 301 of the first-layer super-junction substructure may be inclined, while the grooves of the second-layer P-type sub-pillars 302 of the second-layer super-junction substructure may be vertical. The depth of the first-layer P-type sub-pillars 301 may be at least 10 microns greater than the depth of the second-layer P-type sub-pillars 302. In the second-layer super-junction substructure, charge balance is achieved at all longitudinal positions between the second-layer P-type sub-pillars 302 and the second-layer N-type sub-pillars 204. The charge balance is achieved by ensuring that the deviation in the total amount of impurities in the second-layer P-type sub-pillars 302 and the second-layer N-type sub-pillars 204 is less than 5% of the total amount of impurities in either of the second-layer P-type sub-pillars 302 and the second-layer N-type sub-pillars 204. This results in a higher breakdown voltage.

[0099] Alternatively, the trenches of the first-layer P-type sub-pillars 301 of the first-layer superjunction substructure are vertical trenches, and the depth of the first-layer P-type sub-pillars 301 is at least 10 microns greater than the depth of the second-layer P-type sub-pillars 302. In the first-layer superjunction substructure, charge balance is achieved at all longitudinal positions between the first-layer P-type sub-pillars 301 and the first-layer N-type sub-pillars 203. The charge balance is such that the deviation in the total amount of impurities in the first-layer P-type sub-pillars 301 and the first-layer N-type sub-pillars 203 is less than 5% of the total amount of impurities in either the first-layer P-type sub-pillars 301 or the first-layer N-type sub-pillars 203. The trenches of the second-layer P-type sub-pillars 302 of the second-layer superjunction substructure are inclined trenches, which increases the overall PN column depth and improves the breakdown voltage of the device.

[0100] A front structure of a super junction device is also formed on the super junction structure. The super junction device is a super junction NMOS. The front structure includes multiple super junction device unit structures. The super junction device unit structure includes:

[0101] A P-type well 6 is formed on the top of each P-type column, and the P-type well 6 also extends into the N-type columns on both sides.

[0102] A gate structure formed by stacking a gate dielectric layer, such as a gate oxide layer 8 , and a polysilicon gate 9 is formed on the top of the P-type well 6 . Figure 1 In the embodiment, the gate oxide layer 8 and the polysilicon gate 9 on the top of the two adjacent P-type wells 6 on both sides of the N-type column are connected together to form an integral structure.

[0103] Active regions 10 are formed in the surface areas of the P-type well 6 on both sides of the polysilicon gate 9 .

[0104] The interlayer film 11 covers the top of the polysilicon gates 9 and the area between the polysilicon gates 9 .

[0105] The contact hole 12 passes through the interlayer film 11. Figure 1The contact hole 12 shown in FIG. 1 is a contact hole located at the top of the source region 10 . A contact hole P-type implantation contact region 13 is further formed at the bottom of the contact hole 12 at the top of the source region 10 .

[0106] The front metal layer 14 is patterned to form the source and gate. Figure 1 The source electrode formed by the front metal layer 14 is shown in FIG.

[0107] Typically, in order to further reduce the on-resistance, a JFET implantation region 7 formed by ion implantation is further formed in the surface region of the N-type pillars between the P-type wells 6 .

[0108] A drain electrode formed by the back metal layer 15 is also formed in the drain region 211 .

[0109] The embodiment of the present invention adopts a PN width and concentration matching structure of the PN column of the stacked charge balancing layer of the substrate with a specially set concentration, that is, resistivity. Among them, the PN column of the stacked charge balancing layer is the super junction structure formed by stacking multiple layers of super junction substructures, and the PN width is the width of adjacent P-type columns and N-type columns, which solves the problem of impurity diffusion from the high-concentration substrate. In particular, when used in combination with the stacked charge balancing structure with ultra-low specific on-resistance, a layer of relatively high-concentration redundant epitaxial layer 201 is added between the substrate and the buffer layer 202 of the PN column to ensure that the substrate with the set resistivity is completely removed in the final back grinding, leaving a portion of the redundant epitaxial layer 201 as the bottom part of the device, and performing back-side N-type ion implantation to ensure good ohmic contact between the N+ region on the back of the device and the back metal. In this way, while solving the diffusion problem caused by the high-concentration substrate above, it also ensures that the on-resistance of the device is basically unaffected by the back grinding process.

[0110] In this embodiment of the present invention, the resistivity of substrate 1 is set to be between 0.1 and 10 times the resistivity of the N epitaxial layers 203 and 204 of the PN columns deposited thereon. Furthermore, the resistivity difference between substrate 1 and other epitaxial layers thereon, such as epitaxial layers 201 and 202, should not exceed one order of magnitude. This ensures that during device operation, impurities in high-concentration substrate 1 will not diffuse outward and affect device performance. Furthermore, resistivity fluctuations in the transition region during the deposition of epitaxial layers 201 or 202, caused by the impurity concentration in epitaxial layers 201 or 202 being significantly higher than that in substrate 1, will not increase the difficulty of the process.

[0111] In the embodiment of the present invention, the substrate concentration of the N-type semiconductor substrate 1 is theoretically unrestricted. This means that unlike the high-concentration substrate required in the prior art, if the concentration of the N-type semiconductor substrate 1 is set to 1 / 10 to 10 times the concentration of the N-type top epitaxial sublayer 203 corresponding to the first-layer N-type sub-pillar 203, the interdiffusion effect of the N-type semiconductor substrate 1 on the epitaxy of the N-type top epitaxial sublayers 203 and 204 can be ignored. In production, setting the concentration of the first-layer N-type sub-pillar 203 to the same order of magnitude as the concentration of the N-type top epitaxial sublayer 203 is completely feasible without incurring additional costs, effectively resolving the following issues associated with prior high-concentration substrates:

[0112] Outdiffusion caused by high-concentration substrates has different effects on devices at the edge and center of the wafer.

[0113] High-concentration substrates require control of mix-run during production.

[0114] Backside encapsulation is required before depositing relatively low-concentration epitaxy on a high-concentration substrate.

[0115] It also brings the following additional benefits:

[0116] By back ion implantation, a thin high-concentration N+ region, namely the drain region 211, is formed to reduce the back N+ injection effect of the body diode, reduce Irrm, and improve softness.

[0117] Because the N+ concentration of the substrate is reduced, an appropriate amount of P-type impurities can be injected into the back region to form a partial P-type region, further improving the characteristics of the body diode, including Irrs, especially the softness of reverse recovery.

[0118] The device structure of the embodiment of the present invention is now further described in detail with reference to specific parameters:

[0119] In the embodiment of the present invention, the gate oxide layer 8 (Gox) is

[0120] The concentration of the N-type semiconductor substrate 1, i.e., the corresponding N-type resistivity, is 0.08 ohm·cm to 8 ohm·cm;

[0121] The N-type resistivity of the epitaxial layers 202 , 203 and 204 is 0.8 ohm-cm. Here, the epitaxial layers are distinguished by different reference numerals.

[0122] The top width of the two-layer trench is 3μm, and the top width of the N-type column is 2μm; the trench inclination angle is 88.8 degrees.

[0123] The depth of the first layer of P-type sub-pillars 301 is 30 μm, and the depth of the second layer of P-type sub-pillars 302 is 20 μm;

[0124] The thickness of the epitaxial layer 202 is 10 μm;

[0125] The epitaxial layer 201 has an initial thickness of 20 μm and a resistivity of 0.08 ohm-cm.

[0126] After thinning, phosphorus ion implantation and annealing were performed, and the implantation dose was such that the phosphorus concentration on the back surface was 1E19cm -3 .

[0127] The estimated effect of epitaxial layers 203 and 204 on on-resistance is: 0.8*L(50μm) / W(2μm)=0.8*25;

[0128] The effect of the epitaxial layer 202 on the on-resistance is: 0.8*L(10μm) / W(5μm)=0.8*2;

[0129] The sum of the above two is approximately 0.8*27;

[0130] After the epitaxial layer 201 is thinned to a thickness of 10 μm, its contribution is 0.08*2, which is 1 / 135 of the former;

[0131] After the epitaxial layer 201 is thinned to a thickness of 5 μm, its contribution is 0.08*1, which is 1 / 270 of the former.

[0132] The difference in contribution of the epitaxial layer 201 in the above two cases can be ignored, so the epitaxial layer 201 has a good redundancy effect.

[0133] Taking into account the backside phosphorus ion implantation, the difference in contribution of the epitaxial layer 201 of different thicknesses to the on-resistance will be further reduced, so the actual difference is even smaller.

[0134] The embodiment of the present invention makes a special arrangement for the impurity concentration relationship between the N-type semiconductor substrate 1 and the top epitaxial layer corresponding to the superjunction structure. This arrangement can ensure that the N-type semiconductor substrate 1 does not form impurity diffusion that affects the doping distribution of the superjunction structure. Therefore, the present invention can eliminate the adverse effects of impurity diffusion of a high-concentration substrate on the superjunction structure. This enables the superjunction structure to achieve an ultra-low specific on-resistance structure. For example, the stepping energy of the PN column of the superjunction structure can be smaller and the depth can be deeper, thereby reducing the specific on-resistance of the device.

[0135] Since the embodiment of the present invention does not reduce the device's specific on-resistance by increasing the doping concentration of the N-type semiconductor substrate 1, the N-type semiconductor substrate 1 will be completely removed in the back thinning process to eliminate the adverse effect of the N-type semiconductor substrate 1 on the device's specific on-resistance.

[0136] In order to completely remove the N-type semiconductor substrate 1 without affecting the N-type buffer layer 202, an embodiment of the present invention adds an N-type redundant epitaxial layer 201. The N-type redundant epitaxial layer 201 can increase the process window of the back thinning process, so that the N-type semiconductor substrate 1 can be completely removed without affecting the N-type buffer layer 202.

[0137] The embodiment of the present invention further sets the relationship between the doping concentrations of the N-type redundant epitaxial layer 201 and the N-type semiconductor substrate 1, and between the N-type redundant epitaxial layer 201 and the N-type buffer layer 202. This prevents the adverse effects of excessively high doping concentrations of the N-type redundant epitaxial layer 201, such as fluctuations in the resistivity of the epitaxial layer in the transition region. Furthermore, the embodiment of the present invention can form a drain region 211 with a higher doping concentration by combining back-side N-type ion implantation and form a good ohmic contact with the back-side metal layer, thereby reducing the ratio of the back-side contact resistance to the total on-resistance to less than 1%.

[0138] like Figures 1-8 , which is a schematic diagram of the device structure in each step of the manufacturing method of a super junction device according to an embodiment of the present invention; the manufacturing method of a super junction device according to an embodiment of the present invention includes the following steps:

[0139] Step 1: Figure 2 As shown, an N-type redundant epitaxial layer 201 and an N-type buffer layer 202 are sequentially formed on an N-type semiconductor substrate 1 .

[0140] The resistivity of the N-type semiconductor substrate 1 is 0.1 to 10 times that of the subsequent top epitaxial layer, so as to ensure that the diffusion of dopant impurities in the N-type semiconductor substrate 1 does not affect the performance of the superjunction structure.

[0141] The resistivity of the N-type redundant epitaxial layer 201 is 0.1 to 10 times the resistivity of the N-type semiconductor substrate 1 , and the resistivity of the N-type redundant epitaxial layer 201 is lower than the resistivity of the N-type buffer layer 202 .

[0142] In the method of the present embodiment, a relatively high-resistivity, i.e., low-concentration, N-type semiconductor substrate 1 with a wide resistivity range is used. The substrate resistivity, i.e., the resistivity of the N-type semiconductor substrate 1, is set to be 1 / 10 to 10 times the resistivity of the N-type epitaxial layers 203 and 204 of the PN column, i.e., the subsequent top epitaxial layer, in the superjunction structure. For example, the N-type epitaxial layers 203 and 204 of the PN column are 0.8 ohm·cm, while the N-type semiconductor substrate 1 is 0.08 ohm·cm to 8 ohm·cm. This wide range of resistivity allows for different thicknesses and regions of the semiconductor substrate 1 to have different resistivities, thus facilitating production. The substrate resistivity is set to be between 0.1 and 10 times the resistivity of the N-type epitaxial layers 203 and 204 of the PN column deposited directly thereon. Furthermore, the difference between the substrate resistivity and the resistivity of the other epitaxial layers 201 and 202 on the substrate 1 should not exceed one order of magnitude. This ensures that the device performance will not be affected by the expansion of high-concentration substrate impurities during device operation, and the resistivity fluctuation process in the transition region during epitaxial deposition will not be made more difficult because the epitaxial impurity concentration is much higher than the substrate concentration.

[0143] Figure 1 , an N-type redundant epitaxial layer 201 is deposited on the N-type semiconductor substrate 1 , and the thickness of the N-type redundant epitaxial layer 201 can be 20 μm.

[0144] An N-type buffer layer 202 is deposited on the N-type redundant epitaxial layer 201 .

[0145] The resistivity of the N-type redundant epitaxial layer 201 should be selected to be between 0.1 and 10 times that of the substrate. Compared to the resistivity of the epitaxial layer above it, it should be lower than the resistivity of the N-type buffer layer 202 above it. Generally, the resistivity of the N-type redundant epitaxial layer 201 is selected to be 1 / 10 of the resistivity of the N-type buffer layer 202. The thickness of this N-type redundant epitaxial layer 201 is set based on the control capabilities of the subsequent thinning process. This ensures that after the thinning process is completed, the N-type redundant epitaxial layer 201 is completely removed or partially retained, while the N-type buffer layer 202 remains intact for subsequent processing.

[0146] The resistivity of the N-type buffer layer 202 and the subsequent epitaxial layer 203 may be the same or different. For example, the resistivity of the N-type buffer layer 202 may be 0.5 to 2 times that of the epitaxial layer 203 .

[0147] The thickness of the N-type buffer layer 202 has a certain influence on the characteristics of the body diode and the on-resistance of the device, and can be set to 0 microns to 20 microns. When there is a certain requirement for the device's avalanche resistance, it can generally be set to 5 microns to 20 microns.

[0148] The resistivity of the N-type redundant epitaxial layer 201 is less than 0.2 times the resistivity of the top epitaxial layer. For example, the resistivity of the N-type redundant epitaxial layer 201 is 0.1 times the resistivity of the top epitaxial layer.

[0149] Step 2: A super junction structure is formed on the surface of the N-type buffer layer 202 through a trench filling process. The super junction structure is composed of P-type columns and N-type columns arranged alternately. The P-type columns are composed of a P-type semiconductor layer filled in the trenches. The trenches are formed in the top epitaxial layer, and the N-type columns are composed of the top epitaxial layer filled between the P-type columns.

[0150] In the embodiment method of the present invention, the super junction structure is formed by stacking multiple layers of super junction substructures, and each layer of the super junction substructure is formed by alternating P-type sub-pillars and N-type sub-pillars of the corresponding layer. The P-type sub-pillars of each layer are stacked longitudinally to form the P-type columns, and the N-type sub-pillars of each layer are stacked longitudinally to form the N-type columns.

[0151] The following description takes the case where the super junction structure includes two layers of the super junction substructure as an example. In other embodiments, the super junction substructure also includes three or more layers, thereby reducing the difficulty of the trench filling process for each layer or improving the BVdss of the device. The formation process of the super junction structure with a two-layer stacked structure includes the following steps:

[0152] Step 21, performing epitaxial growth, including: Figure 1 As shown, an N-type top epitaxial sublayer 203 , also referred to as epitaxial layer 203 for short, is formed on the N-type buffer layer 202 .

[0153] The bottom surface of the epitaxial layer 203 is shown as line A1A2, and the top surface is shown as line B1B2.

[0154] Step 22: Trench etching is performed, including depositing a hard mask layer composed of a bottom oxide film, an intermediate silicon nitride film, and a top oxide film on the top surface of the epitaxial layer 203. After removing the hard mask layer in the photolithographically opened areas through photolithography and etching, silicon etching is performed to form the first-layer trenches of the superjunction structure, i.e., the first-layer trenches. The bottom of the first-layer trenches reaches the bottom of the epitaxial layer 203.

[0155] Step 23: perform trench filling, including: Figure 2 As shown in FIG, after the etching is completed, the top oxide film and the middle nitride film in the hard mask layer are etched away by dry or wet etching, leaving the bottom oxide film as a hard mask for the trench filling silicon. Figure 3As shown, the first trench is completely filled with a P-type semiconductor layer, such as a P-type silicon epitaxial layer. Chemical mechanical polishing is used to remove all surface silicon, and then the underlying oxide film is etched away. This forms a first layer of P-type sub-pillars 301 and a first layer of N-type sub-pillars 203. The first layer of P-type sub-pillars 301 and the first layer of N-type sub-pillars 203 are adjacent to each other, forming a first PN-type pillar, or a first layer of superjunction structure. The charges of these pillars are balanced, or the difference in charge is less than 5% of the total charge of the first layer of P-type sub-pillars 301, and also less than 5% of the total charge of the first layer of P-type sub-pillars 301.

[0156] Repeat steps 21 to 23 to form a second PN column, i.e., a second layer of superjunction structure. Figure 4 , forming a second layer of P-type sub-pillars 302 and a second layer of N-type sub-pillars 204. The bottom of the second layer of P-type sub-pillars 302 must contact the top of the first layer of P-type sub-pillars 301, and can have a certain depth of penetration. The resistivity of the epitaxial layer corresponding to the second layer of N-type sub-pillars 204 is set to be the same as the resistivity of the epitaxial layer 203, and can also be set to be different. The second layer of P-type sub-pillars 302 and the second layer of N-type sub-pillars 204 are adjacent to each other to form a second PN-type column, and their charges are balanced or the difference in charge amount is less than 5% of the total charge of the second layer of N-type sub-pillars 204, and less than 5% of the total charge of the second layer of P-type sub-pillars 302.

[0157] Step 3: Complete the front process, including:

[0158] like Figure 5 As shown, a P-type well 6 is formed at the top of each P-type pillar. The P-type well 6 also extends into the N-type pillars on both sides. The top surface of the P-type well 6 is indicated by line D1D2, and the bottom surface is indicated by line C1C2. After the P-type well 6 is formed, the top surface of the second-layer super junction structure is lowered to the position indicated by line C1C2.

[0159] like Figure 6 As shown, a dielectric layer and polysilicon are formed and patterned to form a gate structure composed of a gate dielectric layer such as a gate oxide layer 8 and a polysilicon gate 9 stacked on top of the P-type well 6; Figure 6 In the embodiment, the gate oxide layer 8 and the polysilicon gate 9 on the top of the two adjacent P-type wells 6 on both sides of the N-type column are connected together to form an integral structure.

[0160] N-type heavily doped ions are implanted into the surface areas of the P-type well 6 on both sides of the polysilicon gate 9 to form source regions 10 .

[0161] An interlayer film 11 is formed to cover the top of the polysilicon gates 9 and the area between the polysilicon gates 9 .

[0162] A contact hole opening is formed through the interlayer film 11 , and a contact hole P-type implantation contact region 13 is formed at the bottom of the contact hole opening on the top of the source region 10 .

[0163] The contact hole opening is filled with metal to form a contact hole 12 .

[0164] Form a front metal layer 14 and pattern it to form a source and a gate. Figure 6 The source electrode formed by the front metal layer 14 is shown in FIG.

[0165] Typically, in order to further reduce the on-resistance, a JFET implantation region 7 is formed in the surface region of the N-type pillars between the P-type wells 6 by N-type ion implantation.

[0166] Then the following back process is carried out:

[0167] Step 31: Figure 7 As shown, a backside thinning process is performed to remove the N-type semiconductor substrate 1 .

[0168] The N-type redundant epitaxial layer 201 is partially removed in the back thinning process, and the remaining N-type redundant epitaxial layer is individually marked with a mark 211. The drain region subsequently formed in the remaining N-type redundant epitaxial layer is also marked with a mark 211; the N-type redundant epitaxial layer 201 can also be completely removed.

[0169] After the backside thinning process, the thickness of the N-type buffer layer 202 is completely retained.

[0170] In the backside thinning process, the N-type redundant epitaxial layer 201 is used to ensure that the backside thinning process can completely remove the N-type semiconductor substrate 1 without affecting the N-type buffer layer 202 .

[0171] Step 32: Figure 8 As shown, a backside photoresist 213 pattern is formed by a photolithography process, and the backside photoresist 213 pattern opens the backside P-type impurity region 212;

[0172] Then, back-side P-type ion implantation is performed to implant P-type impurities in the selected area to form the back-side P-type impurity region 212. The injection peak position of the back-side P-type ion implantation is greater than the injection peak position of the subsequent back-side N-type ion implantation. There is a gap between the back-side P-type impurity region 212 and the bottom surface of the P-type column.

[0173] The impurities of the back P-type ion implantation include B or BF2, and the implantation dose is 1E11cm -2 ~5E12cm -2 , the injection energy is 50keV~400keV.

[0174] The dimension of at least one direction of each selected region of the back P-type impurity region 212 is greater than or equal to 5 micrometers; the thickness of the photoresist 213 of the photolithography process is greater than or equal to 4 micrometers.

[0175] The back P-type impurity region 212 has a net P-type doping, and the maximum concentration of the P-type net doping in the back P-type impurity region 212 is less than or equal to the minimum concentration of the P-type pillars. Preferably, the back P-type impurity region 212 has a net P-type doping, and the maximum concentration of the P-type net doping in the back P-type impurity region 212 is less than or equal to 1 / 2 of the minimum concentration of the P-type pillars.

[0176] Alternatively, the back surface P-type impurity region 212 has N-type net doping, and the concentration of the N-type net doping in the back surface P-type impurity region 212 is 1 / 5 to 1 / 100 of the N-type impurity concentration when no P-type impurities are injected.

[0177] Step 33: Figure 9 As shown, back-side N-type ion implantation is performed to form a drain region 211 , and the N-type redundant epitaxial layer 201 also ensures that the drain region 211 can reach the required doping concentration.

[0178] The drain region 211 and the back P-type impurity region 212 are both subjected to laser annealing, and the depth range of the back P-type impurity region 212 is less than or equal to the depth of the laser annealing.

[0179] The area of ​​the backside P-type impurity region 212 is 5% to 30% of the area of ​​the entire drain region 211 .

[0180] The impurities of the back N-type ion implantation include phosphorus or arsenic. The preferred setting is to make the impurity concentration of the back N+ able to form a good ohmic contact with the subsequent back metal layer 15 and the contact resistance accounts for less than 1% of the device's on-resistance, which can be ignored. At the same time, the impurity concentration of N+ is maintained at a low level.

[0181] The implantation energy of the back N-type ion implantation can be set between 20 KeV and 100 KeV, preferably between 30 and 75 KeV. The implantation dose can be set between 5E12 / cm2 and 5E15 / cm2, preferably between 5E13 / cm2 and 1E15 / cm2. Laser annealing is then performed to activate the implanted ions in the back region.

[0182] Afterwards, a back metal layer 15 is deposited on the back side of the drain region 211. The back metal layer 15 can be a Ti layer, a Ni layer or an Ag layer. The thickness of the Ti layer can be set to Ni layer Ag layer

[0183] In the embodiment of the present invention, a patterned backside P-type ion implantation step is added on the basis of the conventional backside N-type ion implantation, such as Figure 7 As shown, through backside lithography, P-type impurities are implanted into the backside of a thinned semiconductor substrate, such as a silicon wafer. The P-type impurities can be B or BF2, with an energy setting between 50 KeV and 4000 KeV. The energy setting must ensure that the peak concentration of the P-type impurities is a certain distance away from the high-concentration region of the N+ drain 211 region on the backside of the silicon wafer, for example, greater than 0.5 microns. The energy setting also needs to consider the effective annealing depth of the subsequent laser annealing equipment. For example, if the laser annealing equipment can only effectively activate ions within a depth of 4 microns from the backside surface, then the peak depth of the P-type implant should not exceed 4 microns. Of course, after annealing, the implanted P-type impurities should be slightly away from the bottom of the PN column, i.e., the superjunction structure. Otherwise, they become connected to the P-type column, reducing or even eliminating their effectiveness in increasing BVdss and improving the softness of the body diode.

[0184] The area of ​​the backside P-type implant is set based on its impact on on-resistance, and is generally recommended to be between 5% and 30% of the total active area. As the distance between the peak position of the P-type ion implantation area and the backside drain region increases, the impact on on-resistance is minimized, and the area ratio can be increased.

[0185] The implantation dose of the back P-type impurity region 212 should be set so that after balancing the original N-type impurities in the implanted region, the remaining P-type impurity concentration should not be higher than the P-type impurity concentration of the PN column. It is generally recommended that the remaining P-type impurity concentration on the back side is less than or equal to 1 / 2 of the lowest P-type impurity concentration of the PN column. Moreover, even if the implanted region fails to completely balance the N-type impurities after the P-type ion implantation, as long as the N-type impurities in the region are effectively reduced, for example, reduced to 1 / 5-1 / 100 of the original N-type impurities, there will be a significant improvement in the softness of the body diode. Generally, for example, the implantation dose of B can be set at 1E11cm -2 ~-5E12cm -2 Level

[0186] The setting of the area for P-type ion injection can adopt a larger-sized pattern, for example, an opening (injection area) with a lateral size greater than or equal to 5 microns. The back-side P-type lithography can use a photoresist with a thickness greater than or equal to 4 microns, leaving room for the selection of ion injection energy.

[0187] The present invention has been described in detail above by means of specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principles of the present invention, those skilled in the art may make many variations and improvements, which should also be considered as the scope of protection of the present invention.

Claims

1. A super junction device, characterized in that: include: An N-type redundant epitaxial layer and an N-type buffer layer are sequentially formed on an N-type semiconductor substrate; A superjunction structure is formed on the N-type buffer layer, wherein the superjunction structure is formed by alternating P-type pillars and N-type pillars, wherein the P-type pillars are composed of a P-type semiconductor layer filled in trenches formed in the top epitaxial layer, and the N-type pillars are composed of the top epitaxial layer filled between the P-type pillars; The backside structure of the superjunction device includes a drain region and a patterned backside P-type impurity region; Forming the backside P-type impurity region includes: Step 31: performing a backside thinning process, wherein the backside thinning process removes the N-type semiconductor substrate, the N-type redundant epitaxial layer is completely or partially removed in the backside thinning process, and the thickness of the N-type buffer layer is completely retained after the backside thinning process; In the backside thinning process, the N-type redundant epitaxial layer is used to ensure that the backside thinning process can completely remove the N-type semiconductor substrate without affecting the N-type buffer layer; Step 32: forming a backside photoresist pattern using a photolithography process, wherein the backside photoresist pattern opens a backside P-type impurity region, and then performing backside P-type ion implantation to implant P-type impurities into a selected region to form the backside P-type impurity region, wherein the injection peak position of the backside P-type ion implantation is greater than the injection peak position of the subsequent backside N-type ion implantation; and a gap is formed between the backside P-type impurity region and the bottom surface of the P-type pillar. The drain region is formed by performing a full backside N-type ion implantation after the backside thinning process; The resistivity of the N-type semiconductor substrate is 0.1 to 10 times that of the top epitaxial layer, so as to ensure that the diffusion of dopant impurities in the N-type semiconductor substrate does not affect the performance of the superjunction structure; The resistivity of the N-type redundant epitaxial layer is 0.1 to 10 times the resistivity of the N-type semiconductor substrate, and the resistivity of the N-type redundant epitaxial layer is lower than the resistivity of the N-type buffer layer. The N-type redundant epitaxial layer is used to ensure that the back thinning process can completely remove the N-type semiconductor substrate without affecting the N-type buffer layer and ensure that the drain region can reach the required doping concentration.

2. The superjunction device according to claim 1, wherein: The resistivity of the N-type buffer layer is 0.5 to 2 times the resistivity of the top epitaxial layer.

3. The super junction device according to claim 2, wherein: The resistivity of the N-type buffer layer is equal to the resistivity of the top epitaxial layer.

4. The superjunction device according to claim 2 or 3, wherein: The resistivity of the N-type redundant epitaxial layer is less than 0.2 times the resistivity of the top epitaxial layer.

5. The super junction device according to claim 4, wherein: The resistivity of the N-type redundant epitaxial layer is 0.1 times the resistivity of the top epitaxial layer.

6. The super junction device according to claim 1, wherein: The impurities of the back N-type ion implantation include phosphorus or arsenic, and the implantation dose is 5E12cm -2 ~1E15cm -2 ; The impurities of the back P-type ion implantation include B or BF2, and the implantation dose is 1E11cm -2 ~5E12cm -2 , the injection energy is 50keV~400keV.

7. The super junction device according to claim 1, wherein: The dimension of at least one direction of each selected region of the back P-type impurity region is greater than or equal to 5 microns; the thickness of the photoresist in the photolithography process is greater than or equal to 4 microns.

8. The super junction device according to claim 1, wherein: The back P-type impurity region has a P-type net doping, and the highest concentration of the P-type net doping in the back P-type impurity region is less than or equal to the lowest concentration of the P-type column.

9. The super junction device according to claim 8, wherein: The back P-type impurity region has a P-type net doping, and the highest concentration of the P-type net doping in the back P-type impurity region is less than or equal to 1 / 2 of the lowest concentration of the P-type pillar.

10. The super junction device according to claim 1, wherein: The back surface P-type impurity region has N-type net doping, and the concentration of the N-type net doping in the back surface P-type impurity region is 1 / 5 to 1 / 100 of the N-type impurity concentration when no P-type impurities are injected.

11. The super junction device according to claim 1, wherein: The drain region and the back P-type impurity region are both subjected to laser annealing, and the depth range of the back P-type impurity region is less than or equal to the depth of the laser annealing.

12. The super junction device according to claim 1, wherein: The area of ​​the back P-type impurity region is 5% to 30% of the area of ​​the entire drain region.

13. The super junction device according to claim 1, wherein: The superjunction structure is formed by stacking multiple layers of superjunction substructures, and each layer of the superjunction substructure is formed by alternating P-type sub-pillars and N-type sub-pillars of the corresponding layer. The P-type sub-pillars of each layer are stacked longitudinally to form the P-type pillars, and the N-type sub-pillars of each layer are stacked longitudinally to form the N-type pillars. The number of layers of the super junction substructure included in the super junction structure is 2 or 3 or more; The opening width of each of the P-type sub-columns is equal to the opening width of the N-type sub-columns in the same layer; Alternatively, the opening width of each of the P-type sub-columns is not equal to the opening width of the N-type sub-columns in the same layer; The charge balance structure in each layer of the superjunction substructure is set to: a deviation of the total amount of impurities of the P-type sub-column and the N-type sub-column is less than 5% of the total amount of impurities of any one of the P-type sub-column and the N-type sub-column; The thickness of the N-type sub-columns in each layer above the second layer is set to ensure that the alignment mark and overlay precision mark at the bottom can be identified after the N-type top epitaxial sub-layer corresponding to the N-type sub-columns are deposited.

14. The super junction device according to claim 13, wherein: The first layer of superjunction structure is located at the bottom, and the second layer of superjunction structure is superimposed on the first layer of superjunction structure; In the second-layer superjunction substructure, the top opening width of the second-layer P-type sub-pillars is greater than the bottom opening width, and the second-layer P-type sub-pillars and the second-layer N-type sub-pillars achieve optimal charge balance at the bottom of the second-layer P-type sub-pillars; in the first-layer superjunction substructure, the top opening width of the first-layer P-type sub-pillars is greater than the bottom opening width, and the first-layer P-type sub-pillars and the first-layer N-type sub-pillars achieve optimal charge balance at the top of the first-layer P-type sub-pillars; Alternatively, the grooves of the first layer of P-type sub-pillars in the first layer of the super junction substructure are inclined grooves, and the grooves of the second layer of P-type sub-pillars in the second layer of the super junction substructure are vertical grooves; the depth of the first layer of P-type sub-pillars is greater than the depth of the second layer of P-type sub-pillars by more than 10 microns; and in the second layer of the super junction substructure, charge balance is achieved between the second layer of P-type sub-pillars and the second layer of N-type sub-pillars at all longitudinal positions; Alternatively, the grooves of the first layer of P-type sub-pillars in the first layer of the super junction substructure are vertical grooves, and the grooves of the second layer of P-type sub-pillars in the second layer of the super junction substructure are inclined grooves; the depth of the first layer of P-type sub-pillars is more than 10 microns greater than the depth of the second layer of P-type sub-pillars; in the first layer of the super junction substructure, charge balance is achieved between the first layer of P-type sub-pillars and the first layer of N-type sub-pillars at all longitudinal positions.

15. A method for manufacturing a super junction device, characterized in that: The steps include: Step 1: forming an N-type redundant epitaxial layer and an N-type buffer layer in sequence on an N-type semiconductor substrate; The resistivity of the N-type semiconductor substrate is 0.1 to 10 times that of the subsequent top epitaxial layer, so as to ensure that the diffusion of dopant impurities in the N-type semiconductor substrate does not affect the performance of the superjunction structure; The resistivity of the N-type redundant epitaxial layer is 0.1 to 10 times the resistivity of the N-type semiconductor substrate, and the resistivity of the N-type redundant epitaxial layer is lower than the resistivity of the N-type buffer layer; Step 2: forming a superjunction structure on the surface of the N-type buffer layer by a trench filling process, wherein the superjunction structure is formed by alternating P-type pillars and N-type pillars, wherein the P-type pillars are composed of a P-type semiconductor layer filled in trenches, wherein the trenches are formed in the top epitaxial layer, and the N-type pillars are composed of the top epitaxial layer filled between the P-type pillars; Step 3: After completing the front process, proceed to the back process as follows: Step 31: performing a backside thinning process, wherein the backside thinning process removes the N-type semiconductor substrate, the N-type redundant epitaxial layer is completely or partially removed in the backside thinning process, and the thickness of the N-type buffer layer is completely retained after the backside thinning process; In the backside thinning process, the N-type redundant epitaxial layer is used to ensure that the backside thinning process can completely remove the N-type semiconductor substrate without affecting the N-type buffer layer; Step 32: forming a backside photoresist pattern using a photolithography process, wherein the backside photoresist pattern opens a backside P-type impurity region, and then performing backside P-type ion implantation to implant P-type impurities into a selected region to form the backside P-type impurity region, wherein the injection peak position of the backside P-type ion implantation is greater than the injection peak position of the subsequent backside N-type ion implantation; and a gap is formed between the backside P-type impurity region and the bottom surface of the P-type pillar. Step 33: Perform back-side N-type ion implantation to form a drain region. The N-type redundant epitaxial layer also ensures that the drain region can reach the required doping concentration.

16. The method for manufacturing a super junction device according to claim 15, wherein: The resistivity of the N-type buffer layer is 0.5 to 2 times that of the top epitaxial layer; The resistivity of the N-type redundant epitaxial layer is less than 0.2 times the resistivity of the top epitaxial layer.

17. The method for manufacturing a super junction device according to claim 15, wherein: The dimension of at least one direction of each selected region of the back P-type impurity region is greater than or equal to 5 microns; the thickness of the photoresist in the photolithography process is greater than or equal to 4 microns.

18. The method for manufacturing a super junction device according to claim 15, wherein: The back P-type impurity region has a P-type net doping, and the maximum concentration of the P-type net doping in the back P-type impurity region is less than or equal to the minimum concentration of the P-type pillar; Alternatively, the back surface P-type impurity region has a net N-type doping, and the concentration of the net N-type doping in the back surface P-type impurity region is 1 / 5 to 1 / 100 of the N-type impurity concentration when no P-type impurities are injected.

19. The method for manufacturing a super junction device according to claim 15, wherein: The drain region and the back P-type impurity region are both subjected to laser annealing, and the depth range of the back P-type impurity region is less than or equal to the depth of the laser annealing.

20. The method for manufacturing a super junction device according to claim 15, wherein: The area of ​​the back P-type impurity region is 5% to 30% of the area of ​​the entire drain region.

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