Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method of forming the same, wherein the structure comprises: a first substrate having a first channel layer thereon, the first channel layer comprising a first source-drain region and a first channel region, the first channel region having a first projected pattern; a second channel layer on the first substrate, the second channel layer comprising a second source-drain region and a second channel region, the second channel region having a second projected pattern, the first projected pattern not overlapping with the second projected pattern. By the first projected pattern not overlapping with the second projected pattern, a first conductive plug on the first source-drain doped layer and a second conductive plug on the second source-drain doped layer are staggered with each other without shorting. Avoiding increasing the volume of the first source-drain doped layer or the second source-drain doped layer to achieve the non-shorting between the first conductive plug and the second conductive plug, the integration of the semiconductor structure is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the rapid development of semiconductor manufacturing technology, semiconductor devices are evolving towards higher component density and higher integration. As the component density and integration of semiconductor devices increase, the size of transistors is also becoming smaller and smaller. The reduction in transistor size makes the short-channel effect more and more significant.

[0003] To reduce short-channel effects, the FinFET was developed. The gate of a FinFET is designed with a forked 3D structure resembling a fish fin. The gate of the FinFET allows for the switching on and off of circuitry on multiple sides of the fin, effectively suppressing short-channel effects.

[0004] The integration density of both planar transistors and fin field-effect transistors remains low. To improve the integration density of semiconductor structures, a complementary field-effect transistor (CFET) device structure has been proposed, which is formed by vertically stacking one or more pairs of NFET and PFET channels.

[0005] However, existing complementary field-effect transistors still have many problems. Summary of the Invention

[0006] The technical problem solved by this invention is to provide a semiconductor structure and a method for forming the same, which can effectively improve the integration of the semiconductor structure.

[0007] To address the aforementioned problems, the present invention provides a semiconductor structure comprising: a first substrate having a first channel layer extending along a first direction, the first channel layer including a plurality of first source / drain regions and a first channel region located between adjacent first source / drain regions, the first source / drain regions and the first channel region being arranged along the first direction, and the first channel layer having a first projection pattern on the first substrate; a first isolation layer located on the first substrate, the first isolation layer covering a portion of the sidewalls of the first channel layer, and the top surface of the first isolation layer being lower than the top surface of the first channel layer; a first gate structure and a plurality of first source / drain doped layers, the first gate structure spanning the first channel region, the first source / drain doped layers located within the first source / drain regions, and the first source / drain doped layers containing first source / drain ions; a first sidewall located on the sidewalls of the first gate structure; a first dielectric layer located on the first isolation layer, the first dielectric layer covering the sidewalls of the first gate structure and the first sidewalls; and a first sidewall located on the top of the first dielectric layer, the first gate structure, and the first sidewalls. A channel stop layer on the surface of the substrate; a second channel layer located on the channel stop layer and extending along the first direction, the second channel layer including a plurality of second source / drain regions and a second channel region located between adjacent second source / drain regions, the second source / drain regions and the second channel region being arranged along the first direction, the second channel layer having a second projected pattern on the first substrate, the first projected pattern and the second projected pattern not overlapping; a second isolation layer, the second isolation layer covering a portion of the sidewalls of the second channel layer, and the top surface of the second isolation layer being lower than the top surface of the second channel layer; a second gate structure and a plurality of second source / drain doped layers, the second gate structure spanning the second channel region, the second source / drain doped layers located within the second source / drain regions, the second source / drain doped layers containing second source / drain ions, and the first source / drain ions and the second source / drain ions having different electrical types; a second sidewall located on the sidewall of the second gate structure; a second dielectric layer located on the second isolation layer, the second dielectric layer covering the sidewalls of the second gate structure and the second sidewall.

[0008] Optionally, it also includes: a first conductive plug located on the first source / drain doped layer; and a second conductive plug located on the second source / drain doped layer.

[0009] Optionally, the first source / drain ion includes N-type ions or P-type ions; the second source / drain ion includes P-type ions or N-type ions.

[0010] Optionally, the first channel layer is a single-layer structure or a multi-layer structure; when the first channel layer is a multi-layer structure, the first channel layer includes several layers of first nanowires overlapping along the normal direction of the first substrate surface, and the first gate structure surrounds the first nanowires.

[0011] Optionally, the second channel layer is a single-layer structure or a multi-layer structure; when the second channel layer is a multi-layer structure, the second channel layer includes several layers of second nanowires overlapping along the normal direction of the surface of the first substrate, and the second gate structure surrounds the second nanowires.

[0012] Optionally, the channel stop layer includes an insulating layer or a PN layer.

[0013] Accordingly, the present invention also provides a method for forming a semiconductor structure, comprising: providing a first substrate, the first substrate having a first channel layer extending along a first direction, the first channel layer including a plurality of first source / drain regions and a first channel region located between adjacent first source / drain regions, the first source / drain regions and the first channel region being arranged along the first direction, the first channel layer having a first projection pattern on the first substrate; a first isolation layer on the first substrate, the first isolation layer covering a portion of the sidewalls of the first channel layer, and the top surface of the first isolation layer being lower than the top surface of the first channel layer; forming a first dielectric layer, a first gate structure, a first sidewall and a plurality of first source / drain doped layers, the first gate structure spanning the first channel region, the first sidewall located on the sidewall of the first gate structure, the first source / drain doped layers located within the first source / drain regions, the first source / drain doped layers having first source / drain ions, the first dielectric layer covering the sidewalls of the first gate structure and the first sidewall; forming a first dielectric layer, a first gate structure, a first sidewall and a plurality of first source / drain doped layers; and forming a first dielectric layer, a first gate structure, a first sidewall and a plurality of first source / drain doped layers. A channel stop layer is formed on the top surface of one sidewall; a second channel layer extending along the first direction is formed on the channel stop layer, the second channel layer includes a plurality of second source / drain regions and a second channel region located between adjacent second source / drain regions, the second source / drain regions and the second channel region are arranged along the first direction, the second channel layer has a second projection pattern on the first substrate, the first projection pattern and the second projection pattern do not overlap; a second isolation layer is formed, the second isolation layer covers part of the sidewall of the second channel layer, and the top surface of the second isolation layer is lower than the top surface of the second channel layer; a second dielectric layer, a second gate junction, a second sidewall and a plurality of second source / drain doped layers are formed, the second gate structure spans the second channel region, the second sidewall is located on the sidewall of the second gate structure, the second source / drain doped layers are located within the second source / drain regions, the second source / drain doped layers contain second source / drain ions, and the first source / drain ions and the second source / drain ions have different electrical types, the second dielectric layer covers the sidewall of the second gate structure and the second sidewall.

[0014] Optionally, after forming the second gate structure and the second source / drain doped layer, the method further includes: forming a first conductive plug on the first source / drain doped layer; and forming a second conductive plug on the second source / drain doped layer.

[0015] Optionally, the method for forming the first dielectric layer, the first gate structure, the first sidewall, and the first source / drain doped layer includes: forming a first dummy gate structure on the first isolation layer, the first dummy gate structure spanning the first channel region; forming the first sidewall on the sidewall of the first dummy gate structure; etching the first source / drain region using the first dummy gate structure and the first sidewall as a mask to form a first source / drain opening in the first source / drain region; forming the first source / drain doped layer in the first source / drain opening; forming the first dielectric layer on the first substrate, the first dielectric layer covering the first source / drain doped layer and the sidewall of the first dummy gate structure; removing the first dummy gate structure to form a first gate opening in the first dielectric layer; and forming the first gate structure in the first gate opening.

[0016] Optionally, the method for forming the first source / drain doped layer within the first source / drain opening includes: forming a first epitaxial layer within the first source / drain opening using an epitaxial growth process; and performing a first source / drain ion implantation process after forming the first epitaxial layer to form a first source / drain ion implantation region, wherein the first source / drain ion implantation region and the first epitaxial layer together constitute the first source / drain doped layer.

[0017] Optionally, a method for forming a second channel layer extending in the first direction on the channel stop layer includes: providing an initial second substrate; bonding the initial second substrate to the channel stop layer; forming a patterned layer on the initial second substrate, the patterned layer exposing a portion of the top surface of the initial second substrate; and etching the initial second substrate using the patterned layer as a mask to form the second substrate, the second substrate having a second channel layer extending in the first direction.

[0018] Optionally, the method for forming the second dielectric layer, the second gate structure, the second sidewall, and the second source / drain doped layer includes: forming a second dummy gate structure on the second isolation layer, the second dummy gate structure spanning the second channel region; forming a second sidewall on the sidewall of the second dummy gate structure; etching the second source / drain region using the second dummy gate structure and the second sidewall as a mask to form a second source / drain opening in the second source / drain region; forming a second source / drain doped layer in the second source / drain opening; forming a second dielectric layer on the second substrate, the second dielectric layer covering the second source / drain doped layer and the sidewall of the second dummy gate structure; removing the second dummy gate structure to form a second gate opening in the second dielectric layer; and forming the second gate structure in the second gate opening.

[0019] Optionally, the method for forming the second source / drain doped layer within the second source / drain opening includes: forming a second epitaxial layer within the second source / drain opening using an epitaxial growth process; and performing a second source / drain ion implantation process after forming the second epitaxial layer to form a second source / drain ion implantation region, wherein the second source / drain ion implantation region and the second epitaxial layer together constitute the second source / drain doped layer.

[0020] Optionally, the first source / drain ion includes N-type ions or P-type ions; the second source / drain ion includes P-type ions or N-type ions.

[0021] Optionally, the first channel layer is a single-layer structure or a multi-layer structure; when the first channel layer is a multi-layer structure, the first channel layer includes several layers of first nanowires overlapping along the normal direction of the first substrate surface, and the first gate structure surrounds the first nanowires.

[0022] Optionally, the second channel layer is a single-layer structure or a multi-layer structure; when the second channel layer is a multi-layer structure, the second channel layer includes several layers of second nanowires overlapping along the normal direction of the surface of the first substrate, and the second gate structure surrounds the second nanowires.

[0023] Optionally, the channel stop layer includes an insulating layer or a PN layer.

[0024] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0025] In the structure of the technical solution of the present invention, by ensuring that the first and second projected patterns do not overlap, the first and second source / drain doped layers are spatially misaligned. This ensures that the first conductive plug on the first source / drain doped layer and the second conductive plug on the second source / drain doped layer are also misaligned and do not short-circuit. This avoids the need to increase the volume of the first or second source / drain doped layer in the first direction to prevent short-circuiting between the first and second conductive plugs, effectively reducing the area occupied by the first or second source / drain doped layer and improving the integration density of the semiconductor structure.

[0026] In the method for forming the technical solution of the present invention, by ensuring that the first and second projected patterns do not overlap, the first and second source / drain doped layers are spatially misaligned. This ensures that the first conductive plug formed on the first source / drain doped layer and the second conductive plug formed on the second source / drain doped layer are also misaligned and do not short-circuit. This avoids the need to increase the volume of the first or second source / drain doped layer in the first direction to prevent short-circuiting between the first and second conductive plugs, effectively reducing the area occupied by the first or second source / drain doped layer and improving the integration density of the semiconductor structure. Attached Figure Description

[0027] Figures 1 to 4 This is a schematic diagram of a semiconductor structure.

[0028] Figures 5 to 24 This is a schematic diagram of the steps in an embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0029] As described in the background section, existing complementary field-effect transistors still have many problems. These will be explained in detail below with reference to the accompanying drawings.

[0030] Please refer to Figures 1 to 3 , Figure 1 This is a top view of the semiconductor structure. Figure 2 yes Figure 1 Schematic diagram of the cross section along line AA. Figure 3 yes Figure 1A cross-sectional view along line BB shows the following: a first substrate 100, on which are a plurality of mutually discrete first channel layers 101 parallel to a first direction X, the plurality of first channel layers 101 arranged along a second direction Y, the first direction X being perpendicular to the second direction Y, each first channel layer 101 including a plurality of first source / drain regions A1 and a first channel region A2 located between adjacent first source / drain regions A1, the first source / drain regions A1 and the first channel region A2 being arranged along the first direction X, the first channel layer 101 having a first projection pattern S1 on the first substrate 100; a first gate structure 102 and a plurality of first source / drain doped layers 103, the first gate structure 102 spanning the first channel region A2, the first source / drain doped layers 103 located within the first source / drain region A1, the first source / drain doped layers 103 containing first source / drain ions; and a second substrate located on the first substrate 100. 200, the second substrate 200 has a plurality of mutually discrete second channel layers 201 parallel to the first direction X, the plurality of second channel layers 201 are arranged along the second direction Y, the second channel layer 201 includes a plurality of second source / drain regions B1, and a second channel region B2 located between adjacent second source / drain regions B1, the second source / drain regions B1 and the second channel region B2 are arranged along the first direction X, the second channel layer 201 has a second projection pattern S2 on the first substrate 100, the first projection pattern S1 coincides with the second projection pattern S2; a second gate structure 202 and a plurality of second source / drain doped layers 203, the second gate structure 202 spans the second channel region B2, the second source / drain doped layers 203 are located within the second source / drain region B1, the second source / drain doped layers 203 have second source / drain ions, and the first source / drain ions and the second source / drain ions have different electrical types.

[0031] Please refer to Figure 4 , Figure 4 and Figure 2 The view direction is consistent, and it also includes: a first conductive plug 104 located on the first source / drain doped layer 103; and a second conductive plug 204 located on the second source / drain doped layer 203.

[0032] In this embodiment, a first transistor is formed on the first substrate 100, and a second transistor is formed on the second substrate 200. Since the first transistor and the second transistor have different electrical types, they can constitute a CMOS transistor. Furthermore, the first transistor and the second transistor are arranged perpendicular to the surface of the first substrate 100, which effectively reduces the occupied area and thus improves the integration density of the semiconductor structure.

[0033] However, since the first projection pattern S1 and the second projection pattern S2 overlap, in order to avoid a short circuit between the first conductive plug 104 and the second conductive plug 204, the volume of the first source / drain doped layer 103 or the second source / drain doped layer 203 needs to be increased in the first direction X, which will increase the area occupied by the first transistor or the second transistor, thereby reducing the integration density of the semiconductor structure.

[0034] Based on this, the present invention provides a semiconductor structure and its formation method. By ensuring that the first and second projected patterns do not overlap, the first conductive plug formed on the first source / drain doped layer and the second conductive plug formed on the second source / drain doped layer are also staggered to avoid short circuits. This avoids the need to increase the volume of the first or second source / drain doped layer in the first direction to prevent short circuits between the first and second conductive plugs, effectively reducing the area occupied by the first or second source / drain doped layer and improving the integration density of the semiconductor structure.

[0035] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0036] Figures 5 to 24 This is a schematic diagram of the formation process of a semiconductor structure according to an embodiment of the present invention.

[0037] Please refer to Figures 5 to 8 , Figure 5 It is a 3D diagram of a semiconductor structure. Figure 6 yes Figure 5 Top view, Figure 7 yes Figure 6 Schematic diagram of the cross section along the CC line. Figure 8 yes Figure 6 A cross-sectional schematic diagram along the DD line shows a first substrate 300. The first substrate 300 has a first channel layer 301 extending along a first direction X. The first channel layer 301 includes a plurality of first source / drain regions A1 and a first channel region A2 located between adjacent first source / drain regions A1. The first source / drain regions A1 and the first channel region A2 are arranged along the first direction X. The first channel layer 301 has a first projection pattern S1 on the first substrate 300.

[0038] In this embodiment, the method for forming the first substrate 300 includes: providing an initial first substrate (not shown); forming a first patterned layer (not shown) on the initial first substrate, the first patterned layer exposing a portion of the top surface of the initial first substrate; and etching the initial first substrate using the first patterned layer as a mask to form the first substrate 300.

[0039] In this embodiment, the material of the first substrate 300 is silicon; in other embodiments, the material of the first substrate may also be germanium, silicon germanide, silicon carbide, gallium arsenide or indium gallium.

[0040] In this embodiment, the first channel layer 301 is a multilayer structure, comprising: a plurality of first nanowires 309 overlapping along the normal direction of the surface of the first substrate 300, a first sacrificial layer 310 between adjacent first nanowires 309, and the first sacrificial layer 310 and the first nanowires 309 being made of different materials.

[0041] In this embodiment, the first nanowire 309 is made of silicon, and the first sacrificial layer 310 is made of silicon-germanium.

[0042] In other embodiments, the first channel layer may also be a single-layer structure, and the material of the first channel layer is silicon.

[0043] Please refer to Figure 9 , Figure 9 and Figure 8 With the view orientation consistent, a first isolation layer 302 is formed on the first substrate 300. The first isolation layer 302 covers a portion of the sidewall of the first channel layer 301, and the top surface of the first isolation layer 302 is lower than the top surface of the first channel layer 301.

[0044] In this embodiment, the method for forming the first isolation layer 302 includes: forming an initial first isolation layer (not shown) on the first substrate 300; etching away a portion of the initial first isolation layer to form the first isolation layer 302, wherein the top surface of the first isolation layer 302 is lower than the top surface of the first channel layer 301.

[0045] The first isolation layer 302 is made of an insulating material, including silicon oxide or silicon oxynitride; in this embodiment, the first isolation layer 302 is made of silicon oxide.

[0046] In this embodiment, after forming the first isolation layer 302, the method further includes forming a first dielectric layer, a first gate structure, a first sidewall, and a plurality of first source / drain doped layers. The first gate structure spans the first channel region A2, the first sidewall is located on the sidewall of the first gate structure, the first source / drain doped layers are located within the first source / drain region A1, and the first source / drain doped layers contain first source / drain ions. The first dielectric layer covers the sidewalls of the first gate structure and the first sidewall. For the specific formation process of the first gate structure and the first source / drain doped layers, please refer to [reference needed]. Figures 10 to 13 .

[0047] Please refer to Figure 10 , Figure 10 and Figure 7 With consistent view orientation, a first pseudo-gate structure 303 is formed on the first substrate 300, and the first pseudo-gate structure 303 spans the first channel region A2.

[0048] In this embodiment, the method for forming the first pseudo-gate structure 303 includes: forming a first pseudo-gate dielectric layer on the first isolation layer 302; and forming a first pseudo-gate layer (not shown) on the first pseudo-gate dielectric layer.

[0049] In this embodiment, the material of the first dummy gate dielectric layer is silicon oxide; in other embodiments, the material of the first dummy gate dielectric layer may also be silicon oxynitride.

[0050] In this embodiment, the material of the first pseudo-gate layer is polycrystalline silicon.

[0051] Please continue to refer to this. Figure 10 It also includes: forming a first sidewall 304 on the sidewall of the first pseudo-gate structure 303.

[0052] In this embodiment, the method for forming the first sidewall 304 includes: forming an initial first sidewall (not shown) on the first isolation layer 302, the sidewall of the first pseudo-gate dielectric layer and the first pseudo-gate layer, and the top surface of the first pseudo-gate layer; and etching back the initial first sidewall until the top surface of the first isolation layer 302 and the first pseudo-gate layer is exposed, thereby forming the first sidewall 304.

[0053] In this embodiment, the first sidewall 304 is made of silicon nitride.

[0054] Please refer to Figure 11 Using the first pseudo-gate structure 303 and the first sidewall 304 as a mask, the first source / drain region A1 is etched to form a first source / drain opening (not shown) in the first source / drain region A1; and the first source / drain doped layer 305 is formed in the first source / drain opening.

[0055] In this embodiment, the method for forming the first source / drain doped layer 305 within the first source / drain opening includes: forming a first epitaxial layer (not shown) within the first source / drain opening using an epitaxial growth process; and performing a first source / drain ion implantation process after forming the first epitaxial layer to form a first source / drain ion implantation region (not shown), wherein the first source / drain ion implantation region and the first epitaxial layer together constitute the first source / drain doped layer 305.

[0056] In this embodiment, the first source / drain ion is a P-type ion; in other embodiments, the first source / drain ion may also be an N-type ion.

[0057] Please continue to refer to this. Figure 11 In this embodiment, before forming the first source / drain doped layer 305, the method further includes: etching back a portion of the first sacrificial layer 310 exposed by the first source / drain opening, forming a first isolation groove (not shown) between adjacent first nanowires 309; and forming a first barrier layer 311 within the first isolation groove.

[0058] In this embodiment, the first barrier layer 311 is made of silicon nitride.

[0059] Please refer to Figure 12 A first dielectric layer 306 is formed on the first substrate 300, and the first dielectric layer 306 covers the first source / drain doped layer 305 and the sidewall of the first dummy gate structure 303.

[0060] In this embodiment, the method for forming the first dielectric layer 306 includes: forming an initial first dielectric layer (not shown) on the first substrate 300, the initial first dielectric layer covering the first dummy gate structure 303 and the first source / drain doped layer 305; and planarizing the initial first dielectric layer until the top surface of the first dummy gate structure 303 is exposed, thereby forming the first dielectric layer 306.

[0061] In this embodiment, the first dielectric layer 306 is made of silicon oxide; in other embodiments, the first dielectric layer may also be made of a low-k dielectric material (referring to a dielectric material with a relative permittivity of less than 3.9) or an ultra-low-k dielectric material (referring to a dielectric material with a relative permittivity of less than 2.5).

[0062] Please refer to Figure 13 Remove the first dummy gate structure 303 and form a first gate opening (not shown) in the first dielectric layer 306; remove the first sacrificial layer 310 and form a first gate trench (not shown) in the first dielectric layer 306; form the first gate structure 307 in the first gate opening and the first gate trench.

[0063] In this embodiment, the first gate structure 307 includes: a first gate dielectric layer and a first gate layer (not shown) located on the first gate dielectric layer.

[0064] In this embodiment, the first gate structure 309 completely surrounds the first nanowire 309.

[0065] At this point, the fabrication process of the first transistor structure formed on the first substrate 300 is complete.

[0066] Please refer to Figures 14 to 16 , Figure 14 This is a top view of the semiconductor structure. Figure 15 yes Figure 14 Schematic diagram of the cross section along the EE line. Figure 16 yes Figure 14 A cross-sectional view along the FF line shows that after forming a first transistor structure on the first substrate 300, a second channel layer 401 extending along the first direction X is formed on the first substrate 300. The second channel layer 401 includes a plurality of second source / drain regions B1 and a second channel region B2 located between adjacent second source / drain regions B1. The second source / drain regions B1 and the second channel region B2 are arranged along the first direction X. The second channel layer 401 has a second projection pattern S2 on the first substrate 300. The first projection pattern S1 and the second projection pattern S2 do not coincide.

[0067] In this embodiment, by ensuring that the first projection pattern S1 and the second projection pattern S2 do not overlap, the first source / drain doped layer 305 and the subsequently formed second source / drain doped layer are spatially misaligned. This ensures that the first conductive plug formed on the first source / drain doped layer 305 and the second conductive plug formed on the second source / drain doped layer are also misaligned and do not short-circuit. This avoids the need to increase the volume of the first source / drain doped layer 305 or the second source / drain doped layer in the first direction X to prevent short-circuiting between the first and second conductive plugs, effectively reducing the area occupied by the first source / drain doped layer 305 or the second source / drain doped layer and improving the integration density of the semiconductor structure.

[0068] In this embodiment, the method of forming a second channel layer 401 extending along the first direction X on the first substrate 300 includes: providing an initial second substrate (not shown); bonding the initial second substrate to the first substrate 300; forming a patterned layer (not shown) on the initial second substrate, the patterned layer exposing a portion of the top surface of the initial second substrate; etching the initial second substrate using the patterned layer as a mask to form the second substrate 400, the second substrate 400 having a second channel layer 401 extending along the first direction X.

[0069] In this embodiment, the material and structure of the second channel layer 401 are the same as those of the first channel layer 301, and will not be described again here.

[0070] Please continue to refer to this. Figures 14 to 16 Before bonding the second substrate 400, the method further includes: forming a channel stop layer 312 on the first dielectric layer 306 and the first gate structure 307, wherein the second substrate 400 is bonded to the channel stop layer 312.

[0071] In this embodiment, the channel stop layer 312 is an insulating layer, and the material of the insulating layer is silicon oxide; in other embodiments, the channel stop layer may also be a PN layer.

[0072] Please refer to Figure 17 , Figure 17 and Figure 16 With the view orientation consistent, a second isolation layer 402 is formed on the second substrate 400. The second isolation layer 402 covers a portion of the sidewall of the second channel layer 401, and the top surface of the second isolation layer 402 is lower than the top surface of the second channel layer 401.

[0073] In this embodiment, the material and formation process of the second isolation layer 402 are the same as those of the first isolation layer 302, and will not be described again here.

[0074] In this embodiment, after forming the second isolation layer 402, the method further includes forming a second dielectric layer, a second gate structure, a second sidewall, and a plurality of second source / drain doped layers. The second gate structure spans the second channel region B2, the second sidewall is located on the sidewall of the second gate structure, the second source / drain doped layers are located within the second source / drain region B1, and the second source / drain doped layers contain second source / drain ions. The second dielectric layer covers the sidewalls of the second gate structure and the second sidewall. For the specific formation process of the second gate structure and the second source / drain doped layers, please refer to [reference needed]. Figures 18 to 23 .

[0075] Please refer to Figure 18 , Figure 18 and Figure 15 With the view orientation consistent, a second pseudo-gate structure 403 is formed on the second substrate 400, and the second pseudo-gate structure 403 spans the second channel region B2.

[0076] In this embodiment, the materials, structures, and formation processes of the second pseudo-gate structure 403 and the second sidewall 404 are the same as those of the first pseudo-gate structure 303 and the first sidewall 304, and will not be described again here.

[0077] Please refer to Figure 19 Using the second pseudo-gate structure 403 and the second sidewall 404 as a mask, the second source / drain region B1 is etched to form a second source / drain opening (not shown) in the second source / drain region B1; and a second source / drain doped layer 405 is formed in the second source / drain opening.

[0078] In this embodiment, the formation process of the second source / drain doped layer 405 is the same as the formation process of the first source / drain doped layer 305, and will not be described again here.

[0079] It should be noted that the second source / drain ion is different from the first source / drain ion. In this embodiment, the second source / drain ion is an N-type ion; in other embodiments, the second source / drain ion may also be a P-type ion.

[0080] Please refer to Figure 20 A second dielectric layer 406 is formed on the second substrate 400, and the second dielectric layer 403 covers the second source / drain doped layer 405 and the sidewalls of the second pseudo-gate structure 403.

[0081] In this embodiment, the material and formation process of the second dielectric layer 406 are the same as those of the first dielectric layer 306, and will not be described again here.

[0082] Please refer to Figures 21 to 23 , Figure 21 This is a top view of the semiconductor structure. Figure 22 yes Figure 21 Schematic diagram of the cross section along the GG line. Figure 23 yes Figure 21 A schematic diagram of the cross-section along the HH line shows the removal of the second dummy gate structure 403, the formation of a second gate opening (not shown) within the second dielectric layer 406; the removal of the second sacrificial layer (not shown), the formation of a second gate trench (not shown) within the second dielectric layer 406; and the formation of the second gate structure 407 within the second gate opening and the second gate trench.

[0083] In this embodiment, the material, structure and formation process of the second gate structure 407 are the same as those of the first gate structure 307, and will not be described again here.

[0084] At this point, the fabrication process of the second transistor structure formed on the second substrate 400 is complete. Since the first transistor and the second transistor have different electrical types, they can be combined to form a CMOS transistor. Furthermore, the arrangement of the first and second transistors perpendicular to the surface of the first substrate 300 effectively reduces the occupied area, thereby improving the integration density of the semiconductor structure.

[0085] Please refer to Figure 24 , Figure 24 and Figure 23 With the view orientation consistent, after the second transistor is formed, a first conductive plug 308 is formed on the first source / drain doped layer 305; and a second conductive plug 408 is formed on the second source / drain doped layer 405.

[0086] In this embodiment, by ensuring that the first central axis a and the second central axis b do not coincide, the first source / drain doped layer 305 and the second source / drain doped layer 405 are spatially misaligned. This results in the first conductive plug 308 on the first source / drain doped layer 305 and the second conductive plug 408 on the second source / drain doped layer 405 being also misaligned and avoiding short circuits. This avoids the need to increase the volume of the first source / drain doped layer 305 or the second source / drain doped layer 405 in the first direction X to prevent short circuits between the first conductive plug 308 and the second conductive plug 408, effectively reducing the area occupied by the first source / drain doped layer 305 or the second source / drain doped layer 405 and improving the integration density of the semiconductor structure.

[0087] Accordingly, an embodiment of the present invention also provides a semiconductor structure, please refer to [link / reference needed]. Figure 24The system includes: a first substrate 300 having a first channel layer 301 extending along a first direction X, the first channel layer 301 including a plurality of first source / drain regions A1 and a first channel region A2 located between adjacent first source / drain regions A1, the first source / drain regions A1 and the first channel region A2 being arranged along the first direction X, and the first channel layer 301 having a first projection pattern S1 on the first substrate 300; and a first isolation layer 302 located on the first substrate 300, the first isolation layer 302 covering a portion of the sidewalls of the first channel layer 301, and the top surface of the first isolation layer 302 being lower than the first channel layer 301. The top surface of channel layer 301; a first gate structure 307 and a plurality of first source / drain doped layers 305, the first gate structure 307 spanning the first channel region A2, the first source / drain doped layers 305 located within the first source / drain region A1, and the first source / drain doped layers 305 containing first source / drain ions; a first sidewall 304 located on the sidewall of the first gate structure 307; a first dielectric layer 306 located on the first isolation layer 302, the first dielectric layer 306 covering the sidewalls of the first gate structure 307 and the first sidewall 304; a channel located on the top surface of the first dielectric layer 306, the first gate structure 307 and the first sidewall 304. Stop layer 312; a second channel layer 402 located on the channel stop layer 312 and extending along the first direction X, the second channel layer 402 including a plurality of second source / drain regions B1 and a second channel region B2 located between adjacent second source / drain regions B1, the second source / drain regions B1 and the second channel region B2 being arranged along the first direction X, the second channel layer 401 having a second projection pattern S2 on the first substrate 300, the first projection pattern S1 and the second projection pattern S2 not coinciding; a second isolation layer 402, the second isolation layer 402 covering a portion of the sidewalls of the second channel layer 401, and the second isolation layer 402 The top surface is lower than the top surface of the second channel layer 401; a second gate structure 407 and a plurality of second source / drain doped layers 405, the second gate structure 407 spanning the second channel region B2, the second source / drain doped layers 405 located within the second source / drain region B1, the second source / drain doped layers 405 containing second source / drain ions, and the first source / drain ions having a different electrical type from the second source / drain ions; a second sidewall 404 located on the sidewall of the second gate structure 407; a second dielectric layer 406 located on the second isolation layer 402, the second dielectric layer 406 covering the sidewalls of the second gate structure 407 and the second sidewall 404.

[0088] In this embodiment, by ensuring that the first projection pattern S1 and the second projection pattern S2 do not overlap, the first source / drain doped layer 305 and the second source / drain doped layer 405 are spatially misaligned. This ensures that the first conductive plug 308 on the first source / drain doped layer 305 and the second conductive plug 408 on the second source / drain doped layer 405 are also misaligned and do not short-circuit. This avoids the need to increase the volume of the first source / drain doped layer 305 or the second source / drain doped layer 405 in the first direction X to prevent short-circuiting between the first conductive plug 305 and the second conductive plug 308, effectively reducing the area occupied by the first source / drain doped layer 305 or the second source / drain doped layer 405 and improving the integration density of the semiconductor structure.

[0089] In this embodiment, it further includes: a first conductive plug 308 located on the first source / drain doped layer 305; and a second conductive plug 408 located on the second source / drain doped layer 405.

[0090] In this embodiment, the first source / drain ion is a P-type ion and the second source / drain ion is an N-type ion; in other embodiments, the first source / drain ion may also be an N-type ion and the second source / drain ion may be a P-type ion.

[0091] In this embodiment, the channel stop layer 312 is an insulating layer, and the material of the insulating layer is silicon oxide; in other embodiments, the channel stop layer may also be a PN layer.

[0092] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: A first substrate has a first channel layer extending along a first direction. The first channel layer includes a plurality of first source / drain regions and a first channel region located between adjacent first source / drain regions. The first source / drain regions and the first channel region are arranged along the first direction. The first channel layer has a first projection pattern on the first substrate. A first isolation layer is located on the first substrate, the first isolation layer covers a portion of the sidewall of the first trench layer, and the top surface of the first isolation layer is lower than the top surface of the first trench layer; A first gate structure and a plurality of first source / drain doped layers, the first gate structure spanning the first channel region, the first source / drain doped layers being located within the first source / drain region, and the first source / drain doped layers having first source / drain ions. The first sidewall located on the sidewall of the first gate structure; A first dielectric layer is located on the first isolation layer, and the first dielectric layer covers the sidewalls of the first gate structure and the first sidewall; A channel stop layer located on the top surface of the first dielectric layer, the first gate structure, and the first sidewall; A second channel layer is located on the channel stop layer and extends along the first direction. The second channel layer includes a plurality of second source / drain regions and a second channel region located between adjacent second source / drain regions. The second source / drain regions and the second channel region are arranged along the first direction. The second channel layer has a second projection pattern on the first substrate. The first projection pattern and the second projection pattern do not overlap. A second isolation layer covers a portion of the sidewall of the second channel layer, and the top surface of the second isolation layer is lower than the top surface of the second channel layer; The second gate structure and a plurality of second source / drain doped layers, the second gate structure spanning the second channel region, the second source / drain doped layers located within the second source / drain region, the second source / drain doped layers containing second source / drain ions, and the first source / drain ions having different electrical types from the second source / drain ions; The second sidewall is located on the sidewall of the second gate structure; A second dielectric layer is located on the second isolation layer, and the second dielectric layer covers the sidewalls of the second gate structure and the second sidewall.

2. The semiconductor structure as described in claim 1, characterized in that, Also includes: The first conductive plug is located on the first source / drain doped layer; The second conductive plug is located on the second source / drain doped layer.

3. The semiconductor structure as described in claim 1, characterized in that, The first source / drain ion includes N-type ions or P-type ions; the second source / drain ion includes P-type ions or N-type ions.

4. The semiconductor structure as described in claim 1, characterized in that, The first channel layer is a single-layer structure or a multi-layer structure; when the first channel layer is a multi-layer structure, the first channel layer includes several layers of first nanowires overlapping along the normal direction of the first substrate surface, and the first gate structure surrounds the first nanowires.

5. The semiconductor structure as described in claim 1, characterized in that, The second channel layer is a single-layer structure or a multi-layer structure; when the second channel layer is a multi-layer structure, the second channel layer includes several layers of second nanowires overlapping along the normal direction of the surface of the first substrate, and the second gate structure surrounds the second nanowires.

6. The semiconductor structure as described in claim 1, characterized in that, The channel stop layer includes an insulating layer or a PN layer.

7. A method for forming a semiconductor structure, characterized in that, include: A first substrate is provided, on which a first channel layer extends along a first direction, the first channel layer including a plurality of first source / drain regions and a first channel region located between adjacent first source / drain regions, the first source / drain regions and the first channel region being arranged along the first direction, and the first channel layer having a first projection pattern on the first substrate. A first isolation layer on the first substrate, the first isolation layer covering a portion of the sidewall of the first trench layer, and the top surface of the first isolation layer being lower than the top surface of the first trench layer; A first dielectric layer, a first gate structure, a first sidewall, and a plurality of first source / drain doped layers are formed. The first gate structure spans the first channel region. The first sidewall is located on the sidewall of the first gate structure. The first source / drain doped layers are located within the first source / drain region. The first source / drain doped layers contain first source / drain ions. The first dielectric layer covers the sidewall of the first gate structure and the first sidewall. A channel stop layer is formed on the top surface of the first dielectric layer, the first gate structure, and the first sidewall; A second channel layer extending along the first direction is formed on the channel stop layer. The second channel layer includes a plurality of second source / drain regions and a second channel region located between adjacent second source / drain regions. The second source / drain regions and the second channel region are arranged along the first direction. The second channel layer has a second projection pattern on the first substrate. The first projection pattern and the second projection pattern do not overlap. A second isolation layer is formed, which covers a portion of the sidewall of the second channel layer, and the top surface of the second isolation layer is lower than the top surface of the second channel layer; A second dielectric layer, a second gate structure, a second sidewall, and a plurality of second source / drain doped layers are formed. The second gate structure spans the second channel region. The second sidewall is located on the sidewall of the second gate structure. The second source / drain doped layers are located within the second source / drain region. The second source / drain doped layers contain second source / drain ions, and the first source / drain ions and the second source / drain ions have different electrical types. The second dielectric layer covers the sidewalls of the second gate structure and the second sidewall.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, After forming the second gate structure and the second source / drain doped layer, the method further includes: forming a first conductive plug on the first source / drain doped layer; and forming a second conductive plug on the second source / drain doped layer.

9. The method for forming a semiconductor structure as described in claim 7, characterized in that, The method for forming the first dielectric layer, the first gate structure, the first sidewall, and the first source / drain doped layer includes: forming a first dummy gate structure on the first isolation layer, the first dummy gate structure spanning the first channel region; forming the first sidewall on the sidewall of the first dummy gate structure; etching the first source / drain region using the first dummy gate structure and the first sidewall as a mask to form a first source / drain opening in the first source / drain region; forming the first source / drain doped layer in the first source / drain opening; forming the first dielectric layer on the first substrate, the first dielectric layer covering the first source / drain doped layer and the sidewall of the first dummy gate structure; removing the first dummy gate structure to form a first gate opening in the first dielectric layer; and forming the first gate structure in the first gate opening.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The method for forming the first source / drain doped layer within the first source / drain opening includes: forming a first epitaxial layer within the first source / drain opening using an epitaxial growth process; and performing a first source / drain ion implantation process after forming the first epitaxial layer to form a first source / drain ion implantation region, wherein the first source / drain ion implantation region and the first epitaxial layer together constitute the first source / drain doped layer.

11. The method for forming a semiconductor structure as described in claim 7, characterized in that, A method for forming a second channel layer extending in the first direction on the channel stop layer includes: providing an initial second substrate; bonding the initial second substrate to the channel stop layer; forming a patterned layer on the initial second substrate, the patterned layer exposing a portion of the top surface of the initial second substrate; and etching the initial second substrate using the patterned layer as a mask to form a second substrate having a second channel layer extending in the first direction.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The method for forming the second dielectric layer, the second gate structure, the second sidewall, and the second source / drain doped layer includes: forming a second dummy gate structure on the second isolation layer, the second dummy gate structure spanning the second channel region; forming a second sidewall on the sidewall of the second dummy gate structure; etching the second source / drain region using the second dummy gate structure and the second sidewall as a mask to form a second source / drain opening in the second source / drain region; forming a second source / drain doped layer in the second source / drain opening; forming a second dielectric layer on the second substrate, the second dielectric layer covering the second source / drain doped layer and the sidewall of the second dummy gate structure; removing the second dummy gate structure to form a second gate opening in the second dielectric layer; and forming a second gate structure in the second gate opening.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The method for forming the second source / drain doped layer within the second source / drain opening includes: forming a second epitaxial layer within the second source / drain opening using an epitaxial growth process; and performing a second source / drain ion implantation process after forming the second epitaxial layer to form a second source / drain ion implantation region, wherein the second source / drain ion implantation region and the second epitaxial layer together constitute the second source / drain doped layer.

14. The method for forming a semiconductor structure as described in claim 7, characterized in that, The first source / drain ion includes N-type ions or P-type ions; the second source / drain ion includes P-type ions or N-type ions.

15. The method for forming a semiconductor structure as described in claim 7, characterized in that, The first channel layer is a single-layer structure or a multi-layer structure; when the first channel layer is a multi-layer structure, the first channel layer includes several layers of first nanowires overlapping along the normal direction of the first substrate surface, and the first gate structure surrounds the first nanowires.

16. The method for forming a semiconductor structure as described in claim 7, characterized in that, The second channel layer is a single-layer structure or a multi-layer structure; when the second channel layer is a multi-layer structure, the first channel layer includes several layers of second nanowires overlapping along the normal direction of the first substrate surface, and the second gate structure surrounds the second nanowires.

17. The method for forming a semiconductor structure as described in claim 7, characterized in that, The channel stop layer includes an insulating layer or a PN layer.

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