IGBT device and method of manufacturing the same

Abstract

The application provides an IGBT device and a preparation method thereof, and the device comprises: a substrate, an emitter, an IGBT gate and a collector of the IGBT device are formed on the substrate; a dummy gate is arranged between the gate and the emitter; a first NMOS tube, a source and a gate of the first NMOS tube are electrically connected with the IGBT gate, and a drain is electrically connected with the dummy gate; a second NMOS tube, a source of the second NMOS tube is electrically connected with the dummy gate, a drain is electrically connected with the emitter, and a gate is electrically connected with the emitter through an inductor; and a PMOS tube, a source of the PMOS tube is electrically connected with the dummy gate, a drain is electrically connected with the emitter, and a gate is electrically connected with the emitter through an inductor. By controlling the potential change of the dummy gate in different working states (on state and off process) of the device, the device heat can be effectively improved, the power density is improved, and then the device performance is improved, so that the IGBT device can be used for higher frequency applications.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit design and manufacturing, and in particular relates to an IGBT device and its fabrication method. Background Technology

[0002] An Insulated Gate Bipolar Transistor (IGBT) is a composite, fully controllable, voltage-driven power semiconductor device composed of a Bipolar Junction Transistor (BJT) and a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). IGBT devices have advantages such as low saturation voltage drop, high current density, low drive power, and fast switching speed, making them suitable for power management systems with a withstand voltage of 600V or higher.

[0003] The losses of IGBT devices typically include conduction losses and switching losses. In device design, a trade-off usually needs to be made between conduction losses and switching losses. In order to optimize the switching losses of the device, a dummy gate is usually used to reduce the switching losses of the device. However, setting a dummy gate will increase the conduction losses of the IGBT device.

[0004] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide an IGBT device and its fabrication method to solve the problem of large conduction losses and / or switching losses in the prior art IGBT devices.

[0006] To achieve the above and other related objectives, the present invention provides an IGBT device, comprising: a substrate on which an emitter, an IGBT gate, and a collector of the IGBT device are formed; a dummy gate disposed between the gate and the emitter; a first NMOS transistor disposed on the substrate and between the IGBT gate and the dummy gate, wherein the source and gate of the first NMOS transistor are electrically connected to the IGBT gate, and the drain is electrically connected to the dummy gate; a second NMOS transistor disposed on the substrate and between the dummy gate and the emitter, wherein the source of the second NMOS transistor is electrically connected to the dummy gate, the drain is electrically connected to the emitter, and the gate is electrically connected to the emitter through an inductor; and a PMOS transistor disposed on the substrate and between the dummy gate and the emitter, wherein the source of the PMOS transistor is electrically connected to the dummy gate, the drain is electrically connected to the emitter, and the gate is electrically connected to the emitter through an inductor.

[0007] Optionally, when the IGBT device is turned on, a threshold voltage is applied to the gate of the IGBT, and the threshold voltage is simultaneously applied to the gate of the first NMOS transistor to turn on the first NMOS transistor, thereby connecting the gate of the IGBT with the dummy gate, and forming a channel below the dummy gate to reduce the conduction loss of the IGBT device.

[0008] Optionally, when the IGBT device is turned on, the current at the emitter increases, and there is a voltage change in the inductance between the PMOS transistor and the emitter, thereby turning on the PMOS transistor and connecting the dummy gate to the emitter, thereby reducing the turn-on loss of the IGBT device.

[0009] Optionally, when the IGBT device is turned off, the current at the emitter decreases, and there is a voltage change in the inductance between the second NMOS transistor and the emitter, which causes the second NMOS transistor to turn on, connecting the dummy gate to the emitter, thereby reducing the turn-off loss of the IGBT device.

[0010] Optionally, the threshold voltage of the first NMOS transistor is less than or equal to the threshold voltage of the IGBT gate, and the threshold voltage of the IGBT gate differs from the threshold voltage of the first NMOS transistor by less than or equal to 5V.

[0011] Optionally, the IGBT gate and the dummy gate are configured as rings, with the dummy gate surrounding the emitter and the IGBT gate surrounding the dummy gate.

[0012] Optionally, the substrate includes a first side and a second side opposite to each other, the emitter and the IGBT gate are disposed on the first side of the substrate, the collector is disposed on the second side of the substrate, and / or the IGBT device further includes a field cutoff layer disposed in the substrate and close to the collector.

[0013] Optionally, the inductance value of the inductor is 10nH to 20nH.

[0014] The present invention also provides a method for fabricating an IGBT device, the method comprising the steps of: providing a substrate, forming an emitter, an IGBT gate, a collector, and a dummy gate of an IGBT device on the substrate, the dummy gate being disposed between the gate and the emitter; disposing a first NMOS transistor on the substrate, the first NMOS transistor being disposed between the IGBT gate and the dummy gate, the source and gate of the first NMOS transistor being electrically connected to the IGBT gate, and the drain being electrically connected to the dummy gate; disposing a second NMOS transistor on the substrate, the second NMOS transistor being disposed between the dummy gate and the emitter, the source of the second NMOS transistor being electrically connected to the dummy gate, the drain being electrically connected to the emitter, and the gate being electrically connected to the emitter through an inductor; and disposing a PMOS transistor on the substrate, the PMOS transistor being disposed between the dummy gate and the emitter, the source of the PMOS transistor being electrically connected to the dummy gate, the drain being electrically connected to the emitter, and the gate being electrically connected to the emitter through an inductor.

[0015] Optionally, the process of fabricating a first NMOS transistor, a second NMOS transistor, and a PMOS transistor on the substrate includes the following steps: forming a first P-well and a second P-well in the substrate using an ion implantation process, and forming an N-well in the substrate; forming a gate dielectric layer and a gate layer on the substrate, and forming an IGBT gate, a dummy gate, the gate of the first NMOS transistor, the gate of the second NMOS transistor, and the gate of the PMOS transistor using a patterning process; forming the source and drain of the first NMOS transistor in the first P-well using an ion implantation process, forming the source and drain of the second NMOS transistor in the second P-well, and forming the PMOS transistor in the N-well. The PMOS transistor has a source and a drain. An insulating layer is formed on the substrate, a contact hole is formed in the insulating layer, a metal layer is formed on the contact hole and the insulating layer, and a wiring layer is formed by a patterning process. Through the contact hole and the wiring layer, the source and gate of the first NMOS transistor are electrically connected to the gate of the IGBT, and the drain is electrically connected to the dummy gate. The source of the second NMOS transistor is electrically connected to the dummy gate, and the drain is electrically connected to the emitter. The gate is connected to a contact point. The source of the PMOS transistor is electrically connected to the dummy gate, and the drain is electrically connected to the emitter. The gate is connected to a contact point.

[0016] Optionally, the method further includes the step of connecting an inductor between the contact point of the gate of the second NMOS transistor and the gate of the PMOS transistor and the emitter via an external pin, wherein the inductance value of the inductor is 10nH to 20nH.

[0017] Optionally, when the IGBT device is turned on, a threshold voltage is applied to the IGBT gate, and the threshold voltage is simultaneously applied to the gate of the first NMOS transistor to turn on the first NMOS transistor, thereby connecting the IGBT gate with the dummy gate. A channel is formed below the dummy gate to reduce the conduction loss of the IGBT device. When the IGBT device is turned on, the emitter current increases, and there is a voltage change in the inductance between the PMOS transistor and the emitter, thereby turning on the PMOS transistor and connecting the dummy gate with the emitter, thereby reducing the turn-on loss of the IGBT device. When the IGBT device is turned off, the emitter current decreases, and there is a voltage change in the inductance between the second NMOS transistor and the emitter, thereby turning on the second NMOS transistor and connecting the dummy gate with the emitter, thereby reducing the turn-off loss of the IGBT device.

[0018] Optionally, the threshold voltage of the first NMOS transistor is less than or equal to the threshold voltage of the IGBT gate, and the threshold voltage of the IGBT gate differs from the threshold voltage of the first NMOS transistor by less than or equal to 5V.

[0019] Optionally, the IGBT gate and the dummy gate are configured as rings, with the dummy gate surrounding the emitter and the IGBT gate surrounding the dummy gate.

[0020] Optionally, the substrate includes a first side and a second side opposite to each other, the emitter and the IGBT gate are disposed on the first side of the substrate, the collector is disposed on the second side of the substrate, and / or the IGBT device further includes a field cutoff layer disposed in the substrate and close to the collector.

[0021] As described above, the IGBT device and its fabrication method of the present invention have the following beneficial effects:

[0022] In this invention, when the IGBT device is turned on, a threshold voltage is applied to the IGBT gate. This threshold voltage is simultaneously applied to the gate of a first NMOS transistor, causing the first NMOS transistor to conduct. This connects the IGBT gate to a dummy gate, forming a channel beneath the dummy gate to reduce the IGBT device's turn-on losses. When the IGBT device is turned on, the emitter current increases, causing a voltage change in the inductance between the PMOS transistor and its emitter. This causes the PMOS transistor to conduct, connecting the dummy gate to the emitter and reducing the IGBT device's turn-on losses. When the IGBT device is turned off, the emitter current decreases, causing a voltage change in the inductance between the second NMOS transistor and its emitter. This causes the second NMOS transistor to conduct, connecting the dummy gate to the emitter and reducing the IGBT device's turn-off losses. By controlling the potential change of the dummy gate during different operating states (on-state and off-state), this invention effectively improves device heating, increases power density, and ultimately enhances device performance, enabling the IGBT device to be used in higher frequency applications.

[0023] The first NMOS transistor, the second NMOS transistor, and the PMOS transistor of the present invention are disposed between the IGBT gate, the dummy gate, and the emitter, without occupying additional device area. This ensures that the device can reduce both turn-off and turn-on losses in a smaller volume. Furthermore, the present invention is compatible with the manufacturing process of conventional IGBT devices, without requiring additional manufacturing equipment, and can effectively control the manufacturing cost of the device. Attached Figure Description

[0024] The accompanying drawings, which form part of this specification, are used to provide a further understanding of the embodiments of this application and to illustrate the implementation of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application.

[0025] Figure 1 The diagram shows the layout structure of an IGBT device according to an embodiment of the present invention.

[0026] Figure 2 The diagram shown is a schematic diagram of the circuit principle of an IGBT device according to an embodiment of the present invention.

[0027] Figures 3-9 The diagram shows the structural schematics of each step in the fabrication method of the IGBT device according to an embodiment of the present invention.

[0028] Component designation explanation

[0029] 10 IGBT gate

[0030] 11. Dummy gate

[0031] 12 emitters

[0032] 13 First NMOS transistor

[0033] 14 Second NMOS transistor

[0034] 15 Inductors

[0035] 16 PMOS transistors

[0036] 101 substrate

[0037] 102 First P-well

[0038] 103 Second P-well

[0039] 104 First NMOS Gate

[0040] 105 Second NMOS Gate

[0041] 106 First NMOS Source

[0042] 107 First NMOS drain

[0043] 108 Second NMOS Source

[0044] 109 Second NMOS drain

[0045] 110 Insulation Layer

[0046] 111 First wiring

[0047] 112 Second wiring

[0048] 113 Contact Point

[0049] 201 N well

[0050] 202 PMOS gate

[0051] 203 PMOS source

[0052] 204 PMOS drain Detailed Implementation

[0053] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0054] It should be emphasized that the term "including / comprises" as used herein refers to the presence of a feature, whole, step, or component, but does not exclude the presence or addition of one or more other features, wholes, steps, or components.

[0055] Features described and / or illustrated for one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0056] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0057] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0058] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0059] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0060] like Figures 1-9As shown, this embodiment provides an IGBT device, which includes: a substrate 101 on which an emitter 12, an IGBT gate 10, and a collector are formed; a dummy gate 11 disposed between the gate and the emitter 12; a first NMOS transistor 13 disposed on the substrate 101 and between the IGBT gate 10 and the dummy gate 11, wherein the source 109 and gate 104 of the first NMOS transistor 13 are electrically connected to the IGBT gate 10, and the drain 107 is electrically connected to the dummy gate 11; and a second NMOS transistor 14. S-channel transistor 14 is disposed on the substrate 101 and between the dummy gate 11 and the emitter 12. The source 108 of the second NMOS transistor 14 is electrically connected to the dummy gate 11, the drain 109 is electrically connected to the emitter 12, and the gate 105 is electrically connected to the emitter 12 through the inductor 15. PMOS transistor 16 is disposed on the substrate 101 and between the dummy gate 11 and the emitter 12. The source 203 of the PMOS transistor 16 is electrically connected to the dummy gate 11, the drain 204 is electrically connected to the emitter 12, and the gate 202 is electrically connected to the emitter 12 through the inductor 15.

[0061] The substrate 101 may be, for example, a silicon substrate 101, and may also include other semiconductors, such as germanium, silicon carbide (SiC), or silicon germanium (SiGe). The substrate 101 may include compound semiconductors and / or alloy semiconductors, such as gallium nitride, gallium arsenide, etc. Furthermore, the substrate 101 may include an epitaxial layer (epitaxy layer) and may be strained to improve performance. In this embodiment, the substrate 101 includes drift regions, such as lightly doped N-type drift regions.

[0062] The substrate 101 includes a first side and a second side opposite to each other. The emitter 12 and the IGBT gate 10 are disposed on the first side of the substrate 101, and the collector is disposed on the second side of the substrate 101. The IGBT device further includes a field cutoff layer disposed in the substrate 101 and close to the collector.

[0063] In one embodiment, the emitter 12 of the IGBT device includes an N+ type emitter region and a P- type body region disposed between the N+ type emitter region and the N- type drift region, which is not shown in the figure.

[0064] like Figure 1As shown, the IGBT gate 10 and the dummy gate 11 are configured as rings, such as rectangular rings, rounded rectangular rings, elliptical rings, circular rings, etc. The dummy gate 11 surrounds the emitter 12, and the IGBT gate 10 surrounds the dummy gate 11. There is a gap between the IGBT gate 10 and the dummy gate 11, and there is a gap between the dummy gate 11 and the emitter 12.

[0065] like Figure 1 and Figure 9 As shown, where, Figure 9 Displayed as Figure 1 The diagram shows cross-sectional views at points A-A' and B-B', where the left side shows the cross-sectional view at A-A' and the right side shows the cross-sectional view at B-B'. The first NMOS transistor 13 is disposed on the substrate 101 and between the IGBT gate 10 and the dummy gate 11. The first NMOS transistor 13 includes a first P-well 102 disposed in the substrate 101, a first NMOS gate 104 located on the first P-well 102, and source and drain terminals disposed in the first P-well 102 on both sides of the first NMOS gate 104. In one embodiment, the threshold voltage of the first NMOS transistor 13 is less than or equal to the threshold voltage of the IGBT gate 10, and the difference between the threshold voltage of the IGBT gate 10 and the threshold voltage of the first NMOS transistor 13 is less than or equal to 5V. For example, the threshold voltage of the IGBT device gate can be 15V, and the threshold voltage of the first NMOS transistor 13 gate can be set between 13.5V and 15V. This invention effectively improves device heating, increases power density, and enhances device performance by controlling the potential change of the dummy gate during different operating states of the device, enabling IGBT devices to be used in higher frequency applications.

[0066] like Figure 1 and Figure 9 As shown, the second NMOS transistor 14 is disposed on the substrate 101 and between the dummy gate 11 and the emitter 12. The second NMOS transistor 14 includes a second P-well 103 disposed in the substrate 101, a second NMOS gate 105 located on the second P-well 103, and a source and drain disposed in the second P-well 103 on both sides of the second NMOS gate 105.

[0067] like Figure 1 and Figure 9As shown, the PMOS transistor 16 is disposed on the substrate 101 and between the dummy gate 11 and the emitter 12. The PMOS transistor 16 includes an N-well 201 disposed in the substrate 101, a PMOS gate 202 located on the N-well 201, and a source 203 and a drain 204 disposed in the N-well 201 on both sides of the PMOS gate 202.

[0068] like Figure 9 As shown, the source and gate of the first NMOS transistor 13 are electrically connected to the gate 10 of the IGBT via a first wiring 111. The drain of the dummy gate 11 is electrically connected to the source of the second NMOS transistor 14 via a second wiring 112. The drain of the second NMOS transistor 14 is electrically connected to the emitter 12. A contact point 113 is provided on the gate via wiring. When a pin is subsequently connected, this contact point 113 is electrically connected to the emitter 12 via an inductor 15. The drain of the PMOS transistor 16 is electrically connected to the emitter 12. A contact point 113 is provided on the gate via wiring. When a pin is subsequently connected, this contact point 113 is electrically connected to the emitter 12 via an inductor 15.

[0069] In one embodiment, the inductance value of the inductor 15 is 10nH to 20nH, for example, the inductance value of the inductor 15 can be 13nH.

[0070] In one embodiment, when the IGBT device is turned on, a threshold voltage is applied to the IGBT gate 10, and the threshold voltage is simultaneously applied to the gate of the first NMOS transistor 13 to turn on the first NMOS transistor 13, thereby connecting the IGBT gate 10 with the dummy gate 11, and forming a channel below the dummy gate 11 to reduce the conduction loss of the IGBT device.

[0071] In one embodiment, when the IGBT device is turned on, the current at the emitter 12 increases, and there is a voltage change in the inductor 15 between the PMOS transistor 16 and the emitter 12, thereby turning on the PMOS transistor 14 and connecting the dummy gate 11 to the emitter 12, thereby reducing the turn-on loss of the IGBT device.

[0072] In one embodiment, when the IGBT device is turned off, the current of the emitter 12 decreases, and there is a voltage change in the inductor 15 between the second NMOS transistor 14 and the emitter 12, thereby turning on the second NMOS transistor 14 and connecting the dummy gate 11 to the emitter 12, thereby reducing the turn-off loss of the IGBT device.

[0073] The circuit schematic of the IGBT device in this embodiment is as follows: Figure 2As shown, specifically, when the IGBT device is in the on state, the gate voltage is usually about 15V. At this time, the drain of the first NMOS transistor 13 is shorted to the IGBT gate 10, and the dummy gate 11 is shorted to the source. When the voltage of the first NMOS gate 104 is 15V, the first NMOS transistor 13 is turned on, and the potentials of the IGBT gate 10 and the dummy gate 11 are the same. This will open the channels on both sides of the dummy gate 11, reduce the VCESAT of the device, and thus reduce the conduction loss of the device.

[0074] In this embodiment, the emitter 12 of the IGBT device has an inductor 15. For example, the inductor 15 integrated inside the TO247 is approximately 13nH. When the device is in the turn-on process, the emitter 12 current rises. Taking a 650V 15A IGBT device as an example, during the turn-on process, the current change di / dt in the inductor 15 is approximately 130A / µs to 300A / µs. Thus, the voltage change across the emitter 12 inductor 15 is 1.69-3.9V, which turns on the PMOS transistor 16 to activate the dummy gate. The emitter 11 and emitter 12 are connected together, which can effectively reduce the turn-on loss of the device. When the device is in the turn-off process, the current of emitter 12 decreases. Taking a 650V 15A IGBT device as an example, during the turn-off process, the current change di / dt in inductor 15 is about 150A / us. Thus, the voltage change across inductor 15 is about 1.95V, which turns on the second NMOS transistor 14 to connect the dummy gate 11 and emitter 12 together, thereby effectively reducing the turn-off loss of the device.

[0075] like Figures 1-9As shown, this embodiment also provides a method for fabricating an IGBT device, the method comprising the following steps: providing a substrate 101, forming an emitter 12, an IGBT gate 10, a collector, and a dummy gate 11 on the substrate 101, the dummy gate 11 being disposed between the gate and the emitter 12; disposing a first NMOS transistor 13 on the substrate 101, the first NMOS transistor 13 being disposed between the IGBT gate 10 and the dummy gate 11, the source 106 and gate 104 of the first NMOS transistor 13 being electrically connected to the IGBT gate 10, and the drain 107 being electrically connected to the dummy gate 11; and further disposing a first NMOS transistor 13 on the substrate 101, the first NMOS transistor 13 being disposed between the IGBT gate 10 and the dummy gate 11, the source 106 and gate 104 of the first NMOS transistor 13 being electrically connected to the IGBT gate 10, and the drain 107 being electrically connected to the dummy gate 11; and further disposing a first NMOS transistor 13 on the substrate 101, the emitter 12, the gate 10, the collector, and the dummy gate 11 being electrically connected to the collector ... A second NMOS transistor 14 is disposed on the substrate 101, positioned between the dummy gate 11 and the emitter 12. The source 108 of the second NMOS transistor 14 is electrically connected to the dummy gate 11, the drain 109 is electrically connected to the emitter 12, and the gate is electrically connected to the emitter 12 via an inductor 15. A PMOS transistor 16 is disposed on the substrate 101, positioned between the dummy gate 11 and the emitter 12. The source 203 of the PMOS transistor 16 is electrically connected to the dummy gate 11, the drain 204 is electrically connected to the emitter 12, and the gate 202 is electrically connected to the emitter 12 via an inductor 15. Wherein, as... Figure 1 As shown, the PMOS transistor 16 and the second NMOS transistor 14 are respectively disposed on opposite sides of the emitter 12, and the first NMOS transistor is disposed below the emitter 12, so that there is a large gap and fabrication space between the first NMOS transistor 13, the second NMOS transistor 14 and the PMOS transistor 16, so as to facilitate their fabrication. Subsequently, the corresponding electrical connection is realized through contact holes and wiring.

[0076] In one embodiment, such as Figures 3-9 As shown, the process of setting a first NMOS transistor 13, a second NMOS transistor 14, and a PMOS transistor 16 on the substrate 101 includes the following steps:

[0077] like Figures 3-4 As shown, step 1) is performed first, and a first P-well 102 and a second P-well 103 are formed in the substrate 101 by ion implantation, and an N-well 201 is formed in the substrate 201. Of course, during this process, structures such as the P-type body region of the IGBT device can also be fabricated at the same time to save process costs.

[0078] like Figure 5As shown, step 2) is then performed, in which a gate dielectric layer and a gate layer are formed on the substrate 101, and an IGBT gate 10, a dummy gate 11, the gate of the first NMOS transistor 13, the gate of the second NMOS transistor 14, and the gate 202 of the PMOS transistor 16 are formed by a patterning process. The gate dielectric layer can be, for example, silicon dioxide, or a high-k dielectric such as hafnium oxide, and the gate layer can be polysilicon or metal.

[0079] like Figure 6 Then, in step 3), the source and drain of the first NMOS transistor 13 are formed in the first P-well 102 by ion implantation, the source and drain of the second NMOS transistor 14 are formed in the second P-well 103, and the source 203 and drain 204 of the PMOS transistor are formed in the N-well 201. Of course, during this process, structures such as the emitter region of the IGBT can also be fabricated simultaneously to save on process costs.

[0080] like Figures 8-9 As shown, in step 4), an insulating layer 110 is formed on the substrate 101, a contact hole is formed in the insulating layer 110, a metal layer is formed on the contact hole and the insulating layer 110, and a wiring layer is formed by a patterning process. Through the contact hole and the wiring layer, the source and gate of the first NMOS transistor 13 are electrically connected to the gate 10 of the IGBT, and the drain is electrically connected to the dummy gate 11. The source of the second NMOS transistor 14 is electrically connected to the dummy gate 11, the drain is electrically connected to the emitter 12, and the gate is connected to contact point 113. The source 203 of the PMOS transistor 16 is electrically connected to the dummy gate 11, the drain 204 is electrically connected to the emitter 12, and the gate 202 is connected to contact point 113.

[0081] In one embodiment, the method further includes the step of connecting an inductor 15 between the contact point 113 of the gate of the second NMOS transistor 14 and the gate 202 of the PMOS transistor 16 and the emitter 12 via an external pin, wherein the inductance value of the inductor 15 is 10nH to 20nH.

[0082] In one embodiment, when the IGBT device is turned on, a threshold voltage is applied to the IGBT gate 10, which is simultaneously applied to the gate of the first NMOS transistor 13 to turn on the first NMOS transistor 13, thereby connecting the IGBT gate 10 to the dummy gate 11. A channel is formed below the dummy gate 11 to reduce the conduction loss of the IGBT device. When the IGBT device is turned on, the current of the emitter 12 increases, and there is a voltage change in the inductor 15 between the PMOS transistor 16 and the emitter 12, thereby turning on the PMOS transistor 14 and connecting the dummy gate 11 to the emitter 12, thereby reducing the turn-on loss of the IGBT device. When the IGBT device is turned off, the current of the emitter 12 decreases, and there is a voltage change in the inductor 15 between the second NMOS transistor 14 and the emitter 12, thereby turning on the second NMOS transistor 14 and connecting the dummy gate 11 to the emitter 12, thereby reducing the turn-off loss of the IGBT device.

[0083] In one embodiment, the threshold voltage of the first NMOS transistor 13 is less than or equal to the threshold voltage of the IGBT gate 10, and the threshold voltage of the IGBT gate 10 differs from the threshold voltage of the first NMOS transistor 13 by less than or equal to 5V.

[0084] In one embodiment, the IGBT gate 10 and the dummy gate 11 are arranged in a ring shape, with the dummy gate 11 surrounding the emitter 12 and the IGBT gate 10 surrounding the dummy gate 11.

[0085] In one embodiment, the substrate 101 includes a first side and a second side opposite to each other, the emitter 12 and the IGBT gate 10 are disposed on the first side of the substrate 101, the collector is disposed on the second side of the substrate 101, and / or the IGBT device further includes a field cutoff layer disposed in the substrate 101 and close to the collector.

[0086] As described above, the IGBT device and its fabrication method of the present invention have the following beneficial effects:

[0087] In this invention, when the IGBT device is turned on, a threshold voltage is applied to the IGBT gate 10. This threshold voltage is simultaneously applied to the gate of the first NMOS transistor 13, causing the first NMOS transistor 13 to conduct. This connects the IGBT gate 10 to the dummy gate 11, forming a channel below the dummy gate 11 to reduce the IGBT device's turn-on losses. When the IGBT device is turned on, the current at the emitter 12 increases, causing a voltage change in the inductor 15 between the PMOS transistor 14 and the emitter 12. This causes the PMOS transistor 14 to conduct, connecting the dummy gate 11 to the emitter 12, thereby reducing the IGBT device's turn-on losses. When the IGBT device is turned off, the current at the emitter 12 decreases, causing a voltage change in the inductor 15 between the second NMOS transistor 14 and the emitter 12. This causes the second NMOS transistor 14 to conduct, connecting the dummy gate 11 to the emitter 12, thereby reducing the IGBT device's turn-off losses. This invention effectively improves device heating, increases power density, and enhances device performance by controlling the potential change of the dummy gate 11 under different operating states of the device, enabling IGBT devices to be used in higher frequency applications.

[0088] The first NMOS transistor 13 and the second NMOS transistor 14 of the present invention are disposed between the IGBT gate 10, the dummy gate 11 and the emitter 12, without occupying additional device area. This ensures that the device can reduce both turn-off loss and turn-on loss in a smaller volume. Furthermore, the present invention is compatible with the manufacturing process of conventional IGBT devices, without requiring additional manufacturing equipment, and can effectively control the manufacturing cost of the device.

[0089] Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0090] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. An IGBT device, characterized in that, The IGBT device includes: A substrate on which the emitter, gate, and collector of an IGBT device are formed; A dummy gate is disposed between the gate and the emitter; A first NMOS transistor is disposed on the substrate and between the IGBT gate and the dummy gate. The source and gate of the first NMOS transistor are electrically connected to the IGBT gate, and the drain is electrically connected to the dummy gate. The second NMOS transistor is disposed on the substrate and between the dummy gate and the emitter. The source of the second NMOS transistor is electrically connected to the dummy gate, the drain is electrically connected to the emitter, and the gate is electrically connected to the emitter through an inductor. The PMOS transistor is disposed on the substrate and between the dummy gate and the emitter. The source of the PMOS transistor is electrically connected to the dummy gate, the drain is electrically connected to the emitter, and the gate is electrically connected to the emitter through an inductor.

2. The IGBT device according to claim 1, characterized in that: When the IGBT device is turned on, a threshold voltage is applied to the IGBT gate. The threshold voltage is also applied to the gate of the first NMOS transistor to turn on the first NMOS transistor, thereby connecting the IGBT gate with the dummy gate. A channel is formed under the dummy gate to reduce the conduction loss of the IGBT device.

3. The IGBT device according to claim 1, characterized in that: When the IGBT device is turned on, the current at the emitter increases, and there is a voltage change in the inductance between the PMOS transistor and the emitter, which causes the PMOS transistor to conduct, connecting the dummy gate to the emitter, thereby reducing the turn-on loss of the IGBT device.

4. The IGBT device according to claim 1, characterized in that: When the IGBT device is turned off, the current at the emitter decreases, and there is a voltage change in the inductance between the second NMOS transistor and the emitter, which causes the second NMOS transistor to turn on, connecting the dummy gate to the emitter, thereby reducing the turn-off loss of the IGBT device.

5. The IGBT device according to claim 1, characterized in that: The threshold voltage of the first NMOS transistor is less than or equal to the threshold voltage of the IGBT gate, and the threshold voltage of the IGBT gate differs from the threshold voltage of the first NMOS transistor by less than or equal to 5V.

6. The IGBT device according to claim 1, characterized in that: The IGBT gate and the dummy gate are arranged in a ring shape, with the dummy gate surrounding the emitter and the IGBT gate surrounding the dummy gate.

7. The IGBT device according to claim 1, characterized in that: The substrate includes a first side and a second side opposite to each other. The emitter and the IGBT gate are disposed on the first side of the substrate, and the collector is disposed on the second side of the substrate. The IGBT device further includes a field cutoff layer disposed in the substrate and close to the collector.

8. The IGBT device according to claim 1, characterized in that: The inductance value of the inductor is 10nH to 20nH.

9. A method for fabricating an IGBT device, characterized in that, The preparation method includes the following steps: A substrate is provided on which an emitter, an IGBT gate, a collector, and a dummy gate of an IGBT device are formed, wherein the dummy gate is disposed between the gate and the emitter; A first NMOS transistor is disposed on the substrate, the first NMOS transistor is placed between the gate of the IGBT and the dummy gate, the source and gate of the first NMOS transistor are electrically connected to the gate of the IGBT, and the drain is electrically connected to the dummy gate; A second NMOS transistor is disposed on the substrate and placed between the dummy gate and the emitter. The source of the second NMOS transistor is electrically connected to the dummy gate, the drain is electrically connected to the emitter, and the gate is electrically connected to the emitter through an inductor. A PMOS transistor is disposed on the substrate, between the dummy gate and the emitter. The source of the PMOS transistor is electrically connected to the dummy gate, the drain is electrically connected to the emitter, and the gate is electrically connected to the emitter through an inductor.

10. The method for fabricating an IGBT device according to claim 9, characterized in that: The steps of fabricating a first NMOS transistor, a second NMOS transistor, and a PMOS transistor on the substrate include: A first P-well and a second P-well are formed in the substrate by ion implantation, and an N-well is formed in the substrate. A gate dielectric layer and a gate layer are formed on the substrate, and an IGBT gate, a dummy gate, a first NMOS transistor gate, a second NMOS transistor gate, and a PMOS transistor gate are formed by a patterning process. The source and drain of a first NMOS transistor are formed in the first P-well by ion implantation, the source and drain of a second NMOS transistor are formed in the second P-well, and the source and drain of a PMOS transistor are formed in the N-well. An insulating layer is formed on the substrate, a contact hole is formed in the insulating layer, a metal layer is formed on the contact hole and the insulating layer, and a wiring layer is formed by a patterning process. Through the contact hole and the wiring layer, the source and gate of the first NMOS transistor are electrically connected to the gate of the IGBT, and the drain is electrically connected to the dummy gate. The source of the second NMOS transistor is electrically connected to the dummy gate, and the drain is electrically connected to the emitter. The gate is connected to a contact point. The source of the PMOS transistor is electrically connected to the dummy gate, and the drain is electrically connected to the emitter. The gate is connected to a contact point.

11. The method for fabricating an IGBT device according to claim 10, characterized in that: The method also includes the step of connecting an inductor between the contact point between the gate of the second NMOS transistor and the gate of the PMOS transistor and the emitter via an external pin, wherein the inductance value of the inductor is 10nH to 20nH.

12. The method for fabricating an IGBT device according to claim 11, characterized in that: When the IGBT device is turned on, a threshold voltage is applied to the IGBT gate. This threshold voltage is simultaneously applied to the gate of the first NMOS transistor to turn on the first NMOS transistor, thereby connecting the IGBT gate to the dummy gate. A channel is formed below the dummy gate to reduce the conduction loss of the IGBT device. When the IGBT device is turned on, the emitter current increases, and a voltage change occurs in the inductance between the PMOS transistor and the emitter, causing the PMOS transistor to turn on and connecting the dummy gate to the emitter, thereby reducing the turn-on loss of the IGBT device. When the IGBT device is turned off, the emitter current decreases, and a voltage change occurs in the inductance between the second NMOS transistor and the emitter, causing the second NMOS transistor to turn on and connecting the dummy gate to the emitter, thereby reducing the turn-off loss of the IGBT device.

13. The method for fabricating an IGBT device according to claim 9, characterized in that: The threshold voltage of the first NMOS transistor is less than or equal to the threshold voltage of the IGBT gate, and the threshold voltage of the IGBT gate differs from the threshold voltage of the first NMOS transistor by less than or equal to 5V.

14. The method for fabricating an IGBT device according to claim 9, characterized in that: The IGBT gate and the dummy gate are arranged in a ring shape, with the dummy gate surrounding the emitter and the IGBT gate surrounding the dummy gate.

15. The method for fabricating an IGBT device according to claim 9, characterized in that: The substrate includes a first side and a second side opposite to each other. The emitter and the IGBT gate are disposed on the first side of the substrate, and the collector is disposed on the second side of the substrate. The IGBT device further includes a field cutoff layer disposed in the substrate and close to the collector.

Images