A data selector circuit and a data selection method based on a memristor

Abstract

The application discloses a data selector circuit based on a memristor and a data selection method, and belongs to the technical field of microelectronic devices; wherein the 2-to-1 data selector based on the memristor is used for selecting one data from a logic value a and a logic value b based on a logic value s; the data selector circuit comprises three memristors and one resistor, is simple in structure, low in circuit complexity, small in circuit area and high in expandability; specifically, the logic value s is defined in the form of a voltage at the voltage input end of a memristor M1 and a memristor M2, the logic value a is defined as the resistance state of the memristor M1, the logic value b is defined as the resistance state of the memristor M2, and the resistance state of a memristor M3 is used as the output; only three steps of setting the states of the memristor M1 and the memristor M2 and pressurizing the memristor and the resistor are needed to realize the data selection function; compared with the existing 2-to-1 data selector, the data selection operation can be realized with higher calculation efficiency under the condition of fewer devices and operation steps.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of microelectronic devices, and more particularly relates to a data selector circuit based on a memristor and a data selection method. BACKGROUND

[0002] Under the background of the big data era, emerging data-intensive applications such as cloud computing, the Internet of Things, and artificial intelligence are developing rapidly. Under the traditional memory-computing separation von Neumann architecture, key problems such as memory wall, slowing down of Moore's Law, and failure of Denard scaling law are gradually emerging, and the traditional irreversible computing paradigm will also face the problem of the thermodynamic wall, which limits the computing performance of chips due to energy consumption, delay, and heat dissipation. As a new type of semiconductor memory device, the memristor has the advantages of small device size, fast read-write speed, low power consumption, and compatibility with CMOS technology, and can provide a hardware foundation for in-memory computing research. The logic computing design based on the memristor aims to combine non-volatile storage and information processing to provide a path for more efficient computing mode.

[0003] A data selector is a logic circuit that selects and transmits data from multiple channels to a unique common data channel, realizing the function of data selection. As a switch with multiple inputs and a single output, it transmits analog or digital signals at a higher speed on a single line. At the same time, as a very common logic gate in today's circuits, it is the basis for implementing other complex logic. The traditional CMOS data selector circuit requires a NOT gate circuit, two AND gate circuits, and an OR gate circuit, and each gate circuit is composed of multiple transistors, occupying a large area. The circuit of an N-to-1 data selector will become more complex. For a data selector based on the IMP logic of the memristor, the initialization operation is not considered in the operation steps, and a large number of memristors and operation steps are required. Therefore, it is an urgent problem to provide a data selector circuit with small circuit area, few devices, and few operation steps, and an operation method thereof. SUMMARY

[0004] In view of the above defects or improvement needs of the prior art, the present application provides a data selector circuit based on a memristor and a data selection method to solve the technical problem that the prior art cannot realize data selection operation with high computing efficiency under the condition of fewer devices and operation steps.

[0005] To achieve the above purpose, in a first aspect, the present application provides a 2-to-1 data selector based on a memristor, which is used to select one data from logic value a and logic value b based on logic value s, comprising a controller, a memristor M1, a memristor M2, a memristor M3, and a resistor; wherein the initial state of the memristor M3 is a high resistance state.

[0006] The controller is connected to the positive terminals of memristors M1, M2, and M3 respectively; the negative terminals of memristors M1, M2, and M3 are all connected to the same word line WL; one end of word line WL is left floating and the other end is grounded; a resistor is connected to word line WL, one end of which is connected to the ground terminal of word line WL, and the other end is connected to the negative terminal of the memristor closest to the ground terminal; memristors M1, M2, and M3 are identical.

[0007] Before data selection, the controller sets memristor M1 to the resistance state corresponding to logic value a and memristor M2 to the resistance state corresponding to logic value b. During data selection, voltage A is applied to memristor M1, voltage B is applied to memristor M2, and voltage V is applied to memristor M3. p And read the resistance state of memristor M3 to obtain the result of the 2-to-1 data selection;

[0008] Wherein, voltage A is taken as 2V-2V. p The voltage B is -2V; when the logic value s is 0, V is 0; when the logic value s is 1, V is V. p V p Satisfy V set / 2 <V p <V set And V p <2|V reset |;V set V is the threshold value for the memristor to transition from a high-resistance state to a low-resistance state. reset The threshold value at which a memristor transitions from a low-resistance state to a high-resistance state.

[0009] More preferably, the memristors M1, M2 and M3 all include a high-resistance state and a low-resistance state; the high-resistance state corresponds to the logic value "0" and the low-resistance state corresponds to the logic value "1".

[0010] More preferably, the resistance value is between the high-resistance and low-resistance values ​​of the memristor; the resistance value is... Where R H R is the high-resistance resistance value of the memristor. L This is the low-resistance resistance value of the memristor.

[0011] More preferably, the controller includes a control terminal T1, a control terminal T2, and a control terminal T3; control terminal T1 is connected to the positive terminal of memristor M1, control terminal T2 is connected to the positive terminal of memristor M2, and control terminal T3 is connected to the positive terminal of memristor M3.

[0012] When selecting data, the controller applies voltage A to memristor M1 through control terminal T1, voltage B to memristor M2 through control terminal T2, and voltage V to memristor M3 through control terminal T3.p The resistance state of memristor M3 is read to obtain the data selection result.

[0013] Secondly, the present invention provides a 2-to-1 data selection method for selecting one data from logical values ​​a and b based on a logical value s, comprising the following steps:

[0014] S1. Set memristor M1 to the resistance state corresponding to logic value a, and set memristor M2 to the resistance state corresponding to logic value b; keep the resistance state of memristor M3 in its initial high resistance state.

[0015] S2. When selecting data, apply voltage A to memristor M1, voltage B to memristor M2, and voltage C to memristor M3, and read the resistance state of memristor M3 to obtain the result of 2-to-1 data selection.

[0016] In this configuration, the negative terminals of memristors M1, M2, and M3 are all connected to the same word line WL; one end of word line WL is left floating, and the other end is grounded; a resistor is connected to word line WL, with one end connected to the ground terminal of word line WL and the other end connected to the negative terminal of the memristor closest to the ground terminal; memristors M1, M2, and M3 are identical.

[0017] Voltage A is 2V-2V p Voltage B is -2V, and voltage C is V. p When the logical value s is 0, V takes the value 0; when the logical value s is 1, V takes the value V. p V p Satisfy V set / 2 <V p <V set And V p <2|V reset |;V set V is the threshold value for the memristor to transition from a high-resistance state to a low-resistance state. reset The threshold value at which a memristor transitions from a low-resistance state to a high-resistance state.

[0018] Thirdly, the present invention provides an N-to-1 data selector based on a memristor, wherein N=2 n And n is an integer greater than 1, used to determine the input address A0A1......A n-1 From the input data D0, D1, ..., D N-1 Select one data point from the list;

[0019] The N-to-1 data selector consists of: a controller, 2N-1 identical memristors, and a resistor;

[0020] The controller is connected to the positive terminal of each memristor; the negative terminal of each memristor is connected to the same word line; one end of the word line is left floating and the other end is grounded; a resistor is connected to the word line, one end of which is connected to the ground terminal of the word line, and the other end is connected to the negative terminal of the memristor closest to the ground terminal.

[0021] The controller is used to divide the N-to-1 data selection process into n rounds of data selection sub-processes; each round of data selection sub-processes performs a 2-to-1 data selection operation; specifically, it performs the following operations:

[0022] The first round of data selection sub-process: randomly select 3N / 2 memristors from 2N-1 memristors, and divide the selected 3N / 2 memristors into groups of three, resulting in N / 2 groups of memristors; input data D0, D1, ..., D... N-1 The input data is divided into N / 2 groups of adjacent pairs, each corresponding to one of the N / 2 groups of memristors. In each group of memristors under the current sub-process, the first memristor is set to the resistance state corresponding to the first data in the input data pair, the second memristor is set to the resistance state corresponding to the second data in the input data pair, the third memristor is set to a high resistance state, and a voltage V is applied to the first memristor. A1 Apply voltage V to the second memristor B1 Apply voltage V to the third memristor p Among them, voltage V A1 The value is 2V1-2V p Voltage V B1 The value is -2V1; when the logic value A0 is 0, V1 takes the value 0; when the logic value A0 is 1, V1 takes the value V. p ;

[0023] The i-th round of data selection sub-process: N / 2 from the previous round of data selection sub-process... i-1 The memristors are grouped according to the order of their corresponding input data. The third memristor is grouped into pairs of adjacent third memristors, with the first third memristor in the sequence becoming the new first memristor, and the last third memristor in the sequence becoming the new second memristor, resulting in N / 2. i Group memristors; and respectively at N / 2 i Add a new third memristor to each group of memristors; in the current subprocess, apply a voltage V to the first memristor of each group of memristors. Ai Apply voltage V to the second memristor Bi Apply voltage V to its third memristor p Among them, voltage V Ai The value is 2V i -2V pVoltage V Bi The value is -2V i When logical value A i-1 When V is 0, i The value is 0; when the logical value A i-1 When V is 1, i The value is V p i = 2, 3, ..., n;

[0024] Read the resistance state of the third memristor during the nth round of data selection subprocess to obtain the result of N-to-1 data selection;

[0025] Among them, V p Satisfy V set / 2 <V p <V set And V p <2|V reset |;V set V is the threshold value for the memristor to transition from a high-resistance state to a low-resistance state. reset The threshold value at which a memristor transitions from a low-resistance state to a high-resistance state.

[0026] More preferably, the memristor includes a high-resistance state and a low-resistance state; the high-resistance state corresponds to the logic value "0", and the low-resistance state corresponds to the logic value "1".

[0027] More preferably, the resistance value is between the high-resistance and low-resistance values ​​of the memristor; the resistance value is... Where R H R is the high-resistance resistance value of the memristor. L This is the low-resistance resistance value of the memristor.

[0028] Fourthly, the present invention provides an N-to-1 data selection method for selecting data based on input addresses A0A1......A n-1 From the input data D0, D1, ..., D N-1 Select one data point from the pool; this includes: dividing the N-to-1 data selection process into n rounds of data selection sub-processes; each round of data selection sub-processes performs a 2-to-1 data selection operation; specifically, the following operations are performed:

[0029] The first round of data selection sub-process: randomly select 3N / 2 memristors from 2N-1 memristors, and divide the selected 3N / 2 memristors into groups of three, resulting in N / 2 groups of memristors; input data D0, D1, ..., D... N-1The input data is divided into N / 2 groups of adjacent pairs, each corresponding to one of the N / 2 groups of memristors. In each group of memristors under the current sub-process, the first memristor is set to the resistance state corresponding to the first data in the input data pair, the second memristor is set to the resistance state corresponding to the second data in the input data pair, the third memristor is set to a high resistance state, and a voltage V is applied to the first memristor. A1 Apply voltage V to the second memristor B1 Apply voltage V to the third memristor p Among them, voltage V A1 The value is 2V1-2V p Voltage V B1 The value is -2V1; when the logic value A0 is 0, V1 takes the value 0; when the logic value A0 is 1, V1 takes the value V. p ;

[0030] The i-th round of data selection sub-process: N / 2 from the previous round of data selection sub-process... i-1 The memristors are grouped according to the order of their corresponding input data. The third memristor is grouped into pairs of adjacent third memristors, with the first third memristor in the sequence becoming the new first memristor, and the last third memristor in the sequence becoming the new second memristor, resulting in N / 2. i Group memristors; and respectively at N / 2 i Add a new third memristor to each group of memristors; in the current subprocess, apply a voltage V to the first memristor of each group of memristors. Ai Apply voltage V to the second memristor Bi Apply voltage V to its third memristor p Among them, voltage V Ai The value is 2V i -2V p Voltage V Bi The value is -2V i When logical value A i-1 When V is 0, i The value is 0; when the logical value A i-1 When V is 1, i The value is V p i = 2, 3, ..., n;

[0031] Read the resistance state of the third memristor during the nth round of data selection subprocess to obtain the result of N-to-1 data selection;

[0032] Where N = 2 nAnd n is an integer greater than 1; the negative terminals of 2N-1 memristors are all connected to the same word line; one end of the word line is left floating and the other end is grounded; a resistor is connected to the word line, one end of the resistor is connected to the ground terminal of the word line, and the other end is connected to the negative terminal of the memristor closest to the ground terminal;

[0033] V p Satisfy V set / 2 <V p <V set And V p <2|V reset |;V set V is the threshold value for the memristor to transition from a high-resistance state to a low-resistance state. reset The threshold value at which a memristor transitions from a low-resistance state to a high-resistance state.

[0034] In summary, the above-described technical solutions conceived in this invention can achieve the following beneficial effects:

[0035] 1. This invention provides a 2-to-1 data selector circuit and data selection method based on memristors, used to select a data from logic values ​​a and b based on a logic value s. The data selector circuit includes three memristors and one resistor, with a simple structure, low circuit complexity, small circuit area, and strong scalability. The logic value s is defined as a voltage at the voltage input terminals of memristors M1 and M2, logic value a is defined as the resistance state of memristor M1, logic value b is defined as the resistance state of memristor M2, and the resistance state of memristor M3 is used as the output. The data selection function can be achieved in just three steps: setting the states of memristors M1 and M2, and applying voltage to the memristors and the resistor. Compared with existing 2-to-1 data selectors, this invention can achieve data selection with higher computational efficiency under conditions of fewer components and fewer operation steps.

[0036] 2. This invention provides an N-to-1 data selector circuit and data selection method based on memristors, used for selecting data based on input addresses A0A1......A1. n-1 From the input data D0, D1, ..., D N-1 Selecting one data from the given list, the entire N-to-1 data selector consists of 2N-1 memristors and one resistor. It has a simple structure, low circuit complexity, and small circuit area. By using N (N=2... n The N-to-1 data selection process is divided into n rounds of data selection sub-processes, and each round of data selection sub-processes performs a 2-to-1 data selection operation. This makes the actual operation steps required for the entire N-to-1 data selector only 2N-1 steps. Compared with the existing N-to-1 data selectors, it can achieve data selection operation with higher computational efficiency under the condition of fewer devices and fewer operation steps.

[0037] 3. The data selector circuit provided by this invention, based on the non-volatile characteristics of memristors, allows the logic output to be directly stored in the memristor after the data selection function is completed, eliminating the need for additional data transmission and storage, thus reducing power consumption and latency. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of the structure of a memristor-based 2-to-1 data selector provided in Embodiment 1 of the present invention;

[0039] Figure 2 This is a test diagram of the resistance-to-voltage (IV) characteristic of the memristor provided in Embodiment 1 of the present invention;

[0040] Figure 3 This is a voltage configuration diagram for each actual operation step under different logic inputs provided in Embodiment 1 of the present invention;

[0041] Figure 4 The circuit diagram of the 2-to-1 data selector provided by the present invention;

[0042] Figure 5 The truth table for the 2-to-1 data selector provided by this invention;

[0043] Figure 6 The experimental results of the data selector circuit under various input conditions when the logic value s=0 are provided by the present invention.

[0044] Figure 7 The circuit diagram of the 4-to-1 data selector provided by the present invention. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0046] Example 1

[0047] A memristor-based 2-to-1 data selector is used to select data based on input logic values ​​s, a, and b (selecting a data value from logic values ​​a and b based on logic value s), such as... Figure 1 As shown, it includes: a controller, memristors M1, M2, M3 and resistors (a fixed resistor is used in this embodiment); wherein, the initial state of memristor M3 is a high-resistance state;

[0048] The controller is connected to the positive terminals of memristors M1, M2, and M3 respectively; the negative terminals of memristors M1, M2, and M3 are all connected to the same word line WL; one end of word line WL is left floating and the other end is grounded; a resistor is connected to word line WL, one end of which is connected to the ground terminal of word line WL, and the other end is connected to the negative terminal of the memristor closest to the ground terminal; memristors M1, M2, and M3 are identical. Specifically, in one optional implementation, the controller includes a control terminal T1, a control terminal T2, and a control terminal T3; control terminal T1 is connected to the positive terminal of memristor M1 via bit line BL1, control terminal T2 is connected to the positive terminal of memristor M2 via bit line BL2, and control terminal T3 is connected to the positive terminal of memristor M3 via bit line BL3; when the controller performs data selection, it applies voltage A to memristor M1 via control terminal T1, voltage B to memristor M2 via control terminal T2, and voltage V to memristor M3 via control terminal T3. p The resistance state of memristor M3 is read to obtain the data selection result. It should be noted that memristors M1, M2, and M3 are identical, each including a high-resistance state and a low-resistance state; the high-resistance state corresponds to the logic value "0", and the low-resistance state corresponds to the logic value "1". The resistance-to-voltage (IV) characteristic test diagram of the memristor used is shown below. Figure 2 As shown, specifically, when a voltage greater than V is applied across the memristor... set When a positive voltage less than V is applied across the memristor, the memristor changes from a high-resistance state to a low-resistance state, and its resistance is set to low. reset When a negative voltage is applied, the memristor transitions from a low-resistance state to a high-resistance state, at which point its resistance is set to high. By controlling the voltage across the memristor, it can switch between high and low resistance states. Here, the high-resistance state of the memristor corresponds to the logic value "0", and the low-resistance state corresponds to the logic value "1"; where V... set V is the threshold value for the memristor to transition from a high-resistance state to a low-resistance state. reset This is the threshold voltage at which the memristor transitions from a low-resistance state to a high-resistance state. It should be noted that to prevent excessively large positive voltages from damaging the memristor, a damaged device cannot return to a high-resistance state by applying a negative reset voltage. Therefore, applying a voltage greater than V across the memristor... set When a forward voltage is applied to cause the memristor to transition from a high-resistance state to a low-resistance state, the current in the memristor is limited by a current limit of I. cc Specifically, such as Figure 2 As shown, in this embodiment, the current limiting value of the memristor used is set to 1mA, i.e., I cc It is 1mA.

[0049] Before data selection, the controller sets memristor M1 to the resistance state corresponding to logic value a and memristor M2 to the resistance state corresponding to logic value b. During data selection, voltage A is applied to memristor M1, voltage B is applied to memristor M2, and voltage V is applied to memristor M3. p And read the resistance state of memristor M3 to obtain the result of the 2-to-1 data selection;

[0050] The values ​​of voltages A and B are determined by the logic value s; specifically, voltage A is 2V-2V. p The voltage B is -2V; when the logic value s is 0, V is 0; when the logic value s is 1, V is V. p ;

[0051] Since the electrical signals used in the data selection process are all voltage pulse signals, to prevent the memristor, which is originally in a high-resistance state, from changing to a low-resistance state when no operation is being performed, a 2V pulse is applied across the memristor. p During voltage drop, ensure that the memristor undergoes a resistance change, and the voltage V p The amplitude should be between V set / 2 and V set In addition, to ensure that the memristor, initially in a low-resistance state, does not transition to a high-resistance state when no operation is performed, V must also be satisfied. p <2|V reset Based on this, V p V must be satisfied set / 2 <V p <V set And V p <2|V reset |

[0052] Furthermore, to clearly distinguish the low-resistance state, high-resistance state of the memristor, and the resistance value of the fixed resistor, a memristor with a switching ratio greater than or equal to a preset switching threshold is used. In this embodiment, the preset switching threshold is set to 100. The resistance value is between the high-resistance state and the low-resistance state of the memristor. Since the high-resistance state and the low-resistance state of the memristor are on different orders of magnitude, to further clearly distinguish the low-resistance state, high-resistance state, and the resistance value of the fixed resistor, preferably, the resistance value of the fixed resistor is set to [value missing]. Among them, R H R is the high-resistance resistance value of the memristor. L This is the low-resistance resistance value of the memristor. The fixed resistor mainly serves as a current limiter in this logic circuit; furthermore, considering that both the high-resistance and low-resistance states of the memristor have a certain fluctuation range, the resistance value R of the fixed resistor can be slightly larger than this value to provide better assurance for the reliability of the circuit.

[0053] Example 2

[0054] A 2-to-1 data selection method for selecting one data from logical values ​​a and b based on logical value s, comprising the following steps:

[0055] S1. Set memristor M1 to the resistance state corresponding to logic value a, and set memristor M2 to the resistance state corresponding to logic value b; keep the resistance state of memristor M3 in its initial high resistance state.

[0056] S2. When selecting data, apply voltage A to memristor M1, voltage B to memristor M2, and voltage C to memristor M3, and read the resistance state of memristor M3 to obtain the result of 2-to-1 data selection.

[0057] In this configuration, the negative terminals of memristors M1, M2, and M3 are all connected to the same word line WL; one end of word line WL is left floating, and the other end is grounded; a resistor is connected to word line WL, with one end connected to the ground terminal of word line WL and the other end connected to the negative terminal of the memristor closest to the ground terminal; memristors M1, M2, and M3 are identical.

[0058] Voltage A is 2V-2V p Voltage B is -2V, and voltage C is V. p When the logical value s is 0, V takes the value 0; when the logical value s is 1, V takes the value V. p V p Satisfy V set / 2 <V p <V set And V p <2|V reset |;V set V is the threshold value for the memristor to transition from a high-resistance state to a low-resistance state. reset The threshold value at which a memristor transitions from a low-resistance state to a high-resistance state.

[0059] The above-described 2-to-1 data selection method corresponds to the control method of the 2-to-1 data selector in Embodiment 1. The relevant technical solutions are the same as in Embodiment 1, and will not be repeated here.

[0060] It should be noted that the control method for the 2-to-1 data selector provided in Embodiment 1 of the present invention and the corresponding 2-to-1 data selection method in Embodiment 2 only include three actual operation steps, such as... Figure 3 The diagram shows the voltage configuration for each actual operation step under different logic inputs. Specifically, since the initial state of the memristor is high impedance, there is no need to set memristor M3 to a high impedance state. Therefore, S1 only includes the operations of setting memristor M1 to the impedance state corresponding to logic value a and setting memristor M2 to the impedance state corresponding to logic value b. Figure 3The actual operation steps are STEP1 and STEP2; in S2, the 2-to-1 data selection function is achieved by applying the corresponding voltage. Figure 3 The actual operation steps are STEP3.

[0061] To make the technical solutions and advantages of Embodiments 1 and 2 of the present invention clearer, specifically, the present invention provides the resistance changes measured in an actual circuit for eight input states of a 2-to-1 data selector. In this embodiment, the resistor R is 10KΩ, and the memristor's switching ratio is greater than 100, making it possible to clearly distinguish the low-resistance state, high-resistance state of the memristor, and the resistance value of the fixed resistor R. Specifically, as... Figure 4 The diagram shown is a 2-to-1 data selector circuit diagram. Figure 5 The following is the truth table for a 2-to-1 data selector. The specific operation and memristor states are as follows:

[0062] Memristor M3 is initialized to a high-impedance state;

[0063] When the inputs a=0, b=0, and s=0, V=0, memristor M1 and memristor M2 are set to high impedance. At this time, the voltage V across memristor M1 is... M1 Approximately -2V p The voltage V across memristor M2 M2 The voltage V across memristor M3 is approximately 0. M3 Approximately V p Because of V set / 2 <V p <V set And V p <2|V reset Therefore, at this time, the memristor M3 remains in a high-impedance state and outputs a logic value of 0, that is, the output result of the data selector is 0; at this time, the output logic value a is selected.

[0064] When the inputs are a=0, b=1, and s=0, V=0, memristor M1 is set to a high-resistance state, and memristor M2 is set to a low-resistance state. At this time, the voltage V across memristor M1 is... M1 Approximately -2V p The voltage V across memristor M2 M2 The voltage V across memristor M3 is approximately 0. M3 Approximately V p Therefore, at this time, the memristor M3 remains in a high impedance state and outputs a logic value of 0, that is, the output result of the data selector is 0; at this time, the output logic value a is selected.

[0065] When the inputs are a=1, b=0, and s=0, V=0, memristor M1 is set to low resistance, and memristor M2 is set to high resistance. At this time, the voltage V across memristor M1 is... M1The voltage V across memristor M2 is approximately 0. M2 Approximately 2V p The voltage V across memristor M3 M3 Approximately 3V p Because of V set / 2 <V p <V set And V p <2|V reset Therefore, at this time, memristor M3 switches to a low-impedance state and outputs a logic value of 1, that is, the output result of the data selector is 1; at this time, the output logic value a is selected.

[0066] When the inputs are a=1, b=1, and s=0, V=0, memristor M1 and memristor M2 are set to low resistance. At this time, the voltage V across memristor M1 is... M1 Approximately -V p The voltage V across memristor M2 M2 Approximately V p The voltage V across memristor M3 M3 Approximately 2V p Therefore, at this time, the memristor M3 switches to a low-impedance state and outputs a logic value of 1, that is, the output result of the data selector is 1; at this time, the output logic value a is selected.

[0067] When the inputs are a=0, b=0, and s=1, V=V p When memristor M1 and memristor M2 are both set to high impedance, the voltage V across memristor M1 is... M1 The voltage V across memristor M2 is approximately 0. M2 Approximately -2V p The voltage V across memristor M3 M3 Approximately V p Therefore, at this time, the memristor M3 remains in a high impedance state and outputs a logic value of 0, that is, the output result of the data selector is 0; at this time, the output logic value b is selected.

[0068] When the inputs are a=0, b=1, and s=1, V=V p When memristor M1 is set to a high-resistance state and memristor M2 is set to a low-resistance state, the voltage V across memristor M1 is... M1 Approximately 2V p The voltage V across memristor M2 M2 The voltage V across memristor M3 is approximately 0. M3 Approximately 3V p Therefore, at this time, the memristor M3 switches to a low-impedance state and outputs a logic value of 1, that is, the output result of the data selector is 1; at this time, the output logic value b is selected.

[0069] When the input is a=1, b=0, s=1, V=Vp When memristor M1 is set to low resistance and memristor M2 is set to high resistance, the voltage V across memristor M1 is... M1 The voltage V across memristor M2 is approximately 0. M2 Approximately -2V p The voltage V across memristor M3 M3 Approximately V p Because of V set / 2 <V p <V set And V p <2|V reset Therefore, at this time, the memristor M3 remains in a high-impedance state and outputs a logic value of 0, that is, the output result of the data selector is 0; at this time, the output logic value b is selected.

[0070] When the inputs are a=1, b=1, s=1, V=V p When memristor M1 and memristor M2 are both set to low resistance, the voltage V across memristor M1 is... M1 Approximately V p The voltage V across memristor M2 M2 Approximately -V p The voltage V across memristor M3 M3 Approximately 2V p Therefore, at this time, the memristor M3 switches to a low-impedance state and outputs a logic value of 1, that is, the output result of the data selector is 1; at this time, the output logic value b is selected.

[0071] Furthermore, such as Figure 6 The diagram shows the experimental results of the data selector circuit under various input conditions when the logic value s = 0. Since the voltage configuration of the bit lines (BL1, BL2) is symmetrical when the logic value s = 0 compared to when the logic value s = 1, the case of logic value s = 1 will not be described here. As can be seen from the diagram, the data selector operation method provided by this invention can operate according to the following... Figure 5 The truth table of the 2-to-1 data selector shown is used to effectively control the logic input and output; where y = b·s + a·s.

[0072] This invention operates a data selector composed of a memristor and a fixed resistor. The data selector circuit operation is achieved through three steps: setting the memristor and configuring different operating voltages at the control terminal. This invention has advantages such as using fewer components, fewer operation steps, a simple circuit structure, and no damage to input information, thus laying the foundation for complex logic operations.

[0073] In summary, Embodiments 1 and 2 of this invention disclose a 2-to-1 data selector circuit based on memristors and a 2-to-1 data selection method based on memristors. The circuit includes three memristors and a fixed resistor. The data selector logic function can be realized through three steps: setting the memristors and configuring the two control terminals (T1, T2) of the circuit. Specifically, the positive terminals of memristors M1, M2, and M3 are connected to different bit lines (BL1, BL2, and BL3), while the negative terminals are connected to the same word line (WL). One end of the fixed resistor is connected to the word line, and the other end is connected to the control terminal T4. In the logic calculation, one input logic value s is defined as a voltage at the control terminals T1 and T2, another input logic value a is defined as the resistance state of memristor M1, another input logic value b is defined as the resistance state of memristor M2, and the resistance state of memristor M3 serves as the output. Compared with existing logic methods, this scheme uses fewer operation steps and fewer devices, improving computational efficiency and saving circuit area, which helps to realize more complex logic functions. Furthermore, the logic implementation method used is non-destructive, which helps to protect the integrity of input information.

[0074] Example 3

[0075] An N-to-1 data selector based on memristors, where N=2 n And n is an integer greater than 1, used to determine the input address A0A1......A n-1 From the input data D0, D1, ..., D N-1 Select one data point from the list;

[0076] The N-to-1 data selector includes: a controller, 2N-1 identical memristors, and a resistor (a fixed resistor is used in this embodiment). Similarly, in this embodiment, the memristors have high-resistance and low-resistance states; the high-resistance state corresponds to the logic value "0", and the low-resistance state corresponds to the logic value "1". The resistance value is between the high-resistance and low-resistance values ​​of the memristors; the resistance value is... Where R H R is the high-resistance resistance value of the memristor. L This is the low-resistance resistance value of the memristor.

[0077] Specifically, the controller is connected to the positive terminal of each memristor; the negative terminal of each memristor is connected to the same word line; one end of the word line is left floating and the other end is grounded; a resistor is connected to the word line, one end of which is connected to the ground terminal of the word line, and the other end is connected to the negative terminal of the memristor closest to the ground terminal.

[0078] The controller is used to divide the N-to-1 data selection process into n rounds of data selection sub-processes; each round of data selection sub-processes performs a 2-to-1 data selection operation; specifically, it performs the following operations:

[0079] The first round of data selection sub-process: randomly select 3N / 2 memristors from 2N-1 memristors, and divide the selected 3N / 2 memristors into groups of three, resulting in N / 2 groups of memristors; input data D0, D1, ..., D... N-1 The input data is divided into N / 2 groups of adjacent pairs, each corresponding to one of the N / 2 groups of memristors. In each group of memristors under the current sub-process, the first memristor is set to the resistance state corresponding to the first data in the input data pair, the second memristor is set to the resistance state corresponding to the second data in the input data pair, the third memristor is set to a high resistance state, and a voltage V is applied to the first memristor. A1 Apply voltage V to the second memristor B1 Apply voltage V to the third memristor p Among them, voltage V A1 The value is 2V1-2V p Voltage V B1 The value is -2V1; when the logic value A0 is 0, V1 takes the value 0; when the logic value A0 is 1, V1 takes the value V. p ;

[0080] The i-th round of data selection sub-process: N / 2 from the previous round of data selection sub-process... i-1 The memristors are grouped according to the order of their corresponding input data. The third memristor is grouped into pairs of adjacent third memristors, with the first third memristor in the sequence becoming the new first memristor, and the last third memristor in the sequence becoming the new second memristor, resulting in N / 2. i Group memristors; and respectively at N / 2 i Add a new third memristor to each group of memristors; in the current subprocess, apply a voltage V to the first memristor of each group of memristors. Ai Apply voltage V to the second memristor Bi Apply voltage V to its third memristor p Among them, voltage V Ai The value is 2V i -2V p Voltage V Bi The value is -2V i When logical value A i-1 When V is 0, i The value is 0; when the logical value A i-1 When V is 1, iThe value is V p i = 2, 3, ..., n;

[0081] Read the resistance state of the third memristor during the nth round of data selection subprocess to obtain the result of N-to-1 data selection;

[0082] As in Example 1, V p Satisfy V set / 2 <V p <V set And V p <2|V reset |;V set V is the threshold value for the memristor to transition from a high-resistance state to a low-resistance state. reset This is the threshold value for the memristor to transition from a low-resistance state to a high-resistance state. The specific design rationale, namely the selection of the resistance value, is the same as in Example 1, and will not be repeated here.

[0083] It should be noted that the N-to-1 data selector is an extension of the 2-to-1 data selector described in Example 1, but it is only an extension of the memristor part. The entire N-to-1 data selector includes only one resistor. The actual operation steps required for the entire N-to-1 data selector are 2N-1 steps. It has the advantages of small area, easy expansion, low circuit complexity and low delay during expansion.

[0084] Example 4

[0085] An N-to-1 data selection method for selecting data based on input addresses A0A1......A n-1 From the input data D0, D1, ..., D N-1 Select one data point from the pool; this includes: dividing the N-to-1 data selection process into n rounds of data selection sub-processes; each round of data selection sub-processes performs a 2-to-1 data selection operation; specifically, the following operations are performed:

[0086] The first round of data selection sub-process: randomly select 3N / 2 memristors from 2N-1 memristors, and divide the selected 3N / 2 memristors into groups of three, resulting in N / 2 groups of memristors; input data D0, D1, ..., D... N-1 The input data is divided into N / 2 groups of adjacent pairs, each corresponding to one of the N / 2 groups of memristors. In each group of memristors under the current sub-process, the first memristor is set to the resistance state corresponding to the first data in the input data pair, the second memristor is set to the resistance state corresponding to the second data in the input data pair, the third memristor is set to a high resistance state, and a voltage V is applied to the first memristor. A1 Apply voltage V to the second memristor B1 Apply voltage V to the third memristor pAmong them, voltage V A1 The value is 2V1-2V p Voltage V B1 The value is -2V1; when the logic value A0 is 0, V1 takes the value 0; when the logic value A0 is 1, V1 takes the value V. p ;

[0087] The i-th round of data selection sub-process: N / 2 from the previous round of data selection sub-process... i-1 The memristors are grouped according to the order of their corresponding input data. The third memristor is grouped into pairs of adjacent third memristors, with the first third memristor in the sequence becoming the new first memristor, and the last third memristor in the sequence becoming the new second memristor, resulting in N / 2. i Group memristors; and respectively at N / 2 i Add a new third memristor to each group of memristors; in the current subprocess, apply a voltage V to the first memristor of each group of memristors. Ai Apply voltage V to the second memristor Bi Apply voltage V to its third memristor p Among them, voltage V Ai The value is 2V i -2V p Voltage V Bi The value is -2V i When logical value A i-1 When V is 0, i The value is 0; when the logical value A i-1 When V is 1, i The value is V p i = 2, 3, ..., n;

[0088] Read the resistance state of the third memristor during the nth round of data selection subprocess to obtain the result of N-to-1 data selection;

[0089] Where N = 2 n And n is an integer greater than 1; the negative terminals of 2N-1 memristors are all connected to the same word line; one end of the word line is left floating and the other end is grounded; a resistor is connected to the word line, one end of the resistor is connected to the ground terminal of the word line, and the other end is connected to the negative terminal of the memristor closest to the ground terminal;

[0090] V p Satisfy V set / 2 <V p <V set And V p <2|V reset |;V set V is the threshold value for the memristor to transition from a high-resistance state to a low-resistance state. resetThe threshold value at which a memristor transitions from a low-resistance state to a high-resistance state.

[0091] The above-described N-to-1 data selection method corresponds to the control method of the N-to-1 data selector in Embodiment 3 above. The related technical solutions are the same as in Embodiment 3, and will not be repeated here.

[0092] To make the technical solutions and advantages of Embodiments 3 and 4 of the present invention clearer, a 4-to-1 data selector circuit will be used as an example for the following explanation:

[0093] like Figure 7 The diagram shows a 4-to-1 data selector circuit provided by this invention. The 4-to-1 data selector circuit can be obtained by performing data selection calculations using two 2-to-1 data selector circuits, taking the resistance state of their respective output memristors as data inputs, and the resistance state of an additional memristor as data outputs, and then performing another 2-to-1 data selection calculation. Therefore, seven memristors and seven steps are required to implement the 4-to-1 data selector logic circuit. Among them, memristors M1-M7 are connected to BL1-BL7 respectively.

[0094] Based on the extended data selector circuit, this invention also provides a 4-to-1 data selection method for selecting one data from input data D0, D1, D2, and D3 based on input address A0A1; wherein memristors M3 and M6 are both pre-initialized to a high-impedance state; specifically, the above data selection method includes the following seven practical operation steps:

[0095] STEP 1: Set memristor M1 to the state corresponding to logic value D0;

[0096] STEP 2: Set the memristor M2 to the state corresponding to logic value D1;

[0097] STEP 3: Apply voltage A to memristor M1, voltage B to memristor M2, and voltage V to memristor M3. p And read the resistance state of memristor M3;

[0098] STEP 4: Set the memristor M4 to the state corresponding to logic value D2;

[0099] STEP 5: Set memristor M5 to the state corresponding to logic value D3;

[0100] STEP 6: Apply voltage A' to memristor M4, voltage B' to memristor M5, and voltage V to memristor M6. p And read the resistance state of memristor M6;

[0101] STEP 7: Apply voltage A to memristor M3, voltage B to memristor M6, and voltage V to memristor M7. p And read the resistance state of memristor M7, which is the result of N-to-1 data selection;

[0102] The values ​​of voltage A, voltage A', voltage B, and voltage B' are determined by logic value A0; the values ​​of voltage A" and voltage B" are determined by logic value A1; specifically, voltage A and voltage A' are 2V-2V. p Voltages B and B' are both -2V; when logic value A0 is 0, V is 0; when logic value A0 is 1, V is V. p The voltage A is set to 2V - 2V. p The voltage "B" takes the value -2V; when logic value A1 is 0, "V" takes the value 0; when logic value A1 is 1, "V" takes the value V. p .

[0103] It should be noted that the order of STEP1-STEP3 as a whole and STEP4-STEP6 as a whole is not limited to the above order and can be reversed; the order of STEP1 and STEP2 is also not limited to the above order and can be reversed; the order of STEP4 and STEP5 is also not limited to the above order and can be reversed.

[0104] It should be further noted that the circuit structure and operation process of other N-to-1 data selectors based on the present invention are similar to the logic operation process of 4-to-1 data selectors, and will not be described in detail here.

[0105] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A 2-to-1 data selector based on a memristor, characterized in that, The system is used to select a data from logic values ​​a and b based on logic value s, and includes: a controller, memristors M1, M2, M3, and a resistor; the initial state of memristor M3 is a high-resistance state. The controller is connected to the positive terminals of memristors M1, M2, and M3 respectively; the negative terminals of memristors M1, M2, and M3 are all connected to the same word line WL; one end of word line WL is floating and the other end is grounded; the resistor is connected to word line WL, one end of which is connected to the ground terminal of word line WL, and the other end is connected to the negative terminal of the memristor closest to the ground terminal; memristors M1, M2, and M3 are identical. The controller is configured to set memristor M1 to the resistance state corresponding to logic value a and memristor M2 to the resistance state corresponding to logic value b before data selection; during data selection, a voltage A is applied to memristor M1, a voltage B is applied to memristor M2, and a voltage V is applied to memristor M3. p And read the resistance state of the memristor M3 to obtain the result of the 2-to-1 data selection; Wherein, the voltage A is taken as 2V-2V. p The voltage B is -2V; when the logic value s is 0, V is 0; when the logic value s is 1, V is V. p V p Satisfy V set / 2 <V p <V set And V p <2|V reset |;V set V is the threshold value for the memristor to transition from a high-resistance state to a low-resistance state. reset The threshold value at which a memristor transitions from a low-resistance state to a high-resistance state.

2. The 2-to-1 data selector according to claim 1, characterized in that, The memristors M1, M2, and M3 each include a high-resistance state and a low-resistance state; the high-resistance state corresponds to the logic value "0", and the low-resistance state corresponds to the logic value "1".

3. The 2-to-1 data selector according to claim 2, characterized in that, The resistance value is between the high-resistance and low-resistance values ​​of the memristor; the resistance value is... Where R H R is the high-resistance resistance value of the memristor. L This is the low-resistance resistance value of the memristor.

4. The 2-to-1 data selector according to any one of claims 1-3, characterized in that, The controller includes a control terminal T1, a control terminal T2, and a control terminal T3; the control terminal T1 is connected to the positive terminal of the memristor M1, the control terminal T2 is connected to the positive terminal of the memristor M2, and the control terminal T3 is connected to the positive terminal of the memristor M3. When selecting data, the controller applies voltage A to memristor M1 via control terminal T1, voltage B to memristor M2 via control terminal T2, and voltage V to memristor M3 via control terminal T3. p The resistance state of the memristor M3 is read to obtain the data selection result.

5. A 2-out-of-1 data selection method, characterized in that, To select a data point from logical values ​​a and b based on logical value s, the following steps are included: S1. Set memristor M1 to the resistance state corresponding to logic value a, and set memristor M2 to the resistance state corresponding to logic value b; keep the resistance state of memristor M3 in its initial high resistance state. S2. When selecting data, apply voltage A to memristor M1, voltage B to memristor M2, and voltage C to memristor M3, and read the resistance state of memristor M3 to obtain the result of 2-to-1 data selection. In this configuration, the negative terminals of memristors M1, M2, and M3 are all connected to the same word line WL; one end of the word line WL is floating, and the other end is grounded; a resistor is connected to the word line WL, one end of which is connected to the ground terminal of the word line WL, and the other end is connected to the negative terminal of the memristor closest to the ground terminal; memristors M1, M2, and M3 are identical. The voltage A is 2V-2V. p The voltage B is -2V, and the voltage C is V. p When the logical value s is 0, V takes the value 0; when the logical value s is 1, V takes the value V. p V p Satisfy V set / 2 <V p <V set And V p <2|V reset |;V set V is the threshold value for the memristor to transition from a high-resistance state to a low-resistance state. reset The threshold value at which a memristor transitions from a low-resistance state to a high-resistance state.

6. An N-to-1 data selector based on a memristor, characterized in that, Used for input addresses A0A1......A n-1 From the input data D0, D1, ..., D N-1 Select one data point from the list; N=2 n And n is an integer greater than 1; The N-to-1 data selector includes: a controller, 2N-1 identical memristors, and a resistor; The controller is connected to the positive terminal of each memristor; the negative terminal of each memristor is connected to the same word line; one end of the word line is left floating and the other end is grounded; the resistor is connected to the word line, with one end connected to the ground terminal of the word line and the other end connected to the negative terminal of the memristor closest to the ground terminal. The controller is used to divide the N-to-1 data selection process into n rounds of data selection sub-processes; each round of data selection sub-processes performs a 2-to-1 data selection operation; specifically, it performs the following operations: The first round of data selection sub-process: randomly select 3N / 2 memristors from 2N-1 memristors, and divide the selected 3N / 2 memristors into groups of three, resulting in N / 2 groups of memristors; input data D0, D1, ..., D... N-1 The input data is divided into N / 2 groups of adjacent pairs, each corresponding to one of the N / 2 groups of memristors. In each group of memristors under the current sub-process, the first memristor is set to the resistance state corresponding to the first data in the input data pair, the second memristor is set to the resistance state corresponding to the second data in the input data pair, the third memristor is set to a high resistance state, and a voltage V is applied to the first memristor. A1 Apply voltage V to the second memristor B1 Apply voltage V to the third memristor p The voltage V A1 The value is 2V1-2V p The voltage V B1 The value is -2V1; when the logic value A0 is 0, V1 takes the value 0; when the logic value A0 is 1, V1 takes the value V. p ; The i-th round of data selection sub-process: N / 2 from the previous round of data selection sub-process... i-1 The memristors are grouped according to the order of their corresponding input data. The third memristor is grouped into pairs of adjacent third memristors, with the first third memristor in the sequence becoming the new first memristor, and the last third memristor in the sequence becoming the new second memristor, resulting in N / 2. i Group memristors; and respectively at N / 2 i Add a new third memristor to each group of memristors; in the current subprocess, apply a voltage V to the first memristor of each group of memristors. Ai Apply voltage V to the second memristor Bi Apply voltage V to its third memristor p The voltage V Ai The value is 2V i -2V p The voltage V Bi The value is -2V i When logical value A i-1 When V is 0, i The value is 0; when the logical value A i-1 When V is 1, i The value is V p i = 2, 3, ..., n; Read the resistance state of the third memristor during the nth round of data selection subprocess to obtain the result of N-to-1 data selection; Among them, V p Satisfy V set / 2 <V p <V set And V p <2|V reset |;V set V is the threshold value for the memristor to transition from a high-resistance state to a low-resistance state. reset The threshold value at which a memristor transitions from a low-resistance state to a high-resistance state.

7. The N-to-1 data selector according to claim 6, characterized in that, The memristor includes a high-resistance state and a low-resistance state; the high-resistance state corresponds to the logic value "0", and the low-resistance state corresponds to the logic value "1".

8. The N-to-1 data selector according to claim 7, characterized in that, The resistance value is between the high-resistance and low-resistance values ​​of the memristor; the resistance value is... Where R H R is the high-resistance resistance value of the memristor. L This is the low-resistance resistance value of the memristor.

9. A method for selecting 1 out of N data, characterized in that, Used for input addresses A0A1......A n-1 From the input data D0, D1, ..., D N-1 Select one data point from the pool; this includes: dividing the N-to-1 data selection process into n rounds of data selection sub-processes; each round of data selection sub-processes performs a 2-to-1 data selection operation; specifically, the following operations are performed: The first round of data selection sub-process: randomly select 3N / 2 memristors from 2N-1 memristors, and divide the selected 3N / 2 memristors into groups of three, resulting in N / 2 groups of memristors; input data D0, D1, ..., D... N-1 The input data is divided into N / 2 groups of adjacent pairs, each corresponding to one of the N / 2 groups of memristors. In each group of memristors under the current sub-process, the first memristor is set to the resistance state corresponding to the first data in the input data pair, the second memristor is set to the resistance state corresponding to the second data in the input data pair, the third memristor is set to a high resistance state, and a voltage V is applied to the first memristor. A1 Apply voltage V to the second memristor B1 Apply voltage V to the third memristor p The voltage V A1 The value is 2V1-2V p The voltage V B1 The value is -2V1; when the logic value A0 is 0, V1 takes the value 0; when the logic value A0 is 1, V1 takes the value V. p ; The i-th round of data selection sub-process: N / 2 from the previous round of data selection sub-process... i-1 The memristors are grouped according to the order of their corresponding input data. The third memristor is grouped into pairs of adjacent third memristors, with the first third memristor in the sequence becoming the new first memristor, and the last third memristor in the sequence becoming the new second memristor, resulting in N / 2. i Group memristors; and respectively at N / 2 i Add a new third memristor to each group of memristors; in the current subprocess, apply a voltage V to the first memristor of each group of memristors. Ai Apply voltage V to the second memristor Bi Apply voltage V to its third memristor p The voltage V Ai The value is 2V i -2V p The voltage V Bi The value is -2V i When logical value A i-1 When V is 0, i The value is 0; when the logical value A i-1 When V is 1, i The value is V p i = 2, 3, ..., n; Read the resistance state of the third memristor during the nth round of data selection subprocess to obtain the result of N-to-1 data selection; Where N = 2 n And n is an integer greater than 1; the negative terminals of 2N-1 memristors are all connected to the same word line; one end of the word line is floating and the other end is grounded; a resistor is connected to the word line, one end of the resistor is connected to the ground terminal of the word line, and the other end is connected to the negative terminal of the memristor closest to the ground terminal; V p Satisfy V set / 2 <V p <V set And V p <2|V reset |;V set V is the threshold value for the memristor to transition from a high-resistance state to a low-resistance state. reset The threshold value at which a memristor transitions from a low-resistance state to a high-resistance state.

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