A voltage-controlled oscillator circuit, chip and electronic device

Abstract

The application provides a voltage-controlled oscillator circuit, a chip and an electronic device. The voltage-controlled oscillator circuit comprises a first delay circuit comprising at least one first inverter; a second delay circuit connected with the first delay circuit and comprising at least one second inverter; and a control circuit connected with the second delay circuit and used for adjusting the number of the second inverters contained in the oscillator loop. The frequency of the voltage-controlled oscillator circuit can be adjusted according to actual requirements.

Description

Technical Field

[0001] This invention relates to an oscillator circuit, and more particularly to a voltage-controlled oscillator circuit, chip, and electronic device. Background Technology

[0002] A voltage-controlled oscillator (VCO) is an oscillation circuit whose output frequency corresponds to its input control voltage. A commonly used type of VCO is the ring oscillator. Current technology controls the oscillation frequency of a ring oscillator by adjusting the power supply voltage. However, in practical applications, the ring oscillator often operates in the same power domain as other devices, and adjusting the power supply voltage may affect the normal operation of other devices. Therefore, providing a solution for frequency adjustment of the ring oscillator without adjusting the power supply voltage has become one of the urgent technical problems to be solved by those skilled in the art. Summary of the Invention

[0003] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a voltage-controlled oscillator circuit, chip, and electronic device to solve the aforementioned problems existing in the prior art.

[0004] To achieve the above and other related objectives, a first aspect of the present invention provides a voltage-controlled oscillator circuit, comprising an oscillator loop, the voltage-controlled oscillator circuit comprising: a first delay circuit including at least one first inverter; a second delay circuit connected to the first delay circuit and including at least one second inverter; and a control circuit connected to the second delay circuit for adjusting the number of the second inverters included in the oscillator loop.

[0005] In one embodiment of the first aspect, the voltage-controlled oscillator circuit further includes: a multiplexer, connected to the second delay circuit and the control circuit respectively, for adjusting the number of the second inverters included in the oscillator loop under the control of the control circuit.

[0006] In one embodiment of the first aspect, the input terminals of the multiplexer are respectively connected to different terminals of the second inverter, and the control circuit adjusts the number of the second inverters included in the oscillator loop by controlling the selection path of the multiplexer.

[0007] In one embodiment of the first aspect, the first delay circuit includes an odd number of cascaded first inverters, the second delay circuit includes at least one pair of second inverters, the input of the multiplexer is connected to different endpoints of the second inverter pair, and the control circuit adjusts the number of second inverter pairs included in the oscillator loop by controlling the selection path of the multiplexer.

[0008] In one embodiment of the first aspect, the second delay circuit includes at least two cascaded delay sub-circuits, each of the delay sub-circuits including the multiplexer and at least two branches, and the number of second inverters included in different branches of the same delay sub-circuit is different. The multiplexer is used to add the corresponding branch to the oscillator loop under the control of the control circuit.

[0009] In one embodiment of the first aspect, the number of the second inverters included in each of the branches is an integer power of 0 or 2.

[0010] In one embodiment of the first aspect, the control circuit is further configured to enable the second inverter; and / or the voltage-controlled oscillator circuit further includes a glitch elimination circuit; and / or the voltage-controlled oscillator circuit includes one or more inverters with different threshold voltages.

[0011] In one embodiment of the first aspect, the voltage-controlled oscillator circuit is in the same power domain as a processor, and / or the voltage-controlled oscillator circuit is disposed adjacent to the processor, and / or the voltage-controlled oscillator circuit and the processor have the same threshold voltage logic unit.

[0012] A second aspect of the present invention provides a chip comprising the voltage-controlled oscillator circuit described in any of the first aspects of the present invention.

[0013] A third aspect of the present invention provides an electronic device comprising the voltage-controlled oscillator circuit described in any of the first aspects of the present invention.

[0014] As described above, the technical solution of the voltage-controlled oscillator circuit, chip, and electronic device of the present invention has the following beneficial effects:

[0015] In the voltage-controlled oscillator circuit, the control circuit can adjust the number of inverters contained in the oscillator loop to adjust the oscillation frequency of the voltage-controlled oscillator circuit. In this process, there is no need to adjust the power supply voltage, so it will not affect the normal operation of other devices. Attached Figure Description

[0016] Figure 1 The diagram shown is a schematic diagram of the circuit structure of the voltage-controlled oscillator circuit described in a specific embodiment of the present invention.

[0017] Figure 2 The diagram shown is a circuit diagram of the voltage-controlled oscillator circuit described in this invention in a specific embodiment.

[0018] Figure 3 The diagram shown is a circuit diagram of the voltage-controlled oscillator circuit described in this invention in a specific embodiment.

[0019] Figure 4A The diagram shown is a circuit diagram of the voltage-controlled oscillator circuit described in this invention in a specific embodiment.

[0020] Figure 4B and Figure 4C The following are circuit diagrams of the delay sub-circuit of the voltage-controlled oscillator circuit described in this invention in a specific embodiment.

[0021] Figure 5 The diagram shown is a structural schematic of the chip described in a specific embodiment of the present invention.

[0022] Component designation explanation

[0023] 100 Voltage-Controlled Oscillator Circuit

[0024] 110 First Delay Circuit

[0025] 120 Second Delay Circuit

[0026] 121_1 Delay Sub-circuit

[0027] 121_2 Delay Sub-circuit

[0028] 121_M3 Delay Sub-circuit

[0029] 130 Control Circuit

[0030] 140 multiplexer Detailed Implementation

[0031] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0032] It should be noted that the illustrations provided in the following embodiments are merely schematic representations of the basic concept of the present invention. The illustrations only show components relevant to the present invention and are not drawn according to the actual number, shape, and size of components in implementation. In actual implementation, the type, quantity, and proportion of each component can be arbitrarily changed, and the component layout may be more complex. Furthermore, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, in this document, connections between circuits include direct connections between circuits or indirect connections between circuits through devices or other circuits.

[0033] Please see Figure 1 In one embodiment of the present invention, the voltage-controlled oscillator circuit 100 includes an oscillator loop, the oscillator loop including an odd number of inverters cascaded in sequence. Specifically, the voltage-controlled oscillator circuit 100 includes a first delay circuit 110, a second delay circuit 120, and a control circuit 130.

[0034] The first delay circuit 110 includes at least one first inverter, the second delay circuit 120 includes at least one second inverter, and the second delay circuit 120 is connected to the first delay circuit 110.

[0035] The control circuit 130 is connected to the second delay circuit 120 and is used to adjust the number of second inverters included in the oscillator loop, so that the oscillator loop includes all the first inverters but not the second inverters, or so that the oscillator loop includes all the second inverters and at least one second inverter. The control circuit 130 can be implemented, for example, by a processor on a chip, or by devices such as FPGA or PLC; the specific implementation is not limited here.

[0036] It should be noted that the terms "first" and "second" in the first inverter and the second inverter are only used to distinguish whether the inverter belongs to the first delay circuit 110 or the second delay circuit 120. Both the first inverter and the second inverter are inverters and there is no essential difference between them.

[0037] In this embodiment, the oscillation frequency of the voltage-controlled oscillator circuit 100 is: Where n is the number of the first inverters included in the oscillator loop, and its value is any positive integer; m is the number of the second inverters included in the oscillator loop, and its value is an integer greater than or equal to 0, and m+n should be an odd number. Furthermore, the value of m can be adjusted by the control circuit 130.d T is the time delay for a single inverter. e T is the delay of all devices included in the oscillator loop except the inverter. When the oscillator loop contains only inverters, T e =0. Furthermore, when the first inverter and the second inverter use MOSFETs as logic units, Where VDD is the power supply voltage, which is also the operating voltage of the voltage-controlled oscillator circuit 100, L is the channel length of the MOSFET in the voltage-controlled oscillator circuit 100, and W... n W is the channel width of the N-channel MOSFET in the voltage-controlled oscillator circuit 100. p V is the channel width of the P-channel MOSFET in the voltage-controlled oscillator circuit 100; THN (T) represents the initial turn-on voltage of the N-channel MOSFET in the voltage-controlled oscillator circuit 100 at a temperature of T Kelvin. THP (T) represents the initial turn-on voltage of the P-channel MOSFET in the voltage-controlled oscillator circuit 100 at a temperature of T Kelvin. Taking an N-channel MOSFET as an example, its initial turn-on voltage... Among them, V THN (T0) represents the initial turn-on voltage of the N-channel MOSFET at a reference temperature T0. μ n (T) represents the carrier mobility of the N-channel MOSFET in the voltage-controlled oscillator circuit 100 at a temperature of T Kelvin, in μ. p (T) represents the carrier mobility of the P-channel MOSFET in the voltage-controlled oscillator circuit 100 at a temperature of T Kelvin. Taking an N-channel MOSFET as an example, its carrier mobility... Where, μ n (T0) represents the carrier mobility of an N-channel MOSFET at a reference temperature T0.

[0038] As described above, the control circuit 130 in this embodiment can adjust the oscillation frequency of the voltage-controlled oscillator circuit 100 by adjusting the number m of the second inverters included in the oscillator loop. During this process, no adjustment of the power supply voltage is required, thus not affecting the normal operation of other devices. It should be understood that the voltage-controlled oscillator circuit 100 in this embodiment can also adjust the oscillation frequency by adjusting the power supply voltage, or by adjusting both the power supply voltage and the number m of the second inverters included in the oscillator loop.

[0039] Furthermore, the oscillation frequency of the voltage-controlled oscillator circuit 100 in this embodiment is a function of temperature T, power supply voltage VDD, and process technology (including the channel length and channel width of the MOSFET). It should be noted that the above description of the oscillation frequency of the voltage-controlled oscillator circuit 100 only uses a MOSFET as an example. When the logic unit of the voltage-controlled oscillator circuit 100 is another device, its oscillation frequency is also a function of temperature, operating voltage, and process technology. When the voltage-controlled oscillator circuit 100 is used as a clock source for a chip, the chip's operating frequency is also a function of temperature, operating voltage, and process technology. Therefore, it can be seen that the voltage-controlled oscillator circuit 100 in this embodiment has a good correlation with the chip's process technology, voltage, and temperature, and the number of inverters included in the oscillator loop can be adjusted according to actual needs to obtain the desired oscillation frequency.

[0040] In one embodiment of the present invention, the voltage-controlled oscillator circuit 100 further includes a multiplexer, which is connected to the second delay circuit 120 and the control circuit 130 respectively, and is used to adjust the number of the second inverters included in the oscillator loop under the control of the control circuit 130. Specifically, the multiplexer includes at least two input terminals (i.e., selection terminals), and each input terminal of the multiplexer is connected to the first terminal and / or the second terminal of a different inverter. The control circuit 130 adds different numbers of the second inverters to the oscillator loop by controlling the selection path of the multiplexer. The first terminal of the inverter is, for example, its input terminal, and its second terminal is, for example, its output terminal.

[0041] Please see Figure 2 In one embodiment of the present invention, the second delay circuit 120 includes M1 cascaded second inverters, where M1 is a positive integer. The input terminals of the multiplexer 140 are respectively connected to different endpoints of the second inverters, wherein the second inverter endpoints are, for example, the input and / or output endpoints of the second inverters. The input terminals of the multiplexer 140 can be connected to all the second inverter endpoints, or only some of the second inverter endpoints can be connected according to actual needs. The control terminal of the multiplexer 140 is connected to the control circuit 130, which adjusts the number of second inverters included in the oscillator loop by controlling the selection path of the multiplexer 140. For example, the control circuit 130 can adjust the selection path of the multiplexer 140 by adjusting the tap position of the multiplexer 140. In this embodiment, the oscillation frequency of the voltage-controlled oscillator circuit 100 is... Where n_1 is the number of first inverters included in the oscillator loop, i.e., N1, m_1 is the number of second inverters included in the oscillator loop, and its value is an integer greater than or equal to 0 and less than or equal to M1. Furthermore, the value of m_1 can be adjusted by the control circuit 130 by controlling the selection path of the multiplexer 140. m This is the delay of the multiplexer 140.

[0042] exist Figure 2 For example, the control circuit 130 can control the path between the multiplexer 140 and the input terminal A of the second inverter 1 as a selected path. In this case, the inverters in the oscillator loop contain only N1 first inverters, where N1 is an odd number. As another example, the control circuit 130 can control the path between the multiplexer 140 and the output terminal B of the second inverter M1 as a selected path. In this case, the inverters in the oscillator loop contain N1 first inverters and M1 second inverters, where N1 + M1 is an odd number.

[0043] As can be seen from the above description, in this embodiment, the control circuit 130 controls the selection path of the multiplexer 140, thereby adjusting the number of inverters included in the oscillator loop, and thus adjusting the oscillation frequency of the voltage-controlled oscillator circuit 100.

[0044] Please see Figure 3 In one embodiment of the present invention, to reduce circuit structure and control complexity, the first delay circuit 110 includes N2 cascaded first inverters, where N2 is any odd number. The second delay circuit 120 includes M2 pairs of second inverters, each pair containing two second inverters connected in series, where M2 is a positive integer. The input terminals of the multiplexer 140 are connected to different endpoints of the second inverter pairs, where the endpoints of the second inverter pairs are, for example, the input and / or output endpoints of the second inverter pairs. The input terminals of the multiplexer 140 can be connected to all the endpoints of the second inverter pairs, or only some of the endpoints can be connected according to actual needs. The control circuit 130 adjusts the number of second inverter pairs included in the oscillator loop by controlling the selection path of the multiplexer 140.

[0045] exist Figure 3For example, the control circuit 130 can control the path between the multiplexer 140 and the input terminal C of the second inverter pair 1 as a selected path. In this case, the inverters in the oscillator loop only contain N2 first inverters. As another example, the control circuit 130 can control the path between the multiplexer 140 and the output terminal D of the second inverter pair 1 as a selected path. In this case, the inverters in the oscillator loop contain N2 first inverters and two second inverters.

[0046] Please see Figure 4A In one embodiment of the present invention, the second delay circuit 120 includes M3 cascaded delay sub-circuits 121_1, 121_2, ..., 121_M3, where M3 is a positive integer. Each delay sub-circuit includes a multiplexer 140, a first branch 1, and a second branch 2. In this embodiment, the first branch 1 of the delay sub-circuit 121_1 includes 0 second inverters, and the second branch 2 includes 2 second inverters. 1 The first branch 1 of the delay sub-circuit 121_2 contains 0 second inverters, and the second branch 2 contains 2 second inverters. 2 ...the first branch 1 of the delay sub-circuit 121_M3 contains 0 second inverters; the second branch 2 contains 2... M3 A second inverter. Each of the multiplexers 140 is used, under the control of the control circuit 130, to add either the first branch 1 or the second branch 2 in the corresponding delay sub-circuit to the oscillator loop. Specifically, in this embodiment, the two input terminals of each multiplexer 140 are respectively connected to the first branch 1 and the second branch 2 in the corresponding delay sub-circuit, and the control circuit 130 adds either the first branch 1 or the second branch 2 to the oscillator loop by controlling the selection path of the multiplexer 140.

[0047] In this embodiment, the control circuit 130 can be connected to each of the multiplexers 140 via a configuration bus, and controls the selection path of the multiplexers 140 via the configuration bus, thereby combining different inverter cascade methods. Furthermore, in this embodiment, the oscillation frequency of the voltage-controlled oscillator circuit 100 is... Where n_2 is the number of first inverters included in the oscillator loop, and m_2 is the number of second inverters included in the oscillator loop, both of which are integers greater than or equal to 0. The value of m_2 can be adjusted by the control circuit 130 through controlling the selection path of the multiplexer 140. m q represents the delay of the multiplexer 140, and q represents the number of multiplexers 140 included in the oscillator loop.

[0048] exist Figure 4A For example, the control circuit 130 can control all multiplexers 140 in the delay sub-circuits to select the first branch 1. In this case, the oscillator loop contains only N3 first inverters, where N3 is any odd number. As another example, the control circuit 130 can control the multiplexers 140 in delay sub-circuits 121_1 and 121_2 to select the first branch 2, while controlling the multiplexers 140 in the remaining delay sub-circuits to select the second branch 1. In this case, the oscillator loop contains N3 first inverters and 6 second inverters.

[0049] Preferably, each of the delay sub-circuits includes only a first branch and a second branch, wherein the first branch does not include a second inverter, and the second branch includes at least one second inverter. More preferably, the number of second inverters included in each second branch is an integer power of 2, and the number of second inverters included in the second branches of different delay sub-circuits increases sequentially with their cascade position; that is, the second branch of the first delay sub-circuit includes 2... 1 The second inverter, the second branch of the second delay sub-circuit contains 2 2 The second inverter, ..., the second branch of the M3rd delay sub-circuit contains 2 M3 A second inverter. At this time, the number of second inverters contained in each branch is an integer power of 2, so no additional decoder is needed in the voltage-controlled oscillator circuit 100, which helps to reduce circuit complexity.

[0050] It should be noted that the above is only one feasible solution in this embodiment. In practical applications, the number of branches included in each delay sub-circuit and the number of second inverters included in each branch can be arbitrarily set according to actual needs, for example... Figure 4B and Figure 4C As shown, K1 and K2 are arbitrary positive integers.

[0051] In one embodiment of the present invention, the control circuit 130 is further configured to enable the second inverter, that is, the control circuit 130 can control the enable state of one or more second inverters in the second delay circuit 120 to add or remove the one or more second inverters from the oscillator loop, thereby more accurately adjusting the oscillation frequency of the voltage-controlled oscillator circuit 100, and thus better achieving precise matching of critical timing paths.

[0052] In one embodiment of the present invention, the voltage-controlled oscillator circuit 100 further includes a glitch elimination circuit, which is used to reduce or even eliminate glitch in the voltage-controlled oscillator circuit 100. The glitch elimination circuit can be implemented using existing technology, which will not be elaborated upon here.

[0053] In one embodiment of the present invention, the voltage-controlled oscillator circuit 100 includes one or more inverters with different threshold voltages. As previously mentioned, the delay T of the inverters... d The change in oscillation frequency caused by the change in the threshold voltage is smaller than the change in the number of inverters in the oscillator loop. Therefore, by configuring one or more inverters with different threshold voltages in the voltage-controlled oscillator circuit 100 as needed, the accuracy and flexibility of the oscillation frequency adjustment in the voltage-controlled oscillator circuit 100 can be improved, thereby better achieving accurate matching of critical timing paths.

[0054] In one embodiment of the present invention, the voltage-controlled oscillator circuit 100 is in the same power domain as a processor, and / or the voltage-controlled oscillator circuit 100 is arranged adjacent to the processor, and / or the voltage-controlled oscillator circuit 100 and the processor have the same threshold voltage logic unit.

[0055] Specifically, the voltage-controlled oscillator circuit 100 and the processor are in the same power domain, meaning that the voltage-controlled oscillator circuit 100 and the processor have the same power supply. In this case, fluctuations in the power supply voltage will simultaneously affect the logic units in both the voltage-controlled oscillator circuit 100 and the processor, causing the delays of the voltage-controlled oscillator circuit 100 and the logic units in the processor to change in the same direction. Therefore, the voltage-controlled oscillator circuit 100 and the processor have good voltage correlation. Based on this, combined with... Figure 1 , Figure 2 , Figure 3 or Figure 4A As can be seen from the voltage-controlled oscillator circuit 100 shown, this embodiment can ensure that the clock signal provided by the voltage-controlled oscillator circuit 100 always meets the requirements of the critical timing path in the processor when the power supply voltage changes. The critical timing path refers to the logic path with the longest delay from input to output in the design.

[0056] Specifically, when the power supply voltage drops, the delays of both the voltage-controlled oscillator circuit 100 and the logic units in the processor decrease. At this time, the delay of the critical path in the processor also decreases, requiring a higher clock frequency. Correspondingly, the frequency of the clock signal provided by the voltage-controlled oscillator circuit 100 also increases when the power supply voltage drops. If the clock frequency required by the critical path in the processor is not significantly different from the frequency of the clock signal provided by the voltage-controlled oscillator circuit 100, they are in the same power domain, allowing the clock signal provided by the voltage-controlled oscillator circuit 100 to meet the requirements of the critical timing path in the processor. Otherwise, the control circuit 130 can determine the number of inverters that should be included in the oscillator loop based on the difference between the clock frequency required by the critical path and the oscillation frequency of the voltage-controlled oscillator circuit 100. Then, the control circuit 130 adjusts the number of second inverters included in the oscillator loop to ensure that the clock signal provided by the voltage-controlled oscillator circuit 100 meets the requirements of the critical timing path in the processor. When the power supply voltage increases, the clock signal provided by the voltage-controlled oscillator circuit 100 in this embodiment can also meet the needs of the critical timing path in the processor. The specific method is similar to that when the power supply voltage decreases, and will not be described in detail here.

[0057] Furthermore, the voltage-controlled oscillator circuit 100 is positioned adjacent to the processor, ensuring that their temperatures are essentially the same. Temperature changes also cause changes in the delay of the logic units. When the voltage-controlled oscillator 100 is positioned adjacent to the processor, temperature fluctuations simultaneously affect both the voltage-controlled oscillator 100 and the logic units in the processor, causing the delays of the voltage-controlled oscillator circuit 100 and the logic units in the processor to change in the same direction. Therefore, the voltage-controlled oscillator circuit 100 and the processor have good temperature correlation. Based on this, combined with... Figure 1 , Figure 2 , Figure 3 or Figure 4A As can be seen from the voltage-controlled oscillator circuit 100 shown, this embodiment can ensure that the clock signal provided by the voltage-controlled oscillator circuit 100 always meets the requirements of the critical timing path in the processor when the temperature changes.

[0058] Specifically, when temperature changes increase the delay of both the voltage-controlled oscillator circuit 100 and the logic units in the processor, the delay of the critical path in the processor will increase, and its clock frequency requirement will decrease. Correspondingly, the frequency of the clock signal provided by the voltage-controlled oscillator circuit 100 will also decrease under temperature conditions. If the required frequency of the critical path in the processor is not significantly different from the frequency of the clock signal provided by the voltage-controlled oscillator circuit 100, they can be arranged adjacently so that the clock signal provided by the voltage-controlled oscillator circuit 100 can meet the requirements of the critical timing path in the processor. Otherwise, the control circuit 130 can determine the number of inverters that should be included in the oscillator loop based on the difference between the required frequency and the oscillation frequency of the voltage-controlled oscillator circuit 100, and then adjust the number of second inverters included in the oscillator loop through the control circuit 130 to ensure that the clock signal provided by the voltage-controlled oscillator circuit 100 meets the requirements of the critical timing path in the processor. When temperature changes reduce the delay of both the voltage-controlled oscillator circuit 100 and the logic unit in the processor, the clock signal provided by the voltage-controlled oscillator circuit 100 in this embodiment can also meet the requirements of the critical timing path in the processor. The specific method is similar to that when temperature changes cause the delay to increase, and will not be described in detail here.

[0059] The voltage-controlled oscillator circuit 100 and the processor have logic units with the same threshold voltage, making their manufacturing processes essentially identical. As mentioned earlier, differences in the manufacturing process of logic units can also lead to variations in logic unit delays. When the voltage-controlled oscillator circuit 100 and the processor have logic units with the same threshold voltage, the impact of manufacturing process differences on the voltage-controlled oscillator circuit 100 and the logic units in the processor is essentially the same. Therefore, the voltage-controlled oscillator circuit 100 and the processor have good manufacturing process compatibility. Based on this, combined with... Figure 1 , Figure 2 , Figure 3 or Figure 4A As can be seen from the voltage-controlled oscillator circuit 100 shown, this embodiment can ensure that the clock signal provided by the voltage-controlled oscillator circuit 100 always meets the requirements of the critical timing paths in the processor, regardless of the process technology of the logic unit.

[0060] Specifically, if both the voltage-controlled oscillator circuit 100 and the logic units in the processor have inferior manufacturing processes, the latency of the logic units in the processor is greater than that of standard logic units, resulting in lower clock frequency requirements. Correspondingly, the latency of the logic units in the voltage-controlled oscillator circuit 100 is also greater than that of standard logic units, thus the frequency of the clock signal provided by the voltage-controlled oscillator circuit 100 is lower. If the required frequency of the critical path in the processor is not significantly different from the frequency of the clock signal provided by the voltage-controlled oscillator circuit 100, then logic units with the same threshold voltage ensure that the clock signal provided by the voltage-controlled oscillator circuit 100 can meet the requirements of the critical timing path in the processor. Otherwise, the control circuit 130 can determine the number of inverters to be included in the oscillator loop based on the difference between the required frequency and the oscillation frequency of the voltage-controlled oscillator circuit 100, and then adjust the number of second inverters included in the oscillator loop through the control circuit 130 to ensure that the clock signal provided by the voltage-controlled oscillator circuit 100 meets the requirements of the critical timing path in the processor. When the voltage-controlled oscillator circuit 100 and the logic unit in the processor are both of good quality, the clock signal provided by the voltage-controlled oscillator circuit 100 in this embodiment can also meet the requirements of the critical timing path in the processor. The specific method is similar to that when the logic unit of both is of poor quality, and will not be described in detail here.

[0061] As can be seen from the above description, in this embodiment, by configuring the voltage-controlled oscillator circuit 100 to be in the same power domain as a processor, adjacent to the processor, and / or having the same threshold voltage as the processor, the voltage-controlled oscillator circuit 100 has good voltage, temperature, and / or process correlation, and the clock signal provided by the voltage-controlled oscillator circuit 100 can always meet the requirements of the critical timing paths in the processor.

[0062] In one embodiment of the present invention, the voltage-controlled oscillator circuit 100 and the processor are located on the same chip. When the voltage-controlled oscillator circuit 100 and the processor are in the same power domain, adjacent to the processor, and / or in a logic unit with the same threshold voltage as the processor, the power-on process of the chip is as follows: After the chip is powered on and reset, the operating clock will default to "precise clock" and the voltage-controlled oscillator circuit 100 will be started; the configuration of the voltage-controlled oscillator circuit 100 that matches the critical timing path will be obtained, and the clock of the processor will be switched to the voltage-controlled oscillator circuit 100. Through the above process, the critical timing path in the processor can be associated with the clock frequency of the voltage-controlled oscillator circuit 100, thereby ensuring that the operating clock of the processor can always match the changes in voltage, process, and temperature well, and that the clock of the voltage-controlled oscillator circuit 100 can always meet the timing requirements of the critical timing path, so as to ensure that the processor will not have timing violations and logic operation errors.

[0063] Based on the above description of the voltage-controlled oscillator circuit, the present invention also provides a chip. Please refer to [link / reference]. Figure 5 In one embodiment of the present invention, the chip includes Figure 1 , Figure 2 , Figure 3 or Figure 4A The voltage-controlled oscillator circuit 100 is shown. Optionally, the chip further includes a processor, which is a logic unit located in the same power domain as the voltage-controlled oscillator circuit 100, situated in an adjacent location, and / or having a consistent threshold voltage.

[0064] Specifically, the chip includes at least a portion of the components in the voltage-controlled oscillator circuit 100. For example, the chip may include the entire voltage-controlled oscillator circuit 100, or it may include only the first delay circuit 110 and / or the second delay circuit 120 in the voltage-controlled oscillator circuit 100. The chip may be represented as a commercially available active device packaged from a voltage-controlled oscillator circuit 100 manufactured on a wafer using semiconductor technology; or as a commercially available active device packaged from the voltage-controlled oscillator circuit 100 using PCB packaging technology.

[0065] Based on the above description of the voltage-controlled oscillator circuit and the chip, the present invention also provides an electronic device. The electronic device includes... Figure 1 , Figure 2 , Figure 3 or Figure 4A The voltage-controlled oscillator circuit 100 shown, or including Figure 5 The chip shown.

[0066] In the voltage-controlled oscillator circuit of the present invention, the control circuit can adjust the number of inverters contained in the oscillator loop to adjust the oscillation frequency of the voltage-controlled oscillator circuit. In this process, there is no need to adjust the power supply voltage, so it will not affect the normal operation of other devices.

[0067] Furthermore, the voltage-controlled oscillator circuit can also be configured as a logic unit in the same power domain as a processor, adjacent to the processor, and / or having the same threshold voltage as the processor, thereby enabling good voltage, temperature, and / or process correlation between the voltage-controlled oscillator circuit and the processor, while the frequency of the voltage-controlled oscillator circuit can be adjusted according to actual needs.

[0068] In summary, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0069] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A voltage-controlled oscillator circuit, characterized in that, The voltage-controlled oscillator circuit includes an oscillator loop, comprising: The first delay circuit includes at least one first inverter; The second delay circuit is connected to the first delay circuit and includes at least one second inverter; A control circuit, connected to the second delay circuit, is used to adjust the number of the second inverters included in the oscillator loop. The oscillation frequency of the voltage-controlled oscillator circuit is: , in The number of the first inverters included in the oscillator loop. The number of the second inverters included in the oscillator loop. Integers greater than or equal to 0 and It is an odd number. The value is adjusted by the control circuit. The time delay for a single inverter, This refers to the delay of all devices included in the oscillator loop, excluding the inverter. The second delay circuit includes at least two cascaded delay sub-circuits. Each delay sub-circuit includes a multiplexer and at least two branches. The number of second inverters included in different branches of the same delay sub-circuit is different. The number of second inverters included in each branch is an integer power of 0 or 2. The multiplexer is used to add the corresponding branch to the oscillator loop under the control of the control circuit to adjust the number of second inverters included in the oscillator loop.

2. The voltage-controlled oscillator circuit according to claim 1, characterized in that: The input terminals of the multiplexer are connected to different endpoints of the second inverter, and the control circuit adjusts the number of the second inverters included in the oscillator loop by controlling the selection path of the multiplexer.

3. The voltage-controlled oscillator circuit according to claim 1, characterized in that: The first delay circuit includes an odd number of cascaded first inverters, the second delay circuit includes at least one pair of second inverters, the input of the multiplexer is connected to different endpoints of the second inverter pair, and the control circuit adjusts the number of second inverter pairs included in the oscillator loop by controlling the selection path of the multiplexer.

4. The voltage-controlled oscillator circuit according to claim 1, characterized in that: The control circuit is also used to enable the second inverter; and / or The voltage-controlled oscillator circuit further includes a glitch elimination circuit; and / or The voltage-controlled oscillator circuit includes one or more inverters with different threshold voltages.

5. The voltage-controlled oscillator circuit according to any one of claims 1 to 4, characterized in that: The voltage-controlled oscillator circuit is in the same power domain as a processor, and / or the voltage-controlled oscillator circuit is arranged adjacent to the processor, and / or the voltage-controlled oscillator circuit and the processor have the same threshold voltage logic unit.

6. A chip, characterized in that: The chip includes the voltage-controlled oscillator circuit according to any one of claims 1 to 5.

7. An electronic device, characterized in that: The electronic device includes the voltage-controlled oscillator circuit according to any one of claims 1 to 5.

Images