A Detection Method for a High-Bandwidth 3 Video Processing Circuit of a Suspended Object Management System

Abstract

The invention discloses a detection method for a high-bandwidth 3 video processing circuit of a suspension management system. The method controls a multi-channel video cross-point switch chip to switch a signal to a test output end through an SPI interface by simulating an input signal with a DA chip, and then tests the output signal through an AD chip to detect whether there is an abnormality in the high-bandwidth 3 video processing circuit. The method of the invention can realize the detection of the high-bandwidth 3 video processing circuit of the suspension management system, thereby improving the reliability of the suspension management system.

Description

Technical Field

[0001] The present invention belongs to the technical field of aircraft suspension management, and particularly relates to a detection method for a high-bandwidth 3 video processing circuit. Background Art

[0002] High-bandwidth 3 is a type of aircraft suspension electrical interface with a characteristic impedance of 75 ohms, used to transmit a monochrome raster composite video signal. The high-bandwidth 3 video signals at each aircraft hanging point are switched by the suspension management system and then transmitted to the aircraft cockpit display for display.

[0003] The high-bandwidth 3 video processing circuit usually consists of a multi-channel video cross-point switch chip, which is used to realize the switching operation from multiple video inputs to multiple video outputs. The multi-channel video cross-point switch chip is a non-blocking multi-channel video cross-point switch with buffered inputs and outputs, and the input and output impedances are both 75 ohms. This chip can be controlled through the SPI interface and can realize the switching function from any input channel to any output channel.

[0004] During the use of the high-bandwidth 3 video processing circuit, problems such as SPI interface communication failure, power supply abnormality, and chip failure may occur, directly affecting the function of the suspension management system. Summary of the Invention

[0005] In order to overcome the deficiencies of the prior art, the present invention provides a detection method for a high-bandwidth 3 video processing circuit of a suspension management system. By using a DA chip to simulate an input signal, the multi-channel video cross-point switch chip is controlled through the SPI interface to switch the signal to the test output terminal, and then the output signal is tested through an AD chip to detect whether there is an abnormality in the high-bandwidth 3 video processing circuit. The method of the present invention can realize the detection of the high-bandwidth 3 video processing circuit of the suspension management system, thereby improving the reliability of the suspension management system.

[0006] The technical solution adopted by the present invention to solve its technical problems includes the following steps:

[0007] Step 1: The high-bandwidth 3 video processing circuit includes an FPGA, a DA chip, an AD chip, a multi-channel video cross-point switch chip, and a bus transceiver;

[0008] Step 2: The test ports select the unused IN port and OUT port of the multi-channel video cross-point switch chip;

[0009] Step 3: Power on the system to enter the test mode, and the FPGA controls the DA chip to simulate and generate a signal with a voltage of 1V;

[0010] Step 4: The FPGA controls the IN port to be switched through to the OUT port through the SPI;

[0011] Step 5: The FPGA controls the AD chip to test the voltage of the OUT port of the multi-channel video cross-point switch chip. When the 1V voltage is not detected at the OUT port, the high-bandwidth 3 video processing circuit is abnormal, and the FPGA reports the fault information through the bus; when the 1V voltage is detected, the detection process proceeds to the next step;

[0012] Step 6: The FPGA controls the turn-off from the IN port to the OUT port through the SPI interface;

[0013] Step 7: The FPGA controls the AD chip to test the voltage of the OUT port of the multi-channel video cross-point switch chip. When the 1V voltage is not detected at the OUT port, the detection process proceeds to the next step; when the 1V voltage is detected, the high-bandwidth 3 video processing circuit is abnormal, and the FPGA reports the fault information through the bus;

[0014] Step 8: Decrease the voltage value simulated and generated by the DA chip step by step with a1V. Each time the signal voltage is adjusted, the FPGA controls the multi-channel video cross-point switch chip and the AD to complete a turn-on test and a turn-off test. Before the voltage decreases to 0V, if the test signal voltages are all normal, it indicates that the high-bandwidth 3 video switching circuit works normally, and the circuit test is completed. The FPGA reports the test passed information through the bus;

[0015] Step 9: After the test is completed, the FPGA enters the normal working mode and adjusts the input port video to the corresponding output port according to the system requirements.

[0016] Further, the multi-channel video cross-point switch chip is MAX9675ECQ+.

[0017] Further, a1 = 0.1.

[0018] The beneficial effects of the present invention are as follows:

[0019] By using the method of the present invention, the detection of the high-bandwidth 3 video processing circuit of the suspended object management system can be realized, thereby improving the reliability of the suspended object management system. Description of the Drawings

[0020] Figure 1 It is the structural diagram of the high-bandwidth 3 video processing detection circuit of the present invention. Detailed Embodiment

[0021] The present invention will be further described below in conjunction with the drawings and embodiments.

[0022] The present invention proposes a detection method for a high-bandwidth 3 video processing circuit of a suspension management system. The input signal is simulated by a DA chip, and the multi-channel video cross-point switch chip is controlled by an SPI interface to switch the signal to the test output terminal. Then, the output signal is tested by an AD chip to detect whether there is an abnormality in the high-bandwidth 3 video processing circuit.

[0023] A detection method for a high-bandwidth 3 video processing circuit of a suspension management system includes the following steps:

[0024] Step 1: The high-bandwidth 3 video processing circuit includes an FPGA, a DA chip, an AD chip, a multi-channel video cross-point switch chip, and a bus transceiver;

[0025] Step 2: The unused IN port and OUT port of the multi-channel video cross-point switch chip are selected as the test ports;

[0026] Step 3: Power on the system to enter the test mode, and the FPGA controls the DA chip to simulate and generate a signal with a voltage of 1V;

[0027] Step 4: The FPGA controls the IN port to be switched through to the OUT port through the SPI;

[0028] Step 5: The FPGA controls the AD chip to test the voltage at the OUT port of the multi-channel video cross-point switch chip. When the 1V voltage is not detected at the OUT port, the high-bandwidth 3 video processing circuit is abnormal, and the FPGA reports the fault information through the bus; when the 1V voltage is detected, the detection process proceeds to the next step;

[0029] Step 6: The FPGA controls the IN port to the OUT port to be turned off through the SPI interface;

[0030] Step 7: The FPGA controls the AD chip to test the voltage at the OUT port of the multi-channel video cross-point switch chip. When the 1V voltage is not detected at the OUT port, the detection process proceeds to the next step; when the 1V voltage is detected, the high-bandwidth 3 video processing circuit is abnormal, and the FPGA reports the fault information through the bus;

[0031] Step 8: With a step of a1V, the voltage value simulated by the DA chip is sequentially decreased. Each time the signal voltage is adjusted, the FPGA controls the multi-channel video cross-point switch chip and the AD to complete a cut-through test and a turn-off test. Before the voltage decreases to 0V, if the test signal voltages are all normal, it indicates that the high-bandwidth 3 video switching circuit works normally, the circuit test is completed, and the FPGA reports the test pass information through the bus;

[0032] Step 9: After the test is completed, the FPGA enters the normal working mode and adjusts the input port video to the corresponding output port according to the system requirements. Specific Embodiment:

[0034] This embodiment includes: a high - bandwidth 3 video control and management unit for realizing the switching control of high - bandwidth 3 video; a high - bandwidth 3 detection unit which can generate test stimuli and monitor the output signal at the same time.

[0035] Figure 1 It is the detection principle block diagram of the high - bandwidth 3 video processing circuit. The FPGA realizes the detection of the high - bandwidth 3 video processing circuit by controlling the DA chip, the high - bandwidth 3 processing circuit and the AD chip. The specific detection process is as follows:

[0036] As Figure 1 shown, taking the 4 - channel video input to 2 - channel video output circuit as an example in the present invention, the selected multi - channel video cross - point switch chip is MAX9675ECQ +. MAX9675ECQ + is a 16#16 video cross - point switch, supporting 16 - channel video input to 16 - channel video output. The high - bandwidth 3 video processing circuit of the present invention uses 4 inputs plus 2 outputs, and the unused IN5 and OUT3 ports are selected as the test ports.

[0037] When the power is on, the system enters the test mode, and the FPGA controls the DA chip to analog - generate a signal with a voltage of 1V.

[0038] The FPGA controls the IN5 interface to be switched through to the OUT3 interface via SPI.

[0039] The FPGA controls the AD chip to test the voltage at the OUT3 output terminal of MAX9675ECQ +. When the 1V voltage is not detected at OUT3, the high - bandwidth 3 video processing circuit is abnormal, and the FPGA reports the fault information through the bus. When the 1V voltage is detected, the detection process enters the next step.

[0040] The FPGA controls the IN5 to OUT3 interface to be turned off through the SPI interface.

[0041] The FPGA controls the AD chip to test the voltage at the OUT3 output terminal of MAX9675ECQ +. When the 1V voltage is not detected at OUT3, the detection process enters the next step. When the 1V voltage is detected, the high - bandwidth 3 video processing circuit is abnormal, and the FPGA reports the fault information through the bus.

[0042] The FPGA controls the DA to adjust the amplitude of the generated signal, and the voltage is adjusted to 0.9V. Repeat the above operations to test whether the signal can be switched through normally.

[0043] With a step of 0.1V, the signal voltage value output by the DA chip is decreased successively. Each time the signal voltage is adjusted, the FPGA controls the MAX9675ECQ+ and the AD chip to complete a turn-on test and a turn-off test. Before the voltage decreases to 0V, if the test signal voltages are all normal, it indicates that the high-bandwidth 3-video switching circuit works properly, and the circuit test is completed. The FPGA reports the test pass information through the bus.

[0044] After the test is completed, the FPGA enters the normal working mode and adjusts the input interface video to the corresponding output interface according to the system requirements.

Claims

1. A detection method for a high-bandwidth 3 video processing circuit of a suspension management system, characterized in that, It includes the following steps: Step 1: The high-bandwidth 3 video processing circuit includes an FPGA, a DA chip, an AD chip, a multi-channel video cross-point switch chip, and a bus transceiver; Step 2: The test ports select the unused IN port and OUT port of the multi-channel video cross-point switch chip; Step 3: Power on the system to enter the test mode, and the FPGA controls the DA chip to simulate and generate a signal with a voltage of 1V; Step 4: The FPGA controls the IN port to be switched through to the OUT port via SPI; Step 5: The FPGA controls the AD chip to test the voltage at the OUT port of the multi-channel video cross-point switch chip. When the 1V voltage is not detected at the OUT port, the high-bandwidth 3 video processing circuit is abnormal, and the FPGA reports the fault information via the bus; when the 1V voltage is detected, the detection process proceeds to the next step; Step 6: The FPGA controls the IN port to be turned off from the OUT port via the SPI interface; Step 7: The FPGA controls the AD chip to test the voltage at the OUT port of the multi-channel video cross-point switch chip. When the 1V voltage is not detected at the OUT port, the detection process proceeds to the next step; when the 1V voltage is detected, the high-bandwidth 3 video processing circuit is abnormal, and the FPGA reports the fault information via the bus; Step 8: With a step of a1V, sequentially decrease the voltage value simulated and generated by the DA chip. Each time the signal voltage is adjusted, the FPGA controls the multi-channel video cross-point switch chip and the AD to complete a through test and a turn-off test. Before the voltage decreases to 0V, if the test signal voltages are all normal, it indicates that the high-bandwidth 3 video switching circuit works normally, the circuit test is completed, and the FPGA reports the test passed information via the bus; Step 9: After the test is completed, the FPGA enters the normal working mode and adjusts the input port video to the corresponding output port according to the system requirements.

2. The detection method for a high-bandwidth 3 video processing circuit of a suspension management system according to claim 1, characterized in that, The multi-channel video cross-point switch chip is MAX9675ECQ+.

3. The detection method for a high-bandwidth 3 video processing circuit of a suspension management system according to claim 1, characterized in that, The a1 = 0.1.

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