Semiconductor structure and its fabrication method

Abstract

This invention provides a semiconductor structure and a method for fabricating the same. The method includes: providing a substrate; forming bit lines on the substrate and forming semiconductor channels on the surfaces of the bit lines away from the substrate, the semiconductor channels including a first doped region, a channel region, and a second doped region arranged sequentially; forming a first dielectric layer surrounding the sidewalls of the semiconductor channel, with a first gap between adjacent first dielectric layers on the same bit line; forming a second dielectric layer filling the first gap, the material of the second dielectric layer being different from that of the first dielectric layer; removing a portion of the first dielectric layer to expose the sidewalls of the channel region; forming an insulating layer at least covering the surface of the sidewalls of the channel region, with a second gap between the insulating layer and the second dielectric layer; and forming word lines filling the second gap. This invention simplifies the steps of forming word lines and produces word lines that are small in size and have high precision.

Description

Technical Field

[0001] This invention relates to the field of semiconductors, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] As the integration density of semiconductor devices continues to increase, research has begun on the arrangement of transistors in semiconductor structures and how to reduce the size of individual functional devices in semiconductor structures.

[0003] In related technologies, the area occupied by the memory cell of Dynamic Random Access Memory (DRAM) based on saddle-shaped fin transistor is 6F2 (F: the minimum pattern size that can be obtained under given process conditions). In order to further reduce the area occupied by DRAM, when scaling DRAM proportionally, problems such as the proximity gate effect will be encountered, which will have an adverse effect on the electrical performance of DRAM.

[0004] When using a vertical gate-all-around (GAA) transistor structure as an access transistor, its area can reach 4F. 2 In principle, higher density efficiency can be achieved, but in some sizes, due to the limitations of the equipment and manufacturing process used, there are problems such as difficulty in etching the letter lines. Summary of the Invention

[0005] The technical problem solved by the embodiments of the present invention is to provide a semiconductor structure and its fabrication method, which is beneficial to simplifying the word line formation steps and forming word lines and semiconductor channels with high dimensional accuracy and small size.

[0006] To address the aforementioned problems, embodiments of the present invention provide a method for fabricating a semiconductor structure, comprising: providing a substrate; forming bit lines on the substrate, and forming semiconductor channels on the surface of the bit lines away from the substrate, wherein the semiconductor channels include a first doped region, a channel region, and a second doped region arranged sequentially along the direction from the substrate to the bit lines; forming a first dielectric layer, the first dielectric layer surrounding the sidewalls of the semiconductor channel, and having a first gap between adjacent first dielectric layers on the same bit line and adjacent sidewalls of the semiconductor channel; forming a second dielectric layer, the second dielectric layer filling the first gap, and having a material different from that of the first dielectric layer; removing a portion of the first dielectric layer to expose the sidewalls of the channel regions; forming an insulating layer, the insulating layer at least covering the surface of the sidewalls of the channel regions, and having a second gap between the insulating layer and the second dielectric layer; and forming word lines, the word lines filling the second gap.

[0007] Accordingly, embodiments of the present invention also provide a semiconductor structure, comprising: a substrate; a bit line located on the substrate; a semiconductor channel located on the surface of the bit line, wherein, in a direction along the substrate pointing to the bit line, the semiconductor channel includes a first doped region, a channel region, and a second doped region arranged sequentially, the first doped region being in contact with the bit line; a first dielectric layer disposed around the first doped region, wherein the first dielectric layers adjacent to the sidewalls of the first doped region on the same bit line have a first spacing; an insulating layer at least covering the sidewall surface of the channel region; a word line surrounding the insulating layer located on the sidewall of the channel region, wherein adjacent word lines have a second spacing; and an isolation layer located at least in the first spacing and the second spacing, wherein the top surface of the isolation layer away from the substrate is not lower than the top surface of the second doped region away from the substrate.

[0008] Compared with related technologies, the technical solution provided by the embodiments of the present invention has the following advantages:

[0009] In the above technical solution, a vertical GAA transistor is formed on the substrate, and the bit line is located between the substrate and the GAA transistor, thus forming a 3D stacked semiconductor structure, which is beneficial to improving the integration density of the semiconductor structure. Moreover, part of the first dielectric layer occupies the position of the insulating layer and word line to be formed later. After the second dielectric layer is formed, when the first dielectric layer located on the sidewall of the channel region is removed, the remaining first dielectric layer is located on the sidewall of the first doped region. This allows the remaining first dielectric layer to protect the first doped region from being affected when the insulating layer is formed on the sidewall of the channel region. Furthermore, a second gap is formed between the insulating layer and the second dielectric layer. The word line with precise size can be formed in the second gap by self-alignment, and high-precision word lines can be formed without etching processes, which simplifies the word line formation steps. Moreover, by controlling the size of the second gap, small-sized word lines can be obtained. Attached Figure Description

[0010] One or more embodiments are illustrated by way of example with reference to the accompanying drawings, which are not to be limited in scale unless otherwise stated.

[0011] Figures 1 to 25 A schematic diagram of the structure corresponding to each step of the method for fabricating a semiconductor structure according to an embodiment of the present invention;

[0012] Figures 26 to 31 This is a schematic diagram of the steps involved in fabricating a semiconductor structure according to another embodiment of the present invention. Detailed Implementation

[0013] As can be seen from the background technology, the fabrication process for forming vertically structured GAA transistors currently needs to be optimized.

[0014] Analysis revealed that forming word lines around the channel sidewalls of the semiconductor channel in a GAA transistor typically requires two process steps: deposition and etching, to create multiple discrete word lines. However, due to high integration density and small spacing between adjacent semiconductor channels, the etching precision is difficult to control during word line formation, resulting in inconsistent word line dimensional accuracy. Furthermore, when GAA transistors are small, forming vertical GAA junction transistors makes it difficult to control the doping concentration in different regions of the semiconductor channel, affecting the yield of the final PN junction.

[0015] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure and its fabrication method. In the fabrication method, a portion of the first dielectric layer occupies the positions of the subsequently formed insulating layer and word lines. After the second dielectric layer is formed, when the first dielectric layer located on the sidewall of the channel region is removed, the remaining first dielectric layer is located on the sidewall of the first doped region. This ensures that when the insulating layer is formed on the sidewall of the channel region, the remaining first dielectric layer protects the first doped region from being affected. Furthermore, a second gap is formed between the insulating layer and the second dielectric layer. Precise word lines can then be formed in the second gap through self-alignment, achieving high-precision word lines without the need for etching processes. This simplifies the word line formation steps. Moreover, by controlling the size of the second gap, small-sized word lines can be obtained. Additionally, the doping concentrations of the dopant ions in the first doped region, the channel region, and the second doped region can be the same, making the device formed by the semiconductor channel 105 a junctionless transistor.

[0016] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the various embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been presented in the various embodiments of the present invention to enable the reader to better understand this application. However, the technical solutions claimed in this application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0017] An embodiment of the present invention provides a method for fabricating a semiconductor structure. The method for fabricating a semiconductor structure according to an embodiment of the present invention will be described in detail below with reference to the accompanying drawings. Figures 1 to 25 This is a schematic diagram of the structure corresponding to each step of a semiconductor structure fabrication method according to an embodiment of the present invention. It should be noted that, for ease of description and clear illustration of the steps of the semiconductor structure fabrication method, the following diagrams are provided in this embodiment. Figures 1 to 25 These are partial structural diagrams of semiconductor structures.

[0018] refer to Figure 1A substrate 100 is provided. In this embodiment, the substrate 100 includes a substrate 110 and a buffer layer 120 and a protective layer 130 stacked sequentially on the substrate 110.

[0019] In this embodiment, providing the substrate 100 includes the following steps:

[0020] A substrate 110 is provided. Specifically, the material type of the substrate 110 can be an elemental semiconductor material or a crystalline inorganic compound semiconductor material. The elemental semiconductor material can be silicon or germanium; the crystalline inorganic compound semiconductor material can be silicon carbide, silicon germanide, gallium arsenide, or indium gallium, etc.

[0021] The substrate 110 includes: a semiconductor well layer 11, in which first type ions are doped; and an initial semiconductor layer 10 disposed on the semiconductor well layer 11.

[0022] The initial semiconductor layer 10 is doped and annealed to incorporate a second type of ions, which are used to form bit lines and semiconductor channels on top of the initial semiconductor layer 10. The second type of ions differs from the first type of ions; both types are either N-type or P-type ions. Specifically, the N-type ions are at least one of arsenic, phosphorus, or antimony ions; and the P-type ions are at least one of boron, indium, or gallium ions.

[0023] The doping process can be carried out by high-temperature diffusion or ion implantation. When the initial semiconductor layer 10 is doped by ion implantation, the annealing temperature of the annealing process is 800℃~1000℃.

[0024] In this embodiment, the doping concentration of the second type of ions in the initial semiconductor layer 10 is 1×10⁻⁶. 19 atom / cm 3 ~1×10 20 atom / cm 3 Furthermore, in the direction from the initial semiconductor layer 10 to the semiconductor well layer 11, the doping depth of the second type of ions within the initial semiconductor layer 10 is 150 nm to 250 nm. Additionally, the first type of ions are P-type ions, and the second type of ions are N-type ions. In other embodiments, the first type of ions can be N-type ions, and the second type of ions can be P-type ions.

[0025] A buffer layer 120 and a protective layer 130 are sequentially stacked on the side of the initial semiconductor layer 10 away from the semiconductor well layer 11. In some examples, the buffer layer 120 and the protective layer 130 can be formed by a deposition process, wherein the material of the buffer layer 120 is silicon oxide and the material of the protective layer 130 is silicon nitride.

[0026] Furthermore, silicon nitride can be deposited using a chemical vapor deposition process to form a protective layer 130. The oxidation rate of the silicon nitride film is very slow, which is beneficial for protecting the substrate 110 located below the silicon nitride film and preventing the substrate 110 from being oxidized.

[0027] In some examples, substrate 110 is a silicon substrate. Because the mismatch rate between the lattice constant and thermal expansion coefficient of silicon nitride and that of the silicon substrate is very large, directly forming silicon nitride on the silicon substrate results in a high defect density at the silicon-nitride interface. This defect density easily becomes carrier traps and recombination centers, affecting the carrier mobility of silicon and thus impacting the performance and lifespan of the semiconductor structure. Furthermore, silicon nitride films exhibit high stress, making them prone to cracking when directly deposited on a silicon substrate. Therefore, forming silicon oxide as a buffer layer 120 before depositing silicon nitride on the silicon substrate is beneficial for improving the performance and lifespan of the conductor structure.

[0028] refer to Figures 1 to 4 A bit line 104 is formed on a substrate 100, and a semiconductor channel 105 is formed on the surface of the bit line 104 away from the substrate 100. In the direction Z along the substrate 100 to the bit line 104, the semiconductor channel 105 includes a first doped region I, a channel region II and a second doped region III arranged sequentially.

[0029] In this embodiment, forming the bit line 104 and the semiconductor channel 105 includes the following steps:

[0030] Continue to refer to Figure 1 A first mask layer 102 is formed on a substrate 100. The first mask layer 102 has a plurality of mutually independent first openings b. The length of the first opening b is consistent with the length of the bit line subsequently formed along the extension direction X of the first opening b.

[0031] refer to Figure 2 Using the first mask layer 102 as a mask, the substrate 100 is etched to form multiple first trenches a, and the first mask layer 102 is removed.

[0032] In this embodiment, the depth of the first trench a along the direction Z perpendicular to the surface of the substrate 100 is 250–300 nm. Since the depth of the first trench a is greater than the doping depth of the second type of ions in the initial semiconductor layer 10, it is beneficial to ensure that the initial semiconductor layer 10 doped with the second type of ions is etched, which facilitates the subsequent formation of semiconductor channels and bit lines with high doping concentration of the second type of ions.

[0033] refer to Figure 3 A fifth dielectric layer 153 is formed in the first trench a.

[0034] In this embodiment, the fifth dielectric layer 153 can be formed using the following process steps: performing a deposition process to form a fifth dielectric film covering the top surface of the protective layer 130 and filling it; performing chemical mechanical planarization on the fifth dielectric film until the top surface of the protective layer 130 is exposed, with the remaining fifth dielectric film serving as the fifth dielectric layer 153. The material of the fifth dielectric film includes silicon oxide.

[0035] Furthermore, a second mask layer 112 is formed on the top surface formed by the fifth dielectric layer 153 and the remaining substrate 100. The second mask layer 112 has a plurality of mutually independent second openings c. In the extension direction Y of the second openings c, the length of the second openings c is consistent with the length of the word lines subsequently formed.

[0036] In this embodiment, in conjunction with the reference Figure 1 and Figure 3 The extension direction X of the first opening b is perpendicular to the extension direction Y of the second opening c, resulting in a 4F semiconductor channel. 2 This arrangement is beneficial for further improving the integration density of the semiconductor structure. In other embodiments, the extension direction of the first opening intersects the extension direction of the second opening, and the included angle between them may not be 90°.

[0037] Furthermore, the ratio of the opening width of the first opening b along the Y direction to the opening width of the second opening c along the X direction is 2 to 1, to ensure that a via can be formed subsequently to expose the first dielectric layer surrounding the sidewall of the channel region II, thereby facilitating the subsequent formation of the second gap for manufacturing word lines. In some examples, the opening width of the first opening b along the Y direction is equal to the opening width of the second opening c along the X direction, and the spacing between adjacent first openings b is equal to the spacing between adjacent second openings c. On the one hand, this makes the subsequent formation of multiple semiconductor channels more regular, further improving the integration density of the semiconductor structure; on the other hand, the same mask can be used to form the first mask layer 102 and the second mask layer 112, which helps to reduce the fabrication cost of the semiconductor structure.

[0038] In this embodiment, the methods for forming the first mask layer 102 and the second mask layer 112 both include self-aligned quadruple patterning (SAQP) or self-aligned double patterning (SADP).

[0039] refer to Figure 4 Using the second mask layer 112 as a mask, the substrate 100 is etched (reference). Figure 1The second trench d is formed with the fifth dielectric layer 153, forming a plurality of second trenches d, bit lines 104 and semiconductor channels 105. In the direction Z perpendicular to the surface of the substrate 100, the depth of the second trench d is less than the depth of the first trench a. This is beneficial to form a plurality of mutually discrete semiconductor channels 105 on the side of the bit line 104 away from the semiconductor well layer 11 while forming the bit line 104. The bit line 104 is in contact with the first doped region I of the semiconductor channel 105. The second mask layer 112 is removed.

[0040] In some examples, the depth of the second trench d is 100 nm to 150 nm, due to the initial semiconductor layer 10 (reference). Figure 1 The doping depth of the second type of ions in the semiconductor layer is 150nm to 250nm, which is beneficial to transform the initial semiconductor layer 10, which is mostly or entirely doped with the second type of ions, into a semiconductor channel 105 after two etching processes.

[0041] Furthermore, the substrate 110 is made of silicon, and the fifth dielectric layer 153 is made of silicon oxide. In the step of etching the substrate 100 and the fifth dielectric layer 153 using the second mask layer 112 as a mask, the etching rate of silicon oxide is greater than that of silicon, so some sidewalls of the bit line 104 will be exposed.

[0042] In this embodiment, a plurality of spaced bit lines 104 can be formed on the semiconductor well layer 11, and each bit line 104 can be in contact with at least one first doped region I. Figure 4 The example uses four spaced bit lines 104 and each bit line 104 in contact with four first doped regions I. The number of bit lines 104 and the number of first doped regions I in contact with each bit line 104 can be reasonably set according to actual electrical requirements.

[0043] In order to achieve electrical insulation between adjacent bit lines 104 and adjacent semiconductor channels 105, after etching the substrate 100 and the fifth dielectric layer 153 with the second mask layer 112 as a mask, the remaining fifth dielectric layer 153 is also located in the interval between adjacent bit lines 104 and in the interval between adjacent semiconductor channels 105.

[0044] In this embodiment, due to the initial semiconductor layer 10 (reference) Figure 1 Since the bit line 104 and semiconductor channel 105 formed in this step are doped with N-type ions, they can be doped with N-type ions.

[0045] In this embodiment, bit line 104 is doped with N-type ions, and semiconductor well layer 11 is doped with P-type ions. Therefore, bit line 104 and semiconductor well layer 11 form a PN junction. This PN junction helps prevent leakage current in bit line 104 and further improves the electrical performance of the semiconductor structure. It should be noted that in other embodiments, the substrate may not include a semiconductor well layer, that is, the substrate is an initial semiconductor layer, and the bit line is located on the surface of the initial semiconductor layer.

[0046] Furthermore, the device formed by the semiconductor channel 105 is a junctionless transistor, that is, the dopant ions in the first doped region I, the channel region II, and the second doped region III are of the same type, for example, the dopant ions are all N-type ions. Further, the dopant ions in the first doped region I, the channel region II, and the second doped region III can be the same. Here, "junctionless" refers to the absence of a PN junction, meaning the transistor formed by semiconductor channel 105 does not have a PN junction. This means the doping concentration of the dopant ions in the first doped region I, channel region II, and second doped region III is the same. The advantages of this include: firstly, it eliminates the need for additional doping of the first and second doped regions I and III, thus avoiding the difficulty in controlling the doping process of these regions, especially as transistor sizes shrink further, making doping concentration control even more challenging; secondly, since the device is a junctionless transistor, it avoids the phenomenon of creating ultra-steep PN junctions at the nanoscale using ultra-steep source-drain concentration gradient doping processes. This avoids problems such as threshold voltage drift and increased leakage current caused by abrupt doping changes, and also helps suppress short-channel effects, allowing operation at scales of a few nanometers. Therefore, it contributes to further improving the integration density and electrical performance of the semiconductor structure. It is understood that "additional doping" here refers to doping performed to differentiate the dopant ion types in the first and second doped regions III from those in the channel region II.

[0047] Furthermore, the semiconductor channel 105 is formed perpendicular to the bit line 104 and away from the top surface of the semiconductor well layer 11. This can constitute a 3D stacked semiconductor structure, which is beneficial for designing GAA transistors with smaller size features without adversely affecting the electrical performance of the GAA transistors, thereby improving the integration density of the semiconductor structure.

[0048] In this embodiment, bit lines 104 and semiconductor channels 105 are simultaneously formed through two etching processes using a first mask layer 102 and a second mask layer 112. On one hand, this facilitates the control of the size of the semiconductor channel 105 by adjusting the dimensions of the first opening b and the second opening c, resulting in a semiconductor channel 105 with high dimensional accuracy. On the other hand, both bit lines 104 and semiconductor channels 105 are formed by etching the substrate 110, meaning they utilize the same film structure, making them an integral structure. This improves the interface state defects between bit lines 104 and semiconductor channels 105, thereby improving the performance of the semiconductor structure. Furthermore, after etching the substrate 100 using the first mask layer 102, a fifth dielectric layer 153 is formed in the first trench a. This prepares for the subsequent formation of a gap between the sidewall of the channel region II and the second dielectric layer, facilitating the subsequent formation of the second gap for word line fabrication.

[0049] refer to Figures 5 to 8 A first dielectric layer 113 is formed, which surrounds the sidewall of the semiconductor channel 105 and has a first gap e between adjacent first dielectric layers 113 on the same bit line 104.

[0050] in, Figure 7 for Figure 6 The diagram shows a cross-sectional view of the structure along the first section direction AA1. Figure 8 for Figure 6 The diagram shows a cross-sectional view of the structure along the second section direction BB1. It should be noted that subsequent descriptions will include either a cross-sectional view along the first section direction AA1 or a cross-sectional view along the second section direction BB1, or both. When referring to only one drawing, the drawing is a cross-sectional view along the first section direction AA1; when referring to both drawings, the drawing is first a cross-sectional view along the first section direction AA1, and then a cross-sectional view along the second section direction BB1.

[0051] In this embodiment, forming the first dielectric layer includes the following steps:

[0052] refer to Figure 5 A sixth dielectric film 103 is formed, which conformally covers the sidewalls and bottom of the second trench d and is also located on the top surface of the protective layer 130 and the fifth dielectric layer 153.

[0053] Reference Figure 5 and Figure 6 The sixth dielectric film 103 is subjected to a maskless dry etching process until the protective layer 130 is exposed. Within the same etching time, the etching process etches the same thickness in different regions of the sixth dielectric film 103 to form the sixth dielectric layer 163.

[0054] Reference Figures 6 to 8 The sixth dielectric layer 163 is located on the sidewall of the second trench d, and the fifth dielectric layer 153 is located in the interval between adjacent semiconductor channels 105. The fifth dielectric layer 153 and the sixth dielectric layer 163 together form the first dielectric layer 113, and there is a first gap e between the sixth dielectric layers 163 located on the sidewall of the second trench d.

[0055] The material of the sixth dielectric layer 163 is the same as that of the fifth dielectric layer 153, which facilitates the subsequent removal of the sixth dielectric layer 163 and the fifth dielectric layer 153 corresponding to the sidewall of the channel region II through an etching process. This creates a gap between the sidewall of the channel region II and the subsequently formed second dielectric layer, which is beneficial for the subsequent formation of the second gap for the word line. Furthermore, the material of the sixth dielectric layer 163 and the fifth dielectric layer 153 is both silicon oxide.

[0056] In other embodiments, the materials of the sixth dielectric layer and the fifth dielectric layer can also be different, as long as the materials of the sixth dielectric layer and the fifth dielectric layer are materials with good insulation effect. Then, the sixth dielectric layer and the fifth dielectric layer corresponding to the sidewall of the trench region can be removed step by step.

[0057] Reference Figure 7 and Figure 9 A second dielectric layer 123 is formed, which fills the first gap e, and the material of the second dielectric layer 123 is different from the material of the first dielectric layer 113.

[0058] In some examples, the second dielectric layer 123 may be formed using the following process steps: performing a deposition process to form a second dielectric film covering the top surface of the protective layer 130 and filling the first gap e; and depositing the second dielectric film, the protective layer 130, the buffer layer 120, and the first dielectric layer 113 (see reference). Figure 6 The second dielectric film is subjected to chemical mechanical planarization to expose the top surface of the second doped region III, and the remaining second dielectric film serves as the second dielectric layer 123. The material of the second dielectric film includes silicon nitride.

[0059] refer to Figures 10 to 17 Remove part of the first medium layer 113 to expose the sidewall of the channel area II.

[0060] In some examples, removing a portion of the first dielectric layer 113 to expose the sidewall of the trench region II includes the following steps:

[0061] Reference Figure 9 and Figure 10Using the semiconductor channel 105 and the second dielectric layer 123 as a mask, a portion of the first dielectric layer 113 is etched until the sidewall of the second doped region III is exposed. In some examples, the height of the second doped region III is 30 nm to 50 nm in the direction Z perpendicular to the bit line 104 pointing to the semiconductor channel 105.

[0062] refer to Figures 11 to 14 ,in, Figure 12 for Figure 11 A top-down view diagram. Figure 13 This is a schematic cross-sectional view along the direction CC1 of the third section. Figure 14 This is a schematic cross-sectional view along the direction BB1 of the second section.

[0063] A third dielectric layer 133 is formed, which surrounds the sidewall of the second doped region III and the sidewall of the second dielectric layer 123. The third dielectric layer 133 located on the sidewall of the second doped region III and the third dielectric layer 133 located on the sidewall of the second dielectric layer 123 together form a via f. The bottom of the via f exposes the first dielectric layer 113, and the material of the third dielectric layer 133 is different from that of the first dielectric layer 113.

[0064] Further, refer to Figure 13 and Figure 14 The third dielectric layer 133 surrounds the sidewall of the second doped region III and covers the top surface of the sixth dielectric layer 163 and part of the top surface of the fifth dielectric layer 153. The via f exposes part of the top surface of the fifth dielectric layer 153.

[0065] In this embodiment, the third dielectric layer 133 can be formed using the following process steps: A deposition process is performed to form a third dielectric film conformally covering the surface composed of the semiconductor channel 105, the first dielectric layer 113, and the second dielectric layer 123; a maskless dry etching process is performed on the third dielectric film until the top surface of the second doped region III is exposed; using the same etching time, the etching process etches the same thickness in different regions of the third dielectric film, forming a third dielectric layer 133 exposing the first dielectric layer 113. The material of the third dielectric layer 133 includes silicon nitride.

[0066] Furthermore, in the aforementioned first mask layer 102 and second mask layer 112, the ratio of the opening width of the first opening b along the Y direction to the opening width of the second opening c along the X direction is 2 to 1. When forming the third dielectric layer 133, this is beneficial to ensure that the third dielectric layer 133 fills the gap between adjacent semiconductor channels 105 on the same bit line 104 without filling the gap between adjacent semiconductor channels 105 on adjacent bit lines 104. This ensures the formation of a via f that exposes part of the top surface of the fifth dielectric layer 153, which facilitates the subsequent removal of part of the first dielectric layer 113 using the via f.

[0067] refer to Figures 15 to 17 Remove the first dielectric layer 113 exposed on the sidewall of the channel region II by removing the via f, and the remaining first dielectric layer 113 surrounds the sidewall of the first doped region I.

[0068] Since the via f exposes part of the top surface of the first dielectric layer 113, and the material of the first dielectric layer 113 is different from the materials of the second dielectric layer 123 and the third dielectric layer 133, an etching solution can be injected into the via f, and the first dielectric layer 113 located on the sidewall of the channel region II can be removed by a wet etching process, while the first dielectric layer 113 located on the sidewall of the first doped region I can be retained.

[0069] Furthermore, the second dielectric layer 123 and the third dielectric layer 133 together form a support framework, which is in contact with and connected to the second doped region III, and a portion of the support framework is embedded in the first dielectric layer 113. During the wet etching process, on the one hand, the support framework provides support and fixation for the semiconductor channel 105. When the etching solution flows, it generates a squeezing force on the semiconductor channel 105, which helps prevent the semiconductor channel 105 from tilting or shifting due to squeezing, thereby improving the stability of the semiconductor structure. On the other hand, the support framework wraps around the sidewalls of the second doped region III, which helps prevent the etching solution from damaging the second doped region III.

[0070] After the first medium layer 113 located on the side wall of channel area II is removed, a third gap g is formed between channel area II and the second medium layer 123. The through hole f and the third gap g together form the cave structure h.

[0071] refer to Figure 18 and Figure 19 An insulating layer 106 is formed, which at least covers the sidewall surface of the trench region II, and a second gap i is formed between the insulating layer 106 and the second dielectric layer 123. Further, referring to… Figure 19 The second gap i is also located between the insulating layers 106 of the sidewalls of the adjacent semiconductor channel 105 of the adjacent bit line 104.

[0072] In this embodiment, since the semiconductor channel 105 is made of silicon, the step of forming the insulating layer 106 includes: thermally oxidizing the exposed sidewalls of the channel region II to form the insulating layer 106, and the insulating layer 106 covers the remaining sidewall surfaces of the channel region II. The insulating layer 106 is made of silicon oxide. In other embodiments, the insulating layer covering the sidewall surfaces of the channel region can also be formed by a deposition process.

[0073] Because the exposed sidewalls of the channel region II are thermally oxidized, a portion of the channel region II is transformed into an insulating layer 106. This results in the orthogonal projection of the channel region II onto the bit line 104 being smaller than the orthogonal projection of the second doped region III onto the bit line 104, and also smaller than the orthogonal projection of the first doped region I onto the bit line 104. This facilitates the formation of a channel region II with a smaller cross-sectional area in the Z direction perpendicular to the bit line 104 and pointing to the semiconductor channel 105 without the need for etching. This improves the control capability of the subsequently formed word lines over the channel region II, making it easier to control the turn-on or turn-off of the GAA transistor.

[0074] In some examples, in a cross-section perpendicular to direction Z, the width W and length L of channel region II are no more than 10 nm, which helps ensure good control over channel region II by the subsequently formed word lines. Furthermore, the height of channel region II in direction Z is 30 nm to 50 nm.

[0075] Furthermore, since the top surface of the second doped region III is exposed, during the thermal oxidation process, a portion of the second doped region II near its top surface is also transformed into the insulating layer 106. In this embodiment, the insulating layer 106 located on the top surface of the remaining second doped region III is removed in subsequent process steps. In other embodiments, the insulating layer located on the top surface of the remaining second doped region can be removed after the thermal oxidation process, leaving only the insulating layer covering the sidewall surface of the remaining channel region.

[0076] Continue to refer to Figure 18 and Figure 19 The orthographic projection of the periphery of the insulating layer 106 onto the bit line 104 is smaller than the orthographic projection of the periphery of the third dielectric layer 133 onto the bit line 104. That is, the outer wall of the insulating layer 106 away from the semiconductor channel 105 is closer to the semiconductor channel 105 than the outer wall of the third dielectric layer 133 away from the semiconductor channel 105. This ensures a second gap i between the insulating layer 106 and the second dielectric layer 123, allowing subsequent word lines to surround the insulating layer 106 located on the sidewall of the channel region II. Furthermore, the outer wall of the insulating layer 106 away from the semiconductor channel 105 is smaller than the outer wall of the first dielectric layer 113 (see reference). Figure 15 It can be located away from the outer wall of semiconductor channel 105 or closer to semiconductor channel 105.

[0077] refer to Figure 20 and Figure 22 ,in, Figure 22 for Figure 21 A partial cross-sectional view of a single line 107 surrounding four semiconductor channels 105.

[0078] Forming character line 107, character line 107 fills the second gap i.

[0079] In this embodiment, the step of forming word line 107 includes: forming an initial word line that fills the second gap i and the via f. Specifically, the initial word line is located between the insulating layer 106 and the second dielectric layer 123, and between the insulating layers 106 on the sidewalls of adjacent channel regions II on adjacent bit lines 104; removing the initial word line located in the via f, and the remaining initial word line serves as word line 107. The initial word line can be formed by a deposition process, and the material of the initial word line includes at least one of polysilicon, titanium nitride, tantalum nitride, copper, or tungsten.

[0080] The initial word lines self-align and fill the cavity structure h (reference) Figure 15 After removing the initial word line located in the through hole f, it is beneficial to form a word line 107 with precise dimensions in a self-aligned manner. There is no need to design the size of the word line 107 through an etching process, which simplifies the formation steps of the word line 107. Furthermore, by adjusting the size of the second gap i, a small-sized word line 107 can be obtained.

[0081] refer to Figure 23 After forming word line 107, a fourth dielectric layer 143 is formed, which fills the via f (see reference). Figure 21 ).

[0082] In this embodiment, the fourth dielectric layer 143 can be formed using the following process steps: A deposition process is performed to form a fourth dielectric film covering the top surface of the insulating layer 106 located on the top surface of the second doped region III and filling the via f; the fourth dielectric film is then subjected to chemical mechanical planarization until the top surface of the insulating layer 106 is exposed, with the remaining fourth dielectric film serving as the fourth dielectric layer 143. The fourth dielectric film is made of the same material as the second and third dielectric layers, all comprising silicon nitride. In other embodiments, the fourth dielectric film can also be chemically mechanically planarized until the top surface of the second doped region is exposed, i.e., the insulating layer located on the top surface of the second doped region is simultaneously removed, with the remaining fourth dielectric film serving as the fourth dielectric layer.

[0083] refer to Figures 23 to 25 The insulating layer 106 located on the top surface of the second doped region III is removed, and an epitaxial growth process is used to form a capacitor contact layer 108 on the top surface of the second doped region III. The orthogonal projection of the capacitor contact layer 108 on the bit line 104 covers the orthogonal projection of the second doped region III on the bit line 104.

[0084] On the one hand, the epitaxial growth process helps to improve the continuity between the second doped region III and the capacitor contact layer 108, reduce contact defects caused by different lattice characteristics or lattice misalignment, reduce contact resistance caused by contact defects, improve the carrier transport capacity and movement speed, thereby improving the conductivity between the second doped region III and the capacitor contact layer 108, and reducing the heat generation during the operation of the semiconductor structure. On the other hand, the epitaxial growth process helps to increase the orthogonal projection of the capacitor contact layer 108 on the bit line 104. When the lower electrode of the capacitor structure is subsequently formed on the capacitor contact layer 108, it helps to increase the contact area between the capacitor contact layer 108 and the lower electrode, thereby reducing the contact resistance between the capacitor contact layer 108 and the lower electrode.

[0085] Furthermore, during the epitaxial growth process, the capacitor contact layer 108 is also doped with dopant ions of the same type as those in the second doped region III, and the doping concentration of the dopant ions in the capacitor contact layer 108 is greater than that in the second doped region III. Therefore, the resistance of the capacitor contact layer 108 is less than that of the second doped region III, which is beneficial to further reduce the transmission resistance between the second doped region III and the lower electrode.

[0086] Furthermore, a capacitor structure (not shown in the figure) is formed on the surface jointly formed by the capacitor contact layer 108 and the fourth dielectric layer 143.

[0087] In other embodiments, after the word lines are formed, a wet etching process can be used to remove the second and third dielectric layers, forming a fourth gap that exposes the word lines and the entire top surface of the first dielectric layer. A deposition process is then used to form a seventh dielectric layer that fills the fourth gap. Because the seventh dielectric layer is a monolithic structure, it has high density and few internal defects, which helps to enhance the isolation effect of the seventh dielectric layer on adjacent semiconductor channels and adjacent bit lines. Furthermore, the materials of the seventh dielectric layer and the second dielectric layer can be the same; in some examples, both the materials of the seventh dielectric layer and the second dielectric layer are silicon nitride.

[0088] In other embodiments, a capacitor contact layer may not be formed; instead, a capacitor structure may be formed directly on the top surface of the second doped region after removing the insulating layer located on the top surface of the second doped region.

[0089] In summary, by forming a first dielectric layer 113 and a second dielectric layer 123, and using the second dielectric layer 123 as a mask to etch the first dielectric layer 113, a cavity structure h is formed. Using a deposition process, a precisely sized word line 107 is formed in the cavity structure h in a self-aligned manner. There is no need to design the size of the word line 107 through an etching process, which simplifies the formation steps of the word line 107. Furthermore, by adjusting the size of the second gap i, a small-sized word line 107 can be obtained.

[0090] Another embodiment of this application provides a method for fabricating a semiconductor structure, which is largely the same as the previous embodiment, with the main difference being the different process steps of removing a portion of the first dielectric layer to expose the sidewalls of the channel region. The method for fabricating a semiconductor structure according to another embodiment of this application will be described in detail below with reference to the accompanying drawings. It should be noted that parts that are the same as or corresponding to those in the foregoing embodiments can be referred to the detailed descriptions of the foregoing embodiments, and will not be repeated here.

[0091] Figures 26 to 31 This is a schematic diagram illustrating the steps involved in fabricating a semiconductor structure according to another embodiment of the present invention. It should be noted that, for ease of description and clear illustration of the steps in the semiconductor structure fabrication method, the following diagrams are provided in this embodiment. Figures 26 to 31 These are partial structural schematic diagrams of the semiconductor structure. The following will be a cross-sectional schematic diagram along the first cross-section direction AA1 and a cross-sectional schematic diagram along the second cross-section direction BB1, or both, depending on the description requirements. When referring to only one figure, the figure is a cross-sectional schematic diagram along the second cross-section direction BB1; when referring to both figures, the figure is first a cross-sectional schematic diagram along the first cross-section direction AA1, and then a cross-sectional schematic diagram along the second cross-section direction BB1.

[0092] In this embodiment, reference Figure 26 and Figure 27 Bit lines 204 and semiconductor channels 205 are formed on a substrate, as well as a first dielectric layer 213 and a second dielectric layer 223. A semiconductor well layer 21 is also present in the substrate. The first dielectric layer 213 includes a fifth dielectric layer 253 and a sixth dielectric layer 263. Specifically, the steps for forming the bit lines 204, semiconductor channels 205, first dielectric layer 213, and second dielectric layer 223 are the same as those in the above embodiments and will not be repeated here.

[0093] refer to Figure 27 The step of removing part of the first dielectric layer 213 to expose the sidewall of the channel region II also includes removing the first dielectric layer 213 located on the sidewall of the second doped region III, that is, the remaining first dielectric layer 213 is only located on the sidewall surface of the first doped region I.

[0094] refer to Figure 28 and Figure 29 An insulating layer 206 is formed, which not only covers the sidewall surface of the channel region II, but also the sidewall surface and top surface of the second doped region III, and has a second gap i between the insulating layer 206 and the second dielectric layer 223.

[0095] In this embodiment, since the semiconductor channel 205 is made of silicon, the step of forming the insulating layer 206 includes: thermally oxidizing the exposed sidewalls of the channel region II and the sidewalls and top surface of the second doped region III to form the insulating layer 206, and the insulating layer 206 covers the sidewall surfaces of the remaining channel region II and the remaining second doped region III. In other embodiments, the insulating layer covering the sidewalls and top surface of the channel region and the second doped region can also be formed by a deposition process.

[0096] Because the exposed sidewalls of the channel region II and the second doped region III are thermally oxidized, a portion of the channel region II and the second doped region III are transformed into an insulating layer 206. This results in the orthogonal projections of the channel region II and the second doped region III onto the bit line 204 being smaller than the orthogonal projection of the first doped region I onto the bit line 204. This is beneficial for forming a channel region II and the second doped region III with smaller cross-sectional areas in the cross-section perpendicular to the bit line 204 and pointing towards the semiconductor channel 205 without using an etching process. This is beneficial for reducing the threshold voltage of the transistor formed by the semiconductor channel 205, enabling the transistor to be turned on or off at a lower threshold voltage.

[0097] In some examples, in a cross-section perpendicular to direction Z, the width W and length of channel region II are no more than 10 nm, which helps to ensure that the transistor has a low threshold voltage. Furthermore, the height of channel region II in direction Z is 30 nm to 50 nm.

[0098] In this embodiment, the insulating layer 206 located on the top surface of the remaining second doped region III is removed in a subsequent process step. In other embodiments, the insulating layer located on the top surface of the remaining second doped region can be removed after thermal oxidation, leaving only the insulating layer covering the remaining channel region and the sidewall surface of the remaining second doped region.

[0099] refer to Figure 30 and Figure 31 This forms character line 207. Specifically, forming character line 207 includes the following:

[0100] The initial character line is formed, and the initial character line fills the second gap i (reference). Figure 29 The initial word line is located between the insulating layer 206 on the sidewalls of the channel region II and the second doped region III on the adjacent bit line 204. The initial word line can be formed through a deposition process.

[0101] A portion of the initial word lines is removed, and the remaining initial word lines are used as word lines 207. Word lines 207 only surround the insulating layer 206 located on the sidewall of channel region II.

[0102] The initial word line self-aligns and fills the second gap i, which is beneficial for the subsequent self-alignment to form a word line 207 with precise dimensions. There is no need to design the size of the word line 207 through etching process, which simplifies the formation steps of the word line 207. Furthermore, by adjusting the size of the second gap i, a small-sized word line 207 can be obtained.

[0103] Further, a fourth dielectric layer is formed, filling the gaps between the insulating layers 206 located on the sidewalls of the second doped region III. Then, the insulating layer 206 located on the top surface of the second doped region III is removed. Specifically, the steps of forming the fourth dielectric layer and removing part of the insulating layer 206 are the same as those in the above embodiment, and will not be repeated here. In other embodiments, the insulating layers located on the sidewalls and top surface of the second doped region may be removed before forming the fourth dielectric layer, and then the fourth dielectric layer exposing the top surface of the first doped region may be formed.

[0104] In this embodiment, a capacitor contact layer and a capacitor structure can be further formed on the top surface of the second doped region III. Specifically, the steps for forming the capacitor contact layer and the capacitor structure are the same as those in the above embodiment, and will not be repeated here.

[0105] In summary, by forming a first dielectric layer 213 and a second dielectric layer 223, and using the second dielectric layer 223 as a mask to etch the first dielectric layer 213, a second gap i is formed. Using a deposition process, a word line 207 with precise dimensions is formed in the second gap i in a self-aligned manner. This eliminates the need to design the size of the word line 207 through an etching process, which simplifies the formation steps of the word line 207. Furthermore, by adjusting the size of the second gap i, a small-sized word line 207 can be obtained.

[0106] Accordingly, another embodiment of the present invention also provides a semiconductor structure, which is prepared by the method for fabricating the semiconductor structure provided in any of the above embodiments.

[0107] refer to Figure 24 and Figure 25 The semiconductor structure includes: a substrate, the substrate including a semiconductor well layer 11; a bit line 104 located on the semiconductor well layer 11; and a semiconductor channel 105 located on the surface of the bit line 104. In the direction Z along the substrate pointing to the bit line 104, the semiconductor channel 105 includes a first doped region I, a channel region II, and a second doped region III arranged sequentially, and the first doped region I is in contact with the bit line 104.

[0108] In this embodiment, the substrate, bit line 104 and semiconductor channel 105 have the same semiconductor elements. The semiconductor channel 105 and bit line 104 are formed using the same film structure, which is composed of semiconductor elements, so that the semiconductor channel 105 and bit line 104 are an integral structure, thereby improving the interface state defects between the semiconductor channel 105 and bit line 104 and improving the performance of the semiconductor structure.

[0109] The semiconductor element may include at least one of silicon, carbon, germanium, arsenic, gallium, and indium. Specifically, the substrate, bit line 104, and semiconductor channel 105 may be made of elemental semiconductor materials or crystalline inorganic compound semiconductor materials. Elemental semiconductor materials may be silicon or germanium; crystalline inorganic compound semiconductor materials may be silicon carbide, silicon germanide, gallium arsenide, or indium gallium, etc.

[0110] Specifically, the first doped region I, channel region II, and second doped region III are doped with the same type of dopant ions, and the doping concentration of the dopant ions in the first doped region I is the same as the doping concentration in the channel region II and the second doped region III. Therefore, the device formed by the semiconductor channel 105 is a junctionless transistor. This avoids the phenomenon of fabricating ultra-steep PN junctions at the nanoscale using ultra-steep source-drain concentration gradient doping processes. Consequently, it avoids problems such as threshold voltage drift and increased leakage current caused by abrupt doping changes. It also helps suppress short-channel effects, allowing operation at the nanometer scale, thus contributing to further improvements in the integration density and electrical performance of the semiconductor structure. The dopant ions are either N-type or P-type ions.

[0111] The orthogonal projection of channel region II on bit line 104 is smaller than that of the second doped region III on bit line 104, and also smaller than that of the first doped region I on bit line 104. Therefore, without using an etching process, in the cross-section perpendicular to bit line 104 pointing to semiconductor channel 105, it is advantageous to form a channel region II with a smaller cross-sectional area, thereby improving the control capability of word line 107 over channel region II, and thus making it easier to control the turn-on or turn-off of GAA transistors.

[0112] In some examples, in a cross-section perpendicular to direction Z, the width W and length L of channel region II are no more than 10 nm, which helps to ensure that the transistor has a low threshold voltage. Furthermore, the height of channel region II in direction Z is 30 nm to 50 nm.

[0113] Reference Figure 6 and Figures 24 to 25 The semiconductor structure further includes: a first dielectric layer 113, which is disposed around the first doped region I, and the first dielectric layers 113 on the same bit line 104 adjacent to the sidewalls of the first doped region I have a first interval.

[0114] Specifically, the first dielectric layer 113 may include a fifth dielectric layer 153 and a sixth dielectric layer 163. The fifth dielectric layer 153 is located in the spacing between adjacent bit lines 104 and in the spacing between adjacent first doped regions I on adjacent bit lines 104. The sixth dielectric layer 163 is located on the sidewall of the adjacent first doped region I on the same bit line 104 and is located on the sidewall of the fifth dielectric layer 153. The first dielectric layer 113 is used to achieve electrical insulation between adjacent semiconductor channels 105 and adjacent bit lines 104.

[0115] The semiconductor structure further includes an insulating layer 106 that at least covers the sidewall surface of channel region II. In this embodiment, the insulating layer 106 covers only the sidewall surface of channel region II. In other embodiments, the insulating layer may cover the sidewall surfaces of both the channel region and the second doped region.

[0116] The semiconductor structure further includes: word lines 107 surrounding an insulating layer 106 located on the sidewall of the channel region II, and having a second spacing between adjacent word lines 107; an isolation layer 109 located at least in the first and second spacings, and the top surface of the isolation layer 109 away from the substrate is not lower than the top surface of the second doped region III away from the substrate.

[0117] Specifically, the isolation layer 109 may include a second dielectric layer 123 and a third dielectric layer 133. The second dielectric layer 123 is located in the first interval and the second interval, and the top surface of the second dielectric layer 123 away from the substrate is not lower than the top surface of the second doped region III away from the substrate; the third dielectric layer 133 covers the sidewall of the second doped region III.

[0118] In some examples, the top surface of the second dielectric layer 123 is flush with the top surface of the second doped region III, and the isolation layer 109 also includes a fourth dielectric layer 143. (Continue to the previous section) Figure 25 The fourth dielectric layer 143 is located on the top surface formed by the second dielectric layer 123 and the third dielectric layer 133, and in the space formed by adjacent third dielectric layers 133. The second dielectric layer 123, the third dielectric layer 133, and the fourth dielectric layer 143 are made of the same material and together form the isolation layer 109, achieving electrical insulation between adjacent semiconductor channels 105 and adjacent bit lines 104. In other examples, the second dielectric layer, the third dielectric layer, and the fourth dielectric layer can be an integrally formed structure, resulting in a higher density and fewer internal defects in the isolation layer, which is beneficial for enhancing the isolation effect between adjacent semiconductor channels and adjacent bit lines.

[0119] In other embodiments, when the insulating layer covers the sidewall surfaces of both the channel region and the second doped region, the isolation layer includes a second dielectric layer and a fourth dielectric layer, wherein the second dielectric layer is located in the first spacer and the second spacer, and the top surface of the second dielectric layer away from the substrate is not lower than the top surface of the second doped region away from the substrate; the fourth dielectric layer is located in the spacer formed by the second dielectric layer and the insulating layer, and in the spacer formed by adjacent insulating layers, and the fourth dielectric layer covers the top surface of the second dielectric layer.

[0120] Furthermore, the orthographic projection of the periphery of the insulating layer 106 onto the bit line 104 is smaller than the orthographic projection of the periphery of the third dielectric layer 133 onto the bit line 104.

[0121] The semiconductor structure may further include: a capacitor contact layer 108 located on the top surface of the second doped region III, wherein the orthogonal projection of the capacitor contact layer 108 on the bit line 104 covers the orthogonal projection of the second doped region III on the bit line 104, and the capacitor contact layer 108 has doped ions, wherein the doping concentration of the doped ions in the capacitor contact layer 108 is greater than the doping concentration in the second doped region II.

[0122] Since the capacitor contact layer 108 and the second doped region III are doped with the same type of dopant ions, and the doping concentration of the dopant ions in the capacitor contact layer 108 is greater than that in the second doped region III, it is beneficial to further improve the conductivity of the capacitor contact layer 108. Furthermore, the orthogonal projection of the capacitor contact layer 108 onto the bit line 104 overlaps the orthogonal projection of the second doped region III onto the bit line 104, which helps to increase the contact area between the capacitor contact layer 108 and other subsequent conductive structures, thereby reducing the contact resistance between the capacitor contact layer 108 and other subsequent conductive structures.

[0123] The semiconductor structure may also include a capacitor structure (not shown in the figure), which is located on the surface formed by the capacitor contact layer 108 and the fourth dielectric layer 143.

[0124] In summary, in the cross-section perpendicular to the bit line 104 pointing towards the semiconductor channel 105 in direction Z, the cross-sectional area of ​​channel region II is smaller than that of the first doped region I and the second doped region II. This is beneficial for reducing the threshold voltage of the transistor formed by the semiconductor channel 105, enabling the transistor to be turned on or off at a lower threshold voltage. Furthermore, the device formed by the semiconductor channel 105 is a junctionless transistor, which helps avoid the use of ultra-steep source-drain concentration gradient doping processes. Therefore, it avoids problems such as threshold voltage drift and increased leakage current caused by abrupt doping changes, and also helps suppress short-channel effects, thereby further improving the integration density and electrical performance of the semiconductor structure.

[0125] Those skilled in the art will understand that the above embodiments are specific examples of implementing the present invention, and in practical applications, various changes in form and detail can be made without departing from the spirit and scope of the present invention. Any person skilled in the art can make their own modifications and alterations without departing from the spirit and scope of the present invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: Provide a base; A bit line is formed on the substrate, and a semiconductor channel is formed on the surface of the bit line away from the substrate. In the direction along the substrate toward the bit line, the semiconductor channel includes a first doped region, a channel region, and a second doped region arranged sequentially. A first dielectric layer is formed, the first dielectric layer surrounds the sidewall of the semiconductor channel, and there is a first gap between the first dielectric layers located on the same bit line and adjacent sidewalls of the semiconductor channel; A second dielectric layer is formed, which fills the first gap, and the material of the second dielectric layer is different from that of the first dielectric layer; A portion of the first dielectric layer is removed to expose the sidewall of the channel region, with the remaining first dielectric layer surrounding the sidewall of the first doped region. An insulating layer is formed, the insulating layer at least covering the sidewall surface of the trench region, and a second gap is formed between the insulating layer and the second dielectric layer; A character line is formed, which fills the second gap; The first doped region, the channel region, and the second doped region are doped with the same type of dopant ions, and the doping concentration of the dopant ions in the first doped region is the same as the doping concentration in the channel region and the second doped region. The dopant ions are either N-type ions or P-type ions.

2. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, The step of removing a portion of the first dielectric layer to expose the sidewall of the channel region, with the remaining first dielectric layer surrounding the sidewall of the first doped region, includes: Etch a portion of the first dielectric layer until the sidewall of the second doped region is exposed; A third dielectric layer is formed, which surrounds the sidewall of the second doped region and is located on the sidewall of the second dielectric layer. The third dielectric layer located on the sidewall of the second doped region and the third dielectric layer located on the sidewall of the second dielectric layer together form a through hole. The bottom of the through hole exposes the first dielectric layer, and the material of the third dielectric layer is different from that of the first dielectric layer. Remove the first dielectric layer exposed on the sidewall of the channel region through the via, leaving the remaining first dielectric layer surrounding the sidewall of the first doped region.

3. The method for fabricating a semiconductor structure as described in claim 2, characterized in that, The steps for forming the insulating layer include: The exposed sidewalls of the trench area are subjected to thermal oxidation to form the insulating layer, and the insulating layer covers the remaining sidewall surfaces of the trench area.

4. The method for fabricating a semiconductor structure as described in claim 2, characterized in that, The steps for forming the word lines include: An initial word line is formed, which fills the second gap and the through hole, and the initial word line is also located between the insulating layers on the sidewalls of the channel region of the adjacent bit line; Remove the initial word line located in the through hole, and the remaining initial word line is used as the word line.

5. The method for fabricating a semiconductor structure as described in claim 4, characterized in that, After forming the word line, the method further includes: forming a fourth dielectric layer, wherein the fourth dielectric layer fills the via.

6. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, The step of removing a portion of the first dielectric layer to expose the sidewall of the channel region, with the remaining first dielectric layer surrounding the sidewall of the first doped region, further includes removing the first dielectric layer located on the sidewall of the second doped region; the step of forming the insulating layer also includes the insulating layer covering the sidewall of the second doped region.

7. The method for fabricating a semiconductor structure as described in claim 6, characterized in that, The steps for forming the word lines include: An initial word line is formed, the initial word line fills the second gap, and the initial word line is also located between the insulating layers of the semiconductor channel portion sidewalls adjacent to the bit line; A portion of the initial word lines is removed, and the remaining initial word lines are used as the word lines, which only surround the insulating layer located on the sidewall of the channel region.

8. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, The steps of forming the bit line and the semiconductor channel include: A first mask layer is formed on the substrate; The substrate is etched using the first mask layer as a mask to form a plurality of first trenches; Remove the first mask layer and form a fifth dielectric layer in the first trench; A second mask layer is formed on the top surface formed by the fifth dielectric layer and the remaining substrate; Using the second mask layer as a mask, the substrate and the fifth dielectric layer are etched to form a plurality of second trenches, the bit lines and the semiconductor channels, and in the direction perpendicular to the surface of the substrate, the depth of the second trenches is less than the depth of the first trenches; Remove the second mask layer.

9. The method for fabricating a semiconductor structure as described in claim 8, characterized in that, The first mask layer has a plurality of mutually independent first openings, and the second mask layer has a plurality of mutually independent second openings, wherein the extending direction of the first openings is perpendicular to the extending direction of the second openings.

10. The method for fabricating a semiconductor structure as described in claim 9, characterized in that, In the direction perpendicular to the sidewall of the semiconductor channel, the ratio of the opening width of the first opening to the opening width of the second opening is 2 to 1, and the spacing between adjacent first openings is equal to the spacing between adjacent second openings.

11. The method for fabricating a semiconductor structure as described in claim 8, characterized in that, The steps for forming the first dielectric layer include: A sixth dielectric layer is formed, which is located on the sidewall of the second trench. The remaining fifth dielectric layer and the sixth dielectric layer together form the first dielectric layer, and the first gap is present between the sixth dielectric layers located on the sidewall of the second trench.

12. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, Also includes: An epitaxial growth process is used to form a capacitor contact layer on the top surface of the second doped region, and the orthogonal projection of the capacitor contact layer on the bit line covers the orthogonal projection of the second doped region on the bit line.

13. A semiconductor structure, fabricated using the method described in claim 1, characterized in that, include: Base; Bit lines are located on the substrate; A semiconductor channel is located on the surface of the bit line. In the direction from the substrate to the bit line, the semiconductor channel includes a first doped region, a channel region, and a second doped region arranged in sequence, and the first doped region is in contact with the bit line. A first dielectric layer is disposed around the first doped region, and the first dielectric layers adjacent to the sidewalls of the first doped region on the same bit line have a first interval. An insulating layer, at least covering the sidewall surface of the trench area; Word lines, surrounding the insulating layer located on the sidewall of the channel area, and having a second spacing between adjacent word lines; An isolation layer is located at least in the first and second intervals, and the top surface of the isolation layer away from the substrate is not lower than the top surface of the second doped region away from the substrate; The first doped region, the channel region, and the second doped region are doped with the same type of dopant ions, and the doping concentration of the dopant ions in the first doped region is the same as the doping concentration in the channel region and the second doped region. The dopant ions are either N-type ions or P-type ions.

14. The semiconductor structure as described in claim 13, characterized in that, The substrate, the bit line, and the semiconductor channel have the same semiconductor elements.

15. The semiconductor structure as described in claim 13, characterized in that, Also includes: A capacitor contact layer is located on the top surface of the second doped region. The orthographic projection of the capacitor contact layer on the bit line covers the orthographic projection of the second doped region on the bit line. The capacitor contact layer has the doped ions, and the doping concentration of the doped ions in the capacitor contact layer is greater than the doping concentration in the second doped region.

16. The semiconductor structure as described in claim 13, characterized in that, The orthogonal projection of the channel region on the bit line is smaller than the orthogonal projection of the second doped region on the bit line, and smaller than the orthogonal projection of the first doped region on the bit line.

17. The semiconductor structure as claimed in claim 13, characterized in that, The isolation layer includes a second dielectric layer and a third dielectric layer, the second dielectric layer being located between the first interval and the second interval, and the top surface of the second dielectric layer away from the substrate being not lower than the top surface of the second doped region away from the substrate; The third dielectric layer covers the sidewall of the second doped region.

18. The semiconductor structure as claimed in claim 17, characterized in that, The orthographic projection of the outer periphery of the insulating layer on the bit line is smaller than the orthographic projection of the outer periphery of the third dielectric layer on the bit line.

19. The semiconductor structure as claimed in claim 13, characterized in that, The first dielectric layer includes a fifth dielectric layer and a sixth dielectric layer. The fifth dielectric layer is located in the interval between adjacent bit lines and in the interval between adjacent first doped regions on adjacent bit lines. The sixth dielectric layer is located on the sidewall of the first doped region on the same bit line and is located on the sidewall of the fifth dielectric layer.

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