A semiconductor structure and its fabrication method

Abstract

This disclosure provides a semiconductor structure and a method for fabricating the same. The method includes: forming capacitor pillars in an initial structure; removing a portion of the initial structure to form a trench, exposing a portion of the sidewalls of the capacitor pillars and the substrate of the initial structure; forming a dielectric layer that at least covers the exposed surfaces of the capacitor pillars; forming a first upper electrode that covers the surface of the dielectric layer; and forming a second upper electrode that covers the surface of the first upper electrode. The second upper electrode, formed within the trench, is partially discontinuous in the axial direction of the capacitor pillars, and this discontinuous portion forms an air gap. This method of fabricating the semiconductor structure, by forming air gaps between the capacitor pillars, prevents leakage current in the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of electronic device technology, and in particular to a semiconductor structure and its fabrication method. Background Technology

[0002] DRAM (Dynamic Random Access Memory) has advantages such as small size, high integration density, and low power consumption, and its data read speed is faster than ROM (Read-Only Memory). As DRAM integration density increases, the feature size and electrode area of ​​capacitors continue to decrease. Therefore, in DRAM fabrication, it is necessary to select dielectric materials with thinner thickness and higher dielectric constants to increase capacitor density. Simultaneously, it is also necessary to ensure sufficiently large capacitance values ​​while further ensuring sufficiently low leakage current. Summary of the Invention

[0003] To address the aforementioned technical problems, this disclosure provides a semiconductor structure and a method for fabricating the same.

[0004] According to one aspect of this disclosure, a method for fabricating a semiconductor structure is provided, the method comprising:

[0005] Capacitor pillars are formed in the initial structure;

[0006] A trench is formed by removing part of the initial structure, the trench exposing part of the sidewall of the capacitor pillar and the substrate of the initial structure;

[0007] A dielectric layer is formed, which at least covers the exposed surface of the capacitor pillar;

[0008] A first upper electrode is formed, which covers the surface of the dielectric layer;

[0009] A second upper electrode is formed, which covers the surface of the first upper electrode;

[0010] In the axial direction of the capacitor column, the second upper electrode portion formed in the trench is discontinuous, and the discontinuous portion of the second upper electrode forms an air gap.

[0011] The discontinuous portion of the second upper electrode covers the sidewall of the capacitor post exposed by the trench, and the thickness of the second upper electrode on the sidewall of the capacitor post covered by the discontinuous portion varies continuously.

[0012] The formation of the first upper electrode includes:

[0013] The first upper electrode is formed by depositing a first material on the dielectric layer at a first deposition rate using a first process.

[0014] The formation of the second upper electrode includes:

[0015] The second upper electrode is formed by depositing a second material on the first upper electrode using a second process at a second deposition rate.

[0016] The second deposition rate is greater than the first deposition rate.

[0017] The first material and the second material are the same.

[0018] The formation of multiple capacitor pillars on the initial structure includes:

[0019] An initial structure is provided, the initial structure including a substrate and a stacked structure disposed on the substrate;

[0020] A patterned mask layer is formed on the stacked structure, the patterned mask layer having openings;

[0021] A portion of the stacked structure is removed according to the opening of the patterned mask to form a capacitor hole, the bottom of which exposes the substrate;

[0022] The capacitor post is formed in the capacitor hole.

[0023] The stacked structure includes a sacrificial layer and a support layer;

[0024] The removal of the initial structure to form a trench includes:

[0025] The sacrificial layer and part of the support layer of the initial structure are removed to form the trench.

[0026] Alternatively, the sacrificial layer and the support layer are formed above the substrate, and the sacrificial layer and the support layer are stacked alternately.

[0027] After forming the second upper electrode, the process further includes annealing the second upper electrode.

[0028] After forming the second upper electrode, the process also includes:

[0029] A third upper electrode is formed on the surface of the second upper electrode, the third upper electrode covering the exposed outer surface of the second upper electrode, and the third upper electrode may be made of the same or different material as the second upper electrode.

[0030] According to another aspect of this disclosure, a semiconductor structure is provided, comprising:

[0031] Substrate;

[0032] A capacitive contact structure is located within the substrate;

[0033] A capacitor post, the bottom of which is electrically connected to the capacitor contact structure;

[0034] The trench is located between the capacitor pillars;

[0035] A dielectric layer covering the surface of the capacitor pillar and a portion of the substrate;

[0036] The first upper electrode covers the surface of the dielectric layer;

[0037] A second upper electrode covers the first upper electrode. The second upper electrode includes a discontinuous portion located within the trench, and the discontinuous portion has an air gap inside.

[0038] In the axial direction of the capacitor column, the thickness of the discontinuous portion of the second upper electrode covering the sidewall of the capacitor column changes continuously.

[0039] In the axial direction of the capacitor column, the thickness of the discontinuous portion of the second upper electrode covering the sidewall of the capacitor column gradually increases from the middle to both ends.

[0040] The semiconductor structure further includes a third upper electrode that covers the exposed outer surface of the second upper electrode.

[0041] The first upper electrode and the second upper electrode are made of the same material.

[0042] The method for fabricating the semiconductor structure disclosed herein forms an air gap between capacitor pillars, reducing the amount of doped layer filling the space between capacitor pillars and thus preventing leakage current in the semiconductor structure. Attached Figure Description

[0043] The accompanying drawings, which form part of this disclosure, are used to provide a further understanding of this disclosure. The illustrative embodiments of this disclosure and their descriptions are used to explain this disclosure and do not constitute an undue limitation of this disclosure. In the drawings:

[0044] Figure 1 This is a flowchart of a method for fabricating a semiconductor structure in an exemplary embodiment of this disclosure;

[0045] Figure 2 This is a flowchart of a method for fabricating a semiconductor structure in an exemplary embodiment of this disclosure;

[0046] Figure 3 This is a flowchart of a method for fabricating a semiconductor structure in an exemplary embodiment of this disclosure;

[0047] Figure 4 This is a flowchart of a method for fabricating a semiconductor structure in an exemplary embodiment of this disclosure;

[0048] Figure 5 This is a flowchart of a method for fabricating a semiconductor structure in an exemplary embodiment of this disclosure;

[0049] Figure 6 This is a flowchart of a method for fabricating a semiconductor structure in an exemplary embodiment of this disclosure;

[0050] Figure 7 This is a schematic diagram of the initial structure involved in the method for fabricating a semiconductor structure in an exemplary embodiment of this disclosure;

[0051] Figure 8 This is a schematic diagram of forming a patterned mask layer on an initial structure in the method for fabricating a semiconductor structure in an exemplary embodiment of the present disclosure;

[0052] Figure 9 This is a schematic diagram illustrating the process of forming capacitor holes by removing an initial structure from a patterned mask layer in a method for fabricating a semiconductor structure according to an exemplary embodiment of this disclosure.

[0053] Figure 10 This is a schematic diagram of the deposition of capacitor pillar material in a capacitor hole involved in the method of fabricating a semiconductor structure in an exemplary embodiment of this disclosure;

[0054] Figure 11 This is a schematic diagram of the formation of capacitor pillars involved in the method of fabricating a semiconductor structure in an exemplary embodiment of this disclosure;

[0055] Figure 12 This is a schematic diagram of forming a first mask layer on an initial structure in the method for fabricating a semiconductor structure in an exemplary embodiment of the present disclosure;

[0056] Figure 13 It is a schematic diagram of the projection of the first figure onto the top surface of the stacked structure and capacitor pillars;

[0057] Figure 14 This is a schematic diagram illustrating the removal of the second support layer according to the first pattern in the semiconductor structure fabrication method of the exemplary embodiments of this disclosure. Figure 14 yes Figure 13 A diagram of section AA;

[0058] Figure 15 This is a schematic diagram of the removal of the second sacrificial layer involved in the method of fabricating a semiconductor structure in an exemplary embodiment of this disclosure;

[0059] Figure 16 This is a schematic diagram of removing the first support layer according to the first pattern in the method for fabricating a semiconductor structure in an exemplary embodiment of this disclosure;

[0060] Figure 17 This is a schematic diagram illustrating the removal of the first sacrificial layer involved in the method of fabricating a semiconductor structure in an exemplary embodiment of this disclosure;

[0061] Figure 18 This is a schematic diagram of the formation of a dielectric layer involved in the method of fabricating a semiconductor structure in an exemplary embodiment of this disclosure;

[0062] Figure 19 This is a schematic diagram of the formation of the first upper electrode involved in the method of fabricating a semiconductor structure in an exemplary embodiment of this disclosure;

[0063] Figure 20 This is a schematic diagram of the formation of the second upper electrode involved in the method of fabricating a semiconductor structure in an exemplary embodiment of this disclosure;

[0064] Figure 21 This is a schematic diagram of the formation of the third upper electrode involved in the method of fabricating the semiconductor structure in an exemplary embodiment of this disclosure;

[0065] Figure 22 This is a schematic diagram of the back-end processing involved in the method of fabricating a semiconductor structure in an exemplary embodiment of this disclosure. Attached image description:

[0067] 100. Initial structure; 110. Substrate; 120. Stacked structure; 111. Capacitor contact structure; 10. Capacitor pillar; 130. First mask layer; 131. First pattern; 140. Trench; 20. Dielectric layer; 30. First upper electrode; 40. Second upper electrode; 41. Air gap; 150. Patterned mask layer; 151. Opening; 160. Capacitor hole; 121. Sacrificial layer; 121a. First sacrificial layer; 121b. Second sacrificial layer; 122. Support layer; 122a. First support layer; 122b. Second support layer; 60. Third upper electrode. Detailed Implementation

[0068] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and feature vectors in the embodiments of this disclosure can be arbitrarily combined with each other.

[0069] Currently, capacitors are manufactured by forming a dielectric material, then forming a top electrode on the dielectric material, and finally forming a boron-doped layer on the top electrode to increase the capacitor's conductivity. However, due to the small radius of boron particles, the thermal processing accelerates the penetration of boron particles into the dielectric material, easily leading to capacitor leakage.

[0070] In view of this, the present disclosure provides a method for fabricating a semiconductor structure, which forms an air gap between capacitor pillars, reduces the amount of boron doped layer filling the space between capacitor pillars, and reduces the boron particle density in the boron doped layer. The total amount of boron particles diffused into the dielectric material during the thermal process is significantly reduced, which can prevent leakage current in the semiconductor structure.

[0071] As an exemplary embodiment of this disclosure, this embodiment provides a method for fabricating a semiconductor structure, such as... Figure 1 As shown, the manufacturing method in this embodiment includes:

[0072] S110: Form capacitor pillars in the initial structure.

[0073] like Figure 7 As shown, the initial structure 100 includes a substrate 110 and a stacked structure 120 disposed on the substrate 110, and a capacitor contact structure 111 is disposed in the substrate. Please refer to... Figure 11 Capacitor pillars 10 are formed in the stacked structure 120, and are connected to capacitor contact structures 111. The top surface of the capacitor pillars 10 is flush with the top surface of the stacked structure 120. Multiple capacitor contact structures 111 are distributed in the substrate 110, allowing multiple capacitor pillars 10 to be formed in the stacked structure 120. Each capacitor pillar 10 is connected to a corresponding capacitor contact structure 111.

[0074] Substrate 110 is a semiconductor substrate, including silicon-containing material. Substrate 110 may include a silicon substrate, a silicon-germanium substrate, or an SOI (silicon on insulator) substrate.

[0075] The capacitor pillar 10 can be deposited using atomic layer deposition (ALD). The material of the capacitor pillar 10 includes compounds formed from one or two of metal nitrides and metal silicides, such as titanium nitride, titanium silicide, nickel silicide, and titanium silicon nitride (TiSixNy).

[0076] S120: Part of the initial structure is removed to form a trench, which exposes part of the sidewalls of the capacitor pillar and the substrate of the initial structure.

[0077] like Figure 12 As shown, a first mask layer 130 is formed on the stacked structure 120, and a first pattern 131 is defined on the first mask layer 130, the first pattern 131 exposing at least a portion of the top surface of the capacitor pillar 10. All or part of the stacked structure 120 is etched away according to the first mask layer 130 to expose the surface of the substrate 110, and etching is stopped, as shown. Figure 17 As shown, trench 140 is obtained. Trench 140 exposes at least a portion of the sidewalls of capacitor post 10 and the surface of substrate 110.

[0078] S130: Form a dielectric layer that at least covers the exposed surface of the capacitor pillar.

[0079] Reference Figure 18 As shown, the dielectric layer 20 can be deposited using atomic layer deposition (ALD). The material of the dielectric layer 20 is a high-k dielectric material, whose dielectric constant is greater than that of silicon dioxide. In this embodiment, the high-k dielectric material of the dielectric layer can contain compounds of one or more components selected from rare earth elements, Hf, Rh, Ba, and Al. The high-k dielectric material can be hafnium(IV) oxide, titanium dioxide, aluminum oxide, lanthanum oxide, etc.

[0080] S140: Form a first upper electrode, which covers the surface of the dielectric layer.

[0081] Reference Figure 19 As shown, the material of the first upper electrode 30 includes compounds formed from one or two of metal nitrides and metal silicides. In this embodiment, the first upper electrode 30 may include one or two of titanium nitride, titanium silicide, nickel silicide, and titanium silicon nitride (TiSixNy).

[0082] S150: Form a second upper electrode, which covers the surface of the first upper electrode.

[0083] Reference Figure 20 As shown, in the axial direction of the capacitor post 10, the second upper electrode 40 formed in the trench is partially discontinuous, and the discontinuous part of the second upper electrode 40 forms an air gap 41.

[0084] The material of the second upper electrode 40 includes compounds formed from one or two of metal nitrides and metal silicides. In this embodiment, the second upper electrode 40 may include one or two of titanium nitride, titanium silicide, nickel silicide, and titanium silicon nitride (TiSixNy).

[0085] In this embodiment, the discontinuous portion of the second upper electrode 40 covers the sidewall of the capacitor post 10 exposed by the trench 140, and the thickness of the second upper electrode 40 on the sidewall of the capacitor post 10 covered by the discontinuous portion changes continuously.

[0086] The semiconductor structure fabricated by the method in this embodiment is as follows: Figure 20 As shown, an air gap 41 is formed in the trench 140 in the axial direction of the capacitor post 10, and the thickness of the second upper electrode 40 covering the sidewall of the capacitor post 10 changes continuously. That is, the air gap 41 is a closed air gap formed inside the second upper electrode 40. The boron doped layer of the semiconductor structure obtained in this embodiment cannot fill the space between adjacent capacitor posts 10, reducing the total amount of boron particles deposited. The total amount of boron particles diffused into the dielectric material during the thermal process is significantly reduced, which can avoid leakage current in the semiconductor structure.

[0087] As an exemplary embodiment of this disclosure, this embodiment provides a method for fabricating a semiconductor structure, such as... Figure 2 As shown, the manufacturing method in this embodiment includes:

[0088] S210: Form capacitor pillars in the initial structure.

[0089] S220: Part of the initial structure is removed to form a trench, which exposes part of the sidewalls of the capacitor pillar and the substrate of the initial structure.

[0090] S230: Form a dielectric layer that at least covers the exposed surface of the capacitor pillar.

[0091] S240: A first material is deposited on a dielectric layer at a first deposition rate using a first process to form a first upper electrode, the first upper electrode covering the surface of the dielectric layer.

[0092] S250: Form a second upper electrode, which covers the surface of the first upper electrode.

[0093] Steps S210-S230 and S250 in this embodiment are implemented in the same way as steps S110-S130 and S250 in the above embodiment, and will not be described again here.

[0094] In step S240 of this embodiment, when forming the first upper electrode, a first material is deposited on the dielectric layer at a first deposition rate through a first process to form the first upper electrode.

[0095] In this embodiment, the first process can be atomic layer deposition (ALD). The first material can include compounds formed from one or both of metal nitrides and metal silicides, such as titanium nitride, titanium silicide, nickel silicide, and titanium silicon nitride (TiSixNy). The first deposition rate is less than...

[0096] Atomic layer deposition (ALD) can precisely control the thickness of the deposited first top electrode. In this embodiment, the thickness of the first top electrode deposited on the dielectric layer is 8 nm.

[0097] In this embodiment, the first upper electrode is formed using atomic layer deposition, resulting in a uniform thickness and high surface uniformity on the dielectric layer.

[0098] As an exemplary embodiment of this disclosure, this embodiment provides a method for fabricating a semiconductor structure, such as... Figure 3 As shown, the manufacturing method in this embodiment includes:

[0099] S310: Form capacitor pillars in the initial structure.

[0100] S320: A trench is formed by removing part of the initial structure, exposing part of the sidewalls of the capacitor pillar and the substrate of the initial structure.

[0101] S330: Form a dielectric layer that at least covers the exposed surface of the capacitor pillar.

[0102] S340: Form a first upper electrode, which covers the surface of the dielectric layer.

[0103] S350: A second material is deposited on the first upper electrode at a second deposition rate using a second process to form a second upper electrode, the second upper electrode covering the surface of the first upper electrode.

[0104] Steps S310, S330, and S340 in this embodiment are implemented in the same way as steps S210, S230, and S240 in the above embodiment, and will not be described again here.

[0105] In step S320 of this embodiment, as follows Figure 7As shown, the stacked structure 120 includes a sacrificial layer 121 and a support layer 122, with a trench 140 formed by removing a portion of the initial structure 100. During the formation of the trench 140, the sacrificial layer 121 and a portion of the support layer 122 of the initial structure 100 are removed to form the trench 140. The sacrificial layer 121 and the support layer 122 are formed above the substrate 110, and the sacrificial layer 121 and the support layer 122 are stacked alternately. In this embodiment, the capacitor pillar 10 is formed by etching the stacked structure 120. The specific number and stack height of the sacrificial layer 121 and the support layer 122 in the stacked structure 120 are set according to the height of the capacitor pillar 10 to be formed. Figure 7 As shown, along the direction away from the substrate, the stacked structure 120 includes a first sacrificial layer 121a, a first support layer 122a, a second sacrificial layer 121b, and a second support layer 122b.

[0106] The first sacrificial layer 121a and the second sacrificial layer 121b are made of silicon oxide or BPSG (Boro-phospho-silicate glass). The first sacrificial layer 121a and the second sacrificial layer 121b may be doped with boron or phosphorus. The first support layer 122a and the second support layer 122b are made of any one or any combination of two or more of silicon nitride, silicon oxynitride, and silicon carbonitride.

[0107] In the manufacturing method of this embodiment, when forming the groove 140, as follows: Figure 12 As shown, a first mask layer 130 is formed on the stacked structure 120, and a first pattern 131 is defined on the first mask layer 130. For example... Figure 13 As shown, the first pattern 131 exposes at least a portion of the top surface of the capacitor pillar 10. (As...) Figure 14 As shown, and refer to Figure 13 The second support layer 122b corresponding to the first pattern 131 of the first mask layer 130 is removed by dry or wet etching, exposing the second sacrificial layer 121b. For example... Figure 15 As shown, and refer to Figure 14 The entire second sacrificial layer 121b is removed using a wet acid process, exposing the first support layer 122a. The first pattern 131 of the first mask layer 130 is then transferred onto the first support layer 122a. Figure 16 As shown, and refer to Figure 15 Continue etching according to the first pattern 131 of the first mask layer 130 using dry or wet etching to remove the first support layer 122a corresponding to the first pattern 131, exposing the first sacrificial layer 121a. Then, remove all of the first sacrificial layer 121a using a wet acid etching process. Figure 17 As shown, groove 140 is obtained.

[0108] like Figure 17As shown, the trench 140 formed in this embodiment consists of a first support layer 122a, a second support layer 122b, the sidewalls of the capacitor pillar 10, and the top surface of the substrate 10. During the deposition of the second upper electrode 40, titanium nitride enters the trench 140 through the opening of the trench 140 that is not blocked by the top surface of the capacitor pillar 10. The deposition rates of titanium nitride are different in the first support layer 122a, the second support layer 122b, the sidewalls of the capacitor pillar 10, and the top surface of the substrate 10, resulting in the deposition of the second upper electrode 40 on the first upper electrode 30. The second upper electrode 40 deposited on the exposed sidewalls of the capacitor pillar 10 in the trench 140 has discontinuous portions, forming air gaps 41 in the trench 140. This ensures the semiconductor structure of this embodiment and guarantees that the second process deposition of the second upper electrode 40 can form air gaps.

[0109] The second process can employ either Physical Vapor Deposition (PVD) or Chemical Vapor Deposition (CVD). The second material can include compounds formed from one or both of metal nitrides and metal silicides. In this embodiment, the second material can be titanium nitride, titanium silicide, nickel silicide, or titanium silicon nitride (TiSixNy). The second deposition rate can be 5-10 nm / min.

[0110] The second deposition rate is greater than the first deposition rate in step S340, and the second material is the same as the first material.

[0111] In this embodiment, the physical vapor deposition (PVD) process is implemented as follows, using titanium nitride as the second material. The second upper electrode of titanium nitride can be deposited using sputtering or reactive sputtering. In sputtering, titanium nitride or metallic titanium is used as the target. Nitrogen gas is dissociated into nitrogen ions, which bombard the target, dislodging metal from the target and depositing it onto the first upper electrode to form the second upper electrode. However, the PVD process involves multi-directional and multi-angle scattering of sputtered atoms, resulting in a lower step coverage. Consequently, the second upper electrode deposited on the exposed sidewalls of the capacitor pillars in the trench has discontinuous portions, creating air gaps within the trench.

[0112] In other possible embodiments, the implementation process using Chemical Vapor Deposition (CVD) is as follows, with titanium nitride as the second material. A semiconductor structure can be placed in a CVD chamber, and after evacuation, titanium nitride is deposited by reacting TiCl4 or a metal compound of Ti with NH3, forming a second upper electrode on the first upper electrode. The second upper electrode deposited on a portion of the sidewall of the capacitor pillar exposed in the trench has discontinuous portions, forming air gaps within the trench.

[0113] This embodiment utilizes physical vapor deposition and chemical vapor deposition processes to deposit a second material at a faster deposition rate to form a second upper electrode. The thickness of the second upper electrode covering the exposed sidewall of the capacitor pillar has discontinuous parts, which form air gaps, thus solving the problem of leakage current in the semiconductor structure and improving the electrical performance and reliability of the semiconductor structure.

[0114] As an exemplary embodiment of this disclosure, this embodiment provides a method for fabricating a semiconductor structure, such as... Figure 4 As shown, the manufacturing method in this embodiment includes:

[0115] S410: Provides the initial structure.

[0116] S420: A patterned mask layer is formed on the stacked structure, the patterned mask layer having openings.

[0117] S430: Capacitor holes are formed by removing part of the stacked structure based on the openings of the patterned mask layer.

[0118] S440: Forming a capacitor post in the capacitor hole.

[0119] Steps S410-S440 in this embodiment are the same as those in the above embodiment, with step S310 being the step of forming capacitor pillars in the initial structure.

[0120] Please refer to Figure 7 In the process of forming the capacitor pillar 10, an initial structure 100 is first provided. The initial structure 100 includes a substrate 110 and a stacked structure 120 disposed on the substrate 110. A capacitor contact structure 111 is disposed in the substrate. Please refer to... Figure 8 A patterned mask layer 150 is formed on the stacked structure 120. The patterned mask layer 150 has an opening 151, which is positioned corresponding to the location of the capacitor contact structure 111. A portion of the stacked structure 120 is removed according to the opening 151 of the patterned mask layer 150 until the capacitor contact structure 111 is exposed, forming a capacitor hole 160. Figure 9As shown, the bottom of the capacitor hole 160 exposes the capacitor contact structure 111, and a capacitor post 10 is formed in the capacitor hole 160. The capacitor post 10 is connected to the capacitor contact structure 111.

[0121] like Figure 11 As shown, and refer to Figure 9 , Figure 10 Forming capacitor pillar 10 in capacitor hole 160 includes depositing capacitor pillar material on the top surface of capacitor hole 160 and stacked structure 120, and then using a dry etching process to remove the capacitor pillar material on the top surface of stacked structure 120, leaving the capacitor pillar material in capacitor hole 160 as capacitor pillar 10.

[0122] Atomic layer deposition (ALD) can be used to deposit capacitor pillars 20 in capacitor holes 160. The material of capacitor pillars 20 includes compounds formed by one or two of metal nitrides and metal silicides, such as titanium nitride, titanium silicide, nickel silicide, and titanium silicon nitride (TiSixNy). In this embodiment, capacitor pillars 10, the first upper electrode 30, and the second upper electrode 40 are all made of the same material, which is titanium nitride.

[0123] As an exemplary embodiment of this disclosure, this embodiment provides a method for fabricating a semiconductor structure, such as... Figure 5 As shown, the manufacturing method in this embodiment includes:

[0124] S510: Form capacitor pillars in the initial structure.

[0125] S520: A trench is formed by removing part of the initial structure, exposing part of the sidewalls of the capacitor pillar and the substrate of the initial structure.

[0126] S530: Form a dielectric layer that at least covers the exposed surface of the capacitor pillar.

[0127] S540: Form a first upper electrode, which covers the surface of the dielectric layer.

[0128] S550: Form a second upper electrode, which covers the surface of the first upper electrode.

[0129] S560: Anneal the second upper electrode.

[0130] The implementation methods of steps S540-S550 in this embodiment are the same as those of steps S310-S350 in the above embodiment, and will not be repeated here.

[0131] Annealing is performed in an ammonia atmosphere. Annealing can be carried out at different temperature ranges depending on the type of the second material. For example, when the second material is titanium nitride, rapid annealing is performed within a first temperature range of 400°C to 500°C, and the annealing time is less than 1 minute.

[0132] In this embodiment, the second upper electrode 40 is deposited at a relatively fast deposition rate using physical vapor deposition (PVD) or chemical vapor deposition (CVD). Annealing can remove stress from the second upper electrode and remove impurities doped in the vapor-deposited second upper electrode. At the same time, annealing promotes the diffusion of metal atoms in the second upper electrode, thereby filling the deposition vacancies generated during the deposition process. The annealed second upper electrode improves the conductivity and stability of the semiconductor structure.

[0133] As an exemplary embodiment of this disclosure, this embodiment provides a method for fabricating a semiconductor structure, such as... Figure 6 As shown, the manufacturing method in this embodiment includes:

[0134] S610: Form capacitor pillars in the initial structure.

[0135] S620: A trench is formed by removing part of the initial structure, exposing part of the sidewalls of the capacitor pillar and the substrate of the initial structure.

[0136] S630: Form a dielectric layer that at least covers the exposed surface of the capacitor pillar.

[0137] S640: Form a first upper electrode, the first upper electrode covering the surface of the dielectric layer.

[0138] S650: Form a second upper electrode, which covers the surface of the first upper electrode.

[0139] S670: A third upper electrode is formed on the surface of the second upper electrode, and the third upper electrode covers the exposed outer surface of the second upper electrode.

[0140] Steps S610-S650 in this embodiment are implemented in the same way as steps S510-S220 in the above embodiment, and will not be described again here.

[0141] like Figure 21As shown, the third upper electrode 60 can be deposited using either Physical Vapor Deposition (PVD) or Chemical Vapor Deposition (CVD). The material of the third upper electrode can include one or more compounds formed from metals and metal nitrides and metal silicides, such as tungsten, titanium nitride, titanium silicide, nickel silicide, and titanium silicon nitride (TiSixNy). The material of the third upper electrode 60 can be the same as or different from the materials of the first upper electrode 30 and the second upper electrode 40. In this embodiment, the material of the third upper electrode 60 is tungsten.

[0142] In this embodiment, a third upper electrode is deposited on the second upper electrode. This third upper electrode protects the semiconductor structure while increasing its conductivity. Furthermore, tungsten is used as the material for the third upper electrode, replacing the boron doping layer. This fundamentally solves the problem of boron particles penetrating into the dielectric material and causing capacitor leakage.

[0143] Among them, such as Figure 22 As shown, the fabrication method in this embodiment also includes back end of line (BEOL) processes, in which the semiconductor structure undergoes wire bonding, bonding, FCB, and ball grid array (BGA) packaging.

[0144] The semiconductor structure fabricated by the method of this embodiment can be used as a memory device, which can be used in DRAM (Dynamic Random Access Memory). However, it can also be applied to SRAM (Static Random Access Memory), flash memory, FeRAM (Ferroelectric Random Access Memory), MRAM (Magnetic Random Access Memory), PRAM (Phase Change Random Access Memory), etc.

[0145] As an exemplary embodiment of this disclosure, this embodiment provides a semiconductor structure, such as... Figure 20As shown, the semiconductor structure includes a substrate 110 and a capacitor contact structure 111 located within the substrate 110, as well as capacitor pillars 20 whose bottoms are electrically connected to the capacitor contact structure 111. A trench 140 is formed between the capacitor pillars 20. The semiconductor structure of this embodiment also includes a dielectric layer 20, a first upper electrode 30, and a second upper electrode 40. The dielectric layer 20 covers the surface of the capacitor pillars 10 and a portion of the substrate 110. The first upper electrode 30 covers the surface of the dielectric layer 20, and the second upper electrode 40 covers the first upper electrode 30. The second upper electrode 40 includes a discontinuous portion located within the trench 140, and an air gap 41 is formed inside the discontinuous portion. In the axial direction of the capacitor pillars 10, the thickness of the discontinuous portion of the second upper electrode 40 covering the sidewalls of the capacitor pillars 10 varies continuously.

[0146] An air gap 41 is formed between the capacitor pillars 10, which can reduce the amount of boron doped layer filling the space between the capacitor pillars 10 and reduce the boron particle density in the boron doped layer. The total amount of boron particles diffused into the dielectric material of the dielectric layer 30 during the thermal process is significantly reduced, which can prevent leakage current in the semiconductor structure.

[0147] As an exemplary embodiment of this disclosure, this embodiment provides a semiconductor structure. Most of the contents of the semiconductor structure in this embodiment are the same as those in the above embodiments. The difference is that, in this embodiment, in the axial direction of the capacitor post 10, the thickness of the discontinuous portion of the second upper electrode 40 covering the sidewall of the capacitor post 10 gradually increases from the middle to both ends.

[0148] As an embodiment of this application, most of the semiconductor structure in this embodiment is the same as that in the above embodiments, except that, as Figure 21 As shown, the semiconductor structure also includes a third upper electrode 60, which covers the exposed outer surface of the second upper electrode 40.

[0149] The first upper electrode 30 and the second upper electrode 40 are made of the same material. The third upper electrode 60 is made of the same material as or different from the material of the second upper electrode 40.

[0150] The first upper electrode 30 and the second upper electrode 40 are made of titanium nitride, and the third upper electrode is made of tungsten.

[0151] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or device. Without further limitation, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the article or device that includes said element.

[0152] The above embodiments are only used to illustrate the technical solutions of this disclosure and are not intended to limit it. The disclosure has been described in detail with reference to preferred embodiments. Those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of this disclosure without departing from the spirit and scope of this disclosure, and all such modifications and substitutions should be covered within the scope of the claims of this disclosure.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The method includes: Capacitor pillars are formed in the initial structure; A trench is formed by removing part of the initial structure, the trench exposing part of the sidewall of the capacitor pillar and the substrate of the initial structure; A dielectric layer is formed, which at least covers the exposed surface of the capacitor pillar; A first upper electrode is formed, which covers the surface of the dielectric layer; A second upper electrode is formed, which covers the surface of the first upper electrode; Wherein, in the axial direction of the capacitor column, the second upper electrode portion formed in the trench is discontinuous, and the discontinuous portion of the second upper electrode forms an air gap; Forming the first upper electrode includes: The first upper electrode is formed by depositing a first material on the dielectric layer at a first deposition rate using a first process; Forming a second upper electrode includes: A second material is deposited on the first upper electrode using a second process at a second deposition rate to form the second upper electrode, wherein the second deposition rate is greater than the first deposition rate.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The discontinuous portion of the second upper electrode covers the sidewall of the capacitor post exposed by the trench, and the thickness of the second upper electrode on the sidewall of the capacitor post covered by the discontinuous portion changes continuously.

3. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, The first material and the second material are the same.

4. The method for fabricating a semiconductor structure as described in any one of claims 1 to 3, characterized in that, The formation of multiple capacitor pillars on the initial structure includes: An initial structure is provided, the initial structure including a substrate and a stacked structure disposed on the substrate; A patterned mask layer is formed on the stacked structure, the patterned mask layer having openings; A portion of the stacked structure is removed according to the opening of the patterned mask to form a capacitor hole, the bottom of which exposes the substrate; The capacitor post is formed in the capacitor hole.

5. The method for fabricating a semiconductor structure as described in claim 4, characterized in that, The stacked structure includes a sacrificial layer and a support layer; The removal of the initial structure to form a trench includes: The sacrificial layer and part of the support layer of the initial structure are removed to form the trench.

6. The method for fabricating a semiconductor structure as described in claim 5, characterized in that, The sacrificial layer and the support layer are formed on the substrate, and the sacrificial layer and the support layer are stacked alternately.

7. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, After forming the second upper electrode, the process further includes annealing the second upper electrode.

8. The method for fabricating a semiconductor structure as described in claim 1, characterized in that, After forming the second upper electrode, the process also includes: A third upper electrode is formed on the surface of the second upper electrode, the third upper electrode covering the exposed outer surface of the second upper electrode, and the third upper electrode may be made of the same or different material as the second upper electrode.

9. A semiconductor structure, formed using the method for fabricating a semiconductor structure as described in any one of claims 1-8, characterized in that, include: Substrate; A capacitive contact structure is located within the substrate; A capacitor post, the bottom of which is electrically connected to the capacitor contact structure; The trench is located between the capacitor pillars; A dielectric layer covering the surface of the capacitor pillar and a portion of the substrate; The first upper electrode covers the surface of the dielectric layer; A second upper electrode covers the first upper electrode. The second upper electrode includes a discontinuous portion located within the trench, and the discontinuous portion has an air gap inside.

10. The semiconductor structure as described in claim 9, characterized in that, In the axial direction of the capacitor column, the thickness of the discontinuous portion of the second upper electrode covering the sidewall of the capacitor column changes continuously.

11. The semiconductor structure as claimed in claim 10, characterized in that, In the axial direction of the capacitor column, the thickness of the discontinuous portion of the second upper electrode covering the sidewall of the capacitor column gradually increases from the middle to both ends.

12. The semiconductor structure as claimed in claim 9, characterized in that, The semiconductor structure further includes a third upper electrode that covers the exposed outer surface of the second upper electrode.

13. The semiconductor structure as described in claim 9, characterized in that, The first upper electrode and the second upper electrode are made of the same material.

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