Semiconductor structure preparation method and semiconductor structure

Abstract

The present disclosure provides a method for fabricating a semiconductor structure and a semiconductor structure, relating to the field of semiconductor technology. The method comprises providing a substrate; forming a plurality of initial active pillars on the substrate; forming a gate layer between the initial active pillars; forming a first dielectric layer on the gate layer and the initial active pillars; forming a plurality of openings in the first dielectric layer; removing portions of the initial active pillars through the openings to form active pillars; and removing portions of the gate layer to form isolation trenches and word lines, such that two adjacent active pillars in the same row are located on opposite sides of the isolation trench. By separating two adjacent active pillars in the same row on opposite sides of the isolation structure, the present disclosure increases the spacing between two active pillars in the same column on adjacent word lines, reduces signal interference between adjacent word lines, and improves the performance of the semiconductor structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure and a semiconductor structure. Background Art

[0002] In the development of dynamic random access memory (DRAM), methods for increasing device integration include reducing the feature size of memory cell array devices and improving the cell structure. However, as the feature size decreases, small-sized transistors will produce serious short channel effects. Therefore, improving the memory cell topology and reducing the area occupied by the memory cell under the same feature size conditions is another effective way to increase device integration. For example, the current mainstream process uses 6F2 cells to replace the 8F2 cells in the existing technology to significantly improve the integration of DRAM. The future trend is to develop towards 4F2 DRAM memory cells with higher storage density, which requires the length and width of the memory cell to be 2F.

[0003] In the 4F2 cell structure, the structure of the word line transistors has also changed accordingly. As the word line spacing and the isolation structure of the memory array continue to shrink, the mutual interference between word lines becomes increasingly stronger, reducing the performance of the semiconductor structure. Summary of the Invention

[0004] In view of the above problems, the embodiments of the present disclosure provide a method for preparing a semiconductor structure and a semiconductor structure. By separating two adjacent active pillars in the same row on both sides of an isolation structure, the spacing between two active pillars in the same column on adjacent word lines is increased, the signal interference between adjacent word lines is reduced, and the performance of the semiconductor structure is improved.

[0005] In order to achieve the above objectives, the present disclosure provides the following technical solutions:

[0006] A first aspect of the present disclosure provides a method for preparing a semiconductor structure, comprising:

[0007] providing a substrate;

[0008] forming a plurality of initial active pillars on the substrate, wherein the plurality of initial active pillars are arranged in an array;

[0009] forming a gate layer between the initial active pillars, wherein the gate layer is connected to the sidewalls of the initial active pillars;

[0010] forming a first dielectric layer on the gate layer and the initial active pillar;

[0011] forming an opening in the first dielectric layer extending along the arrangement direction of the initial active pillar rows, wherein a projection of the opening on the substrate partially overlaps with a projection of the initial active pillars in the same row on the substrate, and portions where the projections of two adjacent initial active pillars in the same row on the substrate do not overlap with the projections of the opening on the substrate are located on both sides of the opening;

[0012] The initial active pillars exposed in the openings are removed to form active pillars; and the gate layer exposed in the openings are removed to form isolation trenches and word lines, wherein two adjacent active pillars in the same row are located on both sides of the isolation trenches.

[0013] The method for manufacturing a semiconductor structure as described above, wherein the isolation trench includes at least one first segment, at least one second segment, and at least one third segment;

[0014] Along the arrangement direction of the active pillars in the same row, the first segments and the second segments are staggered in sequence, and the third segment is used to connect the adjacent first segments and the second segments;

[0015] In two adjacent active pillars in the same row, the active pillars are located on different sides of the first segment and the second segment respectively.

[0016] The method for preparing the semiconductor structure as described above, wherein, after the step of providing a substrate and before the step of forming a plurality of initial active pillars on the substrate, the method further comprises:

[0017] A plurality of bit line structures are formed in the substrate, and the plurality of bit line structures are arranged at intervals along the row direction of the active pillars on the substrate, wherein the bit line structures include bit lines and bit line contacts arranged on the bit lines, and the top surface of the bit line contact is flush with the top surface of the substrate.

[0018] The method for manufacturing the semiconductor structure as described above, wherein the step of forming a plurality of bit line structures in the substrate includes:

[0019] forming a plurality of first grooves in the substrate and arranged at intervals along a row direction of the active pillars;

[0020] forming a first barrier layer on an inner wall of the first groove, wherein a top surface of the first barrier layer is lower than a top surface of the substrate;

[0021] Filling the first groove with a first conductive layer, wherein a top of the first conductive layer is flush with a top of the first barrier layer;

[0022] A polysilicon layer is formed on the first conductive layer, wherein a top surface of the polysilicon layer is flush with a top surface of the substrate.

[0023] The method for preparing the semiconductor structure as described above, wherein, after the step of forming a polysilicon layer on the first conductive layer, the method further comprises:

[0024] The polysilicon layer is ion doped by ion implantation technology.

[0025] The method for preparing the semiconductor structure as described above, wherein the step of forming a plurality of initial active pillars on the substrate comprises:

[0026] forming a second dielectric layer and a first mask layer stacked in sequence on the substrate;

[0027] removing a portion of the first mask layer and a portion of the second dielectric layer to form a plurality of second grooves spaced apart from each other, each second groove exposing a top surface of the bit line structure;

[0028] An initial active pillar is formed in the second groove, wherein the initial active pillar includes a channel region and a source electrode and a drain electrode respectively disposed at two ends of the channel region.

[0029] The method for manufacturing the semiconductor structure as described above, wherein, before the step of forming the initial active pillar in the second groove, the method further comprises:

[0030] forming a first oxide layer on the sidewall of the second groove, wherein a top surface of the first oxide layer is flush with a top surface of the retained first mask layer;

[0031] The first oxide layer at the bottom of the second groove is removed to expose the bit line structure.

[0032] The method for manufacturing the semiconductor structure as described above, wherein the step of forming an initial active column in the second groove, wherein the initial active column includes a channel region and a source electrode and a drain electrode respectively disposed at two ends of the channel region, comprises:

[0033] forming a silicon pillar in the second groove, and diffusing dopant ions in the polysilicon toward the silicon pillar so that one end of the silicon pillar facing the bit line contact portion forms a drain;

[0034] performing ion doping on an end of the silicon pillar away from the bit line contact portion to form a source;

[0035] The region of the silicon pillar located between the source and the drain constitutes a channel region of the initial active pillar.

[0036] The method for manufacturing the semiconductor structure as described above, wherein, after the step of forming the first dielectric layer covering the gate layer and the initial active pillar, the method further comprises:

[0037] forming a second mask layer on the first dielectric layer;

[0038] patterning the second mask layer to form a plurality of opening regions in the second mask layer;

[0039] The step of forming an opening in the first dielectric layer extending along the initial active pillar row arrangement direction includes:

[0040] The first dielectric layer exposed in the opening area is removed to form a plurality of openings in the first dielectric layer.

[0041] The method for manufacturing the semiconductor structure as described above, wherein, after the step of forming the plurality of isolation trenches in the first dielectric layer, the method further comprises:

[0042] An isolation structure is formed in the isolation trench, and the isolation structure extends out of the isolation trench and covers the gate layer and the active pillar.

[0043] The method for manufacturing the semiconductor structure as described above, wherein, after the step of forming the initial active pillars in the second grooves and before the step of forming the gate layer between the active pillars, the method further comprises:

[0044] removing the first mask layer and the first oxide layer to form a filling region, wherein the filling region exposes an outer peripheral surface of the initial active pillar;

[0045] A second oxide layer is formed in the filling region, the second oxide layer wraps around the outer surface of the initial active pillar and is connected to the retained second dielectric layer, and the second oxide layer and the retained second dielectric layer form a third groove.

[0046] The method for preparing the semiconductor structure as described above, wherein the step of forming a gate layer between the active pillars comprises:

[0047] forming a second barrier layer on an inner wall of the third groove;

[0048] A second conductive layer is formed in the area surrounded by the second barrier layer, and the top surface of the second conductive layer is flush with the top surface of the second barrier layer.

[0049] The method for preparing a semiconductor structure as described above, wherein, with a plane parallel to the substrate as a cross section, the cross-sectional shape of the active column includes an arc segment and a straight line segment connecting the ends of the arc segment, the arc opening of the arc segment is arranged toward the isolation trench, and the straight line segment is adjacent to the boundary of the isolation trench.

[0050] A second aspect of the present disclosure provides a semiconductor structure, comprising:

[0051] substrate;

[0052] A plurality of active pillars, wherein the plurality of active pillars are arranged in an array on the substrate;

[0053] A plurality of isolation structures are provided on the substrate, wherein the isolation structures include a first side and a second side opposite to each other, and the isolation structures extend along the arrangement direction of the active pillars in the same row to separate two adjacent active pillars in the same row on both sides of the isolation structure.

[0054] As described above, in the semiconductor structure, with the surface parallel to the substrate as the cross section, the cross-sectional shape of the active pillar includes an arc segment and a straight line segment connecting the ends of the arc segment, wherein the arc segments of several active pillars in the same column are oriented in the same direction, and the arc segments of the active pillars in two adjacent columns are oriented in opposite directions.

[0055] The semiconductor structure as described above, wherein the isolation structure comprises at least one first isolation segment, at least one second isolation segment, and at least one third isolation segment, the first isolation segment and the second isolation segment are sequentially staggered, and the third isolation segment is used to connect the adjacent first isolation segment and the second isolation segment;

[0056] Among two adjacent active pillars in the same row, one of the active pillars is located on one side of the first isolation segment, and the other active pillar is located on the other side of the second isolation segment.

[0057] The semiconductor structure as described above further includes a plurality of bit line structures in the substrate, wherein the bit line structures extend along the arrangement direction of the active pillars in the same column, wherein the tops of the bit line structures are connected to the bottoms of the active pillars.

[0058] The semiconductor structure as described above, wherein the bit line structure includes a bit line and a bit line contact portion provided on the bit line;

[0059] The bit line includes a first conductive layer and a first barrier layer wrapped outside the first conductive layer;

[0060] The bit line contact portion is located above the first conductive layer and connected to the first conductive layer. The upper top surface of the bit line contact portion is flush with the upper top surface of the substrate.

[0061] The semiconductor structure as described above, wherein the semiconductor structure further includes a plurality of word lines located between the isolation structures and extending in the same direction as the isolation structures, and the word lines are connected to the active pillars between adjacent isolation structures.

[0062] In the semiconductor structure preparation method and semiconductor structure provided by the embodiments of the present disclosure, by separating two adjacent active pillars in the same row on both sides of the isolation structure, the distance between two active pillars located in the same column on adjacent word lines is increased, signal interference between adjacent word lines is reduced, and the performance of the semiconductor structure is improved.

[0063] In addition to the technical problems solved by the embodiments of the present disclosure, the technical features that constitute the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, the preparation method of the semiconductor structure provided by the embodiments of the present disclosure and other technical problems that can be solved by the semiconductor structure, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further described in detail in the specific implementation methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0065] Figure 1 A schematic diagram of an active pillar in a semiconductor structure provided in the related art;

[0066] Figure 2 A schematic diagram of a top view of a semiconductor structure provided in the related art;

[0067] Figure 3 A process flow chart of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0068] Figure 4 A schematic diagram of a semiconductor structure prepared by the method for preparing a semiconductor structure provided by an embodiment of the present disclosure, viewed from above;

[0069] Figure 5 A schematic diagram of forming a first groove in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0070] Figure 6 A schematic diagram of forming a bit line and a polysilicon layer in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0071] Figure 7 A schematic diagram of forming a bit line contact portion in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0072] Figure 8A schematic diagram of forming a bit line structure in a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0073] Figure 9 A schematic diagram of forming a second dielectric layer and a second mask layer in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0074] Figure 10 A schematic diagram of forming a second mask opening in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0075] Figure 11 A schematic diagram of forming a second groove in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0076] Figure 12 A schematic diagram of forming a first initial oxide layer in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0077] Figure 13 A schematic diagram of forming a first oxide layer in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0078] Figure 14 A schematic diagram of forming a silicon pillar in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0079] Figure 15 A schematic diagram of forming an initial active pillar in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0080] Figure 16 A schematic diagram of forming a filling region in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0081] Figure 17 A schematic diagram of forming a third groove in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0082] Figure 18 A schematic diagram of forming a second initial barrier layer in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0083] Figure 19 A schematic diagram of forming a second initial conductive layer in the method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0084] Figure 20 A schematic diagram of forming a gate layer in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0085] Figure 21 A schematic diagram of forming a second mask layer and a second mask opening in the method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0086] Figure 22 for Figure 21 longitudinal section in;

[0087] Figure 23 A schematic diagram of forming an opening in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0088] Figure 24 for Figure 23 Schematic diagram of longitudinal section in;

[0089] Figure 25 A schematic diagram of an isolation trench in a method for fabricating a semiconductor structure provided by an embodiment of the present disclosure;

[0090] Figure 26 for Figure 25 Schematic diagram of the aa direction;

[0091] Figure 27 for Figure 25 Schematic diagram of the bb direction;

[0092] Figure 28 A schematic diagram of forming an isolation material in a method for preparing a semiconductor structure provided by an embodiment of the present disclosure;

[0093] Figure 29 for Figure 28 Schematic diagram of longitudinal section in;

[0094] Figure 30 A schematic diagram of a top view of a semiconductor structure provided by an embodiment of the present disclosure;

[0095] Figure 31 for Figure 30 Schematic diagram of the aa direction (schematic diagram of the formation of the isolation structure);

[0096] Figure 32 for Figure 30 Schematic diagram of the middle bb direction (schematic diagram of the formation of the isolation structure);

[0097] Figure 33 A schematic diagram of an active pillar in a semiconductor structure provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0098] With the development of dynamic random access memory (DRAM), methods to increase device integration include reducing the feature size of memory cell array devices and improving the cell structure. However, as the feature size of memory cell array devices decreases, small-size transistors will produce serious short channel effects. Therefore, improving the memory cell topology and reducing the area occupied by the memory cell under the same feature size conditions is another effective way to increase device integration. For example, the current mainstream process significantly improves the integration of DRAM by using 6F2 cells instead of 8F2 cells in the existing technology. The future trend is to develop towards 4F2 DRAM memory cells with higher storage density, which requires the length and width of the memory cell to be 2F.

[0099] In the 4F2 cell structure, the structure of the word line transistor has also changed accordingly. Figure 1 and Figure 2 As shown, a transistor in the related art includes a substrate 10, a plurality of bitline structures 20 formed within the substrate, and a plurality of active pillars 30 arranged in an array on the substrate. The transistor also includes a plurality of wordlines 150 for connecting adjacent active pillars 30 in the same row, and an isolation structure 160 for separating two adjacent wordlines 150. A ring-shaped gate layer 40 is formed on the active pillars 30, and the extension direction of the bitline structure 20 and the extension direction of the wordline 150 can be perpendicular to each other. As the wordline spacing and the isolation structure of the memory array continue to decrease, the mutual interference between wordlines becomes increasingly stronger, significantly reducing the performance of the semiconductor structure.

[0100] Therefore, during the preparation process of the semiconductor structure in the embodiment of the present disclosure, by separating two adjacent active pillars in the same row on both sides of the isolation structure, the spacing between two active pillars located in the same column on adjacent word lines is increased, signal interference between adjacent word lines is reduced, and the performance of the semiconductor structure is improved.

[0101] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present disclosure more obvious and easy to understand, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present disclosure.

[0102] Figure 3 is a flow chart of a method for preparing a semiconductor structure provided by an embodiment of the present disclosure, Figure 4 It is a schematic diagram of the semiconductor structure from a top view. Figures 5 to 33The schematic diagram of each stage in the preparation method of the semiconductor structure is shown below. Figures 4 to 33 The preparation method of semiconductor structure is introduced in detail.

[0103] This embodiment does not limit the semiconductor structure. The semiconductor structure will be described below using a dynamic random access memory (DRAM) as an example, but this embodiment is not limited thereto. The semiconductor structure in this embodiment may also be other structures.

[0104] like Figure 3 As shown, the present disclosure provides a method for preparing a semiconductor structure, comprising the following steps:

[0105] Step S100: providing a substrate.

[0106] For example, Figure 4 As shown, the substrate 10 serves as a supporting component of the memory, and is used to support other components disposed thereon. The material of the substrate 10 may include single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium compound, silicon on insulator, etc., or other materials known to those skilled in the art.

[0107] It should be noted that after the step of providing the substrate, a bit line structure 20 may be formed in the substrate to facilitate connection of the bit line structure 20 to the source of a transistor to be formed subsequently. Forming the bit line structure 20 on the substrate 10 includes the following steps:

[0108] Step S110 : forming a plurality of first grooves 101 spaced apart along a first direction in the substrate 10 .

[0109] For example, Figure 5 As shown, a third mask layer 50 may be formed on the substrate 10 by a deposition process, and then the third mask layer 50 may be patterned to form a plurality of third mask openings 501 spaced apart along the first direction in the third mask layer 50 .

[0110] A first photoresist layer can be formed on the third mask layer 50, and a third mask pattern can be formed on the first photoresist layer by exposure or development and etching. The first photoresist layer with the third mask pattern is used as a mask plate, and part of the third mask layer is removed to form a plurality of spaced third mask openings 501.

[0111] In this embodiment, the third mask pattern is transferred to the third mask layer, and the third mask layer is used as a mask to etch the substrate, thereby improving the accuracy of pattern transfer and the performance of the semiconductor structure.

[0112] After the third mask openings 501 are formed, an etching solution or an etching gas is used to remove the substrate 10 exposed in each third mask opening 501 , so as to form a plurality of first grooves 101 in the substrate 10 .

[0113] Step S120 : forming a first barrier layer 211 on the inner wall of the first groove 101 , wherein the top surface of the first barrier layer 211 is lower than the top surface of the substrate 10 .

[0114] For example, Figure 6 As shown, a first initial barrier layer may be formed on the inner wall of the first groove 101 by an atomic layer deposition process, and the first initial barrier layer extends to the outside of the first groove 101 and covers the top surface of the substrate 10 .

[0115] The first initial barrier layer on the top surface of the substrate 10 and a portion of the first initial barrier layer on the inner wall of the first groove 101 are removed, and the first initial barrier layer remaining on the inner wall of the first groove 101 forms a first barrier layer 211 .

[0116] The material of the first barrier layer 211 includes a conductive material such as titanium nitride. The first barrier layer 211 has both conductive properties and can prevent the conductive material in the subsequently formed first conductive layer 212 from diffusing into the substrate.

[0117] Step S130 : filling the first groove 101 with a first conductive layer 212 , with the top of the first conductive layer 212 flush with the top of the first barrier layer 211 .

[0118] The first conductive layer 212 located in one of the first grooves 100 and the first barrier layer 211 wrapped around the first conductive layer 212 constitute a bit line 21 . A plurality of bit lines 21 are arranged on the substrate 10 along the first direction at intervals.

[0119] The material of the first conductive layer 212 includes conductive materials such as tungsten.

[0120] Step S140 : forming a polysilicon layer 220 a on the first conductive layer 212 , wherein a top surface of the polysilicon layer 220 a is flush with a top surface of the substrate 10 .

[0121] For example, Figure 7 As shown, a polysilicon layer 220 a may be formed on the first conductive layer 212 by a physical vapor deposition process or a chemical vapor deposition process. The polysilicon layer fills the area enclosed by the first conductive layer 212 and the substrate 10 .

[0122] After the polysilicon layer 220 a is formed, ion doping may be performed on the polysilicon layer using an ion implantation technique, so that the ion-doped polysilicon layer 220 forms a bit line contact portion 22 .

[0123] Thereafter, the third mask layer 50 remaining on the top surface of the substrate 10 is removed.

[0124] It should be noted that in this embodiment, N-type ions, such as phosphorus ions, can be doped into the polysilicon layer 220a to form N-type polysilicon; or P-type ions, such as boron ions, can be doped into the polysilicon layer 220a to form P-type polysilicon.

[0125] Step S200 : forming a plurality of initial active pillars 310 on the substrate 10 , wherein the plurality of initial active pillars 310 are arranged in an array.

[0126] Exemplarily, step S210: forming a second dielectric layer 60 and a first mask layer 70 stacked in sequence on the substrate 10 .

[0127] like Figure 9 As shown, the second dielectric layer 60 and the first mask layer 70 may be stacked and formed on the substrate 10 by an atomic layer deposition process, a chemical vapor deposition process, or a physical vapor deposition process.

[0128] The first mask layer 70 may be a single-layer structure or a stacked-layer structure. When the first mask layer 70 is a stacked-layer structure, the first mask layer 70 may include a tetraethoxysilane (TEOS) layer, a spin-on carbon (SOC) layer, a silicon oxynitride (SiON) layer, a spin-on carbon (SOC) layer, and a silicon oxynitride (SiON) layer stacked in sequence on the second dielectric layer 60.

[0129] The material of the second dielectric layer 60 includes silicon nitride and other materials.

[0130] Step S220 : removing a portion of the first mask layer 70 and a portion of the second dielectric layer 60 to form a plurality of second grooves 200 spaced apart from each other, each second groove 200 exposing a top surface of the bit line structure 20 .

[0131] For example, Figure 10 As shown, the first mask layer 70 may be patterned to form a plurality of first mask openings 701 spaced apart along a first direction on the first mask layer 70 .

[0132] like Figures 9 to 11 As shown, a second photoresist layer 80 can be formed on the first mask layer 70, and a first mask pattern can be formed on the second photoresist layer 80 by exposure or development and etching. The second photoresist layer 80 having the first mask pattern is used as a second mask, and a portion of the first mask layer 70 is removed to form a plurality of first mask openings 701 spaced apart. The width of the first mask openings 701 is greater than the width of the first groove 101.

[0133] After the first mask opening 701 is formed, the remaining first mask layer 70 and the second dielectric layer 60 are etched using an etching solution or an etching gas, and the first mask layer 70 and the second dielectric layer 60 exposed in each first mask opening 701 are removed, so that each second groove 200 exposes the top surface of the corresponding bit line structure 20.

[0134] Step S221 : forming a first oxide layer 90 on the sidewall of the second groove 200 , wherein the top surface of the first oxide layer 90 is flush with the top surface of the retained first mask layer 70 .

[0135] For example, Figure 12 As shown, a first initial oxide layer 901 can be formed on the inner wall of the second groove 200 by an atomic layer deposition process, and the first initial oxide layer 901 extends outside the second groove 200 and covers the top surface of the retained first mask layer 70. The first initial oxide layer 901 on the top surface of the first mask layer 70 is removed by wet etching.

[0136] Step S222 : removing the first oxide layer 90 at the bottom of the second groove 200 to expose the bit line structure 20 .

[0137] For example, Figure 13 As shown, the first initial oxide layer 901 at the bottom of the second groove 200 in step S221 is further etched by wet etching, and the bit line structure 20 is exposed through the second groove 200. The first initial oxide layer 901 remaining on the inner wall of the second groove 200 constitutes the first oxide layer 90.

[0138] Step S230 : forming an initial active pillar 31 in the second groove 200 . The initial active pillar 31 includes a channel region 31 c and a source 31 a and a drain 31 b respectively disposed at two ends of the channel region 31 c .

[0139] Exemplarily, step S231 : forming a silicon pillar 100 in the second groove 200 , and diffusing dopant ions in the ion-doped polysilicon layer 220 toward the silicon pillar 100 , so that the drain 31 b is formed at one end of the silicon pillar 100 facing the bit line contact portion 22 .

[0140] like Figure 14 As shown, the silicon pillar 100 can be formed in the second groove 200 by a chemical vapor deposition process or a physical vapor deposition process. Then, the dopant ions in the ion-doped polysilicon layer 220 in the bit line structure 20 are diffused toward one end of the silicon pillar 100 through an annealing diffusion process, so that the end of the silicon pillar 100 forms the drain 31b, so that the drain 31b is connected to the bit line contact portion 22.

[0141] Step S232 : performing ion doping on an end of the silicon pillar 100 away from the bit line contact portion 22 to form a source 31 a .

[0142] For example, Figure 15 As shown, ion implantation can be used to perform ion doping on the end of the silicon pillar 100 away from the bit line contact portion 22 to form a source 31a, so that the source 31a can be connected to components such as a capacitor. The area between the source 31a and the drain 31b on the silicon pillar 100 constitutes the channel region 31c of the initial active pillar 31.

[0143] The first direction is the extending direction of the rows of the initial active pillars 31 arranged in an array.

[0144] Step S300 : forming a gate layer 40 between the initial active pillars 31 , wherein the gate layer 40 is connected to the sidewalls of the initial active pillars 31 .

[0145] Exemplarily, step S310 : removing the first mask layer 70 and the first oxide layer 90 to form a filling region 41 , wherein the filling region 41 exposes the outer peripheral surface of the initial active pillar 31 .

[0146] like Figure 16 As shown, the first mask layer 70 and the first oxide layer 90 may be removed by cleaning or dry etching.

[0147] Step S320 : forming a second oxide layer 110 in the filling region 41 . The second oxide layer 110 wraps around the outer surface of the initial active pillar 31 and is connected to the retained second dielectric layer 60 . The second oxide layer 110 and the retained second dielectric layer 60 form a third groove 42 .

[0148] like Figure 17 As shown, a second oxide layer 110 may be formed on the outer surface of the initial active pillar 31 by an atomic layer deposition process. It should be noted that the second oxide layer 110 is a gate oxide layer.

[0149] Step S330 : forming a second barrier layer 410 on the inner wall of the third groove 42 , and forming a second conductive layer 420 in the area surrounded by the second barrier layer 410 , with the top surface of the second conductive layer 420 flush with the top surface of the second barrier layer 410 .

[0150] For example, Figures 18 to 20 As shown, a second initial barrier layer 410a can be formed on the inner wall of the third groove 42 by an atomic layer deposition process, and the second initial barrier layer 410a extends to the outside of the third groove 42 and covers the second oxide layer 110 and the top surface of the retained second dielectric layer 60.

[0151] Thereafter, a second preliminary conductive layer 420 a may be deposited on the second preliminary barrier layer 410 a by an atomic layer deposition process. The deposition height of the second preliminary conductive layer 420 a exceeds a predetermined height of the second preliminary barrier layer 410 a deposited on the top surface of the preliminary active pillar 31 .

[0152] Afterwards, a portion of the second initial conductive layer 420a and a portion of the second initial barrier layer 410a can be removed by wet etching. The second initial barrier layer 410a remaining in the third groove 42 constitutes the second barrier layer 410, and the second initial conductive layer 420a remaining on the second barrier layer 410 constitutes the second conductive layer 420. Along the height extension direction of the substrate 10, the top of the second conductive layer 420 is flush with the top of the second barrier layer 410. The second barrier layer 410 and the second conductive layer 420 constitute the gate layer 40, and the gate layer 40 is connected to the sidewalls of the initial active pillar 31 and is disposed on both sides of the sidewalls of the initial active pillar 31.

[0153] The second barrier layer 410 is made of a conductive material such as titanium nitride. The second barrier layer 410 is conductive and can prevent the conductive material in the subsequently formed second conductive layer 420 from diffusing into the substrate. The second conductive layer 420 is made of a conductive material such as tungsten.

[0154] Step S400 : forming a first dielectric layer 120 on the gate layer 40 and the initial active pillar 31 .

[0155] For example, Figure 21 As shown, the first dielectric layer 120 can be formed on the gate layer 40 and the initial active pillar 31 by atomic layer deposition, chemical vapor deposition, and physical vapor deposition processes. The deposition height of the first dielectric layer 120 is higher than the predetermined height of the initial active pillar 31 along the substrate height extension direction.

[0156] The material of the first dielectric layer 120 includes a stacked silicon nitride layer 120 a and a TEOS layer 120 b .

[0157] Step S500: An opening 300 extending along the row arrangement direction of the initial active pillars 31 is formed in the first dielectric layer 120. The projection of the opening 300 on the substrate 10 partially overlaps with the projection of the initial active pillars 31 in the same row on the substrate 10. The portions where the projections of two adjacent initial active pillars 31 in the same row on the substrate 10 do not overlap with the projections of the opening 300 on the substrate 10 are located on both sides of the opening 300.

[0158] For example, Figure 21 As shown, step S510 : forming a second mask layer 130 on the first dielectric layer 120 .

[0159] The second mask layer 130 may be formed on the first dielectric layer 120 by an atomic layer deposition process, a chemical vapor deposition process, or a physical vapor deposition process.

[0160] The second mask layer 130 may be a single layer structure or a stacked layer structure. Figure 21 and Figure 22 As shown, the second mask layer 130 may include a spin-on carbon (SOC) layer 130 a and a silicon oxynitride (SiON) layer 130 b sequentially stacked on the first dielectric layer 120 .

[0161] Step S520 : patterning the second mask layer 130 to form a plurality of opening regions on the second mask layer 130 , wherein the opening regions are arranged at intervals along the extending direction of the rows of the initial active pillars 31 .

[0162] A third photoresist layer can be formed on the second mask layer 130, and a second mask pattern can be formed on the third photoresist layer by exposure or development and etching. The third photoresist layer with the second mask pattern is used as a mask to remove part of the second mask layer to form a plurality of spaced second mask openings 1301.

[0163] In this embodiment, the second mask pattern is transferred to the second mask layer 130 and the second mask layer 130 is etched using the second mask layer as a mask, thereby improving the accuracy of pattern transfer and the performance of the semiconductor structure.

[0164] After the second mask openings 1301 are formed, an etching solution or an etching gas is used to remove the second mask layer 130 exposed in each second mask opening 1301 to form a plurality of opening areas on the second mask layer.

[0165] Step S530 : forming openings 300 in the first dielectric layer 120 , extending along the row arrangement direction of the initial active pillars 31 .

[0166] For example, Figure 23 and Figure 24 As shown, the second mask layer 130 is removed, and the first dielectric layer 120 exposed in the opening area is removed, so as to form an opening 300 in the first dielectric layer 120 extending along the row direction of the initial active pillars 31. The projection of the opening on the substrate 10 partially overlaps with the projection of the initial active pillars 31 in the same row on the substrate 10. At the same time, the non-overlapping portions of the projections of two adjacent initial active pillars 31 in the same row on the substrate 10 and the projection of the opening 300 on the substrate 10 are respectively located on both sides of the opening 300.

[0167] Step S600 : removing the initial active pillars 31 exposed in the openings 300 to form active pillars 30 ; and removing the gate layer 40 exposed in the openings 300 to form isolation trenches 140 and word lines 150 , wherein two adjacent active pillars 30 in the same row are located on both sides of the isolation trench 140 .

[0168] For example, Figure 26 、 Figure 27 and Figure 33 As shown, a portion of the first dielectric layer 120 can be removed by wet etching. Etching is then continued downward to remove the initial active pillars 31 exposed within the openings 300. The remaining initial active pillars 31 constitute the active pillars 30. The gate layer 40 within the openings 300 is removed. The removed area between two adjacent active pillars 31 in the same column constitutes the isolation trench 140 between two adjacent rows of active pillars 30. The remaining second barrier layer 410 and the remaining second conductive layer 420 constitute the word line 150. The two adjacent active pillars 31 in the same row are located on either side of the isolation trench 140.

[0169] Figure 25 FIG. 1 shows a projected shape of the isolation trench 140 on the substrate 10 , wherein the isolation trench 140 includes at least one first segment 140 a , at least one second segment 140 b , and at least one third segment 140 c .

[0170] Along the arrangement direction of the active pillars 30 in the same row, the first segment 140a and the second segment 140b are staggered, and the third segment 140c is used to connect the adjacent first and second segments 140a, 140b. In two adjacent active pillars 30 in the same row, the third segment 140c is located on different sides of the first and second segments 140a, 140b, respectively, and is provided between two adjacent active pillars 30 in the same row. In other words, the two adjacent active pillars 30 in the same row are separated on either side of the isolation trench 140.

[0171] In this embodiment, the cross-section of the active pillar 30, taken along a plane parallel to the substrate 10, includes an arc segment and a straight line segment connecting the ends of the arc segment. The arc opening of the arc segment is disposed toward the isolation trench 140, and the straight line segment is adjacent to the boundary of the isolation trench 140. The arc shape of the arc segment on the active pillar 30 can be a major arc or a semicircular arc. This increases the spacing between two active pillars 30 located in the same column on adjacent word lines, thereby reducing signal interference between adjacent word lines and improving the performance of the semiconductor structure.

[0172] It should be noted that after the steps of forming the isolation trench 140 and the word line 150, an isolation structure 160 may be formed in the isolation trench 140. The isolation structure 160 extends outside the isolation trench 140 and covers the gate layer 40 and the active pillar 30. The steps of forming the isolation structure 160 in the isolation trench 140 include:

[0173] Step S710 : filling the isolation trench 140 with an isolation material 170 .

[0174] For example, Figure 28 and Figure 29 As shown, the isolation material 170 can be deposited in the isolation trench 140 by an atomic layer deposition process, a chemical vapor deposition process, or a physical vapor deposition process, and the deposition thickness of the isolation material 170 along the height extension direction of the substrate 10 is higher than the predetermined height of the active pillar 30.

[0175] Step S720 : removing a portion of the isolation material 170 , a portion of the first dielectric layer 120 , and a portion of the second oxide layer 110 to form an isolation structure 160 .

[0176] For example, Figures 30 to 32 As shown, along the direction from the source 31a of the active pillar 30 to its drain 31b, part of the isolation material 170, part of the first dielectric layer 120 and part of the second oxide layer 110 on the top surface of the source 31a of the active pillar 30 can be removed by wet etching, so that the source 31a of the active pillar 30 is exposed to facilitate connection with devices such as a capacitor tube.

[0177] like Figure 30 and Figure 33 As shown, the embodiment of the present disclosure further provides a semiconductor structure, which includes:

[0178] Base 10;

[0179] A plurality of active pillars 30 , wherein the plurality of active pillars 30 are arranged in an array on the substrate 10 ;

[0180] A plurality of isolation structures 160 are disposed on the substrate 10 . The isolation structures 160 include a first side and a second side that are oppositely disposed. The isolation structures 160 extend along the arrangement direction of the active pillars 30 in the same row to separate two adjacent active pillars 30 in the same row on both sides of the isolation structure 160 .

[0181] like Figure 33 As shown, the cross-section of the active pillar 30, parallel to the surface of the substrate 10, includes arc segments and straight segments connecting the ends of the arc segments. The arc segments of several active pillars 30 in the same row are oriented in the same direction, while the arc segments of active pillars 30 in two adjacent rows are oriented in opposite directions. The arc segments of the active pillars 30 can be major arcs or semicircular arcs.

[0182] The isolation structure 160 includes at least one first isolation segment 160a, at least one second isolation segment 160b and at least one third isolation segment 160c. The first isolation segment and the second isolation segment are staggered in sequence, and the third isolation segment is used to connect the adjacent first isolation segment and the second isolation segment. In two adjacent active pillars 30 in the same row, one of the active pillars is located on one side of the first isolation segment 160a, and the other active pillar 30 is located on the other side of the second isolation segment 160b.

[0183] That is, by separating two adjacent active pillars 30 in the same row on both sides of the isolation structure 160, the distance between two active pillars in the same column on adjacent word lines is increased, signal interference between adjacent word lines is reduced, and the performance of the semiconductor structure is improved.

[0184] like Figure 31 and Figure 32 As shown, the semiconductor structure further includes a plurality of bit line structures 20 in the substrate 10 . The bit line structures 20 extend along the arrangement direction of the active pillars 30 in the same column, wherein the tops of the bit line structures 20 are connected to the bottoms of the active pillars 30 .

[0185] The bitline structure 20 includes a bitline 21 and a bitline contact 22 disposed on the bitline 21. The bitline includes a first conductive layer 212 and a first barrier layer 211 wrapped around the first conductive layer 212. The bitline contact 22 is located above and connected to the first conductive layer 212, and the top surface of the bitline contact 22 is flush with the top surface of the substrate 10. The bitline contact 22 is connected to the drain 31b of the active pillar 30. The source 31a of the active pillar 30 can be connected to a component such as a capacitor. The area between the drain 31b and source 31a of the active pillar 30 is a channel region 31c, on which a semi-annular gate layer is formed.

[0186] like Figure 31 and Figure 32 As shown, the semiconductor structure further includes a plurality of word lines 150 located between the isolation structures 160 and extending in the same direction as the isolation structures 160 . The word lines 150 are connected to the active pillars 30 between adjacent isolation structures 160 .

[0187] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0188] In the description of this specification, reference to terms such as "one embodiment", "some embodiments", "illustrative embodiment", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure.

[0189] In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any suitable manner in any one or more embodiments or examples.

[0190] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: providing a substrate; forming a plurality of initial active pillars on the substrate, wherein the plurality of initial active pillars are arranged in an array; forming a gate layer between the initial active pillars, wherein the gate layer is connected to the sidewalls of the initial active pillars; forming a first dielectric layer on the gate layer and the initial active pillar; forming an opening in the first dielectric layer extending along the arrangement direction of the initial active pillar rows, wherein a projection of the opening on the substrate partially overlaps with a projection of the initial active pillars in the same row on the substrate, and portions where the projections of two adjacent initial active pillars in the same row on the substrate do not overlap with the projections of the opening on the substrate are located on both sides of the opening; removing the initial active pillar exposed in the opening to form an active pillar; and removing the gate layer exposed in the opening to form an isolation trench and a word line, wherein two adjacent active pillars in the same row are located on both sides of the isolation trench; After the step of providing a substrate and before the step of forming a plurality of initial active pillars on the substrate, the preparation method further includes: forming a plurality of bit line structures in the substrate, the plurality of bit line structures being arranged on the substrate at intervals along a row direction of the active pillars, wherein the bit line structures include bit lines and bit line contacts provided on the bit lines, and a top surface of the bit line contact is flush with a top surface of the substrate; The step of forming a plurality of initial active pillars on the substrate includes: forming a second dielectric layer and a first mask layer stacked in sequence on the substrate; removing a portion of the first mask layer and a portion of the second dielectric layer to form a plurality of second grooves spaced apart from each other, each second groove exposing a top surface of the bit line structure; An initial active pillar is formed in the second groove, wherein the initial active pillar includes a channel region and a source electrode and a drain electrode respectively disposed at two ends of the channel region.

2. The method for preparing a semiconductor structure according to claim 1, wherein: The isolation trench includes at least one first segment, at least one second segment, and at least one third segment; Along the arrangement direction of the active pillars in the same row, the first segments and the second segments are staggered in sequence, and the third segment is used to connect the adjacent first segments and the second segments; In two adjacent active pillars in the same row, the active pillars are located on different sides of the first segment and the second segment respectively.

3. The method for preparing a semiconductor structure according to claim 1, wherein: The step of forming a plurality of bit line structures in the substrate includes: forming a plurality of first grooves in the substrate and arranged at intervals along a row direction of the active pillars; forming a first barrier layer on an inner wall of the first groove, wherein a top surface of the first barrier layer is lower than a top surface of the substrate; Filling the first groove with a first conductive layer, wherein the top of the first conductive layer is flush with the top of the first barrier layer; A polysilicon layer is formed on the first conductive layer, wherein a top surface of the polysilicon layer is flush with a top surface of the substrate.

4. The method for preparing a semiconductor structure according to claim 3, wherein: After the step of forming a polysilicon layer on the first conductive layer, the preparation method further comprises: The polysilicon layer is ion doped by ion implantation technology.

5. The method for preparing a semiconductor structure according to claim 1, wherein: Before the step of forming an initial active pillar in the second groove, the preparation method further includes: forming a first oxide layer on the sidewall of the second groove, wherein a top surface of the first oxide layer is flush with a top surface of the retained first mask layer; The first oxide layer at the bottom of the second groove is removed to expose the bit line structure.

6. The method for preparing a semiconductor structure according to claim 3, wherein: The step of forming an initial active column in the second groove, wherein the initial active column includes a channel region and a source electrode and a drain electrode respectively disposed at two ends of the channel region, includes: forming a silicon pillar in the second groove, and diffusing dopant ions in the polysilicon toward the silicon pillar so that one end of the silicon pillar facing the bit line contact portion forms a drain; performing ion doping on an end of the silicon pillar away from the bit line contact portion to form a source; The region of the silicon pillar located between the source and the drain constitutes a channel region of the initial active pillar.

7. The method for preparing a semiconductor structure according to claim 6, wherein: After the step of forming a first dielectric layer on the gate layer and the initial active pillar, the preparation method further comprises: forming a second mask layer on the first dielectric layer; patterning the second mask layer to form a plurality of opening regions in the second mask layer; The step of forming an opening in the first dielectric layer extending along the initial active pillar row arrangement direction includes: The first dielectric layer exposed in the opening area is removed to form a plurality of openings in the first dielectric layer.

8. The method for preparing a semiconductor structure according to claim 7, wherein: After the step of forming the plurality of isolation trenches in the first dielectric layer, the preparation method further comprises: An isolation structure is formed in the isolation trench, and the isolation structure extends out of the isolation trench and covers the gate layer and the active pillar.

9. The method for preparing a semiconductor structure according to claim 1, wherein: After the step of forming the initial active pillars in the second grooves and before the step of forming the gate layer between the active pillars, the preparation method further includes: removing the first mask layer and the first oxide layer to form a filling region, wherein the filling region exposes an outer peripheral surface of the initial active pillar; A second oxide layer is formed in the filling region, the second oxide layer wraps around the outer surface of the initial active pillar and is connected to the retained second dielectric layer, and the second oxide layer and the retained second dielectric layer form a third groove.

10. The method for preparing a semiconductor structure according to claim 9, wherein: The step of forming a gate layer between the active pillars includes: forming a second barrier layer on an inner wall of the third groove; A second conductive layer is formed in the area surrounded by the second barrier layer, and the top surface of the second conductive layer is flush with the top surface of the second barrier layer.

11. The preparation method according to any one of claims 1 to 10, characterized in that: Taking a plane parallel to the substrate as a cross section, the cross-sectional shape of the active column includes an arc segment and a straight line segment connecting the ends of the arc segment, the arc opening of the arc segment is set toward the isolation trench, and the straight line segment is adjacent to the boundary of the isolation trench.

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