Display device

Abstract

A display device capable of supplying a high voltage to a display element is provided. The display device includes an image data generating circuit, a source driver circuit, and a pixel. The source driver circuit is electrically connected to the pixel through first and second wirings used as signal lines. The pixel includes a display element that is a liquid crystal element. A potential of one electrode of the display element can be a potential of the first wiring, and a potential of the other electrode of the display element can be a potential of the second wiring. The image data generating circuit has a function of generating digital image data including first and second data. When image data corresponding to the digital image data is supplied to the pixel, one of the first and second wirings is set to a potential corresponding to the first data, and the other of the first and second wirings is set to a potential corresponding to the second data. By switching the potential of the first wiring and the potential of the second wiring, frame inversion driving or the like can be performed.

Description

[0001] This application is a divisional application of the following application for an invention patent:

[0002] Title of Invention: Display device; Filing date: January 18, 2019; Application number: 201980007073.4. TECHNICAL FIELD

[0003] One embodiment of the present application relates to a display device and a method for driving the same.

[0004] Note that one embodiment of the present application is not limited to the technical field described above. Examples of a technical field of one embodiment of the present application include a semiconductor device, a display device, a light-emitting device, a display system, an electronic device, a lighting device, an input device (e.g., a touch sensor), an input-output device (e.g., a touch panel), and a driving method or a manufacturing method thereof.

[0005] In this specification and the like, a semiconductor device generally means a device that can function by utilizing semiconductor characteristics. A display device (e.g., a liquid crystal display device, a light-emitting display device, or the like), a projection device, a lighting device, an electro-optical device, a power storage device, a memory device, a semiconductor circuit, an imaging device, an electronic device, or the like can be referred to as a semiconductor device. Alternatively, they can be said to include a semiconductor device. BACKGROUND

[0006] Patent Document 1 discloses a display device with high withstand voltage that can drive a display element at a high voltage.

[0007] [Prior Art Documents]

[0008] [Patent Documents]

[0009] [Patent Document 1] Japanese Published Patent Application No. 2011-227479 SUMMARY

[0010] PROBLEMS TO BE SOLVED BY THE INVENTION

[0011] In order to drive a display element such as a liquid crystal element at a high voltage, a source driver circuit capable of outputting a high voltage is needed. However, such a source driver circuit has a large occupied area and is high in cost.

[0012] One of objects of one embodiment of the present application is to provide a display device capable of supplying a high voltage to a display element. One of objects of one embodiment of the present application is to provide a small display device. One of objects of one embodiment of the present application is to provide an inexpensive display device. One of objects of one embodiment of the present application is to provide a low-power-consumption display device. One of objects of one embodiment of the present application is to provide a highly reliable display device. One of objects of one embodiment of the present application is to provide a display device with high display quality. One of objects of one embodiment of the present application is to provide a novel display device. One of objects of one embodiment of the present application is to provide a method for driving the above display device.

[0013] Note that the description of these objects does not preclude the existence of other objects. One embodiment of the present application does not necessarily achieve all the above objects. An object other than the above objects can be extracted from the description, drawings, and claims.

[0014] Means for solving the technical problem

[0015] One embodiment of the present application is a display device including a first circuit, a second circuit, and a pixel, in which the first circuit has a function of generating digital image data including first data and second data, the second circuit is electrically connected to the pixel through a first wiring, the second circuit is electrically connected to the pixel through a second wiring, the second circuit has a function of setting a potential of the first wiring to one of a potential corresponding to the first data and a potential corresponding to the second data, the second circuit has a function of setting a potential of the second wiring to the other of the potential corresponding to the first data and the potential corresponding to the second data, the pixel includes a first transistor, a second transistor, a capacitor, and a display element, one of a source and a drain of the first transistor is electrically connected to one electrode of the capacitor, one electrode of the capacitor is electrically connected to one electrode of the display element, one of a source and a drain of the second transistor is electrically connected to the other electrode of the capacitor, the other of the source and the drain of the first transistor is electrically connected to the first wiring, the other of the source and the drain of the second transistor is electrically connected to the second wiring, and the display element has a function of displaying an image corresponding to the image data.

[0016] In the above embodiment, the second circuit can include a selection circuit including a first input terminal, a second input terminal, a first output terminal, and a second output terminal, the first input terminal is supplied with a potential corresponding to the first data, the second input terminal is supplied with a potential corresponding to the second data, the first output terminal is electrically connected to the first wiring, and the second output terminal is electrically connected to the second wiring.

[0017] In the above-described mode, the second circuit can also include a first switch, a second switch, the second input terminal can be electrically connected to one terminal of the first switch and one terminal of the second switch, another terminal of the first switch can be supplied with the first potential, another terminal of the second switch can be supplied with the second potential, and the opening and closing of the first switch and the second switch can be controlled by the second data.

[0018] In the above-described mode, the second data can also include information about the most significant bit of the digital image data.

[0019] In the above-described mode, the second circuit can also be a source driver circuit.

[0020] In the above-described mode, the display device can also be a liquid crystal device.

[0021] In the above-described mode, the display device can also include liquid crystal exhibiting a blue phase.

[0022] In the above-described mode, the first and second transistors can include a metal oxide in the channel formation region, and the metal oxide can include In, Zn, and M (M is Al, Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf).

[0023] Effects of Invention

[0024] According to one embodiment of the present invention, a display device capable of supplying a high voltage to a display device can be provided. According to one embodiment of the present invention, a small display device can be provided. According to one embodiment of the present invention, an inexpensive display device can be provided. According to one embodiment of the present invention, a low-power-consumption display device can be provided. According to one embodiment of the present invention, a highly reliable display device can be provided. According to one embodiment of the present invention, a display device with high display quality can be provided. According to one embodiment of the present invention, a novel display device can be provided. According to one embodiment of the present invention, a method for operating the above display device can be provided.

[0025] Note that the description of these effects does not preclude the presence of other effects. One embodiment of the present invention does not necessarily achieve all the effects described above. Other effects inherent to the present invention will be apparent from accounts of the present invention made throughout the specification, embodiments, drawings, reference examples and best mode for carrying out the present invention. BRIEF DESCRIPTION OF DRAWINGS

[0026] [FIG. 1] A diagram illustrating one example of a display device and a diagram explaining image data.

[0027] [FIG. 2] A diagram illustrating one example of a display device and a diagram illustrating one example of characteristics of a DA conversion circuit.

[0028] [FIG. 3] A diagram illustrating one example of operation of a display device.

[0029] [ Figure 4 ]FIG. 1 shows an example of a display device.

[0030] [FIG. 5] FIG. 5 shows an example of a display device and shows an example of the operation of the display device.

[0031] [ Figure 6 ]FIG. 6 shows an example of a display device.

[0032] [FIG. 7] FIG. 7 shows an example of the operation of a display device.

[0033] [ Figure 8 ]FIG. 8 shows an example of a pixel.

[0034] [ Figure 9 ]FIG. 9 shows an example of the operation of a pixel.

[0035] [ Figure 10 ]FIG. 10 shows an example of a pixel.

[0036] [ Figure 11 ]FIG. 11 shows an example of the operation of a pixel.

[0037] [FIG. 12] FIG. 12 shows an example of a pixel.

[0038] [FIG. 13] FIG. 13 shows an example of a pixel.

[0039] [ Figure 14 ]FIG. 14 shows an example of a display device.

[0040] [ Figure 15 ]FIG. 15 shows an example of a display device.

[0041] [FIG. 16] FIG. 16 shows an example of a transistor.

[0042] [FIG. 17] FIG. 17 shows an example of a transistor.

[0043] [FIG. 18] FIG. 18 shows an example of a transistor.

[0044] [FIG. 19] FIG. 19 shows an example of a transistor.

[0045] [FIG. 20] FIG. 20 shows an example of an electronic device.

[0046] Embodiment of the Invention

[0047] Embodiments will be described in detail with reference to the accompanying drawings. Note that the present application is not limited to the following description, and it will be readily appreciated by those skilled in the art that the present application can be carried out in various changes and modifications of the embodiments. Therefore, the present application should not be construed as being limited to the following description of the embodiments.

[0048] Note that, in the drawings described below, the same or similar portions are denoted with the same reference numerals, and repeated explanation of these portions is omitted. Furthermore, the same hatching pattern is applied to portions having essentially the same function.

[0049] Furthermore, for the convenience of explanation, the position, size, range, and the like of each component illustrated in the drawings are not necessarily to scale or a realistic one. Therefore, the disclosed application is not necessarily limited to the position, size, range, and the like disclosed in the drawings.

[0050] Furthermore, depending on the case or state, "film" and "layer" can be interchanged. For example, "conductive layer" can be interchanged with "conductive film". Furthermore, "insulating film" can be interchanged with "insulating layer".

[0051] In this specification and the like, a metal oxide means an oxide of a metal in a broad sense. A metal oxide is classified into an oxide insulator, an oxide conductor (including a transparent oxide conductor), an oxide semiconductor (which can also be simply referred to as an OS), and the like. For example, in the case where a metal oxide is used for a semiconductor layer of a transistor, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, an OS transistor can mean a transistor including a metal oxide or an oxide semiconductor.

[0052] In this specification and the like, a metal oxide including nitrogen is also referred to as a metal oxide (metal oxide) in some cases. Furthermore, a metal oxide including nitrogen can also be referred to as a metal oxynitride.

[0053] (Embodiment 1)

[0054] In this embodiment, a display device of one embodiment of the present application will be described with reference to drawings.

[0055] One embodiment of the present application relates to a display device including an image data generating circuit, a source driver circuit, and a pixel. The source driver circuit is electrically connected to the pixel through a first wiring and is electrically connected to the pixel through a second wiring. The pixel includes a display element, and a potential of one electrode of the display element can be a potential of the first wiring and a potential of the other electrode of the display element can be a potential of the second wiring. That is, in the display device of one embodiment of the present application, a difference between the potential of the first wiring and the potential of the second wiring can be a voltage applied to the display element.

[0056] Here, the first and second wirings can be used as signal lines, and the display element can be a liquid crystal element.

[0057] In this specification and the like, a voltage applied to a display element refers to a potential difference between a potential supplied to one electrode of the display element and a potential supplied to the other electrode of the display element.

[0058] The image data generating circuit has a function of generating digital image data. The digital image data includes first data and second data. For example, in the case where the digital image data is 9-bit data, the lower 8 bits can be the first data and the most significant bit can be the second data.

[0059] The display device of one embodiment of the present application can operate in a first mode or a second mode. In the first mode, in the source driver circuit, the potential of the first wiring is a potential corresponding to the first data and the potential of the second wiring is a potential corresponding to the second data. On the other hand, in the second mode, in the source driver circuit, the potential of the first wiring is a potential corresponding to the second data and the potential of the second wiring is a potential corresponding to the first data. That is, the display device of one embodiment of the present application supplies image data to the pixel through both the first wiring and the second wiring. Furthermore, by switching the first mode and the second mode, frame inversion driving can be performed. Alternatively, source line inversion driving, gate line inversion driving, dot inversion driving, or the like can be performed.

[0060] In the display device of one embodiment of the present application, even when the potential supplied to the pixel by the source driver circuit is low, the voltage applied to the display element can be increased, for example, compared to the case where image data is supplied to the pixel only through the first wiring. Thus, power consumption of the display device of one embodiment of the present application can be reduced even when a high voltage is applied to the display element. Furthermore, an amplifier circuit included in the source driver circuit does not need to have high withstand voltage, and thus the display device of one embodiment of the present application can be reduced in size and cost.

[0061] <1-1. Structure Example 1 of Display Device>

[0062] Figure 1AFIG. 1 is a diagram illustrating a structure example of a display device 10 of a display device of one embodiment of the present application. The display device 10 includes a pixel array 14 in which pixels 11 are arranged in a matrix of m rows and n columns (m and n are integers of 2 or more), a gate driver circuit 12, a source driver circuit 13, an image data generation circuit 61, and an image processing circuit 62. Note that the pixel 11 includes a display element 26. As the display element 26, a liquid crystal element can be used, for example.

[0063] The gate driver circuit 12 is electrically connected to the pixel 11 through m wirings 33. The source driver circuit 13 is electrically connected to the pixel 11 through n wirings 31 and n wirings 32. Further, the image data generation circuit 61 is electrically connected to the image processing circuit 62, and the image processing circuit 62 is electrically connected to the source driver circuit 13.

[0064] In this specification and the like, the pixel 11 in the i-th row and the j-th column (i is an integer of 1 or more and m or less, and j is an integer of 1 or more and n or less) is denoted as pixel 11 [i, j]. Further, the wiring 33 electrically connected to the pixel 11 in the i-th row is denoted as wiring 33 [i], and the wiring 31 and the wiring 32 electrically connected to the pixel 11 in the j-th column are denoted as wiring 31 [j] and wiring 32 [j], respectively.

[0065] The potential of one electrode included in the display element 26 of the pixel 11 in the j-th column can be the potential of the wiring 31 [j]. Further, the potential of the other electrode included in the display element 26 of the pixel 11 in the j-th column can be the potential of the wiring 32 [j]. That is, in the display device 10, the difference between the potential of the wiring 31 [j] and the potential of the wiring 32 [j] can be the voltage applied to the display element 26 included in the pixel 11 in the j-th column.

[0066] The image data generation circuit 61 has a function of generating digital image data corresponding to an image displayed on the pixel array 14. Figure 1B FIG. 2 is a diagram illustrating digital image data input to the source driver circuit 13. As Figure 1B indicated in FIG. 2, the digital image data includes first data and second data. For example, in the case where the digital image data is 9-bit data, the lower 8 bits can be the first data and the most significant bit can be the second data. For example, in the case where the digital image data is 10-bit data, the lower 8 bits can be the first data and the upper 2 bits can be the second data. That is, the second data can be data including information on the most significant bit.

[0067] The image processing circuit 62 has a function of performing image processing such as gamma correction, dimming, color adjustment, noise removal, distortion correction, encoding, decryption, and the like on the digital image data input to the source driver circuit 13.

[0068] The gate driver circuit 12 has a function of generating a selection signal for selecting the pixel 11 and supplying the signal to the pixel 11 through the wiring 33. The potential of the wiring 33 is a potential corresponding to the selection signal generated by the gate driver circuit 12. That is, the wiring 33 is used as a scan line.

[0069] The source driver circuit 13 has a function of, after digital-analog conversion (hereinafter, DA conversion) of the first data in the digital image data input to the source driver circuit 13, outputting the data to one of the wiring 31 and the wiring 32. Further, the source driver circuit 13 has a function of outputting a potential corresponding to the second data to the other of the wiring 31 and the wiring 32 in the digital image data input to the source driver circuit 13. As described above, the source driver circuit 13 has a function of the potential of one of the wiring 31 and the wiring 32 being a potential corresponding to the first data and the potential of the other of the wiring 31 and the wiring 32 being a potential corresponding to the second data. Further, the wiring 31 and the wiring 32 are used as signal lines.

[0070] In this specification and the like, an operation mode in which the potential of the wiring 31 is a potential corresponding to the first data and the potential of the wiring 32 is a potential corresponding to the second data is referred to as a first mode. Further, an operation mode in which the potential of the wiring 32 is a potential corresponding to the first data and the potential of the wiring 31 is a potential corresponding to the second data is referred to as a second mode. That is, by switching the first mode and the second mode, the voltage applied to the display device 26 is reversed, and frame inversion driving or the like is performed. Thus, when the display device 26 is a liquid crystal device, deterioration of the display device 26 can be suppressed compared to a case where frame inversion driving or the like is not performed, so the reliability of the display device 10 can be improved.

[0071] Figure 2A is a view illustrating a specific example of the configuration of the source driver circuit 13. Note that, in Figure 2A , the pixel 11[i, j], the gate driver circuit 12, the image data generation circuit 61, and the image processing circuit 62 are illustrated in addition to the source driver circuit 13.

[0072] The source driver circuit 13 includes a shift register 41, a latch circuit 42, a level shift circuit 43, a DA conversion circuit 44, an amplifier circuit 46, a level shift circuit 63, an inverter circuit 64, a switch 48a, a switch 48b, and a selection circuit 65. As the switch 48a and the switch 48b, for example, a CMOS transistor, an n-channel transistor, or a p-channel transistor can be used.

[0073] The output terminal of the image processing circuit 62 is electrically connected to the input terminal of the latch circuit 42 through the data bus wiring 51. The output terminal of the shift register 41 is electrically connected to the clock input terminal of the latch circuit 42. The output terminal of the latch circuit 42 is electrically connected to the input terminal of the level conversion circuit 43. The output terminal of the level conversion circuit 43 is electrically connected to the input terminal of the DA conversion circuit 44 and the input terminal of the level conversion circuit 63. The output terminal of the DA conversion circuit 44 is electrically connected to the input terminal of the amplifier circuit 46. The output terminal of the level conversion circuit 63 is electrically connected to the input terminal of the inverter circuit 64.

[0074] The first input terminal of the selection circuit 65 is electrically connected to the output terminal of the amplifier circuit 46. The second input terminal of the selection circuit 65 is electrically connected to one of the terminals of the switch 48a and one of the terminals of the switch 48b. Here, the connection portion of the wiring connecting the second input terminal of the selection circuit 65, one of the terminals of the switch 48a, and the other terminal of the switch 48b is referred to as a node SN.

[0075] The opening and closing of the switch 48a can be controlled by a signal output from the inverter circuit 64. The opening and closing of the switch 48b can be controlled by a signal output from the level conversion circuit 63.

[0076] The input terminal of the latch circuit 42 is input with digital image data corresponding to an image displayed on the pixel array 14 from the data bus wiring 51. The latch circuit 42 has a function of holding the digital image data in accordance with a signal supplied from the shift register 41 and outputting the held digital image data.

[0077] The level conversion circuit 43 has a function of further increasing or decreasing the amplitude voltage of the input digital image data. Specifically, the level conversion circuit 43 has a function of converting the amplitude voltage of the digital image data supplied from the latch circuit 42 to an amplitude voltage at which the DA conversion circuit 44 appropriately operates.

[0078] The DA conversion circuit 44 has a function of converting first data included in the digital image data to analog data in accordance with the digital value of the first data. Here, the potential that the DA conversion circuit 44 can output is a potential V M to a potential V H . The potential V M may be, for example, a potential higher than the ground potential, the potential V H may be, for example, a potential higher than the potential V M .

[0079] Figure 2B is a graph showing the relationship between the output potential of the DA conversion circuit 44 and the digital value of the input first data. As Figure 2BAs shown, the larger the digital value of the first data input to the DA conversion circuit 44, the higher the output potential. For example, when the number of bits of the first data is 8 bits, the DA conversion circuit 44 can output the potential V M when the digital value is 255 in decimal notation, and can output the potential V H when the digital value is 255 in decimal notation. Note that the DA conversion circuit 44 can also output the lower potential the larger the digital value of the first data input thereto. For example, when the number of bits of the first data is 8 bits, the DA conversion circuit 44 can output the potential V H when the digital value is 255 in decimal notation, and can output the potential V M when the digital value is 255 in decimal notation. Note that, as shown in FIG. 4, the relationship between the output potential in the DA conversion circuit 44 and the digital value of the first data input thereto is preferably linear, but can be nonlinear. For example, it can be a curve having no extreme value. Figure 2B

[0080] The amplification circuit 46 has a function of amplifying and outputting the analog data input to the input terminal to the output terminal. By providing the amplification circuit 46, the potential corresponding to the first data can be stably supplied to the pixel 11. As the amplification circuit 46, a voltage follower circuit including an operational amplifier or the like can be used. Further, in a case where a circuit having a differential input circuit is used as the amplification circuit, the bias voltage of the differential input circuit is preferably infinite approaching to 0 V.

[0081] Here, when the potential output from the amplifier circuit 46 is the potential V S1 , the potential V S1 can be said to be the potential corresponding to the first data. Further, the potential of the potential V S1 may be the potential V M to the potential V H .

[0082] The level conversion circuit 63 has a function of outputting a signal in which the amplitude voltage of the second data included in the digital image data is converted to be higher or lower. Specifically, the level conversion circuit 63 has a function of converting the amplitude voltage of the second data included in the digital image data supplied from the level conversion circuit 43 to the amplitude voltage at which the switch 48a and the switch 48b appropriately operate. For example, the level conversion circuit 63 has a function of converting the amplitude voltage of the second data so that the potential V Figure 1B ​As illustrated, in a case where the number of bits of the second data is one bit, the switch 48b is turned on and the switch 48a is turned off when the value of the second data is "1", and the switch 48a is turned on and the switch 48b is turned off when the value of the second data is "0". Note that the switch 48a can be turned on and the switch 48b can be turned off when the value of the second data is "1", and the switch 48b can be turned on and the switch 48a can be turned off when the value of the second data is "0".

[0083] The inverter circuit 64 has a function of inverting the value of the signal output from the level conversion circuit 63. That is, the inverter circuit 64 has a function of inverting the value of the second data. For example, the inverter circuit 64 has a function of outputting a signal of a value of "0" when the value of the second data is "1" and outputting a signal of a value of "1" when the value of the second data is "0". Thus, the switch 48a can be turned off when the switch 48b is turned on, and the switch 48a can be turned on when the switch 48b is turned off.

[0084] The other terminal of the switch 48a can be applied with a potential V M , for example. Further, the other terminal of the switch 48b can be applied with a potential V L , for example. Here, the potential V L may be a potential lower than the potential V M . For example, the potential V L may be a negative potential. Note that the other terminal of the switch 48a can be applied with the potential V L , and the other terminal of the switch 48b can be applied with the potential V M . Further, the potential of the potential V S1 may be the potential V L to the potential V M , and the other terminal of the switch 48a or the other terminal of the switch 48b can be applied with the potential V H .

[0085] Thus, the potential of the node SN can be a potential corresponding to the second data. Here, when the potential of the node SN is the potential V S2 , the potential V S2 may be a potential corresponding to the second data. Further, the second data can be the potential V M or the potential V L , for example.

[0086] The first input terminal of the selection circuit 65 is supplied with the potential V S1 , and the second input terminal of the selection circuit 65 is supplied with the potential V S2 . The selection circuit 65 has a wire outputting the potential V S1 and outputs the potential V S2The wiring function. Specifically, when the display device 10 operates in the first mode, the potential V is... S1 Output to wiring 31[j], and set the potential V S2 Output to wiring 32[j]. On the other hand, when the display device 10 is operating in the second mode, the potential V is... S1 Output to wiring 32[j] and set the potential V S2 The output is routed to 31[j]. In other words, the selection circuit 65 can be said to have functions such as frame inversion driving.

[0087] The selection circuit 65 is supplied with a mode switching signal MSS. The mode switching signal MSS functions to control the operation of the selection circuit 65. The mode switching signal MSS can be, for example, a 1-bit digital signal. For example, when the value of the mode switching signal MSS is "1", the selection circuit 65 can adjust the voltage V. S1 Output to wiring 31[j] and set the potential V S2 Output to wiring 32[j]. Furthermore, for example, when the mode switching signal MSS has a value of "0", the selection circuit 65 can adjust the potential V. S1 Output to wiring 32[j] and set the potential V S2 Output to wiring 31[j]. That is, for example, when the value of the mode switching signal MSS is "1", the display device 10 operates in the first mode, and when the value of the mode switching signal MSS is "0", the display device 10 operates in the second mode. Note that, for example, the display device 10 can also operate in the first mode when the value of the mode switching signal MSS is "0", and operate in the second mode when the value of the mode switching signal MSS is "1".

[0088] Figure 3A1 , Figure 3A2 It shows the potential V S1 and potential V S2 A graph showing the relationship between the digital values ​​of the digital image data input to the source driver circuit 13. Here, the second data is as follows: Figure 1B The figure shows the most significant bits of the digital image data. Figure 3A1 In the middle, the source driver circuit 13 has Figure 2A The structure shown has a potential V when the value of the second data is "0". S2 Potential V M When the value of the second data is "1", the potential V S2 Potential V L On the other hand, in Figure 3A2 In the middle, regardless of the value of the second data, the potential V S2 Both are potentials V M .

[0089] existFigure 3A1 In the middle, potential V S1 With potential V S2 The maximum value of the difference can be the potential "V". H -V L On the other hand, in Figure 3A2 In the middle, at potential V S1 With potential V S2 The maximum value of the difference is the potential "V". H -V M "That is to say, in" Figure 3A1 and Figure 3A2 The range of potentials that the DA converter circuit 44 can output is equal, that is, the potential V S1 When the possible ranges are equal, Figure 3A1 Compared to the situation shown in Figure 3A2, the potential V is shown in the figure. S1 With potential V S2 The maximum value of the difference can be even larger. As mentioned above, even if the potential V S1 The smaller size also allows for a higher voltage to be applied to the display device 26. Therefore, even when a high voltage is applied to the display device 26, the power consumption of the display device 10 can be reduced. Furthermore, the amplifier circuit 46 does not need to have high voltage withstand capability, thus enabling miniaturization and cost reduction of the display device 10.

[0090] Figure 3B This is a graph showing the relationship between the potential difference between wiring 31 and wiring 32 in the first and second modes and the digital value of the digital image data input to the source driver circuit 13. (See diagram below.) Figure 3B As shown, the potential difference between wiring 31 and wiring 32 in the first mode is a potential "V". S1 -V S2 In the second mode, the potential is "-(V)". S1 -V S2 Therefore, by switching between the first mode and the second mode, the voltage applied to the display device 26 is reversed, thereby enabling frame inversion drive, etc.

[0091] <1-2. Example 2 of the structure of a display device>

[0092] exist Figure 2A In the source driver circuit 13, a level conversion circuit 63, an inverter circuit 64, a switch 48a, a switch 48b, and a selection circuit 65 are provided, or they may not be provided in the source driver circuit 13. Figure 4 yes Figure 2AAs a modification example of the configuration shown in FIG. 6, the inverter circuit 64 and the selection circuit 65 are provided in the switching circuit 16 which is a circuit different from the source driver circuit 13. Further, in the switching circuit 16, the transistor 68a and the transistor 68b are provided as the switch 48a and the switch 48b, respectively. Note that the level shift circuit 63 is not provided in the source driver circuit 13 and the switching circuit 16. Further, the potential generation circuit 70 is provided in the switching circuit 16.

[0093] As the transistor 68a and the transistor 68b, for example, a CMOS transistor, an n-channel transistor, or a p-channel transistor can be used. Hereinafter, a case where an n-channel transistor is used as the transistor 68a and the transistor 68b will be described, and the following description can be referred to when another transistor is used.

[0094] The output terminal of the level shift circuit 43 is electrically connected to the input terminal of the inverter circuit 64 and the gate of the transistor 68b in addition to the input terminal of the DA conversion circuit 44. The output terminal of the inverter circuit 64 is electrically connected to the gate of the transistor 68a.

[0095] The first input terminal of the selection circuit 65 is electrically connected to the output terminal of the amplifier circuit 46 in the same manner as in the case shown in FIG. 6. The second input terminal of the selection circuit 65 is electrically connected to one of the source and the drain of the transistor 68a and one of the source and the drain of the transistor 68b. Here, a connection portion of a wiring connecting the second input terminal of the selection circuit 65, one of the source and the drain of the transistor 68a, and one of the source and the drain of the transistor 68b is referred to as a node SN. Figure 2A

[0096] The other of the source and the drain of the transistor 68a can be supplied with, for example, a potential V M The other of the source and the drain of the transistor 68b can be supplied with, for example, a potential V L .

[0097] The transistor 68b is provided with a back gate in addition to the gate. The back gate is electrically connected to the potential generation circuit 70. The potential generation circuit 70 has a function of generating a predetermined potential. The potential generated by the potential generation circuit 70 can be supplied to the back gate of the transistor 68b. Thus, the threshold voltage of the transistor 68b can be controlled. For example, by generating a negative potential by the potential generation circuit 70 and supplying the potential to the back gate of the transistor 68b, the threshold voltage of the transistor 68b can be shifted in the positive direction.

[0098] In this specification, simply referred to as a "gate" is sometimes referred to as a front gate. Alternatively, both the front gate and the back gate are sometimes referred to.

[0099] ​When the back gate is not provided in the transistor 68b, for example, when the threshold voltage of the transistor 68b is 0 V, in order to turn off the transistor 68b, it is necessary to make the potential of the gate of the transistor 68b be the potential V L or lower. However, when the potential V L or lower cannot be output from the source driver circuit 13, for example, when the potential V L is negative, the transistor 68b cannot be turned off. In that case, by supplying a negative potential to the back gate of the transistor 68b with the potential generation circuit 70, the threshold voltage of the transistor 68b is drifted in the positive direction, and the transistor 68b can be turned off. Note that the transistor 68a can also include a back gate. Further, the switching circuit 16 can also include Figure 2A the level shift circuit 63. At this time, the back gate can not be provided in the transistor 68b, and the potential generation circuit 70 can not be provided.

[0100] As the transistor 68a and the transistor 68b, a transistor including a metal oxide in a channel formation region (hereinafter referred to as an OS transistor) can be used. The OS transistor has a high withstand voltage property. Thus, a high potential can be applied to the source, the drain, and the gate of the transistor 68a and the transistor 68b. In particular, by using the OS transistor as the transistor 68b, the potential V L can be made a smaller negative potential, that is, a potential with a larger absolute value, and thus is preferable.

[0101] Further, as the transistor 68a and the transistor 68b, a transistor including silicon in a channel formation region (hereinafter referred to as an Si transistor) can be used. Note that as the Si transistor, a transistor including amorphous silicon, a transistor including crystalline silicon (typically, low-temperature polysilicon), a transistor including monocrystalline silicon, and the like can be given. Since the on-state current of the Si transistor is high, when the potential of the switching potential V S2 is changed, the potential of the node SN can be determined quickly.

[0102] Note that when the other of the source and the drain of the transistor 68a is supplied with the potential V L , it is preferable that the transistor 68a include a back gate and the back gate be electrically connected to the potential generation circuit 70.

[0103] <1-3. Structure Example 3 of Display Device>

[0104] Figure 5A is a modification example of the structure illustrated in FIG. 1A, Figure 4 is a modification example of the structure illustrated in FIG. 1A, Figure 5A is a modification example of the structure illustrated in FIG. 1A, and Figure 4The difference in the structure shown is that the switching circuit 16 does not include the potential generation circuit 70; the switching circuit 16 includes a transistor 71 and a capacitor 72. Note that in Figure 5A In this configuration, transistors 68a, 68b, and 71 do not include a back gate, but some or all of the transistors may include a back gate. Furthermore, the back gate may be electrically connected to a potential generation circuit and its potential may be controlled. Alternatively, a structure may be adopted in which the gate and back gate are electrically connected, and the potential of the back gate is equal to the potential of the gate.

[0105] As with transistors 68a and 68b, transistor 71 can be, for example, a CMOS transistor, an n-channel transistor, or a p-channel transistor. The following describes the case where an n-channel transistor is used as transistor 71, but the following description can also be used when other transistors are used.

[0106] The output terminal of the level conversion circuit 43, except for the input terminals of the DA conversion circuit 44 and the inverter circuit 64, is electrically connected to one electrode of the capacitor 72. The gate of transistor 68b is electrically connected to one of the source and drain terminals of transistor 71 and the other electrode of capacitor 72. The gate of transistor 71 is electrically connected to the gate driver circuit 12 via wiring 81. Here, the wiring connecting the input terminals of the DA conversion circuit 44, the input terminals of the inverter circuit 64, and one electrode of capacitor 72 is called node FN1. Furthermore, the wiring connecting the gate of transistor 68b, one of the source and drain terminals of transistor 71, and the other electrode of capacitor 72 is called node FN2. Moreover, the connection portion of the wiring connecting the output terminal of inverter circuit 64 and the gate of transistor 68a is called node FN3.

[0107] Another potential VSS can be applied to the source and drain of transistor 71, for example. Potential VSS can be a potential V... L The following potentials.

[0108] Switching circuit 16 has in Figure 5A In the structure shown, the gate driver circuit 12 controls the conduction and non-conduction functions of the transistor 71 by controlling the potential of the wiring 81.

[0109] Figure 5B It is shown Figure 5A The timing diagram shows an example of the operation of the switching circuit 16 with the shown structure. Here, the potential VDD can be the potential V. H The above potentials, where potential "VSS+VDD" is higher than potential V LFurther, the source driver circuit 13 can output a potential of GND or higher. Further, the second data included in the digital image data is 1-bit data, and the source driver circuit 13 supplies the potential GND or the potential VDD to the switching circuit 16 in accordance with the value of the second data. Further, the threshold voltage of the transistor 68a and the transistor 68b is 0 V, and the potential V M is the potential GND. Further, the potential supplied to the gate of the transistor 68a is the potential VDD when the potential at the node FN1 is the potential GND, and is the potential GND when the potential at the node FN1 is the potential VDD.

[0110] The potential at the node FN1 and the potential at the node FN2 are reset from the time T01 to the time T02. At the time T01, the source driver circuit 13 outputs the potential GND to the switching circuit 16, and writes the potential GND to the node FN1. Further, at the time T01, when the potential at the wire 81 is the potential VDD, the transistor 71 is turned on, and the potential VSS is written to the node FN2. Further, the potential at the node FN3 is the potential VDD. Note that the operation from the time T01 to the time T02 can be performed, for example, during a retrace period of the operation of the display device 10.

[0111] The time T02 to the time T03 shows a case where the source driver circuit 13 supplies the potential VDD to the switching circuit 16 as a potential corresponding to the second data. At the time T02, when the potential at the wire 81 is set to the potential VSS, and then the potential VDD is supplied to the switching circuit 16 from the source driver circuit 13, the potential at the node FN1 becomes the potential VDD. Thus, when the capacitive coupling coefficient at the node FN2 is 1, the potential at the node FN2 is the potential "VSS+VDD", which is higher than the potential V L Further, the potential at the node FN3 becomes the potential GND. As described above, since the threshold voltage of the transistor 68a and the transistor 68b is 0 V, the transistor 68a is not turned on, and the transistor 68b is turned on. Thus, the value of the potential V S2 becomes the potential V L .

[0112] The time T03 or later shows a case where the source driver circuit 13 supplies the potential GND to the switching circuit 16 as a potential corresponding to the second data. At the time T03, when the potential at the wire 81 is set to the potential VSS, and then the potential GND is supplied to the switching circuit 16 from the source driver circuit 13, the potential at the node FN1 becomes the potential GND. Thus, when the capacitive coupling coefficient at the node FN2 is 1, the potential at the node FN2 is the potential VSS, which is the potential V LBelow. Furthermore, the potential of node FN3 is potential VDD. As mentioned above, since the threshold voltages of transistors 68a and 68b are 0V, transistor 68a is turned on, and transistor 68b is not turned on. Therefore, the potential V S2 The value becomes the potential V M .

[0113] Transistor 71 is preferably a transistor with extremely low off-state current. This allows the potential of node FN2 to be maintained for a long time. An example of a transistor with extremely low off-state current is the OS transistor.

[0114] As the semiconductor material for the OS transistor, metal oxides with a bandgap of 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more, can be used. Typically, indium-containing oxide semiconductors are used, for example, CAAC (C-Axis Aligned Crystalline)-OS or CAC (Cloud-Aligned Composite)-OS. CAAC-OS is a crystalline oxide semiconductor. Furthermore, because the reliability of transistors using this crystalline oxide semiconductor can be improved, it is preferable to use this transistor in a display device according to one aspect of the present invention. In addition, CAC-OS exhibits high mobility characteristics, making it suitable for transistors and the like that used for high-speed driving.

[0115] OS transistors have a large bandgap and exhibit extremely low off-state current. Unlike Si transistors, OS transistors do not experience impact ionization, avalanche breakdown, or short-channel effects, thus enabling the formation of highly reliable circuits.

[0116] As described above, the OS transistor has high voltage withstand characteristics. Therefore, by using the OS transistor as transistor 71, high voltages can be applied to the source, drain, and gate of transistor 71. Thus, for example, the potential VSS can be a smaller negative potential, that is, a potential with a larger absolute value.

[0117] Alternatively, a Si transistor can be used as transistor 71. As mentioned above, the Si transistor has a higher on-state current, so the potential of node FN2 can be reset in a short time.

[0118] <1-4. Example 4 of the structure of a display device>

[0119] exist Figure 2A The example shown is a source driver circuit 13 with a second data bit length of 1 bit, which is included in the digital image data input to the source driver circuit 13. The second data bit length can also be 2 bits or more. Figure 6Fig. 2 shows a configuration example of the source driver circuit 13 when the number of bits of the second data is 2 bits, which is a modification example of Fig. 1. Figure 2A

[0120] The source driver circuit 13 includes the shift register 41, the latch circuit 42, the level conversion circuit 43, the DA conversion circuit 44, the amplifier circuit 46, and the selection circuit 65, and further includes the switch 49a, the switch 49b, the switch 49c, the switch 49d, the level conversion circuit 63a, the level conversion circuit 63b, the level conversion circuit 63c, and the level conversion circuit 63d. As the switches 49a to 49d, for example, CMOS transistors, n-channel transistors, or p-channel transistors can be used.

[0121] Note that the switches 49a to 49d, the level conversion circuits 63a to 63d, and the selection circuit 65 can be provided in a circuit different from the source driver circuit 13.

[0122] The output terminal of the level conversion circuit 43 is electrically connected to the input terminals of the level conversion circuits 63a to 63d, in addition to the input terminal of the DA conversion circuit 44. The first input terminal of the selection circuit 65 is electrically connected to the output terminal of the amplifier circuit 46, as in the case shown in Fig. 1. Figure 2A The second input terminal of the selection circuit 65 is electrically connected to one of the terminals of the switch 49a, one of the terminals of the switch 49b, one of the terminals of the switch 49c, and one of the terminals of the switch 49d. Here, the connection portions of the wirings connecting the second input terminal of the selection circuit 65, one of the terminals of the switch 49a, one of the terminals of the switch 49b, one of the terminals of the switch 49c, and one of the terminals of the switch 49d are referred to as nodes SN.

[0123] The opening and closing of the switch 49a can be controlled by a signal output from the level conversion circuit 63a. The opening and closing of the switch 49b can be controlled by a signal output from the level conversion circuit 63b. The opening and closing of the switch 49c can be controlled by a signal output from the level conversion circuit 63c. The opening and closing of the switch 49d can be controlled by a signal output from the level conversion circuit 63d.

[0124] ​The level conversion circuits 63a to 63d have a function of outputting a signal in which the amplitude voltage of the second data is converted to be higher or lower. Specifically, the level conversion circuits 63a to 63d have a function of converting the amplitude voltage of the second data included in the digital image data supplied from the level conversion circuit 43 to an amplitude voltage at which the switches 49a to 49d appropriately operate. For example, in the switches 49a to 49d, the level conversion circuits 63a to 63d have a function of converting the amplitude voltage of the second data so that only the switch 49a is turned on when the value of the second data is "00" expressed in binary, only the switch 49b is turned on when the value of the second data is "01", only the switch 49c is turned on when the value of the second data is "10", and only the switch 49d is turned on when the value of the second data is "11".

[0125] The other terminal of the switch 49a can be applied with a potential V M , for example. Further, the other terminal of the switch 49b can be applied with a potential V ML , for example. In addition, the other terminal of the switch 49c can be applied with a potential V LM , for example. In addition, the other terminal of the switch 49d can be applied with a potential V L , for example. At this time, the potential V S2 may be a potential V M , a potential V ML , a potential V LM , or a potential V L . Note that the potentials can be arranged in order from low to high as the potential V M , the potential V ML , the potential V LM , the potential V L . Here, the difference between the potential V VM and the potential V ML , the difference between the potential V ML and the potential V LM , and the difference between the potential V LM and the potential V L are preferably equal to the difference between the potential V H and the potential V M .

[0126] Figure 7A1 , Figure 7A2 is a graph showing the relationship of the potential V S1 , the potential V S2 , and the digital value of the digital image data input to the source driver circuit 13. In Figure 7A1 , the source driver circuit 13 has the structure shown in Figure 6 , the potential V S2 is applied when the value of the second data is "00" expressed in binary.Potential V M When the value of the second data is "01", the potential V S2 Potential V ML When the value of the second data is "10", the potential V S2 Potential V LM When the value of the second data is "11", the potential V S2 Potential V L On the other hand, in Figure 7A2 In the middle, regardless of the value of the second data, the potential V S2 Both are potentials V M .

[0127] like Figure 7A1 As shown, by increasing the number of bits in the second data, even the potential V S1 The maximum value of the available potential V H Potential V at the minimum value M If the difference is small, the potential V can also be increased. S1 With potential V S2 The maximum potential of the difference "V" H -V L Therefore, even if the potential V H The smaller size allows for a higher voltage to be applied to the display device 26. Therefore, even when a high voltage is applied to the display device 26, the power consumption of the display device 10 can be reduced. Furthermore, the amplifier circuit 46 does not need to have high voltage withstand capability, thus enabling miniaturization and cost reduction of the display device 10.

[0128] Figure 7B This is a graph showing the relationship between the potential difference between wiring 31 and wiring 32 in the first and second modes and the digital values ​​of the digital image data input to the source driver circuit 13. Figure 3B Similarly, as shown, the potential difference between wiring 31 and wiring 32 in the first mode is a potential "V". S1 -V S2 In the second mode, the potential is "-(V)". S1 -V S2 Therefore, by switching between the first mode and the second mode, the voltage applied to the display device 26 is reversed, thereby enabling frame inversion drive, etc.

[0129] <1-5. Example 1 of pixel structure>

[0130] The following is an example of the structure of pixel 11. Figure 8is a diagram illustrating a pixel 11a which can be used as the pixel 11. The pixel 11a includes a transistor 21, a transistor 22, a capacitor 25, and a display element 26. Here, as the transistor 21 and the transistor 22, for example, a CMOS transistor, an n-channel transistor, or a p-channel transistor can be used. Hereinafter, a case where an n-channel transistor is used as the transistor 21 and the transistor 22 is described, and the following description can be referred to when another transistor is used.

[0131] One of a source and a drain of the transistor 21 is electrically connected to one electrode of the capacitor 25. One electrode of the capacitor 25 is electrically connected to one electrode of the display element 26. One of a source and a drain of the transistor 22 is electrically connected to the other electrode of the capacitor 25. The other electrode of the capacitor 25 is electrically connected to the other electrode of the display element 26.

[0132] Here, a wiring connecting one of the source and the drain of the transistor 21, one electrode of the capacitor 25, and one electrode of the display element 26 is referred to as a node N1. Further, a connection portion of a wiring connecting one of the source and the drain of the transistor 22, the other electrode of the capacitor 25, and the other electrode of the display element 26 is referred to as a node N2.

[0133] The other of the source and the drain of the transistor 21 is electrically connected to a wiring 31. The other of the source and the drain of the transistor 22 is electrically connected to a wiring 32. The gate of the transistor 21 and the gate of the transistor 22 are electrically connected to a wiring 33.

[0134] The transistor 21 has a function of supplying a potential of the wiring 31 to the pixel 11a. The transistor 22 has a function of supplying a potential of the wiring 32 to the pixel 11a.

[0135] The potential of the wiring 31 is held in the node N1. The potential of the wiring 32 is held in the node N2. Thus, by using transistors with extremely low off-state current as the transistor 21 and the transistor 22, the potentials of the node N1 and the node N2 can be held for a long time. As the transistors, for example, OS transistors can be used.

[0136] Note that Si transistors can be used as the transistor 21 and the transistor 22. Alternatively, an OS transistor can be used as one of the transistor 21 and the transistor 22 and a Si transistor can be used as the other.

[0137] Next, a description is given with reference to Figure 9The timing diagram shown illustrates an example of how pixel 11a operates. Here, times T11 to T13 and times T14 to T16 can both be one frame period. Note that transistors 21 and 22 are turned on by setting the potential of wiring 33 to potential VDD, but it is not necessary to set the potential of wiring 33 to potential VDD as long as transistors 21 and 22 can be turned on. Furthermore, transistors 21 and 22 are de-conducted by setting the potential of wiring 33 to potential VSS, but it is not necessary to set the potential of wiring 33 to potential VSS as long as transistors 21 and 22 can be de-conducted.

[0138] At time T11, the potential of wiring 33 is set to potential VDD, causing transistors 21 and 22 to conduct. Then, at time T12, the potential of wiring 31 is set to potential VDD. S1 Set the potential of wiring 32 to potential V. S2 This causes nodes N1 and N2 to be written with potential V respectively. S1 and potential V S2 Therefore, the display device 26 performs a response corresponding to the potential V. S1 and potential V S2 The display. Note that in Figure 9 In the middle, potential V S2 Potential V M .

[0139] At time T13, the potential of wiring 33 is set to potential VSS, making transistors 21 and 22 non-conducting, thereby keeping nodes N1 and N2 at potential V. S1 and potential V S2 Therefore, during time T12 to time T13, the display device 10 can operate in the first mode.

[0140] At time T14, the potential of wiring 33 is set to potential VDD, causing transistors 21 and 22 to conduct. Then, at time T15, the potential of wiring 31 is set to potential VDD. S2 And set the potential of wiring 32 to potential V. S1 The voltage applied to the display device 26 is reversed. This enables frame inversion driving, etc.

[0141] At time T16, the potential of wiring 33 is set to potential VSS, making transistors 21 and 22 non-conductive, thereby maintaining the potentials VSS at nodes N1 and N2 respectively. S2 and potential V S1 Therefore, during time T15 to time T16, the display device 10 can operate in the second mode. The above is an example of the operation method of pixel 11a.

[0142] <1-6. Structure Example 2 of Pixel>

[0143] Figure 10 is a diagram illustrating a pixel 11b that can be used as the pixel 11. The pixel 11b is a modification example of the pixel 11a, and is different from the pixel 11a in that a transistor 23 is provided. Here, as the transistor 23, for example, a CMOS transistor, an n-channel transistor, or a p-channel transistor can be used. The following describes a case where an n-channel transistor is used as the transistor 23, and the following description can be referred to when another transistor is used.

[0144] One of a source and a drain of the transistor 23 is electrically connected to the node N2. The other of the source and the drain of the transistor 23 is electrically connected to a wiring 35. A gate of the transistor 23 is electrically connected to a wiring 34.

[0145] The wiring 35 functions as a common wiring. That is, the other of the source and the drain of the transistor 23 in all the pixels 11b included in the display device 10 can be electrically connected to each other by one wiring 35, for example. The wiring 35 can be supplied with a constant potential, and for example, can be supplied with a ground potential or a potential V M Further, the wiring 34 functions as a scan line that controls the transistor 23.

[0146] As with the pixel 11a, the node N2 holds the potential of the wiring 32. As the transistor 23, a transistor having a low off-state current, such as an OS transistor, which is the same as the transistor 22, is used. The transistor 23 can also use a Si transistor.

[0147] Next, one example of an operation method of the pixel 11b is described with reference to a timing chart illustrated in FIG. 18. Figure 11 M Further, the period from time T21 to time T25 and the period from time T26 to time T30 can be one frame period. Note that the potential of the wiring 34 is set to the potential VDD to make the transistor 23 conductive, but the potential of the wiring 34 does not necessarily need to be set to the potential VDD as long as the transistor 23 can be made conductive. Further, the potential of the wiring 34 is set to the potential VSS to make the transistor 23 non-conductive, but the potential of the wiring 34 does not necessarily need to be set to the potential VSS as long as the transistor 23 can be made non-conductive.

[0148] The potential of the wiring 34 is set to the potential VSS at time T21, the potential of the wiring 33 is set to the potential VDD at time T22, and the potential of the wiring 31 is set to the potential V S1 The potential of the wiring 32 is set to the potential V S2 ​As a result, transistors 21 and 22 are turned on, causing nodes N1 and N2 to be written with potential V respectively. S1 and potential V S2 Therefore, the display device 26 performs a response corresponding to the potential V. S1 and potential V S2 The display. Note that in Figure 11 In the middle, potential V S2 Potential V L .

[0149] At time T24, the potential of wiring 33 is set to potential VSS, making transistors 21 and 22 non-conductive, thereby keeping nodes N1 and N2 at potential V. S1 and potential V S2 Therefore, during time T23 to time T24, the display device 10 can operate in the first mode.

[0150] At time T25, the potential of wiring 34 is set to potential VDD, causing transistor 23 to conduct, thus making the potential of node N2 become potential V. M In other words, the potential of node N2 rises by "V". M -V S2 Therefore, when the capacitive coupling coefficient of node N1 is 1, the potential of node N1 also increases by "V". M -V S2 ", to become "V" S1 +V M -V S2 In other words, the voltage applied to the display device 26 remains constant. Here, sometimes the potential "V" S1 +V M -V S2 "Greater than potential V" H Note that in the following description, the capacitive coupling coefficient of node N1 is 1.

[0151] At time T26, the potential of wiring 34 is set to potential VSS; at time T27, the potential of wiring 33 is set to potential VDD; and at time T28, the potential of wiring 31 is set to potential V. S2 Set the potential of wiring 32 to potential V. S1 As a result, transistors 21 and 22 are turned on, and the voltage applied to the display device 26 is reversed. This enables frame inversion driving, etc.

[0152] At time T29, the potential of wiring 33 is set to potential VSS, making transistors 21 and 22 non-conductive, thereby maintaining the potentials VSS at nodes N1 and N2 respectively. S2 and potential V S1Therefore, during time T28 to time T29, the display device 10 can operate in the second mode.

[0153] At time T30, the potential of wiring 34 is set to potential VDD, causing transistor 23 to conduct, thus making the potential of node N2 become potential VDD. M In other words, the potential of node N2 rises by "V". M -V S1 ", that is, the descent of "V" S1 -V M Therefore, the potential of node N1 also increases by "V". M -V S1 ", that is, the descent of "V" S1 -V M ", becomes the potential "V" S2 +V M -V S1 Therefore, the voltage applied to the display device 26 remains unchanged. Here, sometimes the potential "V" S2 +V M -V S1 "less than the potential V" L The above is an example of how pixel 11b works.

[0154] like Figure 11 As shown, a potential V is written to node N1. S1 and potential V S2 One of them, and node N2 is written with potential V S1 and potential V S2 After that, the potential of node N2 is set to potential V. M The potential of node N2 can be set to potential V. M With the voltage applied to the display device 26 remaining constant before and after, the potential of node N2 is set to potential V. M Therefore, fluctuations in the voltage applied to the display device 26 due to electrical noise generated by wiring 31 to wiring 34 can be suppressed. This improves the display quality of the image displayed on the display device 10.

[0155] <1-7. Example 3 of pixel structure>

[0156] Figure 12A This is a diagram illustrating which pixel 11c can be used as pixel 11. Figure 12Bis a diagram illustrating a pixel 11d which can be used as the pixel 11. The pixel 11c has a structure in which the transistor 21 and the transistor 22 provided in the pixel 11a have a back gate. The pixel 11d has a structure in which the transistors 21 to 23 provided in the pixel 11b have a back gate. The back gate can be electrically connected to a front gate of the transistor having the back gate, which has an effect of increasing on-state current. Further, a different potential from the front gate can be supplied to the back gate. By employing this structure, the threshold voltage of the transistor can be controlled. Although a structure in which all the transistors have a back gate is shown in Figure 12A and Figure 12B , a transistor without a back gate can be used.

[0157] <1-8. Structure Example 4 of Pixel>

[0158] Figure 13A is a diagram illustrating a pixel 11e which can be used as the pixel 11. The pixel 11e has a structure in which another electrode in the display element 26 provided in the pixel 11b is not connected to the node N2. In the pixel 11e, another electrode in the display element 26 can be electrically connected to a wiring 36 which is used as a common wiring. Here, the wiring 36 can be supplied with a constant potential. The wiring 36 can be supplied with, for example, the same potential as that supplied to the wiring 35. The wiring 36 can be supplied with, for example, a ground potential or a potential V M Note that the pixel 11e can operate in the same manner as that shown in Figure 11

[0159] Figure 13B is a diagram illustrating a pixel 11f which can be used as the pixel 11. The pixel 11f has a structure in which the transistors 21 to 23 provided in the pixel 11e have a back gate. Note that although a structure in which all the transistors are provided with a back gate is shown in Figure 13B , a transistor without a back gate can be included.

[0160] <1-9. Structure Example 5 of Display Device>

[0161] Figure 14 is a cross-sectional view illustrating a structure example of the display device 10, and illustrates a case where the display device 10 is a transmissive liquid crystal display device to which a horizontal electric field mode is applied.

[0162] Figure 14 Structure examples of the pixel array 14 and the circuit 15 are illustrated. The circuit 15 can be the gate driver circuit 12 or the source driver circuit 13, or the like.

[0163] ​The display device 10 has a structure in which the substrates 111 and 113 are bonded. In the pixel array 14, the transistor 21, the capacitor 25, and the display element 26 are provided over the substrate 111. In the circuit 15, the transistor 24 is provided over the substrate 111. Further, the colored layer 131 and the light-blocking layer 132 are provided over the substrate 113.

[0164] The transistor 21 includes a conductive layer 221 which is used as a gate electrode, an insulating layer 211 which is used as a gate insulating layer, a semiconductor layer 231, a conductive layer 222a and a conductive layer 222b which are used as source and drain electrodes. Further, the capacitor 25 includes the conductive layer 224 and the conductive layer 222a which are used as electrodes, and the insulating layer 211 which is used as a dielectric layer. The transistor 21, the transistor 24, and the capacitor 25 are covered with an insulating layer 212 and an insulating layer 217. Further, the insulating layer 215 which is used as an interlayer insulating layer is provided between the transistor 21, the transistor 24, and the capacitor 25 and the display element 26.

[0165] The semiconductor layer 231 can include a metal oxide. In this case, the transistor 21 is an OS transistor. Further, other transistors provided over the substrate 111, such as the transistor 24, can have the same structure as the transistor 21.

[0166] The display element 26 is a liquid crystal element to which a horizontal electric field mode, specifically, a fringe field switching (FFS) mode is applied. The display element 26 includes an electrode 181, an electrode 182, and a liquid crystal layer 183. The alignment of the liquid crystal layer 183 can be controlled by an electric field generated between the electrode 181 and the electrode 182. The liquid crystal layer 183 is positioned over the insulating layer 220 and the electrode 182. The electrode 181 is electrically connected to the conductive layer 222a through an opening provided in the insulating layer 215, the insulating layer 217, and the insulating layer 212. The electrode 182 is electrically connected to the conductive layer 224 through an opening provided in the insulating layer 215, the insulating layer 217, the insulating layer 212, and the insulating layer 211. Further, the electrode 182 can have a comb-like top surface shape (also referred to as a planar shape) or a top surface shape in which slits are formed. One or plural openings can be formed in the electrode 182.

[0167] The insulating layer 220 is provided between the electrode 181 and the electrode 182. The electrode 181 has a portion overlapping with the electrode 182 with the insulating layer 220 interposed therebetween. Further, in a region where the electrode 181 overlaps with the colored layer 131, there is a portion where the electrode 182 is not provided over the electrode 181.

[0168] Light from the backlight unit 552 is emitted to the outside of the display device through the substrate 111, the electrode 181, the electrode 182, the liquid crystal layer 183, the colored layer 131, and the substrate 113. As a material of these layers which transmit light from the backlight unit 552, a material which transmits visible light is used.

[0169] Here, by being a backlight unit 552, a backlight unit that supplies light of each color of red, green, blue, and the like in sequence using a field sequential system can be used, and color display can be performed by the display device 10 without forming the coloring layer 131. Note that white display can be performed when light of all colors is supplied at the same time.

[0170] It is preferable that a cover layer 121 be provided between the coloring layer 131 and the light-blocking layer 132 and the liquid crystal layer 183. The cover layer 121 can suppress diffusion of impurities included in the coloring layer 131 and the light-blocking layer 132 and the like into the liquid crystal layer 183.

[0171] The substrate 111 and the substrate 113 are attached with the adhesive layer 141. The liquid crystal layer 183 is sealed in a region surrounded by the substrate 111, the substrate 113, and the adhesive layer 141.

[0172] The polarizing plate 125a and the polarizing plate 125b are arranged so as to sandwich the pixel array 14 and the circuit 15 and the like of the display device. Light from the backlight unit 552 located on the outer side of the polarizing plate 125a is incident on the display device 10 through the polarizing plate 125a. At this time, the orientation of the liquid crystal layer 183 can be controlled by a voltage applied between the electrode 181 and the electrode 182, and the optical modulation of light can be controlled. That is, the intensity of light emitted from the display device 10 through the polarizing plate 125b can be controlled. Furthermore, since light other than a specific wavelength region of light incident on the display element 26 is absorbed by the coloring layer 131, light emitted from the display device 10 becomes light that appears red, blue, or green, for example. Note that the polarizing plate 125a and the polarizing plate 125b can not be provided.

[0173] The conductive layer 565 is electrically connected to the FPC 162 through the conductive layer 255 and the connector 242.

[0174] By using a liquid crystal element to which a horizontal electric field system is applied as the display element 26, both the electrode 181 used as one electrode in the display element 26 and the electrode 182 used as the other electrode in the display element 26 can be formed on one surface in the liquid crystal layer 183. Thus, both the electrode 181 and the electrode 182 can be electrically connected to the electrode included in the capacitor 25.

[0175] As the liquid crystal used for the liquid crystal element, a liquid crystal that exhibits a blue phase can be used. In this case, it is preferable to apply a high voltage to the display element 26. Since the display device 10 can apply a high voltage to the display element 26, the display device 10 can operate normally even when a liquid crystal that exhibits a blue phase is used as the display element 26.

[0176] The blue phase is one of liquid crystal phases, and refers to a phase that appears just before a cholesteric liquid crystal is changed from a cholesteric phase to a homogeneous phase when the temperature of the cholesteric liquid crystal is increased. Since the blue phase appears only within a narrow temperature range, a liquid crystal composition in which several wt% or more of a chiral agent is mixed with a liquid crystal is used for a liquid crystal in order to expand the temperature range. Since a liquid crystal composition including a liquid crystal exhibiting a blue phase and a chiral agent has a fast response speed and has optical isotropy. Furthermore, a liquid crystal composition including a liquid crystal exhibiting a blue phase and a chiral agent does not require an alignment treatment and has a small viewing angle dependence. Furthermore, since an alignment film does not need to be provided and a rubbing treatment is not required, electrostatic breakdown due to the rubbing treatment can be prevented and defects and breakage of a liquid crystal display device in a manufacturing process can be reduced.

[0177] Furthermore, as the liquid crystal used for the liquid crystal device, a liquid crystal other than a blue phase can be used. For example, a thermotropic liquid crystal, a low-molecular liquid crystal, a high-molecular liquid crystal, a high-molecular dispersion type liquid crystal, a ferroelectric liquid crystal, an anti-ferroelectric liquid crystal, or the like can be used. These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, or the like depending on the conditions. Furthermore, as the liquid crystal material, either a positive liquid crystal or a negative liquid crystal can be used. In the case where a liquid crystal other than a liquid crystal exhibiting a blue phase is used as the liquid crystal used for the liquid crystal device, an alignment film is preferably provided in order to control the alignment of the liquid crystal.

[0178] <1-10. Structure Example 6 of Display Device>

[0179] Figure 15 is a cross-sectional view illustrating a structure example of the display device 10, and illustrates a case where the display device 10 is a transmissive liquid crystal display device to which the vertical electric field system is applied. When the pixel 11 provided in the display device is the pixel 11e or the pixel 11f, the electrode 182 included in the display device 26 can not be electrically connected to the electrode included in the capacitor 25. Thus, the electrode 181 included in the display device 26 and the electrode 182 can be provided at positions opposite to each other with the liquid crystal layer 183 interposed therebetween, and thus the display device 10 can be a transmissive liquid crystal display device to which the vertical electric field system is applied. When the display device 10 is a transmissive liquid crystal display device to which the vertical electric field system is applied, a liquid crystal device to which a TN (Twisted Nematic) mode, a VA (Vertical Alignment) mode, an MVA (Multidomain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an OCB (Optically Compensated Bend) mode, or the like is applied can be used as the display device 26.

[0180] Note that, in the case where the display device 10 is a transmissive liquid crystal display device to which the vertical electric field system is applied, the pixel 11 can be the pixel 11e or the pixel 11f.Figure 14 As in the case of the structure shown in FIG. 1, the display device 10 can also be used as a backlight unit 552 that supplies light of each color in a field sequential system.

[0181] This embodiment mode can be implemented in appropriate combination with the structures described in other embodiment modes and the like.

[0182] (Embodiment 2)

[0183] In this embodiment mode, an example of a transistor that can be used instead of each transistor shown in the above embodiment modes is described with reference to drawings.

[0184] The display device of one embodiment of the present application can be manufactured using a transistor of various modes such as a bottom-gate transistor or a top-gate transistor. Thus, the semiconductor layer material or the transistor structure used can be easily replaced in correspondence with an existing production line.

[0185] [Bottom-gate transistor]

[0186] Figure 16A1 A cross-sectional view of a channel length direction of a channel protective transistor 810 which is one of bottom-gate transistors is shown. In this embodiment mode, the transistor 810 is formed over a substrate 771. Further, the transistor 810 includes an electrode 746 over the substrate 771 with an insulating layer 772 interposed therebetween. Further, a semiconductor layer 742 is included over the electrode 746 with an insulating layer 726 interposed therebetween. The electrode 746 can be used as a gate electrode. The insulating layer 726 can be used as a gate insulating layer. Figure 16A1

[0187] Further, an insulating layer 741 is included over a channel formation region of the semiconductor layer 742. Further, an electrode 744a and an electrode 744b are included over the insulating layer 726 so as to be in contact with a part of the semiconductor layer 742. The electrode 744a can be used as one of a source electrode and a drain electrode. The electrode 744b can be used as the other of the source electrode and the drain electrode. A part of the electrode 744a and a part of the electrode 744b are formed over the insulating layer 741.

[0188] The insulating layer 741 can be used as a channel protective layer. By providing the insulating layer 741 over the channel formation region, the semiconductor layer 742 can be prevented from being exposed when the electrode 744a and the electrode 744b are formed. Thus, the channel formation region of the semiconductor layer 742 can be prevented from being etched when the electrode 744a and the electrode 744b are formed. According to one embodiment of the present application, a transistor with favorable electrical characteristics can be implemented.

[0189] Further, the transistor 810 includes an insulating layer 728 over the electrode 744a, the electrode 744b, and the insulating layer 741, and an insulating layer 729 over the insulating layer 728. ​

[0190] When the oxide semiconductor is used for the semiconductor layer 742, a material that can extract oxygen from part of the semiconductor layer 742 to generate an oxygen vacancy is preferably used for at least a portion of the electrode 744a and the electrode 744b in contact with the semiconductor layer 742. The carrier concentration of the region in the semiconductor layer 742 where the oxygen vacancy is generated increases, the region is n-type and becomes an n-type region (n + layer). Thus, the region can be used as a source region or a drain region. When the oxide semiconductor is used for the semiconductor layer 742, as one example of a material that can extract oxygen from the semiconductor layer 742 to generate an oxygen vacancy, tungsten, titanium, or the like can be given.

[0191] By forming a source region and a drain region in the semiconductor layer 742, the contact resistance of the electrode 744a and the electrode 744b to the semiconductor layer 742 can be reduced. Thus, the electric characteristics of the transistor, such as field-effect mobility and threshold voltage, can be favorable.

[0192] When a semiconductor such as silicon is used for the semiconductor layer 742, a layer used as an n-type semiconductor or a p-type semiconductor is preferably provided between the semiconductor layer 742 and the electrode 744a and between the semiconductor layer 742 and the electrode 744b. The layer used as an n-type semiconductor or a p-type semiconductor can be used as a source region or a drain region of the transistor.

[0193] The insulating layer 729 is preferably formed using a material having a function of preventing impurities from diffusing into the transistor from the outside or reducing diffusion of impurities. In addition, the insulating layer 729 can be omitted as necessary.

[0194] Figure 16A2 The transistor 811 illustrated in FIG. 8A is different from the transistor 810 in that an electrode 723 which can be used as a back gate electrode is included over the insulating layer 729. The electrode 723 can be formed using the same material and method as the electrode 746.

[0195] Generally, a back gate electrode is formed using a conductive layer and is provided so that a channel formation region of a semiconductor layer is interposed between the gate electrode and the back gate electrode. Thus, the back gate electrode can have the same function as the gate electrode. The potential of the back gate electrode can be equal to that of the gate electrode, or can be a ground potential (GND potential) or an arbitrary potential. In addition, by independently changing the potential of the back gate electrode without being linked to the gate electrode, the threshold voltage of the transistor can be changed.

[0196] The electrode 746 and the electrode 723 can each be used as a gate electrode. Thus, the insulating layer 726, the insulating layer 728, and the insulating layer 729 can each be used as a gate insulating layer. In addition, the electrode 723 can be provided between the insulating layer 728 and the insulating layer 729.

[0197] Note that when one of the electrode 746 and the electrode 723 is referred to as a "gate electrode", the other is referred to as a "back gate electrode". For example, in the transistor 811, when the electrode 723 is referred to as a "gate electrode", the electrode 746 is referred to as a "back gate electrode". Furthermore, when the electrode 723 is used as a "gate electrode", the transistor 811 is one of top-gate transistors. Furthermore, one of the electrode 746 and the electrode 723 is sometimes referred to as a "first gate electrode", and the other is sometimes referred to as a "second gate electrode".

[0198] By providing the electrode 746 and the electrode 723 so as to sandwich the semiconductor layer 742 and setting the potential of the electrode 746 and the electrode 723 to be the same, a region through which a carrier in the semiconductor layer 742 flows is more expanded in the film thickness direction, so that the amount of migration of the carrier increases. As a result, the on-state current of the transistor 811 increases, and the field-effect mobility is also increased.

[0199] Accordingly, the transistor 811 is a transistor with a high on-state current relative to the size. That is, the size of the transistor 811 can be reduced relative to the on-state current required. According to one embodiment of the present application, the size of a transistor can be reduced. Thus, according to one embodiment of the present application, a display device with high integration can be achieved.

[0200] Further, since the gate electrode and the back gate electrode are formed using a conductive layer, they have a function of preventing an electric field generated outside the transistor from affecting the semiconductor layer in which a channel is formed (particularly, an electric field shielding function against static electricity or the like). Further, when the back gate electrode is provided so as to include a region overlapping with the semiconductor layer, the electric field shielding function can be improved.

[0201] Further, by forming the back gate electrode using a conductive film having a light shielding property, light can be prevented from entering the semiconductor layer from the side of the back gate electrode. Thus, light-induced degradation of the semiconductor layer can be prevented, and the deterioration of the electric characteristics of the transistor such as shift in threshold voltage can be prevented.

[0202] According to one embodiment of the present application, a transistor with high reliability can be achieved. Further, a semiconductor device with high reliability can be achieved.

[0203] Figure 16B1 A display device including a transistor is described. Figure 16A1A cross-sectional view of the channel length direction of a channel-protective transistor 820 of a different structure. The transistor 820 has substantially the same structure as the transistor 810, and differs therefrom in that an insulating layer 741 covers the end portion of the semiconductor layer 742. In an opening portion formed by removing the portion of the insulating layer 741 overlapping with the semiconductor layer 742, the semiconductor layer 742 is electrically connected to the electrode 744a. Further, in another opening portion formed by removing the portion of the insulating layer 741 overlapping with the semiconductor layer 742, the semiconductor layer 742 is electrically connected to the electrode 744b. The region of the insulating layer 741 overlapping with the channel formation region can be used as a channel protective layer.

[0204] Figure 16B2 The transistor 821 shown differs from the transistor 820 in that the electrode 723 which can be used as a back gate electrode is included over the insulating layer 729.

[0205] By providing the insulating layer 741, the exposure of the semiconductor layer 742 at the time of formation of the electrode 744a and the electrode 744b can be prevented. Thus, the semiconductor layer 742 can be prevented from being thinned at the time of formation of the electrode 744a and the electrode 744b.

[0206] Further, the distance between the electrode 744a and the electrode 746 and the distance between the electrode 744b and the electrode 746 are longer in the transistor 820 and the transistor 821 than in the transistor 810 and the transistor 811. Thus, the parasitic capacitance generated between the electrode 744a and the electrode 746 can be reduced. Further, the parasitic capacitance generated between the electrode 744b and the electrode 746 can be reduced. According to one embodiment of the present application, a transistor with good electrical characteristics can be provided.

[0207] Figure 16C1 The transistor 825 shown is a cross-sectional view of the channel length direction of a channel-etching transistor 825 which is one of bottom-gate transistors. In the transistor 825, the electrode 744a and the electrode 744b are formed without using the insulating layer 741. Thus, a portion of the semiconductor layer 742 exposed at the time of formation of the electrode 744a and the electrode 744b is sometimes etched. On the other hand, since the insulating layer 741 is not provided, the productivity of the transistor can be improved.

[0208] Figure 16C2 The transistor 826 shown differs from the transistor 825 in that the electrode 723 which can be used as a back gate electrode is included over the insulating layer 729.

[0209] Figure 17A1 , Figure 17A2 , Figure 17B1 , Figure 17B2 , Figure 17C1 and Figure 17C2A cross-sectional view of the channel width direction of the transistor 810, the transistor 811, the transistor 820, the transistor 821, the transistor 825, and the transistor 826 is shown.

[0210] In Figure 17B2 and Figure 17C2 In the structure shown, the gate electrode and the back gate electrode are connected to each other, whereby the potentials of the gate electrode and the back gate electrode are the same. Further, the semiconductor layer 742 is sandwiched between the gate electrode and the back gate electrode.

[0211] In the channel width direction, the lengths of the gate electrode and the back gate electrode are larger than the semiconductor layer 742, and the semiconductor layer 742 as a whole is covered with the gate electrode or the back gate electrode with the insulating layer 726, the insulating layer 741, the insulating layer 728, and the insulating layer 729 interposed therebetween.

[0212] With this structure, the semiconductor layer 742 included in the transistor can be surrounded by the electric field of the gate electrode and the back gate electrode.

[0213] A device structure of a transistor in which the semiconductor layer 742 forming a channel formation region is surrounded by the electric field of the gate electrode and the back gate electrode, like the transistor 811, the transistor 821, and the transistor 826, can be referred to as a Surrounded channel (S-channel) structure.

[0214] With the S-channel structure, the electric field for causing channel formation can be effectively applied to the semiconductor layer 742 using one or both of the gate electrode and the back gate electrode. Thus, the current drivability of the transistor is improved, so that a higher on-state current characteristic can be obtained. Further, since the on-state current can be increased, the transistor can be miniaturized. Furthermore, with the S-channel structure, the mechanical strength of the transistor can be improved.

[0215] [Top-gate transistor]

[0216] Figure 18A1 The transistor 842 exemplified is one of top-gate transistors. The transistor 842 is formed after the formation of the insulating layer 729, and the electrode 744a and the electrode 744b. The electrode 744a and the electrode 744b are electrically connected to the semiconductor layer 742 in the opening portions formed in the insulating layer 728 and the insulating layer 729.

[0217] Further, a portion of the insulating layer 726 which does not overlap with the electrode 746 is removed, and impurities are introduced into the semiconductor layer 742 using the electrode 746 and the insulating layer 726 remaining after the removal as masks, whereby an impurity region can be formed in the semiconductor layer 742 in a self-alignment manner. The transistor 842 includes a region where the insulating layer 726 extends beyond the end portion of the electrode 746. The impurity concentration of the region of the semiconductor layer 742 into which impurities are introduced through the insulating layer 726 is lower than that of the region of the semiconductor layer 742 into which impurities are not introduced through the insulating layer 726. Thus, an LDD (Lightly Doped Drain) region is formed in the region of the semiconductor layer 742 which does not overlap with the electrode 746.

[0218] Figure 18A2 The transistor 843 illustrated in FIG. 8B differs from the transistor 842 in that the electrode 723 is included. The transistor 843 includes the electrode 723 formed over the substrate 771. The electrode 723 has a region overlapping with the semiconductor layer 742 with the insulating layer 772 interposed therebetween. The electrode 723 can be used as a back gate electrode.

[0219] Further, as in the transistor 844 illustrated in FIG. 8C and the transistor 845 illustrated in FIG. 8D, the insulating layer 726 in the region which does not overlap with the electrode 746 can be completely removed. Further, as in the transistor 846 illustrated in FIG. 8E and the transistor 847 illustrated in FIG. 8F, the insulating layer 726 can not be removed. Figure 18B1 Figure 18B2 Further, as in the transistor 844 illustrated in FIG. 8C and the transistor 845 illustrated in FIG. 8D, the insulating layer 726 in the region which does not overlap with the electrode 746 can be completely removed. Further, as in the transistor 846 illustrated in FIG. 8E and the transistor 847 illustrated in FIG. 8F, the insulating layer 726 can not be removed. Figure 18C1 Figure 18C2 Further, as in the transistor 844 illustrated in FIG. 8C and the transistor 845 illustrated in FIG. 8D, the insulating layer 726 in the region which does not overlap with the electrode 746 can be completely removed. Further, as in the transistor 846 illustrated in FIG. 8E and the transistor 847 illustrated in FIG. 8F, the insulating layer 726 can not be removed.

[0220] In the transistors 842 to 847, impurities can be introduced into the semiconductor layer 742 using the electrode 746 as a mask after the formation of the electrode 746, whereby an impurity region can be formed in the semiconductor layer 742 in a self-alignment manner. According to one embodiment of the present application, a transistor with excellent electric characteristics can be implemented. Further, according to one embodiment of the present application, a semiconductor device with high integration can be implemented.

[0221] Figure 19A1 Figure 19A2 Figure 19B1 Figure 19B2 Figure 19C1 Figure 19C2 Cross-sectional views of the channel width direction of the transistor 842, the transistor 843, the transistor 844, the transistor 845, the transistor 846, and the transistor 847 are each illustrated in FIGS. 8A to 8F.

[0222] The transistor 843, the transistor 845, and the transistor 847 have the S-channel structure described above. However, the transistor 843, the transistor 845, and the transistor 847 are not limited to this structure and can not have the S-channel structure. ​​​​​​​

[0223] This embodiment mode can be implemented in appropriate combination with the structures described in other embodiment modes and the like.

[0224] (Embodiment 3)

[0225] In this embodiment mode, a detailed structure example of an OS transistor is described with reference to the drawings.

[0226] As the semiconductor layer in the OS transistor, for example, a film represented by "In-M-Zn-based oxide" containing indium, zinc, and M (aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium, or the like) can be used.

[0227] When the oxide semiconductor that constitutes the semiconductor layer is an In-M-Zn-based oxide, it is preferable that the atomic ratio of metal elements of a sputtering target used for forming the In-M-Zn-based oxide film satisfy In > M and Zn > M. The atomic ratio of the metal elements of the sputtering target is preferably In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, or the like. Note that the atomic ratio of the semiconductor layer formed can vary within a range of ±40% of the atomic ratio of the metal elements of the sputtering target.

[0228] As the semiconductor layer, an oxide semiconductor with low carrier density can be used. For example, as the semiconductor layer, an oxide semiconductor with a carrier density of 1 x 10 17 / cm 3 Hereinafter, it is preferable that the carrier density be 1 x 10 15 / cm 3 Hereinafter, it is more preferable that the carrier density be 1 x 10 13 / cm 3 Hereinafter, it is further preferable that the carrier density be 1 x 10 11 / cm 3 Hereinafter, it is still further preferable that the carrier density be less than 1 x 10 10 / cm 3 , 1 x 10 -9 / cm 3 The above oxide semiconductor. Such an oxide semiconductor is referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. The oxide semiconductor has a low density of defect states and thus can be said to be an oxide semiconductor with stable characteristics.

[0229] Note that the present application is not limited to the above description, and a material with an appropriate composition can be used depending on the semiconductor properties and the electrical properties (field-effect mobility, threshold voltage, etc.) of the transistor required. Further, the carrier density, the impurity concentration, the defect density, the atomic ratio of a metal element to oxygen, the interatomic distance, the density, and the like of the semiconductor layer are preferably set as appropriate so that the transistor has the desired semiconductor properties.

[0230] When the oxide semiconductor that forms the semiconductor layer contains silicon or carbon, which is one of Group 14 elements, the number of oxygen vacancies increases, which makes the semiconductor layer n-type. Thus, the concentration of silicon or carbon in the semiconductor layer (the concentration measured by secondary ion mass spectrometry) is set to be lower than or equal to 2 x 10 18 atoms / cm 3 In the following, the concentration is preferably lower than or equal to 2 x 10 17 atoms / cm 3 In the following, the concentration is preferably lower than or equal to 2 x 10

[0231] Further, when an alkali metal or an alkaline earth metal is bonded to the oxide semiconductor, a carrier is sometimes generated, which increases the off-state current of the transistor. Thus, the concentration of an alkali metal or an alkaline earth metal in the semiconductor layer (the concentration measured by secondary ion mass spectrometry) is set to be lower than or equal to 1 x 10 18 atoms / cm 3 In the following, the concentration is preferably lower than or equal to 2 x 10 16 atoms / cm 3 In the following, the concentration is preferably lower than or equal to 2 x 10

[0232] Further, when the oxide semiconductor that forms the semiconductor layer contains nitrogen, electrons serving as carriers are generated, the carrier density increases, and n-type properties are easily obtained. As a result, a transistor using an oxide semiconductor containing nitrogen easily has normally-on characteristics. Thus, the concentration of nitrogen in the semiconductor layer (the concentration measured by secondary ion mass spectrometry) is preferably lower than or equal to 5 x 10 18 atoms / cm 3 In the following, the concentration is preferably lower than or equal to 2 x 10

[0233] Further, the semiconductor layer can have a non-single-crystal structure, for example. The non-single-crystal structure includes a c-axis aligned crystalline oxide semiconductor (CAAC-OS) having a crystal with a c-axis aligned in a direction parallel to a normal line of a surface, a polycrystal structure, a microcrystal structure, or an amorphous structure, for example. In the non-single-crystal structure, an amorphous structure has the highest density of defect states, whereas a CAAC-OS has the lowest density of defect states.

[0234] An oxide semiconductor film of an amorphous structure has, for example, an atomic arrangement that is not ordered and does not have a crystal component. Alternatively, an oxide film of an amorphous structure is, for example, completely amorphous and does not have a crystal portion.

[0235] Further, the semiconductor layer can also be a mixed film of two or more of a region having an amorphous structure, a region having a microcrystalline structure, a region having a polycrystalline structure, a region having a CAAC-OS, and a region having a single crystal structure. The mixed film has, for example, a single-layer structure or a stacked-layer structure including two or more of the above regions.

[0236] The configuration of one embodiment of a CAC-OS of a non-single-crystal semiconductor layer will be described below.

[0237] The CAC-OS refers to a configuration in which elements are unevenly distributed in an oxide semiconductor, for example, and the size of a material containing the elements unevenly distributed is greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 1 nm and less than or equal to 2 nm or a size close thereto. Note that in the following, a state in which one or a plurality of metal elements are unevenly distributed in an oxide semiconductor and a region containing the metal elements is mixed in a size greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 1 nm and less than or equal to 2 nm or a size close thereto, is referred to as a mosaic or patch-like state.

[0238] The oxide semiconductor preferably contains at least indium. In particular, indium and zinc are preferably contained. In addition to the above, one or more selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium, and the like can be further contained.

[0239] For example, the CAC-OS in an In-Ga-Zn oxide (in the CAC-OS, the In-Ga-Zn oxide can be referred to as CAC-IGZO, in particular) refers to a configuration in which a material is divided into an indium oxide (hereinafter referred to as InO X1 (X1 is a real number greater than 0) or an indium zinc oxide (hereinafter referred to as In X2 Zn Y2 O Z2 (X2, Y2, and Z2 are real numbers greater than 0) and a gallium oxide (hereinafter referred to as GaO X3 (X3 is a real number greater than 0) or a gallium zinc oxide (hereinafter referred to as Ga X4 Zn Y4 O Z4 (X4, Y4, and Z4 are real numbers greater than 0) and the like, and the InO X1 or In X2 Zn Y2 O Z2 are uniformly distributed in the film (hereinafter, also referred to as cloud-like).

[0240] In other words, the CAC-OS is a configuration having a region in which GaO X3 is a main component and a region in which In X2 ZnY2 O Z2 or InO X1 The composite oxide semiconductor is configured with the regions in which In is the main component mixed together. In this specification, for example, when the atomic ratio of In to the element M in the first region is higher than the atomic ratio of In to the element M in the second region, the In concentration in the first region is higher than that in the second region.

[0241] Note that IGZO is a general term, and sometimes refers to a compound containing In, Ga, Zn, and O. As a typical example, InGaO3(ZnO) m1 (m1 is a natural number) or In (1+x0) Ga (1-x0) O3(ZnO) m0 (-1 ≤ x0 ≤ 1, m0 is an arbitrary number) indicates a crystalline compound.

[0242] The above crystalline compound has a single crystal structure, a polycrystal structure, or a CAAC structure. The CAAC structure is a crystalline structure in which a plurality of IGZO nanocrystals have c-axis alignment and are connected in an unaligned manner in a-b planes.

[0243] On the other hand, CAC-OS is related to the material composition of an oxide semiconductor. CAC-OS refers to a structure in which, in a material composition containing In, Ga, Zn, and O, a region in which Ga is the main component and a region in which In is the main component are observed in some parts and are irregularly dispersed in a mosaic pattern, respectively. Thus, in CAC-OS, the crystalline structure is a secondary factor.

[0244] CAC-OS does not include a stacked structure of two or more films having different compositions. For example, it does not include a structure of two layers of a film in which In is the main component and a film in which Ga is the main component.

[0245] Note that a clear boundary between a region in which GaO X3 is the main component and a region in which In X2 Zn Y2 O Z2 or InO X1 is the main component is not observed.

[0246] In the case where one or more kinds selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium are included in CAC-OS instead of gallium, CAC-OS refers to a structure in which a region in which the metal element is the main component and a region in which In is the main component are observed in some parts and are irregularly dispersed in a mosaic pattern.

[0247] The CAC-OS can be formed, for example, by a sputtering method under conditions in which no intentional heating is performed on a substrate. In the case where the CAC-OS is formed by a sputtering method, as a film formation gas, one or more selected from among an inert gas (typically, argon), an oxygen gas, and a nitrogen gas can be used. Further, it is more preferable that the flow rate ratio of the oxygen gas in the total flow rate of the film formation gas at the time of film formation be lower, for example, the flow rate ratio of the oxygen gas is set to 0% or more and less than 30%, and preferably 0% or more and 10% or less.

[0248] The CAC-OS has a characteristic that, when measured by the Out-of-plane method, one of the X-ray diffraction (XRD) measurement methods, using a θ / 2θ scan, no clear peak is observed. That is, according to the X-ray diffraction measurement, it is known that there is no orientation in the a-b plane direction and the c-axis direction in the measurement region.

[0249] Further, in the electron diffraction pattern of the CAC-OS obtained by irradiation of an electron beam (also referred to as a nanobeam) having a beam diameter of 1 nm, a ring-shaped region having high brightness (ring-shaped region) and a plurality of bright spots within the ring-shaped region are observed. From this, according to the electron diffraction pattern, it is known that the crystal structure of the CAC-OS has an nc (nano-crystal) structure in which there is no orientation in the planar direction and the cross-sectional direction.

[0250] Further, for example, in the CAC-OS of an In-Ga-Zn oxide, from an EDX mapping obtained by an energy dispersive X-ray spectroscopy (EDX), it is confirmed that a region having GaO X3 as a main component and a region having In X2 Zn Y2 O Z2 or InO X1 as a main component are unevenly distributed and mixed.

[0251] The structure of the CAC-OS is different from that of the IGZO compound in which metal elements are uniformly distributed, and has a property different from that of the IGZO compound. In other words, the CAC-OS has a structure in which a region having GaO X3 as a main component and a region having In X2 Zn Y2 O Z2 or InO X1 as a main component are separated from each other and the regions having each element as a main component are in a mosaic pattern.

[0252] Here, a region having In X2Zn Y2 O Z2 or InO X1 regions in which GaO X3 or the like is the main component. In other words, when a carrier flows through a region in which In X2 Zn Y2 O Z2 or InO X1 is the main component, the conductivity of the oxide semiconductor is exhibited. Thus, when a region in which In X2 Zn Y2 O Z2 or InO X1 is the main component is distributed in the oxide semiconductor, high field-effect mobility (μ) can be achieved.

[0253] On the other hand, the insulating property of a region in which GaO X3 or the like is the main component is higher than that of a region in which In X2 Zn Y2 O Z2 or InO X1 is the main component. In other words, when a region in which GaO X3 or the like is distributed in the oxide semiconductor, leakage current can be suppressed and good switching operation can be achieved.

[0254] Thus, when CAC-OS is used for a semiconductor device, high on-state current (I X3 ) and high field-effect mobility (μ) can be achieved by the complementary action of the insulating property of GaO X2 Zn Y2 O Z2 or InO X1 . on

[0255] Further, a semiconductor device using CAC-OS has high reliability. Thus, CAC-OS is suitable for a material for constituting various semiconductor devices.

[0256] This embodiment mode can be implemented in appropriate combination with the structures described in other embodiment modes and the like.

[0257] (Embodiment 4)

[0258] In this embodiment mode, an electronic device of one embodiment of the present application is described with reference to FIG. 20.

[0259] The electronic device of this embodiment mode includes a display device of one embodiment of the present application. Thus, an inexpensive electronic device can be achieved.

[0260] ​The display portion of the electronic device in this embodiment mode can display an image with a resolution of full high definition, 2K, 4K, 8K, 16K, or more, for example. Further, the screen size of the display portion can be a diagonal size of 20 inches or more, 30 inches or more, 50 inches or more, 60 inches or more, or 70 inches or more.

[0261] As the electronic device, for example, a television device, a desktop or notebook personal computer, a display for a computer or the like, a digital signboard, an electronic device with a large screen such as a large game machine (a pinball machine or the like), a digital camera, a digital video camera, a digital photo frame, a mobile phone, a portable game console, a portable information terminal, and a sound reproduction device can be given.

[0262] The electronic device of one embodiment of the present application can also include an antenna. By receiving a signal with the antenna, the electronic device can display an image or information on the display portion, or the like. When the electronic device includes an antenna and a secondary battery, the antenna can be used for non-contact power transfer.

[0263] The electronic device of one embodiment of the present application can also include a sensor (which has a function of measuring a factor such as force, displacement, position, velocity, acceleration, angular velocity, rotational frequency, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electric power, radiation, flow rate, humidity, inclination, vibration, odor, or infrared rays).

[0264] The electronic device of one embodiment of the present application can have various functions such as a function of displaying various information (a still image, a moving image, a text image, or the like) on the display portion; a function of a touch panel; a function of displaying a calendar, a date, or a time; a function of executing various kinds of software (programs); a function of performing wireless communication; a function of reading a program or data stored in a storage medium; and the like.

[0265] Figure 20A An example of a television device is shown. In the television device 7100, a housing 7101 is assembled with a display portion 7000. Further, in this case, the housing 7101 is supported with a stand 7103.

[0266] The display device of one embodiment of the present application can be used in the display portion 7000.

[0267] The display portion 7000 can be controlled by operating a switch provided in the housing 7101 or a remote control 7111. Figure 20AThe television device 7100 shown is operated. In addition, the display portion 7000 can have a touch sensor. The television device 7100 can be operated by touch of the display portion 7000 with a finger or the like. Furthermore, a display portion which displays data output from the remote control device 7111 can be provided in the remote control device 7111. By operating the operation keys or the touch panel of the remote control device 7111, the channel and the volume can be operated, and an image displayed on the display portion 7000 can be operated.

[0268] In addition, the television device 7100 includes a receiver and a modem or the like. General television broadcasting can be received by the receiver. Furthermore, when the television device is connected to a communication network by the modem, unidirectional (from a sender to a receiver) or bidirectional (between senders, between receivers, or the like) communication can be performed.

[0269] Figure 20B An example of a notebook personal computer is shown. The notebook personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, and the like. The display portion 7000 is incorporated in the housing 7211.

[0270] The display device of one embodiment of the present application can be used for the display portion 7000.

[0271] Figure 20C 、 Figure 20D An example of a digital sign is shown.

[0272] Figure 20C The digital sign 7300 shown includes a housing 7301, the display portion 7000, and a speaker 7303, and the like. In addition, the digital sign can include an LED lamp, an operation key (including a power source switch or an operation switch), a connection terminal, various sensors, a microphone, and the like.

[0273] Figure 20D A digital sign 7400 installed on a cylindrical column 7401 is shown. The digital sign 7400 includes the display portion 7000 provided along the curved surface of the column 7401.

[0274] The display device of one embodiment of the present application can be used for each of the display portions 7000 shown in FIGS. 1A to 1C. Figure 20C and Figure 20D The display device of one embodiment of the present application can be used for each of the display portions 7000 shown in FIGS. 1A to 1C.

[0275] The larger the area of the display portion 7000 is, the more information can be provided at a time. Furthermore, the larger the display portion 7000 is, the more likely it is to attract attention, and thus the effect of advertisement can be improved, for example.

[0276] By using the touch panel for the display portion 7000, not only a still image or a moving image can be displayed, but also a user can intuitively perform an operation, and thus it is preferable. Further, in a use for providing information such as route information or traffic information, the ease of use can be improved by intuitive operation.

[0277] Further, as illustrated in FIGS. 27A and 27B, the digital sign 7300 or the digital sign 7400 can be linked to an information terminal 7311 or an information terminal 7411 carried by a user through wireless communication. For example, information of an advertisement displayed on the display portion 7000 can be displayed on a screen of the information terminal 7311 or the information terminal 7411. Further, by operating the information terminal 7311 or the information terminal 7411, display of the display portion 7000 can be switched. Figure 20C Figure 20D Further, the digital sign 7300 or the digital sign 7400 can use the screen of the information terminal 7311 or the information terminal 7411 as an operation unit (controller) to execute a game. Thus, a plurality of users can participate in the game at the same time, and enjoy the game.

[0278] Further, the digital sign 7300 or the digital sign 7400 can use the screen of the information terminal 7311 or the information terminal 7411 as an operation unit (controller) to execute a game. Thus, a plurality of users can participate in the game at the same time, and enjoy the game.

[0279] The display system of one embodiment of the present application can be assembled along a curved surface of an inner wall or an outer wall of a house or a high-rise building, an interior or an exterior of a vehicle.

[0280] This embodiment can be implemented in appropriate combination with the structures described in other embodiments and the like.

[0281] [Explanation of Symbols]

[0282] ​10: display device, 11: pixel, 11a: pixel, 11b: pixel, 11c: pixel, 11d: pixel, 11e: pixel, 11f: pixel, 12: gate driver circuit, 13: source driver circuit, 14: pixel array, 15: circuit, 16: switching circuit, 21: transistor, 22: transistor, 23: transistor, 24: transistor, 25: capacitor, 26: display device, 31: wiring, 32: wiring, 33: wiring, 34: wiring, 35: wiring, 36: wiring, 41: shift register, 42: latch circuit, 43: level shift circuit, 44: DA conversion circuit, 46: amplifier circuit, 48a: switch, 48b: switch, 49a: switch, 49b: switch, 49c: switch, 49d: switch, 51: data bus wiring, 61: image data generation circuit, 62: image processing circuit, 63: level shift circuit, 63a: level shift circuit, 63b: level shift circuit, 63c: level shift circuit, 63d: level shift circuit, 64: inverter circuit, 65: selection circuit, 68a: transistor, 68b: transistor, 70: potential generation circuit, 71: transistor, 72: capacitor, 81: wiring, 111: substrate, 113: substrate, 121: cover layer, 125a: polarizing plate, 125b: polarizing plate, 131: colored layer, 132: light-blocking layer, 141: adhesive layer, 162: FPC, 181: electrode, 182: electrode, 183: liquid crystal layer, 211: insulating layer, 212: insulating layer, 215: insulating layer, 217: insulating layer, 220: insulating layer, 221: conductive layer, 222a: conductive layer, 222b: conductive layer, 224: conductive layer, 231: semiconductor layer, 242: connecting body, 255: conductive layer, 552: backlight unit, 565: conductive layer, 723: electrode, 726: insulating layer, 728: insulating layer, 729: insulating layer, 741: insulating layer, 742: semiconductor layer, 744a: electrode, 744b: electrode, 746: electrode, 771: substrate, 772: insulating layer, 810: transistor, 811: transistor, 820: transistor, 821: transistor, 825: transistor, 826: transistor, 842: transistor, 843: transistor, 844: transistor, 845: transistor, 846: transistor, 847: transistor, 7000: display portion, 7100: television device, 7101: housing, 7103: stand, 7111: remote controller, 7200: notebook personal computer, 7211: housing, 7212: keyboard, 7213: pointing device, 7214: external connection port, 7300: digital sign, 7301: housing, 7303: speaker, 7311: information terminal, 7400: digital sign, 7401: column, 7411: information terminal

Claims

1. A display device comprising: a pixel; and a circuit comprising: a selection circuit; a first switch; and a second switch, wherein the display device is configured to display an image corresponding to digital image data including first data and second data, the selection circuit includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal, the second input terminal is electrically connected to one terminal of the first switch and one terminal of the second switch, the first output terminal is electrically connected to the pixel through a first wiring, the second output terminal is electrically connected to the pixel through a second wiring, a potential of the first wiring corresponds to the first data, and a potential of the second wiring corresponds to the second data.

2. The display device according to claim 1, wherein another terminal of the first switch is supplied with a first potential, another terminal of the second switch is supplied with a second potential, and the second data controls opening and closing of the first switch and the second switch.

3. The display device according to claim 1, wherein the second data includes information on a most significant bit of the digital image data.

4. The display device according to claim 1, wherein, the circuit is a source driver circuit.

5. The display device according to claim 1, wherein the pixel includes a liquid crystal device.

6. A display device comprising: a display device; and a source driver circuit comprising: a selection circuit; a first switch; and a second switch, wherein the selection circuit includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal, the second input terminal is electrically connected to one terminal of the first switch and one terminal of the second switch, the first output terminal is electrically connected to one terminal of the display device through a first wiring, the second output terminal is electrically connected to another terminal of the display device through a second wiring, digital image data including first data and second data is supplied to the source driver circuit, in a first mode, the source driver circuit supplies a potential corresponding to the first data to the first wiring through the selection circuit, and supplies a potential corresponding to the second data to the second wiring through the selection circuit, and in a second mode, the source driver circuit supplies a potential corresponding to the first data to the second wiring through the selection circuit, and supplies a potential corresponding to the second data to the first wiring through the selection circuit.

7. The display device according to claim 6, wherein another terminal of the first switch is supplied with a first potential, another terminal of the second switch is supplied with a second potential.

8. A display device comprising: a source driver circuit comprising a selection circuit; and a pixel comprising: a first transistor; a second transistor; a capacitor; and a display device, wherein one of a source and a drain of the first transistor is electrically connected to a first wiring, the other of the source and the drain of the first transistor is electrically connected to one terminal of the capacitor and one terminal of the display element, one of a source and a drain of the second transistor is electrically connected to a second wiring, the other of the source and the drain of the second transistor is electrically connected to the other terminal of the capacitor and the other terminal of the display element, image data including first data and second data is supplied to the source driver circuit, in a first mode, the source driver circuit supplies a potential corresponding to the first data to the first wiring through the selection circuit, and supplies a potential corresponding to the second data to the second wiring through the selection circuit, and, in a second mode, the source driver circuit supplies a potential corresponding to the first data to the second wiring through the selection circuit, and supplies a potential corresponding to the second data to the first wiring through the selection circuit.

9. The display device according to claim 6 or 8, wherein, the display element is a liquid crystal element.

Images