FPGA-based DDR continuous storage circuit and implementation method thereof

Abstract

The application relates to the field of integrated circuits, and discloses a DDR continuous storage circuit based on an FPGA and an implementation method thereof, which can realize data continuous writing function and does not lose data even if an interrupt signal is generated in the process of processing high-speed data by a memory controller. The circuit comprises a sampling buffer module, a data switching module, a first register, a second register, a data processing module, an address switching module and a memory controller. When the memory controller sends an interrupt signal: the address switching module controls the sampling buffer module to output data to the data switching module, the data switching module stops sending data, and the received data is sequentially stored into the first register and the second register respectively, and the data processing module stops forwarding data. After the interruption ends, the data processing module reads the data stored in the first register and the second register and transmits the data to the memory controller, and then continues to forward the data output by the data processing module to the memory controller; and the memory controller writes the received data into a DDR memory through a DDR physical layer interface.

Description

Technical Field

[0001] This application relates to the field of integrated circuits, specifically to an FPGA-based DDR continuous memory circuit and its implementation method. Background Technology

[0002] This section is intended to provide background or context for the embodiments of this application as set forth in the claims. The description herein is not intended to imply that it is prior art that has been disclosed, simply because it is included in this section.

[0003] With the rapid development of the information age, the total amount of data is also constantly increasing, which puts forward a more urgent demand for data processing speed and capacity. In order to solve this problem, the high-capacity and high-bandwidth DDR interface has emerged.

[0004] Because Double Data Rate (DDR) chips have many pins and are complex to operate, optimizations have been made to the DDR interface, commonly referred to as the DDR user interface. This interface is implemented by a combination of the memory controller (MC) and the physical layer (PHY). The PHY directly connects to the DDR chip, resolving the timing matching issues between the logic device and the DDR for data and addresses. The other end of the PHY connects to the MC via the DFI bus. The interface of the MC connecting to the user end is the DDR user interface.

[0005] The traditional method for writing user data to DDR is to directly process the user data into the DFI bus protocol interface and connect it directly to the PHY. However, the DFI protocol is relatively complex and not convenient for general engineers to operate. Later, adding MC to PHY greatly simplified the user's design logic, but also increased the pressure on MC to process data. When the MC module processes high-speed data, it will generate an interrupt signal. During the interrupt, the data written by the user will be lost, and the data can only be written again after the interrupt ends. Summary of the Invention

[0006] The purpose of this application is to provide an FPGA-based DDR continuous memory circuit and its implementation method, which can continuously write data even if the memory controller generates an interrupt signal and does not lose data after the interrupt is recovered.

[0007] This application discloses a DDR continuous memory circuit based on FPGA, including: a sampling buffer module, a data switching module, a first register, a second register, a data processing module, an address switching module, and a memory controller;

[0008] The sampling cache module is configured to acquire input data and cache it.

[0009] The address switching module is configured to subtract two units from the current address when it receives an interrupt signal from the memory controller, and control the sampling buffer module to output two units of data to the data switching module in the next two clock cycles.

[0010] The data switching module is configured to immediately stop sending data to the data processing module when it receives an interrupt signal from the memory controller, and to store the data from the two units received in the next two clock cycles into the first register and the second register respectively.

[0011] The data processing module is configured to immediately stop forwarding the data output by the data processing module to the memory controller when it receives an interrupt signal from the memory controller, and to read the data stored in the first register and the second register in sequence and transmit them to the memory controller within two clock cycles after the interrupt ends, and then continue to forward the data output by the data processing module to the memory controller.

[0012] The memory controller is configured to write received data into DDR memory via the DDR physical layer interface.

[0013] In a preferred embodiment, when the memory controller does not generate an interrupt, the sampling buffer module acquires and buffers the input data, then outputs the data to the data switching module. The data switching module sends the data to the data processing module, and the data processing module forwards the data output by the data processing module to the memory controller.

[0014] In a preferred embodiment, the sampling buffer module includes a sampling module, a first random access memory, and a second random access memory; the sampling module alternately stores the acquired input data into the first random access memory and the second random access memory.

[0015] In a preferred embodiment, the address switching module includes an enable selection module and a first address accumulator. The sampling cache module sends a chip select signal to the enable selection module. The enable selection module outputs a first read enable signal and a second read enable signal according to the chip select signal. The first address accumulator is configured to automatically accumulate to the maximum value and then reset to 0 to start counting again. When an interrupt signal is received from the memory controller, the current address is subtracted by 2 units.

[0016] In a preferred embodiment, when the chip select signal is high, the first read enable signal output by the enable selection module is high and the second read enable signal is low; or, when the chip select signal is low, the first read enable signal output by the enable selection module is low and the second read enable signal is high.

[0017] In a preferred embodiment, the data processing module includes a second address accumulator and a selector. The second address accumulator is configured to stop address accumulation when an interrupt signal is received from the memory controller and continue accumulation after the interrupt ends. The selector is configured to arrange the data streams in the data switching module, the first register, and the second register in address order and write them sequentially into the memory controller.

[0018] In a preferred embodiment, the first random access memory and the second random access memory share a single address and data signal.

[0019] In a preferred embodiment, a phase-locked loop is further included to provide clock signals to the data processing module, the memory controller, the address switching module, and the data switching module.

[0020] This application also discloses a method for implementing a DDR continuous memory circuit based on FPGA, including the following steps:

[0021] The sampling and caching module acquires input data and caches it;

[0022] The memory controller sends an interrupt signal;

[0023] When the address switching module receives the interrupt signal, it subtracts two units from the current address and controls the sampling buffer module to output two units of data to the data switching module in the next two clock cycles.

[0024] When the data switching module receives the interrupt signal, it immediately stops sending data to the data processing module and stores the data from the two units received in the next two clock cycles into the first register and the second register respectively.

[0025] When the data processing module receives the interrupt signal, it immediately stops forwarding the data output by the data processing module to the memory controller.

[0026] The memory controller interrupt has ended;

[0027] The data processing module reads the data stored in the first register and the second register sequentially and transmits it to the memory controller in two clock cycles after the interrupt ends. After that, it continues to forward the data output by the data processing module to the memory controller.

[0028] The memory controller writes the received data into the DDR memory through the DDR physical layer interface.

[0029] In a preferred embodiment, the sampling buffer module acquiring and buffering input data further includes the sampling module acquiring input data and alternately storing it in a first random access memory and a second random access memory.

[0030] In the embodiments of this application, when a data interruption occurs, DDR can be written seamlessly.

[0031] Furthermore, by using two random access memories (RAMs), after an interrupt occurs, the address of the lost data in the RAM can be recalculated to prevent data loss.

[0032] Furthermore, by alternately storing data in two random access memories, the sampling module can avoid read / write conflicts and enhance data stability.

[0033] The various technical features disclosed in the above-described invention, the various technical features disclosed in the following embodiments and examples, and the various technical features disclosed in the accompanying drawings can be freely combined to form various new technical solutions (all of which should be considered as having been recorded in this specification), unless such a combination of technical features is technically infeasible. For example, in one example, feature A+B+C is disclosed, and in another example, feature A+B+D+E is disclosed. Features C and D are equivalent technical means that serve the same function, and technically only one needs to be used; it is impossible to use both simultaneously. Feature E can be technically combined with feature C. Therefore, the solution A+B+C+D should not be considered as having been recorded because it is technically infeasible, while the solution A+B+C+E should be considered as having been recorded. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of a circuit structure according to one embodiment of this application;

[0035] Figure 2 This is a schematic diagram of a sampling module structure according to one embodiment of this application;

[0036] Figure 3 This is a schematic diagram of the address switching module structure according to one embodiment of this application;

[0037] Figure 4 This is a schematic diagram of the data processing module structure according to one embodiment of this application;

[0038] Figure 5 This is a timing diagram according to one embodiment of this application;

[0039] Figure 6 This is a flowchart illustrating one embodiment of this application. Detailed Implementation

[0040] In the following description, many technical details are presented to help the reader better understand this application. However, those skilled in the art will understand that the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0041] Explanation of some concepts:

[0042] Field-Programmable Gate Arrays (FPGAs) are a further development of programmable devices such as Programmable Array Logic (PAL) and General Purpose Array Logic (GAL). They emerged as a semi-custom circuit in the field of Application-Specific Integrated Circuits (ASICs), addressing the shortcomings of custom circuits while overcoming the limited gate count of earlier programmable devices.

[0043] Random Access Memory (RAM), also called main memory, is an internal memory that directly exchanges data with the Central Processing Unit (CPU). It can be read from and written to at any time (except during refresh) and is very fast. It is typically used as a temporary data storage medium for the operating system or other running programs. When RAM is working, information can be written to (stored) or read from (retrieved) at any specified address at any time.

[0044] Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), commonly known as DDR, is a synchronous dynamic random access memory (SDRAM) with double the data transfer rate. Its data transfer speed is twice that of the system clock frequency, and due to the increased speed, its transfer performance is superior to that of traditional SDRAM.

[0045] The memory controller is a crucial component within a computer system that controls memory and is responsible for data exchange between memory and the processor. The memory controller determines important parameters such as the maximum memory capacity the processor can use, memory type and speed, memory chip data depth and width, etc., thus determining the processor's memory performance and consequently significantly impacting the overall processor performance.

[0046] A phase-locked loop (PLL) is a negative feedback control system that uses the voltage generated by phase synchronization to tune a voltage-controlled oscillator (VCO) to generate a target frequency.

[0047] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0048] The first embodiment of this application relates to a DDR continuous memory circuit based on FPGA, the schematic diagram of which is shown below. Figure 1 As shown, the circuit includes: a sampling buffer module, a data switching module, a first register, a second register, a data processing module, an address switching module, and a memory controller.

[0049] The sampling cache module is configured to acquire and cache input data. Optionally, the sampling cache module includes a sampling module, a first random access memory, and a second random access memory; the sampling module alternately stores the acquired input data in the first random access memory and the second random access memory, which can avoid read-write conflicts and enhance data stability.

[0050] The structure diagram of the sampling module is as follows: Figure 2 As shown. Optionally, the sampling module includes a data receiving module, an address counter, and a data selector. User-input data enters the data receiving module, and the data is sampled by an externally input on-path clock.

[0051] Optionally, data is first written to the first random access memory (RAM), at which point the first RAM enable signal is high. The number of samples is counted using an address counter. When the address count reaches the maximum capacity of a single RAM, the address value is set to 0, the first RAM enable signal is set low, and the second RAM enable signal is set high. Alternatively, data is first written to the second RAM, at which point the second RAM enable signal is high. When the address count reaches the maximum capacity of a single RAM, the address value is set to 0, the second RAM enable signal is set low, and the first RAM enable signal is set high. The RAM capacity can be various, such as 1024×4bit, 1024×16bit, or 1024×64bit.

[0052] When an interrupt signal is received from the memory controller, the address switching module subtracts two units from the current address and controls the sampling buffer module to output two units of data to the data switching module in the next two clock cycles, thereby avoiding data loss and ensuring data continuity.

[0053] The structural diagram of the address switching module is as follows: Figure 3As shown, optionally, the address switching module includes an enable selection module and a first address accumulator. The sampling cache module sends a chip select signal to the enable selection module, and the enable selection module outputs a first read enable signal and a second read enable signal according to the chip select signal. The first address accumulator is configured to automatically accumulate to the maximum value and then reset to 0 to start counting again. When an interrupt signal is received from the memory controller, the current address is subtracted by 2 units. If the address is less than 2 units, it is set to 0.

[0054] Optionally, when the chip select signal is high, the first read enable signal output by the enable selection module is high and the second read enable signal is low; alternatively, when the chip select signal is low, the first read enable signal output by the enable selection module is low and the second read enable signal is high.

[0055] Upon receiving an interrupt signal from the memory controller, the data switching module immediately stops sending data to the data processing module and stores the data from the two units received in the following two clock cycles into the first register and the second register, respectively. After the interrupt ends, the data obtained from the sampling buffer module is directly transmitted to the data processing module.

[0056] When an interrupt signal is received from the memory controller, the data processing module immediately stops forwarding the data output by the data processing module to the memory controller. After the interrupt ends, it reads the data stored in the first register and the second register in sequence and transmits them to the memory controller within two clock cycles. After that, it continues to forward the data output by the data processing module to the memory controller.

[0057] The structure diagram of the data processing module is as follows: Figure 4 As shown, optionally, the data processing module includes a second address accumulator and a selector. The second address accumulator is configured to stop address accumulation when an interrupt signal is received from the memory controller, and to continue accumulating after the interrupt ends. The selector is configured to arrange the data streams in the data switching module, the first register, and the second register in address order and write them sequentially into the memory controller.

[0058] Optionally, the data switching module to the data processing module is channel 1, the data switching module to the first register and then to the data processing module is channel 2, and the data switching module to the second register and then to the data processing module is channel 3. The data processing module processes data from the three channels 1, 2, and 3. When the memory controller is determined to be idle, the sorted and organized data stream is written to the memory controller sequentially, and finally to the DDR. Optionally, without interruption, data can be continuously transmitted on channel 1, that is, after the data is transmitted to the data switching module, it is directly transmitted to the data processing module, which then forwards it to the memory controller. When the memory controller issues an interrupt signal, the module stops transmitting data and waits for the first and second registers to be updated. After the interrupt ends, the data processing module reads the data in the first register and then the data in the second register, or reads the data in the second register and then the data in the first register, and forwards it to the memory controller module. The third and subsequent data are continuously transmitted on channel 1 until the next interrupt occurs. Using two registers allows for the preparation of two units of data in advance, storing them in two registers before the data from channel 1 is transmitted to the data processing module after the interrupt ends, ensuring maximum data transmission efficiency.

[0059] The memory controller writes the received data to the DDR memory through the DDR physical layer interface.

[0060] Optionally, when the memory controller does not generate an interrupt, the sampling buffer module acquires and buffers the input data, then outputs the data to the data switching module. The data switching module sends the data to the data processing module, and the data processing module forwards the data output by the data processing module to the memory controller.

[0061] Optionally, the first random access memory and the second random access memory share a single address and data signal.

[0062] Optionally, the circuit may further include a phase-locked loop (PLL) that provides clock signals to the data processing module, memory controller, address switching module, and data switching module.

[0063] Optionally, the interrupt signal can be greater than or equal to two clock cycles. Optionally, the interrupt signal can be less than two clock cycles, in which case the above implementation can be treated as if the interrupt signal were equal to two clock cycles in length.

[0064] To better understand the technical solution of this application, a specific example is provided below. The details listed in this example are mainly for ease of understanding and are not intended to limit the scope of protection of this application.

[0065] Figure 5This is a timing diagram when an interrupt occurs. In the diagram, clk is the clock signal, addr_ram is the address of the random access memory (RAM), and data_ddr is the data received from the DDR. The interrupt signal is initially low, but later, due to the memory controller being busy processing data, an interrupt command is issued, at which point the interrupt signal is high. The data processing module pauses sending data to the memory controller, and the corresponding addr_ram in the diagram stops incrementing. The current address is decremented by two units, and the system waits for the interrupt to finish.

[0066] The first register and the second register store the data from the two units received in the two clock cycles after the interrupt occurs. When the interrupt ends, the data processing module immediately obtains the data from these two units and writes it to the DDR via the memory controller. After obtaining the data, it continues to obtain data from channel 1. In this way, even if the memory controller is interrupted, data continuity can be achieved.

[0067] The second embodiment of this application relates to a method for implementing a DDR continuous memory circuit based on FPGA, the flowchart of which is shown below. Figure 6 As shown, the method includes the following steps:

[0068] In step 601, the sampling buffer module acquires the input data and buffers it.

[0069] In step 602, the memory controller issues an interrupt signal.

[0070] In step 603, when the address switching module receives an interrupt signal, it subtracts two units from the current address and controls the sampling buffer module to output two units of data to the data switching module in the next two clock cycles.

[0071] In step 604, when the data switching module receives an interrupt signal, it immediately stops sending data to the data processing module and stores the data from the two units received in the next two clock cycles into the first register and the second register respectively.

[0072] In step 605, when the data processing module receives an interrupt signal, it immediately stops forwarding the data output by the data processing module to the memory controller.

[0073] In step 606, the memory controller interrupt ends.

[0074] In step 607, the address switching module continues address accumulation after the interrupt ends.

[0075] In step 608, two clock cycles after the interrupt ends, the data processing module reads the data stored in the first register and the second register in sequence and transmits them to the memory controller. After that, it continues to forward the data output by the data processing module to the memory controller.

[0076] In step 609, the data switching module continues to send data to the data processing module after the interruption ends.

[0077] In step 610, the memory controller writes the received data into the DDR memory through the DDR physical layer interface.

[0078] Optionally, in step 601, the sampling buffer module acquiring and buffering the input data may further include: the sampling module acquiring the input data and alternately storing it in the first random access memory and the second random access memory.

[0079] This embodiment is a method embodiment corresponding to the first embodiment. The technical details in the first embodiment can be applied to this embodiment, and the technical details in this embodiment can also be applied to the first embodiment.

[0080] It should be noted that in this application, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. In this application, if it refers to performing an action according to an element, it means performing the action at least according to that element, including two cases: performing the action only according to that element, and performing the action according to that element and other elements. Expressions such as "multiple," "repeatedly," and "various" include two, two times, two kinds, and more than two, more than two times, and more than two kinds.

[0081] The numbering used in describing the steps of a method does not inherently limit the order of these steps. For example, a step with a higher number does not necessarily have to be executed after a step with a lower number; it can be executed first and then second, or even in parallel, as long as this execution order is reasonable to someone skilled in the art. Similarly, multiple steps with consecutively numbered sequences (e.g., step 101, step 102, step 103, etc.) do not restrict other steps from being executed between them; for example, there can be other steps between step 101 and step 102.

[0082] This specification includes combinations of various embodiments described herein. Individual references to embodiments are made (e.g., "one embodiment," "some embodiments," or "preferred embodiments"); however, these embodiments are not mutually exclusive unless indicated to be mutually exclusive or are readily apparent to those skilled in the art. It should be noted that the word "or" is used in a non-exclusive sense throughout this specification unless the context explicitly indicates or requires it.

[0083] All references to this specification are considered to be incorporated integrally into the disclosure of this application so that they can serve as the basis for modifications if necessary. Furthermore, it should be understood that the above descriptions are merely preferred embodiments of this specification and are not intended to limit the scope of protection of this specification. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments of this specification should be included within the scope of protection of one or more embodiments of this specification.

[0084] In some cases, the actions or steps described in the claims can be performed in a different order than that shown in the embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

Claims

1. A DDR continuous memory circuit based on FPGA, characterized in that, include: The system includes a sampling buffer module, a data switching module, a first register, a second register, a data processing module, an address switching module, and a memory controller. The sampling cache module is configured to acquire input data and cache it. The address switching module is configured to subtract two units from the current address when it receives an interrupt signal from the memory controller, and control the sampling buffer module to output two units of data to the data switching module in the next two clock cycles. The data switching module is configured to immediately stop sending data to the data processing module when it receives an interrupt signal from the memory controller, and to store the data from the two units received in the next two clock cycles into the first register and the second register respectively. The data processing module is configured to immediately stop forwarding the data output by the data processing module to the memory controller when it receives an interrupt signal from the memory controller, and to read the data stored in the first register and the second register in sequence and transmit them to the memory controller within two clock cycles after the interrupt ends, and then continue to forward the data output by the data processing module to the memory controller. The memory controller is configured to write received data into DDR memory via the DDR physical layer interface.

2. The FPGA-based DDR continuous memory circuit as described in claim 1, characterized in that, When the memory controller does not generate an interrupt, the sampling buffer module acquires and buffers the input data, then outputs the data to the data switching module. The data switching module sends data to the data processing module, and the data processing module forwards the data output by the data processing module to the memory controller.

3. The FPGA-based DDR continuous memory circuit as described in claim 1, characterized in that, The sampling buffer module includes a sampling module, a first random access memory, and a second random access memory; the sampling module alternately stores the acquired input data into the first random access memory and the second random access memory.

4. The FPGA-based DDR continuous memory circuit as described in claim 3, characterized in that, The address switching module includes an enable selection module and a first address accumulator. The sampling cache module sends a chip select signal to the enable selection module. The enable selection module outputs a first read enable signal and a second read enable signal according to the chip select signal. The first address accumulator is configured to automatically accumulate to the maximum value and then set it to 0 to start counting again. When an interrupt signal is received from the memory controller, the current address is subtracted by 2 units.

5. The FPGA-based DDR continuous memory circuit as described in claim 4, characterized in that, When the chip select signal is high, the first read enable signal output by the enable selection module is high and the second read enable signal is low; or, when the chip select signal is low, the first read enable signal output by the enable selection module is low and the second read enable signal is high.

6. The FPGA-based DDR continuous memory circuit as described in claim 1, characterized in that, The data processing module includes a second address accumulator and a selector. The second address accumulator is configured to stop address accumulation when it receives an interrupt signal from the memory controller and continue accumulating after the interrupt ends. The selector is configured to arrange the data streams in the data switching module, the first register, and the second register in address order and write them sequentially into the memory controller.

7. The FPGA-based DDR continuous memory circuit as described in claim 3, characterized in that, The first random access memory and the second random access memory share the same address and data signals.

8. The FPGA-based DDR continuous memory circuit as described in claim 1, characterized in that, It also includes a phase-locked loop (PLL) that provides clock signals to the data processing module, the memory controller, the address switching module, and the data switching module.

9. A method for implementing a DDR continuous memory circuit based on FPGA, characterized in that, The steps include the following: The sampling and caching module acquires input data and caches it; The memory controller sends an interrupt signal; When the address switching module receives the interrupt signal, it subtracts two units from the current address and controls the sampling buffer module to output two units of data to the data switching module in the next two clock cycles. When the data switching module receives the interrupt signal, it immediately stops sending data to the data processing module and stores the data from the two units received in the next two clock cycles into the first register and the second register respectively. When the data processing module receives the interrupt signal, it immediately stops forwarding the data output by the data processing module to the memory controller. The memory controller interrupt has ended; The data processing module reads the data stored in the first register and the second register sequentially and transmits it to the memory controller in two clock cycles after the interrupt ends. After that, it continues to forward the data output by the data processing module to the memory controller. The memory controller writes the received data into the DDR memory through the DDR physical layer interface.

10. The implementation method of a DDR continuous memory circuit based on FPGA as described in claim 9, characterized in that, The sampling and caching module acquires input data and caches it, which further includes the sampling module acquiring input data and alternately storing it in a first random access memory and a second random access memory.

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