An embedded flip chip package substrate and a method for manufacturing the same

Abstract

The application provides a kind of embedded flip chip package substrate and its manufacturing method, comprising the following steps: providing carrier plate;First circuit layer is prepared on the upper surface of carrier plate, laminates first dielectric layer on first circuit layer;First window is formed on first dielectric layer, and first copper column is filled in first window;Second window is formed on first dielectric layer, and flip chip is installed on second window;Packaging layer and second dielectric layer are sequentially stacked on first dielectric layer, wherein the upper surface of second dielectric layer is covered with first metal layer;Packaging layer and second dielectric layer are pressed, packaging layer encapsulates first copper column and flip chip, and packaging layer is solidified;First metal layer, second dielectric layer and packaging layer are opened, and interlayer conductive blind hole is formed;Second circuit layer is formed on the upper surface of first metal layer;Remove carrier plate to obtain packaging substrate.The application reduces the packaging process of packaging process, saves cost, effectively protects packaging substrate during packaging process, and prevents warping deformation.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and in particular to a flip-chip packaging substrate and its preparation method. Background Technology

[0002] With the continuous development of the electronics industry, multifunctionality and miniaturization of electronic products have become development trends. In the field of packaging substrates, embedding components inside the substrate can help electronic products meet the needs of high integration, multifunctionality, and miniaturization.

[0003] In related technologies, flip-chip technology typically involves mounting the chip onto the surface of a substrate, specifically the solder mask, and encapsulating it with molding compound, rather than embedding it within the substrate. Furthermore, existing embedding techniques usually involve first creating a cavity on the substrate, then mounting the device to be embedded within the cavity, and finally filling the cavity with dielectric material to cover the embedded device. Finally, small holes for connecting chip terminals are formed using methods such as laser drilling, PID dielectric pattern transfer, and sandblasting, followed by electroplating of the holes to achieve electrical interconnection between the chip and the substrate.

[0004] In addition, during the chip encapsulation process, due to the implementation of single-sided molding, the chip may not have a symmetrical structure on the top and bottom, which can easily cause the entire substrate to bend during the curing process after encapsulation. Summary of the Invention

[0005] In view of this, the purpose of this application is to propose an embedded flip chip packaging substrate and its manufacturing method. The embedded flip chip packaging substrate does not require the fabrication of cavities. The electrical connection between the flip chip and the first circuit layer requires electroplating and other methods such as laser drilling to achieve conductivity, thereby shortening the process flow and reducing manufacturing costs.

[0006] To achieve the above objectives, this application provides an embedded flip-chip packaging substrate and a method for fabricating the same.

[0007] In a first aspect, this application provides a method for fabricating an embedded flip-chip packaging substrate, comprising the following steps: (a) Provide a carrier board; prepare a first circuit layer on the upper surface of the carrier board, and laminate a first dielectric layer on the first circuit layer; (b) A first opening is formed on the first dielectric layer, and a first copper pillar is filled in the first opening, so that the first copper pillar is electrically connected to the first circuit layer; (c) A second opening is formed on the first dielectric layer, and a flip chip is mounted on the second opening, such that the first circuit layer and the terminals of the flip chip are electrically connected through the second opening; (d) A packaging layer and a second dielectric layer are stacked sequentially on the first dielectric layer, wherein the second dielectric layer is covered with a first metal layer on its upper surface away from the packaging layer; (e) Press the encapsulation layer and the second dielectric layer together, such that the encapsulation layer encapsulates the first copper pillar and the flip chip, and cures the encapsulation layer; (f) Openings are made in the first metal layer, the second dielectric layer and the encapsulation layer to form interlayer vias, wherein the interlayer vias expose the upper surface of the first copper pillar; (g) A second circuit layer is formed on the upper surface of the first metal layer, wherein the second circuit layer is electrically connected to the first circuit layer through a first copper pillar; (h) Remove the carrier plate to obtain the encapsulation substrate.

[0008] Secondly, this application also provides an embedded flip-chip packaging substrate, comprising: A first circuit layer; a first dielectric layer on the first circuit layer; a flip chip mounted on the first dielectric layer, the terminals of the flip chip passing through the first dielectric layer and electrically connected to the first circuit layer; an encapsulation layer on the first dielectric layer, wherein the encapsulation layer encapsulates the flip chip; a second dielectric layer on the encapsulation layer; and a second circuit layer on the second dielectric layer, the first circuit layer and the second circuit layer being electrically connected by a first copper pillar; wherein the first dielectric layer and the second dielectric layer are made of the same material.

[0009] Optionally, the second dielectric layer has a thickness substantially the same as the first dielectric layer.

[0010] As can be seen from the above, the embedded flip chip packaging substrate and its manufacturing method provided in this application have at least the following beneficial effects: Using the manufacturing method of this application, since it is not necessary to pre-fabricate cavities as in existing embedded technologies, nor is it necessary to pre-attach adhesive materials to bond the chip, the process steps are reduced and the manufacturing difficulty is lowered; at the same time, by using reflow soldering to solder the chip to the first circuit layer, the electrical interconnection between the chip and the first circuit layer can be easily realized, without the need to create vias and electroplating to fill holes through laser drilling or other methods to achieve the electrical connection between the chip and the first circuit layer.

[0011] Furthermore, since a second dielectric layer that is essentially the same as the first dielectric layer is added to the encapsulation layer, the first and second dielectric layers have the same degree of thermal expansion and thus play a constraining role when the encapsulation layer is heated and cured. This results in the upper and lower surfaces of the encapsulation layer experiencing essentially the same stress, thus preventing the substrate warping problem caused by the different stresses on the upper and lower surfaces of the encapsulation layer during the curing process, which occurs in the prior art. Attached Figure Description

[0012] To more clearly illustrate the technical solutions in this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 This is a schematic cross-sectional view of the overall structure before the removal of the carrier plate according to an embodiment of this application; Figure 2 This is a schematic cross-sectional view of the overall structure of one embodiment of this application; Figures 3a to 3r This is a cross-sectional schematic diagram of an intermediate state in the preparation process of one embodiment of this application. Detailed Implementation

[0014] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit it. Therefore, they do not have substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to size, without affecting the effects and objectives achieved by this application, should still fall within the scope of the technical content disclosed in this application.

[0015] This section will describe in detail the specific embodiments of this application. Preferred embodiments of this application are shown in the accompanying drawings. The purpose of the drawings is to supplement the textual description with graphics, so that people can intuitively and vividly understand each technical feature and the overall technical solution of this application, but they should not be construed as limiting the scope of protection of this application.

[0016] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0017] Unlike related technologies that use flip-chip packaging, this application changes the flip-chip from surface mounting to embedding it inside the substrate. It also eliminates the need to create a cavity on the substrate and then mount the device within that cavity. Furthermore, after embedding the chip, there is no need to create vias or perform electroplating to fill them. Instead, the flip-chip is electrically interconnected with the substrate by mounting the solder joints onto the first circuit layer through a first dielectric layer and then reflow soldering. Previously, creating cavities and requiring laser drilling and electroplating for interconnection resulted in a longer and more expensive process.

[0018] To facilitate understanding of the embedded flip-chip packaging substrate provided in this application embodiment, its specific structure is described below with reference to the accompanying drawings. First, refer to... Figure 1 and Figure 2 ,in, Figure 1 The diagram shows a cross-sectional view of the overall structure of an embedded flip-chip packaging substrate. Figure 2 The diagram shows a schematic cross-sectional view of the overall structure without the carrier plate removed.

[0019] pass Figure 1 and Figure 2 As can be seen, the embedded flip chip packaging substrate includes a first dielectric layer 3 and a first circuit layer 2 below the first dielectric layer 3; a packaging layer 8 on the first dielectric layer 3, wherein the material used to make the packaging layer 8 is generally a fiber-free material, such as Ajinomoto ABF material or RCF material; it also includes a flip chip 7 embedded inside the packaging layer, wherein the flip chip 7 is provided with solder terminals 701, wherein the solder terminals 701 are solder ball bumps, which can be tin-lead bumps or copper bumps; it also includes a second dielectric layer 9 on the packaging layer 8, wherein the second dielectric layer 9 and the first dielectric layer 3 can be made of the same material and thickness, so that during the curing process of the packaging layer 8, the first and second dielectric layers have the same degree of thermal expansion, which provides a constraint effect, and the stress on the upper and lower surfaces of the packaging layer is basically the same, so that the substrate warping problem caused by the different stress on the upper and lower surfaces of the packaging layer during the curing process will not occur in the prior art.

[0020] In some embodiments, a second circuit layer 12 on the second dielectric layer 9 is also included, wherein the first circuit layer 2 is electrically connected to the soldering terminal 701 of the flip chip 7 and the second circuit layer 12, thereby completing the electrical connection inside the entire packaging substrate.

[0021] In some embodiments, the encapsulation layer 8 also encapsulates a first copper pillar 5, which electrically connects the first circuit layer 2 and the second circuit layer 12.

[0022] Reference Figures 3a-3rThe diagram shows a cross-sectional schematic of the intermediate structure of each step in a method for fabricating a flip-chip 7-package substrate.

[0023] A method for fabricating a 7-pack substrate for embedding flip chips includes the following steps: First, provide carrier board 1, such as... Figure 3a As shown, the material of the carrier plate 1 can typically be a mixture of glass, resin and fiberglass, metal, or silicon, etc., and it plays a role in temporary bonding, stacking, and support during the fabrication of the encapsulation substrate. Since subsequent fabrication processes require layer-by-layer fabrication, the carrier plate 1 is chosen to provide subsequent support. A separable metal layer, such as copper, aluminum, stainless steel, or aluminum alloy, is applied to the surface of the carrier plate 1. Preferably, in this embodiment, a double-layer metal foil, such as a double-layer copper foil, is coated on the upper surface of the carrier plate 1. The double-layer metal foil is physically pressed together, and the two layers can also be separated by physical tearing. Examples of the double-layer metal foil are the second metal layer 101 and the third metal layer 102 shown in the figure. The thickness of the second metal layer 101 can be 12-18 mm. The thickness of the third metal layer can be 2. -5 The thicknesses of the second metal layer 101 and the third metal layer 102 can be changed according to actual conditions, and are not limited here.

[0024] Next, the first circuit layer 2 is fabricated on the upper surface of the carrier board 1 using the MSAP process, as shown below. Figure 3b As shown. Typically, a first dielectric layer 3 is formed over the first circuit layer 2, such as... Figure 3c As shown, the first dielectric layer 3 can be reinforced with an organic material, such as PP material containing glass fiber.

[0025] Then, laser drilling is performed on the first dielectric layer 3 to form the first window 4, such as... Figure 3d As shown, the first window 4 exposes the first circuit layer 2, which prepares for the first copper pillar 5 to be electrically connected to the first circuit layer 2 in subsequent processes.

[0026] Next, a first metal seed layer 401 is fabricated on the upper surface of the first dielectric layer 3 and the first window 4 by chemical copper plating or physical sputtering, as follows: Figure 3e As shown. Typically, during the process of establishing an electrical connection between the first copper pillar 5 and the first circuit layer 2, in order to improve the contact accuracy between the first copper pillar 5 and the first circuit layer 2, it is usually necessary to form a first metal seed layer 401 between them. By using chemical copper plating or physical sputtering, forming the first metal seed layer 401 in the first opening 4 can achieve close contact between the first copper pillar 5 and the first circuit layer 2 during the subsequent electroplating of the first copper pillar 5.

[0027] Subsequently, an anti-plating dry film layer 402 is prepared on the upper surface of the first metal seed layer 401, such as... Figure 3f As shown, the anti-plating dry film layer 402 provides anti-plating protection for the overall structure and facilitates the subsequent electroplating to form the first copper pillar 5.

[0028] The resist dry film layer 402 above the first window 4 is exposed and developed, and the window pattern 403 of the first copper pillar 5 is obtained, as shown below. Figure 3g As shown.

[0029] The electroplated windowed pattern 403 forms the first copper pillar 5 within the windowed pattern 403, as shown below. Figure 3h As shown, at this time, the first copper pillar 5 is electrically connected to the first circuit layer 2 through the first metal seed layer 401.

[0030] Next, remove the anti-coating dry film layer 402, as follows: Figure 3i As shown, the first metal seed layer 401 is exposed.

[0031] Etching exposes the first metal seed layer 401 on the upper surface of the first dielectric layer 3, such as Figure 3j As shown.

[0032] Then, the first dielectric layer 3 is drilled using a laser to form the second window 6, as shown. Figure 3d As shown, in order to save on the process flow, when performing the first window 4, the second window 6 can also be formed simultaneously using laser drilling. The second window 6 is used to connect the flip chip 7 to the first circuit layer 2.

[0033] Dip the soldering terminals 701 of the flip chip 7 in a flux film to absorb flux, and then insert the soldering terminals 701 of the flip chip 7 into the second window 6, as follows. Figure 3k The soldering terminal 701 is a solder ball bump, which can be a metal bump, such as a tin-lead bump or a copper bump. The flux is applied to the soldering terminal 701 so that it can be inserted into the second window 6 and fix the flip chip 7. The position of the chip 7 will not change after it is inserted into the second window 6. At the same time, the flux wets the surface of the solder joint 701 and enhances the solderability when the soldering terminal 701 is soldered in the subsequent process.

[0034] Next, power is connected to the first circuit layer 2. The first circuit layer 2 is heated to reflow solder the soldering terminals 701 in the second window 6, thereby achieving electrical connection between the flip chip 7 and the first circuit layer 2. Figure 3l As shown, during the reflow soldering process, the soldering terminal 701 is soldered to ensure that the soldering point 701 is tightly soldered into the second window 6, and the chip 7 is electrically connected to the first circuit layer 2. At the same time, the chip 7 is also fixed through the soldering terminal 701.

[0035] Next, the encapsulation layer 8 is stacked on top of the first copper pillar 5 and the chip 7. Simultaneously, a second dielectric layer 9 is stacked on the upper surface of the encapsulation layer 8, wherein a first metal layer 10 is formed on the upper surface of the second dielectric layer 9. Figure 3m As shown. In this process, the encapsulation layer 8 is configured to bond the first copper pillar 5 and the chip 7 together in a subsequent process flow, thereby encapsulating the first copper pillar 5 and the flip chip 7. The encapsulation layer 8 can be made of a fiberglass-free dielectric material, such as Ajinomoto ABF material or RCF material, etc., and is not limited here.

[0036] Then, the first metal layer 10, the second dielectric layer 9, and the encapsulation layer 8 are simultaneously pressed together on a vacuum laminator, and the encapsulation layer 8 is cured. Figure 3n As shown. After lamination, the entire encapsulation layer 8 completely covers the first copper pillar 5 and the flip chip 7. It can then be baked and cured in an oven, or laminated and cured on a laminator. During lamination, the encapsulation layer 8 utilizes its own fluidity and capillary action to fill the gap between the flip chip 7 and the first dielectric layer 3. To fully encapsulate and protect the flip chip 7, the thickness of the encapsulation layer 8 must be greater than or equal to the thickness of the flip chip 7, ensuring complete coverage of the flip chip 7.

[0037] During the heat curing process of the encapsulation layer 8, the different materials on the upper and lower surfaces of the encapsulation layer 8 often cause an imbalance in stress, leading to warping of the encapsulation layer 8 during curing. In this embodiment, the upper and lower surfaces of the encapsulation layer 8 are a second dielectric layer 9 and a first dielectric layer 3, respectively. Since the second dielectric layer 9 and the first dielectric layer 3 are made of the same material, both have metal circuit layers on their surfaces, and their thicknesses are approximately the same, their coefficients of thermal expansion are roughly equal, providing a symmetrical constraint. Therefore, during the heat curing process of the encapsulation layer 8, its upper and lower surface structures are symmetrical, and the stress is equal, effectively preventing warping of the encapsulation layer 8.

[0038] Next, laser drilling is performed on the first metal layer 10, the second dielectric layer 9, and the encapsulation layer 8 to form interlayer conductive blind vias 11, such as... Figure 3o As shown, the interlayer conductive blind via 11 exposes the upper surface of the first copper pillar 5. The second circuit layer 12 is prepared in the subsequent process flow, and the electrical connection between the first circuit layer 2 and the second circuit layer 12 is prepared through the first copper pillar 5.

[0039] Subsequently, a second metal seed layer 111 is formed on the surface of the first metal layer 10 by chemical copper plating or physical sputtering, wherein the second metal seed layer 111 covers the interlayer via 11, such as... Figure 3p As shown.

[0040] Next, a second circuit layer 12 is fabricated on the upper surface of the second metal, wherein the second circuit layer 12 is electrically connected to the first circuit layer 2 through the first copper pillar 5. The second metal seed layer 111 and the first metal layer 10 are then etched, as shown below. Figure 3q As shown, the lower surface of the first copper pillar 5 is electrically connected to the first circuit layer 2 through the first metal seed layer 401, the upper surface of the first copper pillar 5 is electrically connected to the second circuit layer 12 through the second metal seed layer 111, and the terminals of the chip 7 are electrically connected to the first circuit layer 2 through the first dielectric layer 3.

[0041] Remove carrier plate 1 to obtain the packaging substrate, as shown below. Figure 3r As shown, the second metal layer 101 and the third metal layer 102 are separated by physical tearing. After separation, the second metal layer 101 remains attached to the carrier plate 1. The third metal layer 102 can be physically pressed back onto the upper surface of the second metal layer 101, thus achieving recycling of the second metal layer 101 and the carrier plate 1 and saving costs. After separation, the third metal layer 102 below the first dielectric layer 3 and the first circuit layer 2 is etched. During the etching process, care must be taken not to damage the first circuit layer 2. As another implementation, an etching barrier layer, such as a nickel layer, can be formed on the upper surface of the third metal layer 102 to protect the first circuit layer 2 during etching of the third metal layer 102.

[0042] It should be noted that the above description describes some embodiments of this application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0043] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this application (including the claims) is limited to these examples; within the framework of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the embodiments of this application as described above, which are not provided in the details for the sake of brevity.

[0044] Additionally, to simplify the description and discussion, and to avoid obscuring the embodiments of this application, the well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the provided drawings. Furthermore, the apparatus may be shown in block diagram form to avoid obscuring the embodiments of this application, and this also takes into account the fact that the details of the implementation of these block diagram apparatuses are highly dependent on the platform on which the embodiments of this application will be implemented (i.e., these details should be fully understood by those skilled in the art). While specific details (e.g., circuits) have been set forth to describe exemplary embodiments of this application, it will be apparent to those skilled in the art that the embodiments of this application can be implemented without these specific details or with variations thereof. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0045] Although this application has been described in conjunction with specific embodiments thereof, many substitutions, modifications, and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may be used with the embodiments discussed.

[0046] The embodiments of this application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of this application should be included within the protection scope of this application.

Claims

1. A method for fabricating an embedded flip-chip packaging substrate, characterized in that, Includes the following steps: (a) Provide a carrier board; prepare a first circuit layer on the upper surface of the carrier board, and laminate a first dielectric layer on the first circuit layer; (b) A first opening is formed on the first dielectric layer, and a first copper pillar is filled in the first opening, so that the first copper pillar is electrically connected to the first circuit layer; (c) A second opening is formed on the first dielectric layer, and a flip chip is mounted on the second opening, such that the first circuit layer and the terminals of the flip chip are electrically connected through the second opening; (d) A packaging layer and a second dielectric layer are stacked sequentially on the first dielectric layer, wherein the second dielectric layer is covered with a first metal layer on its upper surface away from the packaging layer; (e) Press the encapsulation layer and the second dielectric layer together, such that the encapsulation layer encapsulates the first copper pillar and the flip chip, and cures the encapsulation layer; (f) Openings are made in the first metal layer, the second dielectric layer and the encapsulation layer to form interlayer vias, wherein the interlayer vias expose the upper surface of the first copper pillar; (g) A second circuit layer is formed on the upper surface of the first metal layer, wherein the second circuit layer is electrically connected to the first circuit layer through a first copper pillar; (h) Remove the carrier plate to obtain the encapsulation substrate.

2. The method according to claim 1, characterized in that, Step (a) includes: A second metal layer is prepared on the upper surface of the carrier plate, and a third metal layer is prepared on the upper surface of the second metal layer, wherein the second metal layer and the third metal layer are physically pressed together and can be separated by physical tearing.

3. The method according to claim 1, characterized in that, Step (b) includes: (b1) The first dielectric layer is drilled using a laser to form a first window, wherein the first window exposes the first circuit layer; (b2) A first metal seed layer is prepared on the upper surface of the first dielectric layer and in the first window by chemical copper plating or physical sputtering; (b3) Prepare a resist dry film layer on the upper surface of the first metal seed layer, and expose and develop the resist dry film above the first window to obtain the window pattern of the first copper pillar, and electroplate the window pattern to form the first copper pillar. (b4) Remove the anti-plating dry film layer and etch the first metal seed layer covering the upper surface of the first dielectric layer; The first copper pillar is electrically connected to the first circuit layer through the first metal seed layer.

4. The method according to claim 1, characterized in that, Step (c) includes: (c1) The first dielectric layer is drilled using a laser to form a second opening, wherein the second opening exposes the first circuit layer; (c2) The terminals of the flip chip are inserted into the second opening and connected to the first circuit layer by reflow soldering, thereby realizing the electrical connection between the flip chip and the first circuit layer.

5. The method according to claim 1, characterized in that, Step (e) includes: (e1) A second dielectric layer is prepared on the upper surface of the encapsulation layer, wherein the second dielectric layer is configured to have the same thickness as the first dielectric layer; (e2) A first metal layer is prepared on the upper surface of the second dielectric layer; (e3) The vacuum laminator presses together the encapsulation layer, the second dielectric layer and the first metal layer and performs a curing process, wherein the first copper pillar and the flip chip are both embedded inside the encapsulation layer.

6. The method according to claim 1, characterized in that, Step (g) includes: A second metal seed layer is formed on the surface of the first metal layer by chemical copper plating or physical sputtering, wherein the second metal seed layer covers the interlayer via blind hole; The second circuit layer is formed on the second metal seed layer; Etch the second metal seed layer and the first metal layer; The second circuit layer is electrically connected to the first copper pillar through the second metal seed layer.

7. The method according to claim 2, characterized in that, Step (h) includes removing the carrier plate by physically tearing apart the second metal layer and the third metal layer.

8. The method according to claim 5, characterized in that, The step (e3) includes: The gap between the flip chip and the first dielectric layer is filled by the fluidity of the encapsulation layer.

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