An inductively loaded ultrawideband semiconductor single-pole double-throw switch

Abstract

This invention discloses an inductor-loaded ultrawideband semiconductor single-pole double-throw switch, belonging to the technical field of basic electronic circuits. The single-pole double-throw switch includes: a first RF port, a first switching arm, a second switching arm, a second RF port, and a third RF port. Each switching arm contains two transistors connected in series and parallel, with a capacitor loaded between the transistors. A short-circuit inductor is loaded at the output of the input matching circuit connected to the first RF port, enabling an additional in-band transmission pole. This effectively widens the bandwidth and reduces the insertion loss of the switching arm in the on state, improving impedance matching bandwidth while maintaining chip miniaturization.

Description

Technical Field

[0001] This invention relates to semiconductor radio frequency single-pole double-throw switches, specifically disclosing an inductor-loaded ultrawideband semiconductor single-pole double-throw switch, which relates to radio frequency integrated circuit design technology and belongs to the technical field of basic electronic circuits. Background Technology

[0002] A radio frequency (RF) single-pole double-throw (SPDT) switch is a control circuit widely used in communications, radar, and detection fields. It is typically a three-port circuit, with one end connected to the antenna, one end to the transmit link, and the other end to the receive link. RF SPDT switches based on field-effect transistors (FETs) offer low power consumption due to their small gate current. Key technical specifications of SPDT switches include: operating bandwidth, conduction branch loss, disconnection branch isolation, chip size, in-band impedance matching, and power capacity. Achieving multiple transmission poles within a limited circuit area remains a challenge for RF SPDT switches; therefore, current RF SPDT switches struggle to simultaneously achieve both wide bandwidth and miniaturization.

[0003] Based on the different design principles of RF single-pole double-throw (SPDT) switch circuits, ultra-wideband SPDT switches can be divided into the following three types: The first type increases the bandwidth of the SPDT switch by loading multiple field-effect transistors and multiple transmission lines on each switching arm. However, the circuit size and losses of this SPDT switch are very large, so the insertion loss of this topology SPDT switch is difficult to be lower than 2dB. The second type is a series-parallel structure with two transistor units added to each switching arm. The transistors in the series-parallel structure do not generate new transmission poles, and like the traditional series-parallel transistor topology, it is difficult to achieve in-band transmission poles. Therefore, the bandwidth performance of this topology SPDT switch is not good. The third type forms a SPDT switch topology by connecting two parallel switching transistors, a transformer, and a quarter-wavelength transmission line. Although this SPDT switch has good bandwidth performance, the insertion loss is relatively large.

[0004] In summary, existing ultrawideband single-pole double-throw switches need improvement in the following aspects: (1) how to abandon the broadband implementation method of cascading multiple transistors and multiple transmission lines to avoid poor size and loss performance; (2) how to abandon the traditional series-parallel transistor topology to overcome the defect of bandwidth limitation caused by the difficulty in realizing in-band transmission poles.

[0005] In view of this, the present invention aims to provide an inductively loaded ultrawideband semiconductor single-pole double-throw switch to overcome the above-mentioned defects. Summary of the Invention

[0006] The purpose of this invention is to address the shortcomings of the aforementioned background technology by providing an inductively loaded ultra-wideband semiconductor single-pole double-throw switch. This solves the technical problems of existing ultra-wideband single-pole double-throw switches achieving broadband at the cost of size and losses, as well as the bandwidth limitations of traditional series-parallel transistor topology single-pole double-throw switches. The invention aims to improve impedance matching bandwidth while maintaining chip miniaturization.

[0007] To achieve the above-mentioned objectives, the present invention employs the following technical solution:

[0008] An inductively loaded ultrawideband semiconductor single-pole double-throw switch, comprising:

[0009] The first RF port is connected to one end of the input matching circuit, the other end of the input matching circuit is connected to one end of the short-circuit inductor, and the other end of the short-circuit inductor is grounded.

[0010] The first switching arm includes a first transistor, a second transistor, a first loading capacitor, and a first output matching circuit. The drain of the first transistor serves as the input terminal of the first switching arm and is connected to the connection point of the short-circuit inductor and the input matching circuit. The source of the first transistor is connected to one terminal of the first loading capacitor. The gate of the first transistor is connected to the first DC port. The other terminal of the first loading capacitor is electrically connected to the drain of the second transistor and one end of the first output matching circuit. The source of the second transistor is grounded, and the gate of the second transistor is connected to the second DC port. The other end of the first output matching circuit is the output terminal of the first switching arm. The logic levels connected to the first DC port and the second DC port are opposite.

[0011] The second switching arm includes a third transistor, a fourth transistor, a second loading capacitor, and a second output matching circuit. The drain of the third transistor serves as the input terminal of the second switching arm and is connected to the connection point of the short-circuit inductor and the input matching circuit. The source of the third transistor is connected to one terminal of the second loading capacitor, and the gate of the third transistor is connected to the third DC port. The other terminal of the second loading capacitor is electrically connected to the drain of the fourth transistor and one end of the second output matching circuit. The source of the fourth transistor is grounded, and the gate of the fourth transistor is connected to the fourth DC port. The other end of the second output matching circuit is the output terminal of the second switching arm. The logic levels connected to the third DC port and the fourth DC port are opposite, the logic levels connected to the third DC port and the first DC port are opposite, and the logic levels connected to the fourth DC port and the second DC port are opposite.

[0012] The second radio frequency port is connected to the output terminal of the first switching arm; and,

[0013] The third RF port is connected to the output of the second switch arm.

[0014] Furthermore, in an inductively loaded ultrawideband semiconductor single-pole double-throw switch, the DC port is connected to a DC bias voltage via a gate resistor.

[0015] Furthermore, in an inductively loaded ultrawideband semiconductor single-pole double-throw switch, the input matching circuit, the first output matching circuit, and the second output matching circuit are pure inductors, pure capacitors, or matching circuits composed of capacitors and inductors.

[0016] Furthermore, in an inductively loaded ultrawideband semiconductor single-pole double-throw switch, the inductors in the input matching circuit, the first output matching circuit, and the second output matching circuit are microstrip line inductors, stripline inductors, or spiral inductors.

[0017] Furthermore, in an inductively loaded ultrawideband semiconductor single-pole double-throw switch, the transistor is a field-effect transistor, a high electron mobility transistor, an mHEMT, or a pHEMT transistor.

[0018] Furthermore, in an inductively loaded ultrawideband semiconductor single-pole double-throw switch, the capacitors in the input matching circuit, the first output matching circuit, and the second output matching circuit are microstrip line capacitors, metal-insulator-metal capacitors, metal-oxide-metal capacitors, planar capacitors, or interdigital capacitors.

[0019] Furthermore, in an inductively loaded ultrawideband semiconductor single-pole double-throw switch, the source of the transistor is grounded and the other end of the short-circuit inductor is grounded through a termination metallized grounding via.

[0020] The present invention, by adopting the above technical solution, has the following beneficial effects:

[0021] (1) The single-pole double-throw switch disclosed in this invention adopts a transistor “series-parallel” switching arm topology. By connecting a capacitor in series after the series transistor in each switching arm and loading a short-circuit inductor connected to the input matching circuit at the input end of the two switching arms, an additional in-band transmission pole can be realized, thereby effectively widening the bandwidth. Each switching arm of the single-pole double-throw switch with this topology shares a short-circuit inductor. Compared with the existing ultra-wideband single-pole double-throw switch, the ultra-wideband single-pole double-throw switch proposed in this invention improves the impedance matching bandwidth while maintaining chip miniaturization.

[0022] (2) The single-pole double-throw switch disclosed in this invention has low loss characteristics. When in the conducting state, the insertion loss of the switch arm is generally less than 1dB within the working bandwidth, which is better than the conduction loss of most disclosed broadband semiconductor switches. Attached Figure Description

[0023] Figure 1This is a schematic diagram of an inductively loaded ultrawideband semiconductor single-pole double-throw switch provided in Embodiment 1 of the present invention.

[0024] Figure 2 This is a simulation curve showing the relationship between scattering parameters and frequency in Embodiment 1 of the present invention.

[0025] Figure 3 This is a schematic diagram of the general form of the inductively loaded ultrawideband semiconductor single-pole double-throw switch provided by the present invention.

[0026] Explanation of the labels in the diagram: P1 is the first RF port, P2 is the second RF port, P3 is the third RF port, and K... 11 For the first DC port, K 12 For the second DC port, K 21 For the third DC port, K 22 For the fourth DC port, X in For the input matching circuit, X 1out X 2out For the first and second output matching circuits, L0, L N1 L M1 L1 is an inductor, and M is a short-circuit inductor. N1a M N1b M M1a M M1b For the first, second, third, and fourth transistors, C N1 C M1 The first and second capacitors are loaded. Detailed Implementation

[0027] The technical solution of the invention will now be described in detail with reference to the accompanying drawings.

[0028] This invention discloses an inductively loaded ultrawideband semiconductor radio frequency single-pole double-throw switch, such as... Figure 3 As shown, it includes: a first radio frequency port P1, a second radio frequency port P2, a third radio frequency port P3, and a first DC port K. 11 Second DC port K 12 Third DC port K 21 Fourth DC port K 22 Short-circuit inductor L1, first switch arm, and second switch arm. The first RF port P1 is connected to the input matching circuit X. in One end of the short-circuit inductor L1 is electrically connected, and the other end of the short-circuit inductor L1 is grounded.

[0029] In the first switching arm, the first transistor M N1a The drain of the transistor is electrically connected to the non-grounded terminal of the short-circuit inductor L1 as the input terminal of the first switching arm. N1a The source and the first loaded capacitor C N1One pole is electrically connected, and the first loading capacitor C N1 The other pole is connected to the second transistor M N1b The drain connection of the second transistor M N1b The source of the transistor is grounded, and the second transistor M N1b The drain of the first output matching circuit X is applied between the second RF port P2 and the second RF port P2. 1out Connection, first transistor M N1a The gate is connected to the first DC port K. 11 The second transistor M N1b The gate is connected to the second DC port K. 12 First DC port K 11 Second DC port K 12 The logic levels connected are reversed.

[0030] The circuit structure of the second switching arm is symmetrical to that of the first switching arm about the first RF port P1 and the short-circuit inductor L1. The second switching arm includes: a third transistor M. M1a Second loading capacitor C M1 Fourth transistor M M1b Second output matching circuit X 2out The third transistor M M1a The drain of the transistor is electrically connected to the non-grounded terminal of the short-circuit inductor L1 as the input terminal of the second switching arm. The third transistor M... M1a The source and the second loaded capacitor C M1 One electrode is electrically connected, and the second loading capacitor C is connected. M1 The other pole and the fourth transistor M M1b The drain and the second output matching circuit X 2out One end is electrically connected to the second output matching circuit X. 2out The other end serves as the output of the second switching arm and is electrically connected to the third RF port P3. The third transistor M M1a The gate is connected to the third DC port K. 21 The fourth transistor M M1b The gate is connected to the fourth DC port K. 22 Third DC port K 21 and the fourth DC port K 22 The logic levels of the input are reversed, and the third DC port K... 21 and the first DC port K 11 The logic levels of the input are reversed, and the fourth DC port K... 22 Second DC port K 12 The logic levels connected are reversed.

[0031] First DC port K 11 Second DC port K 12 Third DC port K 21 Fourth DC port K22 After the logic level is connected as described above, only one of the two switching arms is in the on state. The capacitor loaded in the off state, the equivalent capacitance of the transistor, and the short-circuit inductor resonate in parallel, realizing an additional in-band transfer pole.

[0032] Example 1

[0033] A specific implementation of an inductively loaded ultrawideband semiconductor single-pole double-throw switch disclosed in this invention is as follows: Figure 1 As shown, the input matching circuit X in First output matching circuit X 1out Second output matching circuit X 2out Inductors L0 and L1 are respectively N1 L M1 DC ports K from the first to the fourth 11 K 12 K 21 K 22 The gate protection resistors of the field-effect transistors are respectively connected to the four transistors.

[0034] The equivalent inductance of short-circuit inductor L1 is 620 pH; the equivalent inductance of inductor L0 is 0.007 pH, achieved through a microstrip line with a width of 25 μm and a length of 10 μm; inductor L... N1 The equivalent inductance is 0.1 pH, achieved through a microstrip line with a width of 25 μm and a length of 150 μm; inductance L M1 The equivalent inductance is 0.1 pH, achieved through a microstrip line with a width of 25 μm and a length of 150 μm; the first loading capacitor C N1 Second loading capacitor C M1 The equivalent capacitance is 200fF; the first transistor M N1a Third transistor M M1a The gate width is 100µm, and the transistor gate index is 2; the second transistor M N1b Fourth transistor M M1b The gate width is 75µm; the transistor gate index is 2.

[0035] Figure 2 This is a simulation curve showing the relationship between scattering parameters and frequency in Embodiment 1 of the present invention. Figure 2 As shown, the single-pole double-throw switch disclosed in Embodiment 1 of this invention has a center frequency of 38 GHz, two transmission poles at 22.5 GHz and 45 GHz respectively, an insertion loss of less than 1 dB, and a return loss of greater than 15 dB. Compared with the prior art, the single-pole double-throw switch provided in Embodiment 1 of this invention has a significantly increased bandwidth and significantly improved performance.

[0036] The above embodiments are merely illustrative examples of the present invention and do not limit its scope of protection. Those skilled in the art can make partial changes to it. For example, several switching arms can be added and the input terminals of all switching arms can be connected to the non-grounded terminal of the short-circuit inductor to realize an ultra-wideband radio frequency single-pole multi-throw switch. Any equivalent substitution in any form that conforms to the spirit of the invention falls within the scope of protection of the present invention.

Claims

1. An inductively loaded ultrawideband semiconductor single-pole double-throw switch, characterized in that, include: The first RF port is connected to one end of the input matching circuit, the other end of the input matching circuit is connected to one end of the short-circuit inductor, and the other end of the short-circuit inductor is grounded. The first switching arm includes a first transistor, a second transistor, a first loading capacitor, and a first output matching circuit. The drain of the first transistor serves as the input terminal of the first switching arm and is connected to the connection point of the short-circuit inductor and the input matching circuit. The source of the first transistor is connected to one terminal of the first loading capacitor. The gate of the first transistor is connected to a first DC port. The other terminal of the first loading capacitor is electrically connected to the drain of the second transistor and one end of the first output matching circuit. The source of the second transistor is grounded, and the gate of the second transistor is connected to a second DC port. The other end of the first output matching circuit is the output terminal of the first switching arm. The logic levels connected to the first DC port and the second DC port are opposite. The second switching arm includes a third transistor, a fourth transistor, a second loading capacitor, and a second output matching circuit. The drain of the third transistor serves as the input terminal of the second switching arm and is connected to the connection point of the short-circuit inductor and the input matching circuit. The source of the third transistor is connected to one pole of the second loading capacitor, and the gate of the third transistor is connected to the third DC port. The other pole of the second loading capacitor is electrically connected to the drain of the fourth transistor and one end of the second output matching circuit. The source of the fourth transistor is grounded, and the gate of the fourth transistor is connected to the fourth DC port. The other end of the second output matching circuit is the output terminal of the second switching arm. The logic levels connected to the third DC port and the fourth DC port are opposite, the logic levels connected to the third DC port and the first DC port are opposite, and the logic levels connected to the fourth DC port and the second DC port are opposite. Only one of the two switching arms is in the on state. The loading capacitor, the equivalent capacitance of the transistor, and the short-circuit inductor in the off state of the switching arm resonate in parallel to form an additional in-band transmission pole. The second radio frequency port is connected to the output of the first switch arm; and, The third RF port is connected to the output of the second switch arm.

2. The inductively loaded ultra-wideband semiconductor single-pole double-throw switch according to claim 1, characterized in that, The DC port is connected to a DC bias voltage via a gate resistor.

3. The inductively loaded ultra-wideband semiconductor single-pole double-throw switch according to claim 1, wherein the input matching circuit, the first output matching circuit, and the second output matching circuit are pure inductors, pure capacitors, or matching circuits composed of capacitors and inductors.

4. The inductively loaded ultrawideband semiconductor single-pole double-throw switch according to claim 3, characterized in that, The inductors in the input matching circuit, the first output matching circuit, and the second output matching circuit are microstrip line inductors, stripline inductors, or spiral inductors.

5. The inductively loaded ultra-wideband semiconductor single-pole double-throw switch according to claim 1, characterized in that, The transistor is a field-effect transistor, a high electron mobility transistor, an mHEMT, or a pHEMT transistor.

6. The inductively loaded ultra-wideband semiconductor single-pole double-throw switch according to claim 3, characterized in that, The capacitors in the input matching circuit, the first output matching circuit, and the second output matching circuit are microstrip line capacitors, metal-insulator-metal capacitors, metal-oxide-metal capacitors, planar capacitors, or interdigital capacitors.

7. An inductively loaded ultra-wideband semiconductor single-pole double-throw switch according to any one of claims 1 to 6, characterized in that, The source of the transistor is grounded and the other end of the short-circuit inductor is grounded through a terminal metallized grounding via.

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