Impedance matching array, matching method, radio frequency power supply, and plasma radio frequency system

Abstract

This application relates to an impedance matching array, a matching method, a radio frequency power supply, and a plasma radio frequency system that solve the problem of impedance matching. The impedance matching array includes a plurality of reactance assemblies connected in parallel in stages between the input and output sides. Each stage of the reactance assembly includes a reactance unit, an input transistor, an output transistor, and a series-connected transistor. The input transistor of a given stage is connected between the input side of the impedance matching array and the input side of the reactance unit of the given stage. The output transistor of a given stage is connected between the output side of the reactance unit of the given stage and the output side of the impedance matching array. The series-connected transistor of a given stage is connected between the output side of the reactance unit of the given stage and the input side of the reactance unit of the next stage. By controlling the on / off states of the input transistors, output transistors, and series-connected transistors in each stage of the reactance assembly, a reactance combination is formed to achieve impedance matching. This application enables rapid impedance matching by switching each of the on / off transistors in the reactance assembly.

Description

Technical Field

[0005]

[0001] This application belongs to the technical field of radio frequency power supplies, and specifically relates to an impedance matching array, a matching method, a radio frequency power supply, and a plasma radio frequency system.

Background Art

[0002] The architecture of an integrated radio frequency plasma power supply system includes a radio frequency power supply, a matcher, and a chamber load. The radio frequency power supply outputs a power signal to the matcher, and the matcher performs impedance matching and transfers the power signal to the chamber load. During operation, the chamber load undergoes load changes due to the execution of the process. The matcher performs impedance adjustment according to this load change to bring the impedance combined by the matcher and the chamber load closer to the ideal value and stabilize it.

[0003] Conventional matchers mainly include a controller, a drive motor, and a variable reactance. The controller calculates the position at which the variable reactance should be adjusted based on information received from the outside, and controls the drive motor to adjust the position of the variable reactance. Conventionally, the drive motor is a stepping motor, and the variable reactance may be a variable capacitor or a variable inductor according to the design requirements.

[0004] The variable reactance adjusts the impedance value by a stepping drive motor. Also, since the operating speed of the stepping drive motor is limited, whether it is a capacitor or an inductor, the completion of the adjustment assembly displacement can only reach the s level at the fastest. For processes that require high precision and rapid response of devices, such as semiconductor manufacturing processes and high-precision coating, it is difficult for conventional matchers to meet the requirement of rapidly matching the impedance of the process.

Summary of the Invention

Problems to be Solved by the Invention

[0005] In light of the above analysis, the object of this application is to disclose an impedance matching array, a matching method, a radio frequency power supply, and a plasma radio frequency system that can quickly meet the demand for impedance matching and can be applied to impedance matching configurations of various matching networks. [Means for solving the problem]

[0006] One aspect of the present invention discloses an impedance matching array connected within an impedance matching network, wherein a plurality of reactance assemblies are connected in a stepwise parallel configuration between the input and output sides of the impedance matching array, each stage of the reactance assembly comprising a reactance unit, an input transistor, an output transistor, and a series-connected transistor, wherein the input transistor of a predetermined stage is connected between the input side of the impedance matching array and the input side of the predetermined stage of the reactance unit, the output transistor of a predetermined stage is connected between the output side of the predetermined stage of the reactance unit and the output side of the impedance matching array, and the series-connected transistor of a predetermined stage is connected between the output side of the predetermined stage of the reactance unit and the input side of the next stage of the reactance unit. By controlling the on or off states of the input transistor, output transistor, and series-connected transistor within each stage's reactance assembly, a combination of reactances is formed, achieving impedance matching.

[0007] Another aspect of the present application further discloses an impedance matching method based on the impedance matching array described above, the method being: Step S1 involves creating an impedance matching lookup table for the impedance matching array, where each impedance matching value corresponds to an on / off transistor combination scheme of one reactance assembly. Step S2 involves referencing an impedance combination lookup table based on the required impedance matching value, selecting a corresponding on / off transistor combination scheme, and controlling the connection scheme of the reactance units in the impedance matching array to achieve impedance matching. Step S3 includes, if a matched reactance value does not exist in the impedance combination lookup table, performing an approximate fast match, generating control instructions for an on / off transistor, controlling the connection method of the reactance units in the impedance matching array, and achieving an approximate impedance match.

[0008] Another aspect of the present invention further discloses a radio frequency power supply system including sequentially connected radio frequency power supplies, a matcher and a load, wherein the matcher includes the impedance matching array described above, and impedance matching is performed by controlling each switchable transistor in each stage reactance assembly within the impedance matching array to form reactance combinations with predetermined connection relationships and thereby adjusting the impedance.

[0009] Another aspect of the present invention further discloses a plasma radio frequency system comprising sequentially connected radio frequency power supplies, a matching unit, and a chamber load, wherein the matching unit includes the impedance matching array described above, and when a load change occurs in the chamber load due to the execution of a process, the matching unit controls each switchable transistor in each reactance assembly within the impedance matching array in response to the load change, thereby forming a corresponding reactance combination and adjusting the impedance to bring the impedance of the matching unit and the chamber load closer to an ideal value and stabilize it.

[0010] (Beneficial effects) According to this invention, one of the following beneficial effects can be achieved.

[0011] This invention provides rapid impedance matching by switching each switchable transistor within a reactance assembly. The matching unit employs an array design, making it relatively easy to design and manufacture. If there is sufficient space and enough reactance units can be arranged, it can accommodate more impedance matching points, thus enabling more efficient impedance matching in the process.

[0012] The drawings are used solely to illustrate specific embodiments and are not intended to be considered limitations to this application. The same reference numerals are used in all drawings to indicate the same parts. [Brief explanation of the drawing]

[0013] [Figure 1] This is a schematic diagram showing the configuration and connections of a power supply system according to an embodiment of the present invention. [Figure 2] This is a schematic diagram showing an L-shaped network connection according to an embodiment of the present invention. [Figure 3] This is a schematic diagram illustrating a T-type network connection according to an embodiment of the present invention. [Figure 4] This is a schematic diagram showing a π-type network connection according to an embodiment of the present invention. [Figure 5] This is a schematic diagram showing the configuration and connection of an impedance matching array according to an embodiment of the present invention. [Figure 6] This is a schematic diagram showing the configuration and connection of a reactance assembly according to an embodiment of the present invention. [Figure 7] This is a schematic diagram showing the configuration and connection of a reactance assembly array, using a capacitor as an example, according to an embodiment of the present invention. [Figure 8] This is a schematic diagram showing the configuration and connection of a reactance assembly array, using an inductor as an example, according to an embodiment of the present invention. [Figure 9] This is a schematic diagram showing the connection of a reactance assembly array in which capacitors and inductors are arranged alternately, according to an embodiment of the present invention. [Figure 10]A schematic diagram showing the configuration and connection of a reactance assembly including a bypass transistor according to an embodiment of the present application. [Figure 11] A schematic diagram showing the configuration and connection of a reactance assembly array taking a capacitor as an example according to an embodiment of the present application. [Figure 12] A flowchart showing an impedance matching method of an impedance matching array according to an embodiment of the present application. [Figure 13] A schematic diagram showing the configuration and connection of a plasma radio frequency power supply system according to an embodiment of the present application.

Modes for Carrying Out the Invention

[0014] Hereinafter, preferred embodiments of the present application will be specifically described with reference to the accompanying drawings. The accompanying drawings constitute a part of the present application and are used to explain the principle of the present application together with the embodiments of the present application.

[0015] (Embodiment 1) An embodiment of the present application discloses an impedance matching array, and the impedance matching array can be applied to a matcher of a radio frequency power supply system as shown in FIG. 1, but is not limited thereto. The impedance matching array performs impedance matching in the impedance matching network of the matcher instead of an adjustable reactance element.

[0016] The impedance matching network may include an L-type network shown in FIG. 2, a T-type network shown in FIG. 3, or a π-type network shown in FIG. 4, or may include other types of impedance matching networks.

[0017] The impedance matching network may be designed to include adjustable reactance elements (adjustable capacitors, adjustable inductors) according to the matching requirements, or may be designed to include both adjustable reactance elements (adjustable capacitors, adjustable inductors) and non-adjustable fixed elements (fixed capacitors, fixed inductors). The adjustable reactance elements therein may be replaced in whole or in part by corresponding impedance matching arrays in the impedance matching network in order to achieve high-speed impedance matching according to the design requirements.

[0018] As shown in FIG. 5, the impedance matching array connected within the impedance matching network disclosed in this embodiment includes a plurality of reactance assemblies connected in parallel step by step between its input side RFin and output side RFout. The number of stages of the reactance assembly is determined by the maximum impedance value that the impedance matching array can match, and the minimum impedance value in a single-stage reactance assembly is determined by the impedance matching accuracy of the impedance matching array.

[0019] As shown in FIG. 6, the configuration of each stage of the reactance assembly is the same, and each may include a reactance unit Zj, an input transistor T1, an output transistor T2, and a series connection transistor T3. Here, the input transistor T1 of a predetermined stage is connected between the input side of the impedance matching array and the input side of the reactance unit of the predetermined stage, the output transistor T2 of the predetermined stage is connected between the output side of the reactance unit of the predetermined stage and the output side of the impedance matching array, and the series connection transistor T3 of the predetermined stage is connected between the output side of the reactance unit of the predetermined stage and the input side of the reactance unit of the next stage. By controlling the on or off states of the input transistor, output transistor, and series connection transistor within each stage of the reactance assembly, the impedance matching array is formed into a reactance combination having a predetermined connection relationship, and the corresponding reactance value is obtained to perform impedance matching.

[0020] Here, the on / off state of input transistor T1 indicates whether the reactance unit to which it belongs is a power receiving unit in a reactance combination; the on / off state of series-connected transistor T3 indicates whether the reactance unit to which it belongs is connected in series with a reactance unit in the next stage's reactance assembly; and the on / off state of output transistor T2 indicates whether it is the output of a reactance combination formed by the reactance units.

[0021] Specifically, the reactance combinations that can be formed include combinations of reactances connected in series, in parallel, or in both series and parallel configurations. The reactance units within each stage of the reactance assembly are connected sequentially according to the stage to form combinations of reactances connected in series. The reactance units within each stage of the reactance assembly are connected continuously or intermittently to form combinations of reactances connected in parallel. The combinations of series and parallel configurations are a collection of combinations of series and parallel configurations.

[0022] Each of the reactance units included in the reactance assembly described above is either a capacitor unit or an inductor unit.

[0023] As shown in Figure 7, a reactance assembly array using a capacitor as an example is shown. As can be seen from the figure, each reactance assembly is set up as a parallel connection with the same input / output. A series transistor is connected between the capacitor output side of the next stage reactance assembly and the input transistor of the predetermined stage. The final stage reactance assembly does not have a next stage reactance assembly, so the series transistor within it is omitted and not used.

[0024] By controlling the on or off states of the input transistor, output transistor and series-connected transistor within the reactance assembly, the reactance combinations formed include combinations of series-connected capacitors, combinations of parallel-connected capacitors, or combinations of series-connected and parallel-connected capacitors.

[0025] In the case of series connection of capacitors, the stage numbers of each reactance assembly must be consecutive. That is, among the reactance assemblies with consecutive numbers, the input transistor of the first reactance assembly turns on, the output transistor of the last reactance assembly turns on, and the series-connected transistors of the remaining intermediate stage reactance assemblies turn on, thus forming a series connection of capacitors circuit.

[0026] In the case of parallel capacitor connections, the reactance assemblies of each stage connected in parallel do not need to be numbered consecutively; they can be selected according to the requirements. The series-connected transistors between each parallel branch are turned off, and the input and output transistors are turned on, forming a parallel capacitor circuit.

[0027] In the case of series / parallel connection of capacitors, any branch constituting the parallel connection circuit may be a series connection branch. Within the series connection branch, capacitors with consecutive numbers are connected in series according to the control method for series connection described above, and each series connection branch is connected in parallel according to the control method for parallel connection of capacitors, thereby constituting a series / parallel connection circuit of capacitors.

[0028] In the diagram, the series connection circuit with consecutively numbered transistors C5, C6, ... CA is formed by turning on the input transistor C5, turning off the output transistor CA, turning on the series-connected transistors between C5 and CA, and turning off the remaining switchable transistors.

[0029] In the diagram, the parallel connection circuits where the numbers C3, C9, ... CB are not consecutive are formed by turning on the input transistors and output transistors from C3, C9 to CB, and turning off the series-connected transistors.

[0030] In the diagram, of each parallel connection branch of the formed series / parallel connection circuit, In the first branch C10, the input and output transistors of C10 are turned on, and the series-connected transistors are turned off. In the second branch C14-C16, the input transistor C14 turns on, the output transistor C16 turns on, the series-connected transistors C14 and C15 turn on, and the remaining switchable transistors turn off. ... In the final branch CC-3~CC, the input transistor of CC-3 is on, the output transistor of CC is on, the series-connected transistors between CC-3 and CC are on, and the remaining switchable transistors are off.

[0031] Based on the above analysis, the configuration rules for series and parallel connections are as follows:

[0032] (1) Form one or more series connection sections in response to the demand for series connection, (2) Connect the series sections to each other, or connect one or more independent capacitors to form a parallel connection of two or more branches, (3) The same reactance unit shall be limited to being used in one series connection, one parallel connection, or not used at all.

[0033] In each of the above series connections, parallel connections, or combinations thereof, the capacitors are not limited to being used in order from the highest or lowest value, as long as the result of the combination matches the target capacitance value.

[0034] In a preferred embodiment, a correspondence table between the switching state of the switchable transistors in each capacitor assembly within the capacitor assembly array and the capacitance value of the resulting capacitor array may be formed as a combination lookup table. By obtaining the switch combination state corresponding to the capacitance value to be matched using the lookup table method, and performing switching control of the capacitor assembly array, the capacitance value to be matched is obtained.

[0035] As shown in Figure 8, a reactance assembly array with an inductor as an example is shown. As can be seen from the figure, each reactance assembly is set up as a parallel connection with the same input / output, and a series-connected transistor is connected between the inductor output side of the next stage reactance assembly and the input transistor of the predetermined stage. The final stage reactance assembly does not have a next stage reactance assembly, so the series-connected transistor within it is not used and is omitted.

[0036] By controlling the on or off states of the input transistor, output transistor, and series-connected transistor within the reactance assembly, the reactance combinations formed include combinations of series-connected inductors, combinations of parallel-connected inductors, or combinations of series-connected and parallel-connected inductors.

[0037] In the case of a series connection of inductors, the stage numbers of each reactance assembly must be consecutive. That is, among the reactance assemblies with consecutive numbers, the input transistor of the first reactance assembly turns on, the output transistor of the last reactance assembly turns on, and the series-connected transistors of the remaining intermediate stage reactance assemblies turn on, thus forming a series-connected inductor circuit.

[0038] In the case of parallel inductor connections, the numbers of the reactance assemblies in each stage connected in parallel do not need to be consecutive; they can be selected according to the requirements. The series-connected transistors between each parallel branch are turned off, and the input and output transistors are turned on, forming the inductor parallel connection circuit.

[0039] In the case of series / parallel connection of inductors, any branch constituting the parallel connection circuit may be a series connection branch. Within the series connection branch circuit, inductors with consecutive stage numbers are connected in series according to the control method for series connection of inductors described above, and each series connection branch is connected in parallel according to the control method for parallel connection of inductors, thereby constituting a series / parallel connection circuit of inductors.

[0040] In the diagram, the series connection circuit with consecutively numbered transistors L5, L6, ... LA is formed by turning on the input transistor L5, turning off the output transistor LA, turning on the series-connected transistors between L5 and LA, and turning off the remaining switchable transistors.

[0041] In the diagram, the parallel connection circuits where the numbers L3, L9...LB are not consecutive are formed by turning on the input transistors and output transistors from L3, L9 to LB, and turning off the series-connected transistors.

[0042] In the diagram, of each parallel connection branch of the formed series / parallel connection circuit, In the first branch L1-L2, the input transistor of L1 turns on, the output transistor of L2 turns on, the series-connected transistors of L1 turn on, and the remaining switchable transistors turn off. In the second branch L10, the input and output transistors of L10 are turned on, and the series-connected transistors are turned off. ... In the final branch LC-3~LC, the input transistor of CC-3 is on, the output transistor of LC is on, the series-connected transistors between LC-3~LC are on, and the remaining switchable transistors are off.

[0043] Based on the above analysis, the configuration rules for series and parallel connections are as follows:

[0044] (1) Form one or more series connection sections in response to the demand for series connection, (2) Connecting series sections to each other, or connecting one or more independent inductors to two or more branches in parallel, (3) The same reactance unit shall be limited to being used in one series connection, one parallel connection, or not used at all.

[0045] In each of the above series connections, parallel connections, or combinations thereof, the use of the inductors is not limited to the highest or lowest inductor, as long as the result of the combination matches the target inductance value.

[0046] In a preferred embodiment, a correspondence table between the switching state of the switchable transistors in each inductor assembly within the inductor assembly array and the inductance value of the formed inductor array may be formed as a combination lookup table. By obtaining the switch combination state corresponding to the inductance value to be matched using the lookup table method, the inductance value to be matched is obtained by controlling the switching of the inductor assembly array.

[0047] Furthermore, in a reactance assembly connected in parallel in stages, the reactance units alternate between capacitors and inductors. If the reactance units in a given stage of the reactance assembly are capacitive elements, then the reactance units in the next stage of the reactance assembly will be inductive elements, and vice versa.

[0048] Figure 9 shows a schematic diagram of a connection in which capacitors and inductors are arranged alternately.

[0049] As can be seen from the diagram, each reactance assembly is set up as a parallel connection with the same input / output, with capacitors and inductors arranged alternately. If a given stage of reactance assembly has capacitive elements, the next stage of reactance assembly has inductive elements, and a series transistor is connected between the inductor output side of the next stage of reactance assembly and the input transistor of the given stage. The final stage of reactance assembly does not have a next stage of reactance assembly, so the series transistor within it is omitted and not used.

[0050] By controlling the on or off states of the input transistor, output transistor and series-connected transistor within the reactance assembly, the reactance combinations formed include combinations of capacitor-parallel connections, inductor-parallel connections, capacitor-inductor-parallel connections, alternating LC series connections, or series and parallel connections.

[0051] In this case, with parallel capacitor connections, the series-connected transistors of each stage of reactance assemblies containing capacitive elements are turned off, and the input and output transistors are turned on, forming a parallel capacitor connection circuit.

[0052] In the case of parallel inductor connection, the series-connected transistors of each stage of reactance assembly containing inductance elements are turned off, and the input transistor and output transistor are turned on, forming an inductor parallel connection circuit.

[0053] In the case of a capacitor-inductor parallel connection, the series-connected transistors of each stage of the reactance assembly, which includes capacitive and inductive elements connected in parallel, are turned off, while the input and output transistors are turned on, forming a capacitor-inductor parallel connection circuit.

[0054] In the case of alternating LC series connections, the stage numbers of the reactance assemblies in each stage must be consecutive. That is, among the reactance assemblies with consecutive numbers, the input transistor of the first reactance assembly turns on, the output transistor of the last reactance assembly turns on, and the series-connected transistors of the remaining intermediate stage reactance assemblies turn on, forming an inductor series connection circuit.

[0055] When two consecutive reactance assemblies constitute an alternating LC series connection, an LC series connection circuit can be formed in which a capacitor is connected to an inductor, or an inductor is connected to a capacitor.

[0056] When three consecutive reactance assemblies constitute an alternating LC series connection, a capacitor can be connected to an inductor, and then to another capacitor, or an inductor can be connected to a capacitor, and then to another inductor, forming an LC series connection circuit.

[0057] In this way, a multi-stage LC series connection circuit with alternating LC configurations can be formed.

[0058] In the case of series / parallel connection, any branch constituting the parallel connection circuit may be an LC alternating series connection branch. Within the series connection branch circuit, inductors and capacitors with consecutive numbers are connected alternately in series according to the control method for the LC alternating series connection described above, and each series connection branch is connected in parallel according to the control method for the parallel connection to constitute a series / parallel connection circuit.

[0059] In each of the above series connections, parallel connections, or combinations thereof, the capacitors or inductors are not limited to being used in order from the highest or lowest value, as long as the result of the combination matches the target reactance value.

[0060] In a preferred embodiment, a correspondence table between the switching states of the on / off transistors of each reactance assembly in the reactance assembly array and the reactance values ​​of the formed reactance array may be formed as a combination lookup table. By obtaining the switch combination state corresponding to the reactance value to be matched using the lookup table method, the switching control of the reactance assembly array is performed to obtain the reactance value to be matched.

[0061] In another embodiment of this design, as shown in Figure 10, the reactance assembly further includes a bypass transistor T4 in addition to the reactance unit Zj, input transistor T1, output transistor T2, and series-connected transistor T3. The bypass transistor for a given stage is connected between the output side of the reactance unit for that stage and the output side of the reactance unit for the next stage. By adding the bypass transistor T4, a variety of series-parallel connection combinations can be realized, including series connections of reactance elements across stages.

[0062] Specifically, in an impedance matching array using a reactance assembly that includes a bypass transistor, the capacitance values ​​of the capacitive elements in each reactance assembly may be different, and the inductance values ​​of the inductance elements in each reactance assembly may be different, thus forming a reactance element array with different capacitance or inductance values.

[0063] Furthermore, the basic principle of an impedance matching array using a reactance assembly that includes bypass transistors is similar to that of an impedance matching array using a reactance assembly that does not include bypass transistors. The difference between the two is that in an impedance matching array using a reactance assembly that includes bypass transistors, when the bypass transistors are turned on, more impedance control is possible depending on the control of the on / off transistors in the next stage of the reactance unit.

[0064] As shown in Figure 11, in an example of an impedance matching array using capacitive elements, the following are examples of multiple series-parallel connections formed by the ON control of bypass transistors.

[0065] (1) When the bypass transistor of capacitor C1 is ON / the series-connected transistor is OFF / the output transistor is OFF, the input transistor of capacitor C2 is OFF / the output transistor is OFF / the bypass transistor is OFF / the series-connected transistor is ON, and the input transistor of capacitor C3 is OFF, capacitor C2 can be bypassed and capacitors C1 and C3 can be connected in series.

[0066] (2) When the bypass transistor of capacitor C1 turns on / the series-connected transistor turns off / the output transistor turns off, the input transistor of capacitor C2 turns on / the series-connected transistor turns on / the bypass transistor turns off / the output transistor turns off, and the input transistor of capacitor C3 turns off, capacitors C1 and C2 are connected in parallel and then connected in series with capacitor C3.

[0067] (3) When the bypass transistor of capacitor C1 turns on / the series-connected transistor turns off / the output transistor turns off, the input transistor of capacitor C2 turns off / the series-connected transistor turns on / the bypass transistor turns on / the output transistor turns off, the input transistor of capacitor C3 turns on / the series-connected transistor turns on / the bypass transistor turns off / the output transistor turns off, and the input transistor of capacitor C4 turns off, capacitors C1 and C3 are connected in parallel and then connected in series with capacitor C4.

[0068] Otherwise, when all bypass transistors in an impedance matching array with a reactance assembly that includes bypass transistors are turned off, it is in the same use as an impedance matching array with a reactance assembly that does not include bypass transistors. Therefore, it offers greater flexibility in use.

[0069] Specifically, when forming a series connection circuit from C4, C7, C9...CA in the diagram, First, a series connection is formed between C4 and C7. When the input transistor of C4 is turned on, the bypass transistors of C4 and C5 are turned on, the series-connected transistor of C6 is turned on, and the remaining control transistors from C4 to C7 are turned off, the series connection relationship between C4 and C7 is formed.

[0070] Next, by forming a series connection between C7 and C9, and switching control such that the bypass transistor of C7 turns on, the series-connected transistor of C8 turns on, and the remaining control transistors from C7 to C9 turn off, a series connection relationship between C7 and C9 is formed.

[0071] Connect the capacitors one by one in series according to this control relationship. Finally, until CA is connected in series, the output transistor of CA is turned on, and the series connection circuit is formed from the input side, C4, C7, C9... to CA and then to the output side.

[0072] In the diagram, when forming a parallel connection circuit from C3, C8, C1, ... LB, the input transistors and output transistors from C3, C8, C1, ... LB are turned on, and the series-connected transistors and bypass transistors are turned off, thereby forming a parallel-connected inductor from C3, C8, C1, ... LB.

[0073] In the diagram, when forming a series / parallel connection circuit, each branch connected in parallel must be numbered sequentially. Within each branch, the series capacitors included must be numbered in ascending order, and the maximum capacitor number in the preceding branch must be less than the minimum capacitor number in the following branch.

[0074] In each branch, if non-consecutive capacitors are connected in series, refer to the control method for connecting non-consecutive capacitors in series as described above to form a series capacitor group. Refer to the control method described above, which involves connecting non-consecutive capacitor numbers in parallel to multiple branches, and connect each branch in parallel to form a series / parallel connection circuit.

[0075] Based on the above analysis, the configuration rules for series and parallel connections are as follows:

[0076] (1) Depending on the demand for series connection, one or more series connection sections may be formed, and the capacitors connected in series do not need to be consecutive; it is sufficient that the capacitor number of the preceding section is smaller than that of the following section. (2) Connect the series sections to each other, or connect one or more independent capacitors to form a parallel connection of two or more branches, (3) The same reactance unit shall be limited to being used in one series connection, one parallel connection, or not used at all.

[0077] In each of the above series connections, parallel connections, or combinations thereof, the capacitors are not limited to being used in order from the highest or lowest value, as long as the result of the combination matches the target capacitance value.

[0078] In a preferred embodiment, a correspondence table between the switching state of the switchable transistors in each capacitor assembly within the capacitor assembly array and the capacitance value of the resulting capacitor array may be formed as a combination lookup table. By obtaining the switch combination state corresponding to the capacitance value to be matched using the lookup table method, and performing switching control of the capacitor assembly array, the capacitance value to be matched is obtained.

[0079] Technical details of an impedance matching array composed of inductance elements, including bypass transistors, can be obtained by referring to the impedance matching array composed of capacitive elements described above.

[0080] The technical details of an impedance matching array in which inductors and capacitors are arranged alternately and which includes bypass transistors can also be obtained by combining an impedance matching array in which capacitors and inductors are arranged alternately and which does not include bypass transistors with an impedance matching array composed of the capacitive elements described above.

[0081] Based on the above, according to the embodiment of the present invention, rapid impedance matching is achieved by quickly changing the impedance value by switching each switchable transistor in the reactance assembly. The adjustable reactance elements in the matcher are replaced with an impedance matching array, and an array-type design is adopted, making the design and manufacturing relatively simple. If there is sufficient space and enough reactance units can be arranged, more impedance matching points can be accommodated in the matcher, thus enabling more efficient impedance matching of the process.

[0082] Example 2 One embodiment of the present application discloses an impedance matching method based on the impedance matching array described in Example 1, and as shown in Figure 12, the method is Step S1 involves creating an impedance matching lookup table for the impedance matching array, where each impedance matching value corresponds to an on / off transistor combination scheme of one reactance assembly. Step S2 involves referencing an impedance combination lookup table based on the required impedance matching value, selecting a corresponding on / off transistor combination scheme, and controlling the connection scheme of the reactance units in the impedance matching array to achieve impedance matching. Step S3 includes, if a matched reactance value does not exist in the impedance combination lookup table, performing an approximate fast match, generating control instructions for an on / off transistor, controlling the connection method of the reactance units in the impedance matching array, and achieving an approximate impedance match.

[0083] Specifically, in approximate fast matching, The method for creating an impedance combination lookup table where the total number of impedance units is n is included, and the method for creating the table is: In the first cycle, activate one impedance unit, In the second cycle, activate the two impedance units, (1) The number of rows formed shall be a maximum of 1, and the number of serial connections per row shall be a maximum of 2. (2) The number of rows formed shall be a maximum of 2, and the number of serial connections per row shall be a maximum of 1. In the third cycle, activate the three impedance units, (1) The number of rows formed shall be a maximum of 1, and the number of serial connections per row shall be a maximum of 3. (2) The number of rows formed shall be a maximum of 2, and the number of serial connections per row shall be a maximum of 2. (3) The number of rows formed shall be a maximum of 3, and the number of serial connections per row shall be a maximum of 1. ... In the nth cycle, n impedance units are activated, (1) The maximum number of rows formed is 1, and the maximum number of serial connections per row is n. (2) The number of rows formed shall be a maximum of 2, and the number of serial connections per row shall be a maximum of n-1, (3) The number of rows formed shall be a maximum of 3, and the number of serial connections per row shall be a maximum of n-2, ... (n-1) The maximum number of rows formed is n-1, and the maximum number of serial connections per row is 2. (n) The maximum number of rows formed is n, and the maximum number of serial connections per row is 1. During the execution of a cycle, the reactance value formed each time an execution is performed is recorded, and for each activated impedance unit, the switching states of the input transistor, output transistor, and series-connected transistors corresponding to the number of parallel and series-connected rows to which it belongs are recorded, and only one set of settings is retained for the same reactance value.

[0084] Furthermore, if the reactance assembly further includes bypass transistors, the process includes recording the reactance values ​​formed during each run of the impedance combination lookup table creation cycle, recording the corresponding switching states of the input transistors, output transistors, series-connected transistors, and bypass transistors for each activated impedance unit, for the number of parallel and series connections to which it belongs, and leaving only one set of settings for the same reactance value.

[0085] Furthermore, in approximate high-speed matching, if all reactance units in the impedance matching array are capacitor units, step S3 is performed. (1) A step of converting a consistent capacity value into a fraction, wherein the denominator is factorizable into prime factors less than 10, the numerator is 1 / 4 less than the denominator, and the numerator is a mixed number greater than or equal to 1, the step of borrowing 1 from the mixed number to make it an improper fraction, (2) Find all the prime factors of the denominator, select the largest prime factor from among them, and gradually increase or decrease the numerator until it is a multiple of the nearest largest prime factor, (3) Simplify the fraction to obtain an irreducible fraction, convert it to a mixed number if it is an improper fraction, and then perform a table lookup process. If the numerator of the proper fraction part of the mixed number is not 1, decompose the proper fraction part into multiple fractions with a numerator of 1 and then perform a table lookup process. (4) If a lookup table is not set, the integer parts of the mixed number are considered to be the number of capacitors connected in parallel, the numerator of the proper fraction is the number of rows and the denominator is the number of capacitors connected in series per row, and the proper fraction can be further simplified to an irreducible fraction in order to reduce the number of capacitors to be activated.

[0086] Furthermore, in approximate high-speed matching, if all reactance units in the impedance matching array are inductor units, step S3 is performed. (1) A step of converting the matching inductance value into a fraction, wherein the denominator is factorizable into prime factors less than 10, the numerator is 1 / 4 less than the denominator and has a mixed number of 1 or greater, and the step of borrowing 1 from the mixed number to make it an improper fraction, (2) Find all the prime factors of the denominator, select the largest prime factor from among them, and gradually increase or decrease the numerator until it is a multiple of the nearest largest prime factor, (3) Simplify the fraction to obtain an irreducible fraction, convert it to a mixed number if it is an improper fraction, and then perform a table lookup process. If the numerator of the proper fraction part of the mixed number is not 1, decompose the proper fraction part into multiple fractions with a numerator of 1 and then perform a table lookup process. (4) If a lookup table is not set, the integer part of the mixed number is considered to be the number of inductors connected in series, the numerator of the proper fraction is the number of pairs of inductors connected in parallel, and the denominator is the number of inductors connected in parallel per pair, and the proper fraction can be further simplified to an irreducible fraction in order to reduce the number of inductors that are enabled.

[0087] For more specific technical details and beneficial effects in this embodiment, please refer to Example 1 described above; therefore, a detailed explanation will be omitted here.

[0088] Example 3 One embodiment of the present application discloses a radio frequency power supply system including a radio frequency power supply, a matching circuit, and a load. The radio frequency power supply outputs a power signal to a matching circuit, and the impedance matching network within the matching circuit performs impedance matching before transferring the power signal to the load.

[0089] Specifically, the adjustable reactance elements included in the impedance matching network within the matching circuit can be replaced with the impedance matching array described in Example 1. During impedance matching, impedance matching is achieved by adjusting the impedance by switching each switchable transistor in the reactance assembly of the impedance matching array to form a reactance combination with a predetermined connection relationship.

[0090] Specific technical details and beneficial effects in this embodiment can be found in Example 1, so a detailed explanation is omitted here.

[0091] Example 4 One embodiment of the present invention discloses a plasma radio frequency system including a radio frequency power supply, a matching unit, and a chamber load, as shown in Figure 13. The radio frequency power supply outputs a power signal to a matching circuit, and the impedance matching network within the matching circuit performs impedance matching before transferring the power signal to the chamber load.

[0092] Specifically, the adjustable reactance elements included in the impedance matching network within the matching circuit can be replaced with the impedance matching array described in Example 1. During operation, if a load change occurs in the chamber load due to the execution of the process, the on / off transistor in each reactance assembly within the impedance matching array included in the inductance matching network can be controlled in response to the load change to form a corresponding reactance combination and adjust the impedance, thereby bringing the impedance of the matcher and the chamber load closer to an ideal value and stabilizing it.

[0093] Specific technical details and beneficial effects in this embodiment can be found in Example 1, so a detailed explanation is omitted here.

[0094] The foregoing description is merely a preferred specific embodiment of the present application, and the scope of protection of the present application is not limited thereto. A person skilled in the art would readily conceive of any modifications or substitutions within the technical scope disclosed herein, and all such modifications or substitutions should be considered to fall within the scope of protection of the present application.

Claims

1. An impedance matching array, Connected within an impedance matching network, the input and output sides of the impedance matching array include multiple reactance assemblies connected in a stepped parallel configuration, with each stage of the reactance assembly including a reactance unit, an input transistor, an output transistor, and a series-connected transistor. The input transistor of a predetermined stage is connected between the input side of the impedance matching array and the input side of the reactance unit of a predetermined stage. The output transistor of a predetermined stage is connected between the output side of the reactance unit of the predetermined stage and the output side of the impedance matching array. A predetermined series-connected transistor is connected between the output side of the predetermined stage reactance unit and the input side of the next stage reactance unit. By controlling the on or off states of the input transistors, output transistors, and series-connected transistors within each stage of the reactance assembly, the impedance matching array is formed into a reactance combination with a predetermined connection relationship, thereby achieving impedance matching. An impedance matching array characterized by the following:

2. The formed reactance combination includes combinations by series connection, combinations by parallel connection, or combinations by series and parallel connection. In a series connection configuration, the reactance units within each stage reactance assembly are connected sequentially according to the stage. In a combination using parallel connections, the reactance units within each stage reactance assembly include continuous or intermittent connections. The combinations of series and parallel connections are the set of combinations of series connections and combinations of parallel connections. The impedance matching array according to feature 1.

3. Each of the reactance units included in the reactance assembly of each stage is either a capacitor unit or an inductor unit. The impedance matching array according to feature 1.

4. In the reactance assembly connected in a stepwise parallel configuration, the reactance unit is arranged such that capacitors and inductors are alternately arranged. If the reactance unit in the predetermined stage of the reactance assembly is a capacitive element, The reactance unit in the next stage of the reactance assembly is an inductance element. The impedance matching array according to feature 1.

5. The reactance assembly further comprises a bypass transistor, The bypass transistor of the predetermined stage is connected between the output side of the reactance unit of the predetermined stage and the output side of the reactance unit of the next stage. The impedance matching array according to feature 1.

6. In an impedance matching array using the reactance assembly including the bypass transistor, The capacitance values ​​of the capacitive elements in each reactance assembly are different. The inductance values ​​of the inductors in each reactance assembly are different. An array of reactance elements with different capacitance or inductance values ​​is formed. The impedance matching array according to claim 5.

7. A step of creating an impedance combination lookup table for an impedance matching array, the step S1 of which, in the impedance combination lookup table, each impedance matching value realized by the impedance matching array corresponds to an on / off transistor combination scheme of one reactance assembly, Step S2 involves referencing an impedance combination lookup table based on the required impedance matching value, selecting a corresponding on / off transistor combination scheme, and controlling the connection scheme of the reactance units in the impedance matching array to achieve impedance matching. Step S3: If a matched reactance value does not exist in the impedance combination lookup table, approximate high-speed matching is performed, control commands for the on / off transistor are generated, the connection method of the reactance units in the impedance matching array is controlled, and approximate impedance matching is achieved. An impedance matching method based on an impedance matching array according to any one of claims 1 to 6, characterized by including the following:

8. In the aforementioned approximation high-speed matching, The method for creating an impedance combination lookup table where the total number of impedance units is n is included, and the method for creating the table is: In the first cycle, one impedance unit is activated, In the second cycle, activate the two impedance units, (1) The number of rows formed shall be a maximum of 1, and the number of serial connections per row shall be a maximum of 2. (2) The number of rows formed shall be a maximum of 2, and the number of serial connections per row shall be a maximum of 1. In the third cycle, activate the three impedance units. (1) The number of rows formed shall be a maximum of 1, and the number of serial connections per row shall be a maximum of 3. (2) The number of rows formed shall be a maximum of 2, and the number of serial connections per row shall be a maximum of 2, (3) The number of rows formed shall be a maximum of 3, and the number of serial connections per row shall be a maximum of 1. … In the nth cycle, n impedance units are activated, (1) The maximum number of rows formed is 1, and the maximum number of serial connections per row is n. (2) The number of rows formed shall be a maximum of 2, and the number of series connections per row shall be a maximum of n-1, (3) The number of rows formed shall be a maximum of 3, and the number of series connections per row shall be a maximum of n-2, … (n-1) The maximum number of rows formed is n-1, and the maximum number of serial connections per row is 2. (n) The maximum number of rows formed is n, and the maximum number of serial connections per row is 1. During the execution of a cycle, the reactance value formed each time an execution is performed is recorded, and for each activated impedance unit, the switching states of the input transistor, output transistor, and series-connected transistors corresponding to the number of parallel and series connections to which it belongs are recorded, and only one set of settings is retained for the same reactance value. The impedance matching method according to feature 7.

9. If the reactance assembly further includes bypass transistors, during the execution of a cycle in creating an impedance combination lookup table, the reactance values ​​formed each time the cycle is executed are recorded, and for each activated impedance unit, the switching states of the input transistor, output transistor, series-connected transistor and bypass transistor that match the reactance unit are recorded correspondingly for the number of parallel-connected rows and series-connected rows to which it belongs, and only one set of settings is retained for the same reactance value. The impedance matching method according to feature 8.

10. In the aforementioned approximate high-speed matching, if all reactance units in the impedance matching array are capacitor units, step S3 is performed. (1) A step of converting a consistent capacity value into a fraction, wherein the denominator can be factorized into prime factors less than 10, and the numerator is 1 / 4 less than the denominator and has a mixed number of 1 or more, by borrowing 1 from the mixed number to make it an improper fraction. (2) Find all the prime factors of the denominator, select the largest prime factor from among them, and gradually increase or decrease the numerator until it is a multiple of the nearest largest prime factor, (3) The fraction is simplified to obtain an irreducible fraction, and if it is an improper fraction, it is converted to a mixed number and then a table lookup is performed. If the numerator of the proper fraction part of the mixed number is not 1, the proper fraction part is decomposed into multiple fractions with a numerator of 1 and then a table lookup is performed. (4) If a lookup table is not set, the integer part of the mixed number is considered to be the number of capacitors connected in parallel, the numerator of the proper fraction is the number of rows, and the denominator is the number of capacitors connected in series per row. If the proper fraction can be further simplified, the step of simplifying it to an irreducible fraction is performed in order to reduce the number of capacitors that are activated. The impedance matching method according to claim 7, characterized by including the following:

11. In the aforementioned approximate high-speed matching, if all reactance units in the impedance matching array are inductor units, step S3 is performed. (1) A step of converting the matching inductance value into a fraction, wherein the denominator can be decomposed into prime factors less than 10, and the numerator is 1 / 4 less than the denominator and has a mixed number of 1 or more, by borrowing 1 from the mixed number to make it an improper fraction, (2) Find all the prime factors of the denominator, select the largest prime factor from among them, and gradually increase or decrease the numerator until it is a multiple of the nearest largest prime factor, (3) The fraction is simplified to obtain an irreducible fraction, and if it is an improper fraction, it is converted to a mixed number and then a table lookup is performed. If the numerator of the proper fraction part of the mixed number is not 1, the proper fraction part is decomposed into multiple fractions with a numerator of 1 and then a table lookup is performed. (4) If a lookup table is not set, the integer part of the mixed number is considered to be the number of inductors connected in series, the numerator of the proper fraction is considered to be the number of pairs of inductors connected in parallel, and the denominator is considered to be the number of inductors connected in parallel per pair. If the proper fraction can be further simplified, the step of simplifying it to an irreducible fraction is performed in order to reduce the number of active inductors. The impedance matching method according to claim 7, characterized by including the following:

12. A radio frequency power supply system, Equipped with sequentially connected radio frequency power supplies, matching units, and loads, The matching device includes an impedance matching array according to any one of claims 1 to 6, and performs impedance matching by controlling each switchable transistor in each stage reactance assembly within the impedance matching array to form a reactance combination with a predetermined connection relationship and adjust the impedance. A radio frequency power supply system characterized by the following features.

13. Includes sequentially connected radio frequency power supplies, matching units, and chamber loads, The matching device includes an impedance matching array as described in any one of claims 1 to 6, and when a load change occurs in the chamber load due to the execution of the process, it controls each on / off transistor in each reactance assembly in the impedance matching array in accordance with the load change, forming a corresponding reactance combination and adjusting the impedance so that the impedance coupled between the matching device and the chamber load approaches an ideal value and stabilizes. A plasma radio frequency system characterized by the following features.

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