Simulation method and electronic equipment

Abstract

The present disclosure provides a simulation method and electronic device that uses a circuit netlist and stimulus file to perform simulation and obtain the time difference between a clock signal and a data signal. Because the circuit netlist only includes the netlist of the chip's clock signal receiving circuit and the netlist of the data signal receiving circuit, the circuit netlist structure is relatively simple. When using the circuit netlist and stimulus file for simulation, the time difference between the chip's clock signal and data signal is obtained faster and in less time, greatly improving simulation efficiency.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a simulation method and electronic equipment. Background Art

[0002] Low Power Double Data Rate (LPDDR) is a communication standard for semiconductor devices. In semiconductor devices using standards such as LPDDR4 and LPDDR5, the device receives clock and data signals and samples the data signal based on the clock signal. Once the semiconductor device design is complete, simulation can be used to determine the time difference between the clock and data signals actually received by the device. This allows the device to more accurately sample the data signal based on the clock signal after eliminating this time difference.

[0003] However, in the prior art, the simulation time required to determine the time difference between the clock signal and the data signal of a semiconductor device is relatively long. Therefore, reducing the simulation time required to determine the time difference between the clock signal and the data signal of a semiconductor device is a technical problem that needs to be solved in this field. Summary of the Invention

[0004] The present disclosure provides a simulation method and electronic device. Based on the technical problem in the prior art that the simulation time required to determine the time difference between the clock signal and the data signal of a chip is long, the present disclosure performs simulation through a circuit netlist and an incentive file including a netlist of a clock signal receiving circuit and a netlist of a data signal receiving circuit, so as to reduce the simulation time required to simulate the time difference between the clock signal and the data signal.

[0005] A first aspect of the present disclosure provides a simulation method, comprising: obtaining a circuit netlist, the circuit netlist including a netlist of a clock signal receiving circuit and a netlist of a data signal receiving circuit, the clock signal receiving circuit being used to receive a clock signal, and the data signal receiving circuit being used to receive a data signal; generating an excitation file, the excitation file including clock information and data information; performing simulation based on the circuit netlist and the excitation file to obtain a time difference between the clock signal and the data signal.

[0006] In an embodiment of the first aspect of the present disclosure, the number of netlists of the clock signal receiving circuit and the number of netlists of the data signal receiving circuit are both one.

[0007] In an embodiment of the first aspect of the present disclosure, the data information includes a first data signal and a transmission rate of the first data signal.

[0008] In an embodiment of the first aspect of the present disclosure, a transmission rate of the first data signal is 6.4 Gbit / s.

[0009] In an embodiment of the first aspect of the present disclosure, the clock information includes the time of each shift of the clock signal and the maximum time range of the shift of the clock signal.

[0010] In an embodiment of the first aspect of the present disclosure, the time for each shift of the clock signal is 0.01ns.

[0011] In an embodiment of the first aspect of the present disclosure, the maximum time range of the clock signal shift is -1.5T-1T, where T is the period of the clock signal.

[0012] In an embodiment of the first aspect of the present disclosure, the simulation based on the circuit netlist and the stimulus file to obtain the time difference between the clock signal and the data signal also includes: performing simulation based on the circuit netlist and the stimulus file to obtain a second data signal obtained by the circuit netlist simulation; comparing the second data signal with the first data signal; determining the shift time range of the clock signal when the first data signal and the second data signal are the same; and determining the time difference between the clock signal and the data signal based on the shift time range.

[0013] In an embodiment of the first aspect of the present disclosure, the time difference between the clock signal and the data signal is a middle value of the shift time range.

[0014] The second aspect of the present disclosure provides an electronic device, comprising: at least one processor and a memory; the memory stores computer-executable instructions; the at least one processor executes the computer-executable instructions stored in the memory, so that the at least one processor executes the method as described in any one of the first aspects of the present disclosure.

[0015] The simulation method and electronic device provided by the present disclosure utilize a circuit netlist and stimulus file to perform simulation and obtain the time difference between the clock signal and the data signal. Because the circuit netlist only includes the netlist of the chip's clock signal receiving circuit and the netlist of the data signal receiving circuit, the circuit netlist structure is relatively simple. When simulating using the circuit netlist and stimulus file, the time difference between the chip's clock signal and data signal is obtained more quickly and in less time, significantly improving simulation efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0017] Figure 1 A schematic diagram of the structure of a chip;

[0018] Figure 2 A timing diagram of the chip provided in the present disclosure processing a signal;

[0019] Figure 3 Another timing diagram of the chip provided by the present disclosure when processing signals;

[0020] Figure 4 A schematic diagram of a flow chart of an embodiment of a simulation method provided by the present disclosure;

[0021] Figure 5 A schematic diagram of a circuit netlist provided by the present disclosure;

[0022] Figure 6 A schematic diagram of clock information and data information;

[0023] Figure 7 A schematic diagram of the time range of the shift provided for the present disclosure;

[0024] Figure 8 A schematic structural diagram of an embodiment of a simulation device provided by the present disclosure;

[0025] Figure 9 A schematic structural diagram of an electronic device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0027] The terms "first," "second," "third," "fourth," and the like (if any) in the specification and claims of the present disclosure and in the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or sequential sequence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of the present disclosure described herein, for example, can be implemented in orders other than those illustrated or described herein. In addition, the terms "including" and "having," and any variations thereof, are intended to cover non-exclusive inclusions, e.g., a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0028] Low Power Double Data Rate (LPDDR) is a communication standard for semiconductor devices. In semiconductor devices using standards such as LPDDR4 and LPDDR5, the devices receive clock and data signals and sample the data signals based on the clock signal.

[0029] For example, Figure 1 This is a schematic diagram of the structure of a chip. Figure 1 The chip shown can be used to receive a command signal through the CA pin, multiple data signals through the DQ pin, and multiple clock signals through the CLK pin. In one embodiment, the chip can receive 16 data signals through one DQ pin and receive a clock signal through the CLK pin.

[0030] Figure 2 This is a timing diagram of the chip provided by the present disclosure when processing signals. Figure 2 As shown, Figure 1 The chip can receive the clock signal through the clock signal receiving circuit. At the same time, the chip receives the data signal through the data receiving circuit connected to the DQ pin. Figure 2 In the example shown, the data signals include D1, D2, D3, ... in sequence.

[0031] In one embodiment, the chip can sample the data signal according to the clock signal. Figure 2 In the example shown, the chip can sample the data signal at the rising edge of the clock signal. Specifically, the chip samples the data signal D1 at the rising edge R1 of the clock signal, samples the data signal D2 at the rising edge R2, samples the data signal D3 at the rising edge R3, and so on.

[0032] from Figure 2As can be seen in Figure 2, when the chip samples and processes the data signal based on the clock signal, the clock signal and the data signal are in one-to-one correspondence in terms of timing. However, in one embodiment, during actual operation, although the chip receives the clock signal and the data signal simultaneously, the clock signal and the data signal are not transmitted completely in sync, resulting in a certain time difference between the clock signal and the data signal actually received by the chip.

[0033] For example, Figure 3 Another timing diagram for the chip processing signal provided by the present disclosure, such as Figure 3 As shown in FIG, the rising edge of the clock signal received by the chip through the clock signal receiving circuit when it is transmitted to the data receiving circuit does not correspond one-to-one with the data signal received by the chip through the data signal receiving circuit in terms of timing, but there is a large time difference. Figure 3 Taking the rising edge R1 of the clock signal and the midpoint of the data signal D1 as an example, the time difference between the clock signal and the data signal is Td. For LPDDR4 chips, the time difference between the clock and data signals can be expressed as tdqs2dq; for LPDDR5 chips, the time difference between the clock and data signals can be expressed as tWCK2DQI. If the chip directly samples the data signal based on the clock signal, it is likely that the data signal will not be accurately obtained, affecting the chip's subsequent processing of the data signal.

[0034] After the semiconductor device design is completed, it can be tested and verified by simulation. Figure 1 After the chip design is completed, testers can use test equipment to simulate the chip's netlist. The test equipment can be electronic devices such as computers, servers, and workstations.

[0035] Therefore, after the chip designer designs the chip netlist, the chip tester can use electronic equipment to simulate and determine the time difference between the chip's clock signal and data signal, and store it in the chip. This allows the chip to be used in subsequent actual operation projects. Before the data signal is collected based on the clock signal, the timing of the clock signal and the data signal can be adjusted based on the time difference, for example, Figure 3 The timing relationship between the clock signal and the data signal is adjusted to Figure 2 The timing relationship shown ultimately enables the chip to more accurately sample the data signal according to the clock signal, and ensures the accuracy and effectiveness of the chip's subsequent processing of the data signal.

[0036] In the prior art, when an electronic device determines the time difference between a chip's clock signal and a data signal by simulation, the electronic device may first obtain the following information: Figure 1The netlist of the entire chip is shown, which includes every circuit within the chip and the connections between them. Subsequently, the electronic device executes a Write FIFO command to write the data into the chip's FIFO (First Input First Output) file via the chip's DQ pins. The data in the chip's FIFO file is then read back by executing a Read FIFO command. The system also adjusts the time difference between the clock signal and the data signal to allow for repeated writing and reading. Ultimately, the time difference between the clock signal and the data signal can be determined by determining the correct interval for the data during repeated writing and reading.

[0037] However, using the above-mentioned existing techniques to determine the time difference between a chip's clock and data signals requires simulating all circuits within the entire chip to determine the time difference. This results in a long simulation time. In practice, using existing techniques to calculate the time difference between a chip's clock and data signals requires 2-3 hours for the initial simulation and 15-20 hours for the subsequent simulation, significantly impacting simulation efficiency.

[0038] Therefore, based on the technical problem in the prior art that the simulation time required to determine the time difference between the chip's clock signal and the data signal is long, the present disclosure performs simulation through a circuit netlist and an excitation file including a netlist of a clock signal receiving circuit and a netlist of a data signal receiving circuit to reduce the simulation time required to simulate the time difference between the clock signal and the data signal.

[0039] The following specific embodiments are used to describe the technical solution of the present disclosure in detail. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.

[0040] Figure 4 This is a flow chart of an embodiment of the simulation method provided by the present disclosure, as shown in FIG. Figure 4 The simulation method shown can be executed by electronic devices such as computers, servers, workstations, etc. Figure 4 The methods shown include:

[0041] S101: The electronic device obtains a circuit netlist.

[0042] In one embodiment, Figure 5 This is a schematic diagram of a circuit netlist provided by the present disclosure. Figure 5 As shown, the circuit netlist obtained by the electronic device in S101 includes: a data signal receiving circuit and a clock signal receiving circuit. The data signal receiving circuit is used to receive a data signal, and the clock signal receiving circuit is used to receive a clock signal.

[0043] In one embodiment, the netlist may be a simulation program within integrated circuit emphasis (SPIC) netlist, which includes components included in the circuit and the connections between the components. The netlist may represent the circuit in text form and may be used to simulate and implement the corresponding circuit.

[0044] In one embodiment, the number of netlists for the data signal receiving circuit in the circuit netlist is one, and the number of netlists for the clock signal receiving circuit in the circuit netlist is one.

[0045] S102: The electronic device generates an incentive file.

[0046] In one embodiment, the stimulus file includes clock information and data information.

[0047] In one embodiment, the data information includes a first data signal and a transmission rate of the first data signal. The first data signal may be data that can be received by the chip using a data signal receiving circuit, for example, the first data signal is a 16-bit "1010 0111 0100 0010".

[0048] In one embodiment, the transmission rate of the first data signal is 6.4 Gbit / s.

[0049] In one embodiment, the clock information includes: the time of each shift of the clock signal and the maximum time range of the clock signal shift.

[0050] For example, Figure 6 A schematic diagram of clock information and data information is shown in FIG. Figure 6 As shown, the start time of the data signal is t0, and the period of the data signal is T. The maximum time range of the clock signal in the clock information is the time range between -1.5T and 1T before t0, and the time for each shift of the clock signal is 0.01ns.

[0051] In one embodiment, the stimulus file may be named gen_stimulus.pl, for example, and may be expressed in the following form: "gen_stimulus.pl-pstep 0.01n-datarate 6.4G-start"-3*UI"-end"2*UI"-sp 5n-data'1010 0111 0100 0010'". Wherein, the first data signal "data" is "'1010 0111 0100 0010'", the shift time "Pstep" of the clock signal each time is "0.01n", the starting time "start" of the clock signal shift is "-3*UI", the ending time "end" of the clock signal shift is "2*UI", and UI is half of the clock period of the clock signal. The starting input time "sp" of the first data signal is "5n", that is, the first data signal starts to be input 5ns after the clock signal.

[0052] In one embodiment, when the data type of the time difference between the clock signal and the data signal is char, the start time and the end time of the clock signal shift are set to negative numbers.

[0053] In one embodiment, since the circuit netlist provided in this embodiment only includes a netlist for one data signal processing circuit and a netlist for one clock signal processing circuit, the stimulus file provided in this embodiment only needs to include the one data signal and clock signal in the chip, thereby greatly reducing the amount of data in the stimulus file.

[0054] S103: The electronic device performs simulation based on the circuit netlist and the stimulus file to obtain a time difference between the clock signal and the data signal.

[0055] Specifically, electronic equipment can be simulated through circuit netlist and stimulus file to obtain Figure 5 The second data signal is obtained by simulating the circuit netlist shown.

[0056] In one embodiment, the electronic device can load both the circuit netlist and the stimulus file into a simulator, and create a simulation directory in the simulator to implement simulation.

[0057] In one embodiment, the electronic device simulates the circuit netlist and the stimulus file to obtain different clock signal shift times and corresponding second data signals. For example, when the electronic device simulates the circuit netlist and the stimulus file, the data output by the simulator can be represented by the following Table 1:

[0058] Table 1

[0059] Shift time of the clock signal Shifted clock signal Second data signal -1.5T Td1 Dd1 -1.5T+0.01ns Td2 Dd2 -1.5T+0.02ns Td3 Dd3 … … T-0.02ns Tdn-2 Ddn-2 T-0.01ns Tdn-1 Ddn-1 T Tdn Ddn

[0060] As shown in Table 1, the electronic device simulates the circuit netlist and stimulus file, shifting the clock signal according to the starting time of the clock signal shift -1.5T, and sampling the data signal based on the shifted clock signal Td1 to obtain the second data signal Dd1 corresponding to the shift time -1.5T. Subsequently, the electronic device can also obtain the shift time -1.5T+0.01ns based on the time of the previous shift, and sample the data signal based on the shifted clock signal Td2 to obtain the second data signal Dd2 corresponding to the shift time -1.5T+0.01ns. Similarly, the electronic device can obtain the second data signals corresponding to all clock signals between -1.5T and T.

[0061] Subsequently, the electronic device can determine the shift time range of the clock signal when the first and second data signals are the same by comparing the second data signal obtained by the simulator with the first data signal provided in the stimulus file as shown in FIG1 .

[0062] In one embodiment, the electronic device can run a script to view a report output by the simulator, thereby determining whether the second data signal obtained by circuit netlist simulation is identical to the first data signal by comparing the second data signal with the first data signal. For example, the script to be run can be represented as dqib_cmp_batch.pl-cfgcmp_finesim.cfg-kw'finesim.tr0*'-mp10, etc.

[0063] Exemplarily, Table 2 shows a schematic diagram of the electronic device comparing the second data signal obtained by the simulator with the first data signal.

[0064] Table 2

[0065] Second data signal First data signal Are they the same? Dd1 D Different Dd2 D Different Dd3 D Different … … Different Da D same … … same Db D same … … Different Ddn-2 D Different Ddn-1 D Different Ddn D Different

[0066] As shown in Table 2, when an electronic device performs a simulation based on a circuit netlist and an excitation file, determines the first data signal and the second data signal, and then compares the first data signal and the second data signal, it can be determined that: when the shift time range of the clock signal is -1.5T to a, the first data signal and the second data signal are different; when the shift time range of the clock signal is a to b, the first data signal and the second data signal are the same; when the shift time range of the clock signal is b to -1.5T, the first data signal and the second data signal are different. In the example shown in Table 2, the electronic device can determine that the shift time range is ab based on whether the first data signal and the second data signal are the same.

[0067] Finally, the electronic device can determine the time difference between the clock signal and the data signal corresponding to the chip according to the shift time range.

[0068] In one embodiment, the time difference between the clock signal and the data signal may be specifically a middle value of the shift time range.

[0069] For example, Figure 7 Schematic diagram of the shift time range provided by the present disclosure. Figure 6 As shown in , the maximum time range of the clock signal shift is -1.5T to 1T. When an electronic device simulates based on a circuit netlist and stimulus file, determines a first data signal and a second data signal, and compares the first and second data signals, if the values ​​obtained are the same, the clock signal shift time range can be a to b, where -1.5T < a < b < 1T. Based on the clock signal shift time range, the electronic device can ultimately determine the time difference between the clock signal and the data signal to be c, the midpoint between a and b.

[0070] In summary, the simulation method provided in this embodiment uses a circuit netlist and a stimulus file to perform simulation to obtain the time difference between the clock signal and the data signal. Since the circuit netlist only includes the netlist of the chip's clock signal receiving circuit and the netlist of the data signal receiving circuit, the structure of the circuit netlist is relatively simple, and the scale of the circuit netlist is reduced to less than 10% of the netlist simulation of the entire circuit in the prior art. At the same time, the amount of data in the stimulus file is also relatively small. Ultimately, when the electronic device is simulated using the circuit netlist and stimulus file, the time difference between the chip's clock signal and data signal is obtained faster and in less time.

[0071] In a specific implementation, when this embodiment is used to calculate the time difference between the clock signal and the data signal of the chip, the input excitation of each data signal is also simplified, which reduces the simulation time. The simulation time corresponding to each data signal is reduced from 3us in the prior art to 20ns. Overall, the time required for the front simulation is reduced from 2-3 hours to 5-10 minutes, and the time required for the back simulation is reduced from 15-20 hours to 30-40 minutes, thereby greatly improving the simulation efficiency.

[0072] In one embodiment, the electronic device can simulate different process corners of the chip to obtain the time difference between the clock signal and the data signal corresponding to the different corners, so that different time differences between the clock signal and the data signal are set for different corners of the chip.

[0073] In the aforementioned embodiments, the methods provided by the embodiments of the present disclosure have been described. To implement the various functions of the methods provided by the embodiments of the present disclosure, the device or apparatus that performs the methods may include hardware structures and / or software modules, and the aforementioned functions may be implemented in the form of hardware structures, software modules, or a combination of hardware structures and software modules. Whether a particular function is implemented in the form of hardware structures, software modules, or a combination of hardware structures and software modules depends on the specific application and design constraints of the technical solution.

[0074] For example, Figure 8 This is a structural diagram of an embodiment of the simulation device provided by the present disclosure. Figure 8 As shown, the present disclosure provides a simulation device 1000, comprising an acquisition module 1001, a stimulus module 1002, and a simulation module 1003. Acquisition module 1001 is used to acquire a circuit netlist, and stimulus module 1002 is used to generate a stimulus file. Simulation module 1003 is used to perform simulation based on the circuit netlist and stimulus file to obtain the time difference between the clock signal and the data signal.

[0075] In one embodiment, the number of netlists of the clock signal receiving circuit and the number of netlists of the data signal receiving circuit are both one.

[0076] In one embodiment, the data information includes the first data signal and a transmission rate of the first data signal.

[0077] In one embodiment, the transmission rate of the first data signal is 6.4 Gbit / s.

[0078] In one embodiment, the clock information includes the time of each shift of the clock signal and the maximum time range of the shift of the clock signal.

[0079] In one embodiment, the time for each shift of the clock signal is 0.01 ns.

[0080] In one embodiment, the maximum time range of the clock signal shift is -1.5T-1T, where T is the period of the clock signal.

[0081] In one embodiment, the simulation module 1003 is specifically used to perform simulation based on the circuit netlist and the stimulus file to obtain a second data signal obtained by the circuit netlist simulation; compare the second data signal with the first data signal; determine the shift time range of the clock signal when the first data signal and the second data signal are the same; and determine the time difference between the clock signal and the data signal based on the shift time range.

[0082] In one embodiment, the time difference between the clock signal and the data signal is a middle value of the shift time range.

[0083] The implementation method and principle of the device provided in this embodiment can refer to the method provided in the previous embodiments of the present disclosure, and will not be repeated here.

[0084] It should be noted that it should be understood that the division of the various modules of the above device is merely a division of logical functions. In actual implementation, they can be fully or partially integrated into one physical entity, or they can be physically separated. Moreover, these modules can all be implemented in the form of software called by a processing element; or they can all be implemented in the form of hardware; or some modules can be implemented in the form of software called by a processing element, and some modules can be implemented in the form of hardware. For example, the processing module can be a separately established processing element, or it can be integrated into a chip of the above device. In addition, it can also be stored in the memory of the above device in the form of program code, and called by a processing element of the above device to perform the functions of the above-mentioned module. The implementation of other modules is similar. In addition, these modules can all or partly be integrated together, or they can be implemented independently. The processing element described here can be an integrated circuit with signal processing capabilities. In the implementation process, each step of the above method or each of the above modules can be completed by an integrated logic circuit of hardware in the processor element or instructions in the form of software.

[0085] For example, the above modules may be one or more integrated circuits configured to implement the above methods, such as one or more application specific integrated circuits (ASICs), one or more digital signal processors (DSPs), or one or more field programmable gate arrays (FPGAs). For another example, when a module is implemented by a processing element calling a program code, the processing element may be a general-purpose processor, such as a central processing unit (CPU) or other processor that can call a program code. For another example, these modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).

[0086] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present disclosure is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid state disk (SSD)).

[0087] For example, Figure 9 This is a structural diagram of an embodiment of an electronic device provided by the present disclosure, such as Figure 9 As shown, the present disclosure provides an electronic device comprising: at least one processor 2001 and a memory 2002; wherein the memory 2002 stores computer instructions, and the at least one processor 2001 can execute the computer instructions. When the processor 2001 executes the computer program, the processor 2001 can be used to perform the steps of any method in the aforementioned embodiments of the present disclosure. In one embodiment, the processor 2001 can communicate via a communication interface 2003, for example, to obtain a circuit netlist.

[0088] The present disclosure further provides a computer-readable storage medium storing a computer program. When the computer program is executed, it can be used to perform the steps of any method in the aforementioned embodiments of the present disclosure.

[0089] An embodiment of the present disclosure further provides a chip for executing instructions, wherein the chip is used to execute the steps in any of the aforementioned methods of the present disclosure.

[0090] Those skilled in the art will appreciate that all or part of the steps in the above-described method embodiments can be implemented using hardware associated with program instructions. The aforementioned program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0091] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A simulation method, characterized in that: include: Obtaining a circuit netlist, the circuit netlist including a netlist of a clock signal receiving circuit and a netlist of a data signal receiving circuit, the clock signal receiving circuit being used to receive a clock signal, and the data signal receiving circuit being used to receive a data signal; Generate an incentive file, wherein the incentive file includes clock information and data information; Perform simulation based on the circuit netlist and the stimulus file to obtain a time difference between the clock signal and the data signal; The data information includes a first data signal; the clock information includes the time of each shift of the clock signal and the maximum time range of the shift of the clock signal; The performing simulation based on the circuit netlist and the stimulus file to obtain the time difference between the clock signal and the data signal includes: Perform simulation based on the circuit netlist and the stimulus file to obtain a second data signal obtained by simulating the circuit netlist; comparing the second data signal and the first data signal; determining a shift time range of the clock signal when the first data signal and the second data signal are identical; A time difference between the clock signal and the data signal is determined according to the shift time range.

2. The method according to claim 1, characterized in that The number of netlists of the clock signal receiving circuit and the number of netlists of the data signal receiving circuit are both one.

3. The method according to claim 1, characterized in that The data information further includes a transmission rate of the first data signal.

4. The method according to claim 3, characterized in that The transmission rate of the first data signal is 6.4 Gbit / s.

5. The method according to claim 1, wherein The time for each shift of the clock signal is 0.01 ns.

6. The method according to claim 1, characterized in that The maximum time range of the clock signal shift is -1.5T-1T, where T is the period of the clock signal.

7. The method according to claim 1, characterized in that The time difference between the clock signal and the data signal is a middle value of the shift time range.

8. An electronic device, characterized in that: include: at least one processor and memory; The memory stores computer-executable instructions; the at least one processor executes the computer-executable instructions stored in the memory, so that the at least one processor performs the method according to any one of claims 1 to 7.

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