Pressure-resistant gallium nitride power device, preparation method and chip

Abstract

The application belongs to the technical field of semiconductors and provides a voltage-withstanding gallium nitride power device, a preparation method and a chip. The voltage-withstanding gallium nitride power device comprises a semiconductor substrate, a first channel layer, a second channel layer, a first barrier layer, a second barrier layer, a first cap layer, a second cap layer, a third cap layer, a source electrode, a drain electrode, a gate electrode, a first cathode electrode, a second cathode electrode and an anode electrode. The anode electrode forms ohmic contact with the second cap layer and the third cap layer, and forms Schottky contact with two-dimensional electron gas (2DEG) between the second channel layer and the second barrier layer. When reverse bias is applied, the PN junction barrier is increased, and the two-dimensional electron gas between the second channel layer and the second barrier layer is depleted, so that electrons need to overcome the barrier of the PN junction to reach the Schottky junction. In this way, the reverse breakdown voltage can be improved, and the reverse breakdown voltage of the voltage-withstanding gallium nitride power device is improved.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to a low-voltage gallium nitride power device, its fabrication method, and a chip. Background Technology

[0002] HEMT (High Electron Mobility Transistor) devices, as typical representatives of third-generation wide bandgap semiconductor materials, have a series of material performance advantages such as large bandgap, strong breakdown electric field, high electron saturation drift velocity and good chemical stability, making them a popular material for developing high-performance power electronic devices.

[0003] However, gallium nitride high electron mobility transistors (GaN HEMTs) have low breakdown voltage capability and are more prone to breakdown under high inductance application conditions because they do not have parasitic diodes, which greatly limits their application. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a voltage-resistant gallium nitride power device, its fabrication method, and a chip, aiming to solve the problem of low breakdown voltage in existing gallium nitride power devices.

[0005] A first aspect of this application provides a voltage-resistant gallium nitride (GaN) power device, the voltage-resistant GaN power device comprising:

[0006] Semiconductor substrate;

[0007] A first channel layer and a second channel layer are both disposed on the semiconductor substrate and do not contact each other; wherein the second channel layer has a convex shape.

[0008] The first barrier layer is disposed on the first channel layer;

[0009] The second barrier layer is disposed on the protrusion of the second channel layer;

[0010] The first capping layer is disposed on the first barrier layer;

[0011] The source electrode is disposed on the first channel layer and is in contact with the first side of the first barrier layer;

[0012] The drain electrode is disposed on the first channel layer and is in contact with the second side of the first barrier layer;

[0013] The gate electrode is disposed on the first capping layer;

[0014] The second cap layer is disposed on the second barrier layer;

[0015] The third capping layer is disposed on the second barrier layer and is not in contact with the second capping layer;

[0016] An anode electrode is disposed on the second capping layer, the third capping layer, and the second barrier layer;

[0017] A first cathode electrode and a second cathode electrode, wherein the first cathode electrode is disposed on a first horizontal portion of the second channel layer and the second cathode electrode is disposed on a second horizontal portion of the second channel layer.

[0018] In one embodiment, the voltage-resistant gallium nitride power device further includes:

[0019] The first ion implantation region is located at the corner between the first horizontal portion of the second channel layer and the protrusion of the second channel layer;

[0020] The second ion implantation region is located at the corner between the second horizontal portion of the second channel layer and the protrusion of the second channel layer.

[0021] In one embodiment, both the first ion implantation region and the second ion implantation region are arc-shaped structures.

[0022] In one embodiment, the anode electrode is convex in shape;

[0023] The second cap layer and the third cap layer are arranged symmetrically with respect to the protrusion of the anode electrode.

[0024] In one embodiment, the widths of both the second cap layer and the third cap layer are smaller than the width of the protrusion of the anode electrode.

[0025] In one embodiment, the ion doping concentration of the second capping layer and the third capping layer gradually increases from the protrusion of the anode electrode towards the left and right ends.

[0026] In one embodiment, the width of the first ion implantation region is smaller than the width of the first cathode electrode.

[0027] In one embodiment, the sum of the widths of the first ion implantation region and the first cathode electrode is less than the width of the first horizontal portion of the second channel layer.

[0028] A second aspect of this application provides a method for fabricating a gallium nitride power device with a voltage withstand capability, comprising:

[0029] A first channel layer and a second channel layer are sequentially formed on a semiconductor substrate; wherein the first channel layer and the second channel layer are not in contact with each other;

[0030] A first barrier layer is formed on the first channel layer, and a second barrier layer is formed on the second channel layer; and the second barrier layer is etched so that the shape of the second channel layer is "convex", and the second barrier layer is disposed on the protrusion of the second channel layer.

[0031] A first capping layer is formed on the first barrier layer;

[0032] A second capping layer and a third capping layer are formed on the second barrier layer; wherein the third capping layer and the second capping layer are not in contact with each other;

[0033] A source electrode and a drain electrode are formed in the first channel layer, and a gate electrode is formed on the first capping layer; wherein the source electrode is in contact with a first side of the first barrier layer, and the drain electrode is in contact with a second side of the first barrier layer.

[0034] An anode electrode is formed on the second capping layer, the third capping layer, and the second barrier layer;

[0035] A first cathode electrode is formed on a first horizontal portion of the second channel layer, and a second cathode electrode is formed on a second horizontal portion of the second channel layer.

[0036] A third aspect of this application provides a chip, characterized in that it includes at least one voltage-resistant gallium nitride power device as described in any of the preceding claims; or the chip includes at least one voltage-resistant gallium nitride power device prepared by the preparation method described above.

[0037] The beneficial effects of this application embodiment compared with the prior art are as follows: By setting an ohmic contact between the anode electrode and the second and third capping layers, a Schottky contact between the anode electrode and the two-dimensional electron gas between the second channel layer and the second barrier layer, and a PN junction between the second and third capping layers and the second barrier layer, a voltage-resistant dual-channel Schottky diode can be formed. When the voltage-resistant dual-channel Schottky diode is in operation, under forward bias, because the Schottky barrier is lower than the PN junction barrier, the Schottky junction conducts first. As the forward bias increases, the PN junction conducts, forming a dual-channel carrier transport, reducing the on-resistance, and improving the surge resistance. Under reverse bias, the PN junction barrier increases, and the two-dimensional electron gas between the second channel layer and the second barrier layer is depleted, so that electrons need to cross the PN junction barrier to reach the Schottky junction, thereby increasing the reverse breakdown voltage, and thus increasing the reverse breakdown voltage of the voltage-resistant gallium nitride power device. Attached Figure Description

[0038] Figure 1 This is a top view schematic diagram of a gallium nitride power device provided in one embodiment of this application;

[0039] Figure 2 This is a front view schematic diagram of a gallium nitride power device provided in one embodiment of this application;

[0040] Figure 3 This is a rear view structural schematic diagram of a gallium nitride power device provided in one embodiment of this application;

[0041] Figure 4 This is a schematic diagram of the structure of a gallium nitride power device with withstand voltage provided in one embodiment of this application. Figure 1 ;

[0042] Figure 5 This is a schematic diagram of the structure of a gallium nitride power device with withstand voltage provided in one embodiment of this application. Figure 2 ;

[0043] Figure 6 This is a schematic diagram of the fabrication steps of a gallium nitride power device with withstand voltage provided in one embodiment of this application;

[0044] Figure 7 This is a schematic diagram of the formation of a first trench layer and a second trench layer provided in one embodiment of this application;

[0045] Figure 8 This is a schematic diagram of the formation of the first barrier layer and the second barrier layer according to an embodiment of this application;

[0046] Figure 9 This is a schematic diagram of the formation of a first capping layer, a second capping layer, and a third capping layer according to an embodiment of this application;

[0047] Figure 10 This is a schematic diagram of the formation of a first cathode electrode, a second cathode electrode, an anode electrode, a gate electrode, a drain electrode, and a source electrode provided in one embodiment of this application. Detailed Implementation

[0048] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0049] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0050] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0051] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means one or more, unless otherwise explicitly specified.

[0052] In this application specification, references to "one embodiment," "some embodiments," or "embodiment" mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, phrases such as "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," "in a particular embodiment," "in a particular application," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. Furthermore, in one or more embodiments, specific features, structures, or characteristics may be combined in any suitable manner.

[0053] HEMT (High Electron Mobility Transistor) devices, as typical representatives of third-generation wide bandgap semiconductor materials, have a series of material performance advantages such as large bandgap, strong breakdown electric field, high electron saturation drift velocity and good chemical stability, making them a popular material for developing high-performance power electronic devices.

[0054] However, gallium nitride high electron mobility transistors (GaN HEMTs) have low breakdown voltage capability and are more prone to breakdown under high inductance application conditions because they do not have parasitic diodes, which greatly limits their application.

[0055] To address the aforementioned technical problems, this application provides a gallium nitride power device with a withstand voltage rating, as shown in the reference. Figure 1 , Figure 2 , Figure 3As shown, the voltage-resistant gallium nitride power device includes: a semiconductor substrate 10, a first channel layer 20, a second channel layer 30, a first barrier layer 40, a second barrier layer 50, a first capping layer 60, a second capping layer 70, a third capping layer 80, an anode electrode 90, a first cathode electrode 100, a second cathode electrode 110, a source electrode 140, a drain electrode 150, and a gate electrode 160.

[0056] Specifically, the first channel layer 20 and the second channel layer 30 are both disposed on the semiconductor substrate 10, and the first channel layer 20 and the second channel layer 30 are not in contact with each other. The second channel layer 30 is convex in shape. The first barrier layer 40 is disposed on the first channel layer 20, and the second barrier layer 50 is disposed on the protrusion of the second channel layer 30. The first capping layer 60 is disposed on the first barrier layer 40. The source electrode 140 is disposed on the first channel layer 20, and the source electrode 140 is in contact with the first side of the first barrier layer 40. The drain electrode 150 is disposed on the first channel layer 20, and the drain electrode 150 is in contact with the second side of the first barrier layer 40. The gate electrode 160 is disposed on the first capping layer 60. The second capping layer 70 is disposed on the second barrier layer 50. The third capping layer 80 is disposed on the second barrier layer 50, and the third capping layer 80 is not in contact with the second capping layer 70. The anode electrode 90 is disposed on the second capping layer 70, the third capping layer 80, and the second barrier layer 50. The first cathode electrode 100 is disposed on the first horizontal portion of the second channel layer 30, and the second cathode electrode 110 is disposed on the second horizontal portion of the second channel layer 30.

[0057] In this embodiment, both the first channel layer 20 and the second channel layer 30 are disposed on the semiconductor substrate 10, and the first channel layer 20 and the second channel layer 30 do not contact each other. It is understood that the first channel layer 20 and the second channel layer 30 are located on the same horizontal plane, and the first channel layer 20 and the second channel layer 30 are made of the same material. The first channel layer 20 and the second channel layer 30 can be integrally formed on the semiconductor substrate 10 in one step, and then sheared to ensure that the first channel layer 20 and the second channel layer 30 do not contact each other. Alternatively, an insulating material can be placed between the first channel layer 20 and the second channel layer 30 to ensure that they do not contact each other. By ensuring that the first channel layer 20 and the second channel layer 30 do not contact each other, they can avoid interfering with each other, reducing mutual interference between the first channel layer 20 and the second channel layer 30, allowing the first channel layer 20 and the second channel layer 30 to perform their respective functions, and improving the stability of the gallium nitride power device.

[0058] In this embodiment, since existing gallium nitride power devices generally lack parasitic diodes, their breakdown voltage capability is low under high inductance application conditions, making them prone to breakdown and severely limiting their applications. By setting the first cathode electrode 100 on the first horizontal portion of the second channel layer 30, the second cathode electrode 110 on the second horizontal portion of the second channel layer 30, and the anode electrode 90 on the second capping layer 70, the third capping layer 80, and the second barrier layer 50, a diode function can be achieved. This can serve as the body diode of a voltage-resistant gallium nitride power device. The first cathode electrode 100 and the second cathode electrode 110 can be connected in series with the drain electrode 150, or the anode electrode 90 can be connected in series with the source electrode 140. Specifically, in different application scenarios, for example, the first cathode electrode 100 and the second cathode electrode 110 can be connected in series with the drain electrode 150, or the anode electrode 90 can be connected with the source electrode 140. It should be noted that only one implementation method can be selected: either connecting the first cathode electrode 100 and the second cathode electrode 110 to the drain electrode 150, or connecting the anode electrode 90 to the source electrode 140. For example, when the first cathode electrode 100 and the second cathode electrode 110 are connected to the drain electrode 150, the anode electrode 90 cannot be connected to the source electrode 140. Conversely, when the anode electrode 90 is connected to the source electrode 140, the first cathode electrode 100 and the second cathode electrode 110 cannot be connected to the drain electrode 150. The purpose of this configuration is to connect the body diode formed by the first cathode electrode 100 and the second cathode electrode 110, the anode electrode 90, the second channel layer 30, and the second barrier layer 50 in series with either the drain electrode 150 or the source electrode 140, rather than in parallel.

[0059] In this embodiment, the second capping layer 70 and the third capping layer 80 are both disposed on the second barrier layer 50, and the second capping layer 70 and the third capping layer 80 are not in contact with each other; the anode electrode 90 is disposed on the second capping layer 70, the third capping layer 80, and the second barrier layer 50. Specifically, the first channel layer 20 and the second channel layer 30 are GaN, the first barrier layer 40 and the second barrier layer 50 are AlGaN, the first capping layer 60 is P-type GaN, the anode electrode 90 is a Schottky metal with a work function higher than GaN but lower than P-type GaN, an ohmic contact is formed between the anode electrode 90 and the second capping layer 70 and the third capping layer 80, a Schottky contact is formed between the anode electrode 90 and the two-dimensional electron gas (2DEG) between the second channel layer 30 and the second barrier layer 50, and a PN junction is formed between the second capping layer 70 and the third capping layer 80 and the second barrier layer 50. This allows the formation of a voltage-resistant dual-channel Schottky diode. When a dual-channel Schottky diode is in operation, under forward bias, the Schottky junction conducts first because its barrier is lower than the PN junction barrier. As the forward bias increases, the PN junction conducts, forming a dual-channel carrier transport, reducing on-resistance and improving surge immunity. Under reverse bias, the PN junction barrier increases, simultaneously depleting the two-dimensional electron gas between the second channel layer 30 and the second barrier layer 50. This forces electrons to overcome the PN junction barrier to reach the Schottky junction, thereby increasing the reverse breakdown voltage and consequently improving the reverse breakdown voltage of the gallium nitride power device.

[0060] In one embodiment, reference Figure 4 As shown, the voltage-resistant gallium nitride power device also includes: a first ion implantation region 120 and a second ion implantation region 130.

[0061] Specifically, the first ion implantation region 120 is located at the corner between the first horizontal portion and the protrusion of the second channel layer 30. The second ion implantation region 130 is located at the corner between the second horizontal portion and the protrusion of the second channel layer 30.

[0062] In this embodiment, the implanted ions in the first ion implantation region 120 and the second ion implantation region 130 are fluorine ions. During the operation of the gallium nitride power device, the electric field strength and electric field spikes are relatively large at the corners between the first horizontal portion and the protrusion of the second channel layer 30, and between the second horizontal portion and the protrusion of the second channel layer 30, which leads to a lower breakdown voltage of the power device. By setting the first ion implantation region 120 and the second ion implantation region 130 at the above two corners, the electric field spike effect at the corners can be reduced, the electric field distribution at the corners can be made more uniform, and the performance of the power device can be improved.

[0063] In one embodiment, reference Figure 5As shown, both the first ion implantation region 120 and the second ion implantation region 130 are arc-shaped structures.

[0064] In this embodiment, ion implantation can be performed at a 45° angle at the corner between the first horizontal portion and the protrusion of the second channel layer 30, making the first ion implantation region 120 arc-shaped. Within this arc, the ion concentration is higher closer to the corner and lower further away. This operation enhances the ability to handle electric field spikes at the corner, resulting in a more uniform electric field distribution and improved stability of the power device. The ion concentration distribution principle of the second ion implantation region 130 is similar to that of the first ion implantation region 120 and will not be described further here.

[0065] In one embodiment, reference Figure 4 As shown, both the first ion implantation region 120 and the second ion implantation region 130 are rectangular structures. Specifically, ion implantation can be performed at a 90° angle perpendicularly at the corner between the first horizontal portion and the protrusion of the second channel layer 30, making the first ion implantation region 120 rectangular. Within this rectangular structure, the ion concentration is higher closer to the corner and lower further away. This operation enhances the ability to handle electric field spikes at the corners, resulting in a more uniform electric field distribution and improved stability of the power device. The ion concentration distribution principle of the second ion implantation region 130 is similar to that of the first ion implantation region 120 and will not be elaborated further here.

[0066] In one embodiment, reference Figure 4 As shown, the anode electrode 90 is convex in shape, and the second cap layer 70 and the third cap layer 80 are symmetrically arranged with respect to the convex portion of the anode electrode 90.

[0067] Specifically, the protrusion of the anode electrode 90 contacts the second barrier layer 50, the second capping layer 70 contacts the protrusion of the anode electrode 90, the first horizontal portion of the anode electrode 90, and the second barrier layer 50, respectively, and the third capping layer 80 contacts the protrusion of the anode electrode 90, the second horizontal portion of the anode electrode 90, and the second barrier layer 50, respectively. This arrangement makes the second capping layer 70 and the third capping layer 80 symmetrically arranged with respect to the protrusion of the anode electrode 90. By symmetrically arranging the second capping layer 70 and the third capping layer 80, dual-channel carrier transport is formed, reducing on-resistance and improving surge resistance, while also improving the reverse breakdown voltage, resulting in a more uniform electric field distribution in the voltage-resistant gallium nitride power device.

[0068] In one embodiment, reference Figure 5As shown, the widths of the second capping layer 70 and the third capping layer 80 are both smaller than the width of the protrusion of the anode electrode 90. For example, if the width of the second capping layer 70 is W1, the width of the third capping layer 80 is W2, and the width of the protrusion of the anode electrode 90 is W3, then W1 < W3 and W2 < W3.

[0069] Specifically, an ohmic contact is formed between the anode electrode 90 and the second capping layer 70 and the third capping layer 80, and a Schottky contact is formed between the anode electrode 90 and the two-dimensional electron gas between the second channel layer 30 and the second barrier layer 50. A PN junction is formed between the second capping layer 70 and the third capping layer 80 and the second barrier layer 50. Under reverse bias, the PN junction barrier increases, simultaneously depleting the two-dimensional electron gas between the second channel layer 30 and the second barrier layer 50. This forces electrons to overcome the PN junction barrier to reach the Schottky junction, thereby increasing the reverse breakdown voltage. By setting the widths of the second capping layer 70 and the third capping layer 80 to be relatively small and the width of the protrusion of the anode electrode 90 to be relatively large, the distance that electrons travel when crossing the PN junction barrier to reach the Schottky junction is also greater, which is more conducive to improving the reverse breakdown voltage of the device.

[0070] In one embodiment, the ion doping concentration of the second capping layer 70 and the third capping layer 80 gradually increases from the protrusion of the anode electrode 90 towards both ends. Specifically, the second capping layer 70 and the third capping layer 80 can be doped with p-type gallium nitride, and their ion doping concentration can be graded. For example, the ion doping concentration of the second capping layer 70 and the third capping layer 80 is lower at the locations closer to the anode electrode 90, and higher at the locations farther away from the protrusion of the anode electrode 90. This operation makes it easier to increase the reverse breakdown voltage of the device when electrons cross the potential barrier of the PN junction to the Schottky junction.

[0071] In one embodiment, reference Figure 4 As shown, the width of the first ion implantation region 120 is smaller than the width of the first cathode electrode 100. For example, if the width of the first ion implantation region 120 is W4 and the width of the first cathode electrode 100 is W5, then W4 < W5.

[0072] In this embodiment, the width of the first ion implantation region 120 refers to its maximum width. This is because, during operation, the electric field strength and field spikes are larger at the corners between the first horizontal portion and the protrusion of the second channel layer 30, and between the second horizontal portion and the protrusion of the second channel layer 30, resulting in a lower breakdown voltage for the power device. Since the electric field spikes are only significant at the corners, it is only necessary to provide corresponding first ion implantation regions 120 and second ion implantation regions 130 at these corners. Therefore, setting the width of the first ion implantation region 120 to be smaller than the width of the first cathode electrode 100 not only ensures the normal function of the power device but also reduces the electric field spike effect at the corners, uniformly distributes the electric field at the corners, and improves the performance of the power device.

[0073] In one embodiment, the sum of the widths of the first ion implantation region 120 and the first cathode electrode 100 is less than the width of the first horizontal portion of the second channel layer 30.

[0074] In this embodiment, specifically, since the first ion implantation region 120 is located at the corner between the first horizontal portion and the protrusion of the second channel layer 30, by setting the sum of the widths of the first ion implantation region 120 and the first cathode electrode 100 to be less than the width of the first horizontal portion of the second channel layer 30, a gap can be left between the first ion implantation region 120 and the first cathode electrode 100 to avoid ion contamination of the first cathode electrode 100 by the first ion implantation region 120, thereby affecting the performance of the first cathode electrode 100. This operation can further ensure the stability of the performance of the voltage-resistant gallium nitride power device. The width characteristics of the second ion implantation region 130 and the second cathode electrode 110 are the same, and will not be described again here.

[0075] In one embodiment, a first shallow trench isolation region is further provided between the first ion implantation region 120 and the first cathode electrode 100. The first shallow trench isolation region is used to isolate the first ion implantation region 120 and the first cathode electrode 100, preventing ions from the first ion implantation region 120 from contaminating the first cathode electrode 100 and thus affecting the performance of the first cathode electrode 100. This operation can further ensure the stability of the performance of the voltage-resistant gallium nitride power device. Similarly, a second shallow trench isolation region is provided between the second ion implantation region 130 and the second cathode electrode 110, with the same principle, and will not be described again here.

[0076] In one embodiment, the thickness of the first ion region is one-third of the thickness of the first horizontal portion of the second channel layer 30. In this embodiment, since only the corresponding first ion implantation region 120 and second ion implantation region 130 need to be set at the corner when the power device is working, the width of the first ion implantation region 120 is smaller than the width of the first cathode electrode 100. This not only ensures the normal function of the power device, but also reduces the electric field spike effect at the corner, uniformizes the electric field distribution at the corner, and improves the performance of the power device.

[0077] In one embodiment, the ions implanted in the first ion implantation region 120 are hydrogen ions or fluoride ions.

[0078] In one embodiment, when fluorine ions are implanted in the first ion implantation region 120, interstitial doping is used. Specifically, interstitial doping refers to doping in the interstitial space.

[0079] In one embodiment, the first channel layer 20 and the second channel layer 30 are GaN.

[0080] In this embodiment, the first channel layer 20 and the second channel layer 30 can both be made of gallium nitride material, for example, by depositing gallium nitride material on the semiconductor substrate 10 or by epitaxially growing gallium nitride material, and their thickness and width are the same.

[0081] In one embodiment, the first barrier layer 40 and the second barrier layer 50 are AlGaN.

[0082] In this embodiment, the first barrier layer 40 and the second barrier layer 50 can both be made of aluminum gallium nitride (ANU) material. For example, the first barrier layer 40 is formed by depositing ANU material on the first channel layer 20 or by epitaxially growing ANU material, and the second barrier layer 50 is formed by depositing ANU material on the second channel layer 30 or by epitaxially growing ANU material.

[0083] In one embodiment, the first capping layer 60, the second capping layer 70, and the third capping layer 80 are all P-type GaN.

[0084] In this embodiment, P-GaN is formed by doping GaN with a p-type dopant, wherein the p-type dopant can be boron, gallium, aluminum, etc.

[0085] In one embodiment, the anode electrode 90 is made of Schottky metal, and the first cathode electrode 100 and the second cathode electrode 110 are made of ohmic metal.

[0086] In one embodiment, the Schottky metal can be a layer of platinum, gold, silver, or a conductive semiconductor layer, etc. The ohmic metal is a combination of Ti, Al, Ti, and Au materials.

[0087] In a specific application, Schottky metal is a combination of Ni and Au materials.

[0088] In one embodiment, the thicknesses of the ohmic metals Ti, Al, Ti, and Au are 15 nm, 250 nm, 50 nm, and 150 nm, respectively, and the thicknesses of the Schottky metals Ni and Au are 70 nm and 30 nm, respectively.

[0089] In this embodiment, by setting the anode electrode 90 to Schottky metal, the anode is a Schottky contact, which can provide a higher Schottky barrier height. By setting the thickness of Ni and Au in the Schottky metal to 70nm and 30nm respectively, the leakage current of the anode electrode 90 is further reduced, a higher forward threshold voltage is provided, and the overall performance of the voltage-resistant gallium nitride power device is improved.

[0090] In one embodiment, there may be multiple first cathode electrodes 100 and second cathode electrodes 110, which are respectively disposed on corresponding first horizontal portions and second horizontal portions of multiple second channel layers 30. There may be multiple anode electrodes 90, which are respectively disposed on multiple second barrier layers 50.

[0091] In this embodiment, there are multiple first cathode electrodes 100 and second cathode electrodes 110, and multiple anode electrodes 90. These multiple first cathode electrodes 100 and second cathode electrodes 110, along with the multiple anode electrodes 90, can form multiple body diodes. These body diodes can be connected in parallel or series, allowing for adjustment of the voltage withstand and high current withstand capabilities of the GaN power device. For example, when multiple body diodes are connected in parallel, the high current withstand capability of the GaN power device can be adjusted. Similarly, when multiple body diodes are connected in series, the high voltage withstand capability of the GaN power device can be adjusted. This operation increases the voltage withstand and current withstand capabilities of the GaN power device, expanding its application scenarios.

[0092] This application also provides a method for fabricating a voltage-resistant gallium nitride power device, referencing... Figure 6 As shown, it includes steps S10 to S50.

[0093] Step S10: Reference Figure 7 As shown, a first channel layer 20 and a second channel layer 30 are sequentially formed on a semiconductor substrate 10; wherein the first channel layer 20 and the second channel layer 30 are not in contact with each other.

[0094] In this embodiment, selective etching is performed on the semiconductor substrate 10 to etch out the positions of the first channel layer 20 and the second channel layer 30, respectively. Then, the corresponding semiconductor materials are filled in the corresponding positions of the first channel layer 20 and the second channel layer 30. For example, GaN material is filled in the regions of the first channel layer 20 and the second channel layer 30.

[0095] In one specific application, the semiconductor substrate 10 is a sapphire substrate.

[0096] Step S20: Reference Figure 8 As shown, a first barrier layer 40 is formed on the first channel layer 20, and a second barrier layer 50 is formed on the second channel layer 30; and the second barrier layer 50 is etched so that the shape of the second channel layer 30 is "convex", and the second barrier layer 50 is disposed on the protrusion of the second channel layer 30.

[0097] In this embodiment, a first barrier layer 40 is epitaxially formed on the first channel layer 20, and a second barrier layer 50 is epitaxially formed on the second channel layer 30. The first barrier layer 40 and the second barrier layer 50 are filled with AlGaN material. Then, the shape of the second channel layer 30 is made into a "convex" shape by etching. The second barrier layer 50 is disposed on the protrusion of the second channel layer 30.

[0098] Step S30: Reference Figure 9 As shown, a first capping layer 60 is formed on the first barrier layer 40, and a second capping layer 70 and a third capping layer 80 are formed on the second barrier layer 50; wherein the third capping layer 80 and the second capping layer 70 are not in contact with each other.

[0099] In this embodiment, the first capping layer 60, the second capping layer 70, and the third capping layer 80 are made of P-type GaN. The second capping layer 70 and the third capping layer 80 are located at both ends of the second barrier layer 50, so that the second capping layer 70 and the third capping layer 80 do not contact each other.

[0100] Step S40: Reference Figure 10 As shown, a source electrode 140 and a drain electrode 150 are formed in the first channel layer 20; wherein the source electrode 140 is in contact with the first side of the first barrier layer 40, and the drain electrode 150 is in contact with the second side of the first barrier layer 40; a gate electrode 160 is formed on the first capping layer 60.

[0101] In a specific application, a mask is used to determine the shape of the source electrode 140, drain electrode 150, and gate electrode 160, and metal is deposited on the mask to form the source electrode 140, drain electrode 150, and gate electrode 160.

[0102] Step S50: Reference Figure 10As shown, an anode electrode 90 is formed on the second capping layer 70, the third capping layer 80, and the second barrier layer 50; a first cathode electrode 100 is formed on the first horizontal portion of the second channel layer 30, and a second cathode electrode 110 is formed on the second horizontal portion of the second channel layer 30.

[0103] In one specific application, a mask is used to determine the shape of the first cathode electrode 100, the second cathode electrode 110, and the anode electrode 90, and metal is deposited on the mask to form the first cathode electrode 100, the second cathode electrode 110, and the anode electrode 90.

[0104] In one embodiment, the anode electrode 90 is made of Schottky metal, and the first cathode electrode 100 and the second cathode electrode 110 are made of ohmic metal.

[0105] In one embodiment, the Schottky metal can be a layer of platinum, gold, silver, or a conductive semiconductor layer, etc. The ohmic metal is a combination of Ti, Al, Ti, and Au materials.

[0106] In a specific application, Schottky metal is a combination of Ni and Au materials.

[0107] In one embodiment, the thicknesses of the ohmic metals Ti, Al, Ti, and Au are 15 nm, 250 nm, 50 nm, and 150 nm, respectively, and the thicknesses of the Schottky metals Ni and Au are 70 nm and 30 nm, respectively.

[0108] This application also provides a chip comprising at least one voltage-resistant gallium nitride power device as described above; or a chip comprising at least one voltage-resistant gallium nitride power device fabricated by the fabrication method described above.

[0109] In this embodiment, the chip includes a source terminal, a drain terminal, and a gate terminal, and also includes at least one GaN power device. Because an ohmic contact is formed between the anode electrode 90 of the GaN power device and the second capping layer 70 and the third capping layer 80, and a Schottky contact is formed between the anode electrode 90 and the two-dimensional electron gas (2DEG) between the second channel layer 30 and the second barrier layer 50, and a PN junction is formed between the second capping layer 70 and the third capping layer 80 and the second barrier layer 50, a dual-channel Schottky diode can be formed. When the dual-channel Schottky diode is in operation, under forward bias, the Schottky junction conducts first because the Schottky barrier is lower than the PN junction barrier. As the forward bias increases, the PN junction conducts, forming a dual-channel carrier transport, reducing the on-resistance, and simultaneously improving surge protection. When reverse biased, the PN junction barrier increases, while simultaneously depleting the two-dimensional electron gas between the second channel layer 30 and the second barrier layer 50. This forces electrons to cross the PN junction barrier to reach the Schottky junction, thereby increasing the reverse breakdown voltage and consequently improving the reverse breakdown voltage of the GaN power device.

[0110] In one embodiment, when the first cathode electrode 100 and the second cathode electrode 110 are connected in series to the drain electrode 150, the drain terminal of the chip is connected to the anode electrode 90 through a via, the source terminal of the chip is connected to the source electrode 140 of the voltage-degradable gallium nitride power device through a via, and the source terminal of the chip is connected to the gate electrode 160. When the anode electrode 90 is connected in series to the source electrode 140, the source terminal of the chip is connected to the first cathode electrode 100 and the second cathode electrode 110 through a via, the drain terminal of the chip is connected to the drain electrode 150 through a via, and the source terminal of the chip is connected to the gate electrode 160. Therefore, in general, there are no devices below the source and drain terminals of a chip. However, the design of this application can increase the breakdown voltage of the chip while increasing the space requirements. Furthermore, this application can manufacture the voltage-degradable gallium nitride power device without using an additional photomask, avoiding cumbersome manufacturing processes.

[0111] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0112] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A gallium nitride power device with withstand voltage, characterized in that, The voltage-resistant gallium nitride power device includes: Semiconductor substrate; A first channel layer and a second channel layer are both disposed on the semiconductor substrate and do not contact each other; wherein the second channel layer has a convex shape. The first barrier layer is disposed on the first channel layer; The second barrier layer is disposed on the protrusion of the second channel layer; The first capping layer is disposed on the first barrier layer; The source electrode is disposed on the first channel layer and is in contact with the first side of the first barrier layer; The drain electrode is disposed on the first channel layer and is in contact with the second side of the first barrier layer; The gate electrode is disposed on the first capping layer; The second cap layer is disposed on the second barrier layer; The third capping layer is disposed on the second barrier layer and is not in contact with the second capping layer; An anode electrode is disposed on the second capping layer, the third capping layer, and the second barrier layer; A first cathode electrode and a second cathode electrode, wherein the first cathode electrode is disposed on a first horizontal portion of the second channel layer and the second cathode electrode is disposed on a second horizontal portion of the second channel layer; The first ion implantation region is located at the corner between the first horizontal portion of the second channel layer and the protrusion of the second channel layer; The second ion implantation region is located at the corner between the second horizontal portion of the second channel layer and the protrusion of the second channel layer.

2. The gallium nitride power device as described in claim 1, characterized in that, Both the first ion implantation region and the second ion implantation region are arc-shaped structures.

3. The gallium nitride power device as described in claim 1 or 2, characterized in that, The anode electrode is convex in shape; The second cap layer and the third cap layer are arranged symmetrically with respect to the protrusion of the anode electrode.

4. The gallium nitride power device as described in claim 3, characterized in that, The widths of the second cap layer and the third cap layer are both smaller than the width of the protrusion of the anode electrode.

5. The gallium nitride power device as described in claim 3, characterized in that, The ion doping concentration of the second capping layer and the third capping layer gradually increases from the protrusion of the anode electrode to the left and right ends.

6. The gallium nitride power device as described in claim 1, characterized in that, The width of the first ion implantation region is smaller than the width of the first cathode electrode.

7. The gallium nitride power device as described in claim 1, characterized in that, The sum of the widths of the first ion implantation region and the first cathode electrode is less than the width of the first horizontal portion of the second channel layer.

8. A method for fabricating a gallium nitride power device according to any one of claims 1-7, characterized in that, include: A first channel layer and a second channel layer are sequentially formed on a semiconductor substrate; wherein the first channel layer and the second channel layer are not in contact with each other; A first barrier layer is formed on the first channel layer, and a second barrier layer is formed on the second channel layer; and the second barrier layer is etched so that the shape of the second channel layer is "convex", and the second barrier layer is disposed on the protrusion of the second channel layer. A first capping layer is formed on the first barrier layer; A second capping layer and a third capping layer are formed on the second barrier layer; wherein the third capping layer and the second capping layer are not in contact with each other; A source electrode and a drain electrode are formed in the first channel layer, and a gate electrode is formed on the first capping layer; wherein the source electrode is in contact with a first side of the first barrier layer, and the drain electrode is in contact with a second side of the first barrier layer. An anode electrode is formed on the second capping layer, the third capping layer, and the second barrier layer; A first cathode electrode is formed on a first horizontal portion of the second channel layer, and a second cathode electrode is formed on a second horizontal portion of the second channel layer.

9. A chip, characterized in that, It includes at least one low-voltage gallium nitride power device as described in any one of claims 1-7; or the chip includes at least one low-voltage gallium nitride power device prepared by the preparation method as described in claim 8.

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