I 2 C address allocation method and computing device

Abstract

The present application embodiment discloses a 2 C address allocation method and computing device. The method comprises: in the i-th round I 2 When allocating a C address, the first slave node allocates the I 2 The first slave node is determined as the target slave node; the first slave node obtains the first I from the master node; the first slave node sends the identification information to the master node first after the bit signal sent by the first slave node and the bit signal sent by other slave nodes are arbitrated. 2 The embodiment of the present application improves I 2 C The universality of address allocation.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to an I 2 C address allocation method and computing device. Background Art

[0002] I 2 The I2C bus is a two-wire synchronous serial bus with a master-slave communication mechanism. It has a simple hardware structure, easy function implementation, and supports the interconnection topology of multiple nodes sharing the bus. It is widely used in communication products, electronic equipment and other fields. 2 C supports multi-node common bus interconnection, but requires I 2 The I C address (7-bit address) is unique and cannot conflict. 2 C nodes, such as EEPROM and temperature sensors, will have fixed values ​​for a few address bits (4 or 5 bits) and reserve the remaining address bits (2 or 3 bits) to be determined by the level of the hardware pin. 2 The nodes connected on the I C bus can distinguish different addresses. 2 C nodes, such as SFP+, QSFP+ optical modules, I 2 The I C address is fixed, and there is no reserved interface for hardware settings, which will cause some I 2 I 2 C address may be the same, when performing I 2 C communication, I 2 C address conflicts also cause multiple I 2 C nodes cannot be interconnected by a common bus.

[0003] In order to solve this I 2 C address conflict, when performing I 2 When assigning I C addresses, the master node first enables the first slave node, and then the master node assigns it I 2 C address, and then the first slave node enables the second slave node, and the master node assigns it I 2 C address, and so on, to complete the address allocation of all slave nodes.

[0004] The uniqueness of address allocation is ensured by enabling slave nodes one by one in a cascade manner. However, this allocation method requires the slave nodes to provide additional hardware interfaces for enabling reception and transmission, and the wiring between the master and slave nodes is relatively complicated. However, not all slave nodes can provide such interfaces, which results in the address allocation method not being universal. Therefore, how to achieve dynamic address allocation without increasing the complexity of wiring between master and slave nodes is a technical problem that needs to be solved urgently. Summary of the invention

[0005] This application provides an I2 C address allocation method and computing device, by 2 C timing protocol can be expanded without adding complex wiring between the master node and the slave node to achieve I 2 Dynamic allocation of C addresses.

[0006] In a first aspect, the present application provides an I 2 C address allocation method, the method is applied to any slave node, the method comprises: in the i-th round I 2 When allocating a C address, the first slave node allocates the address through I 2 The C bus sends a bit signal to the master node; if the first slave node sends the identification information to the master node first after the bit signal sent by the first slave node and the bit signals sent by other slave nodes are arbitrated, the first slave node is determined as the target slave node; the first slave node obtains the first I 2 C address.

[0007] First, the first slave node is k. i Any node among the k slave nodes i The slave nodes are the ones that are not assigned to I among the N slave nodes. 2 In addition, the master node allocates I 2 C address, it will go through N rounds of I 2 C address allocation, and each round of allocation allocates an I to each slave node 2 C address. In the i-th round I 2 C address allocation (i.e. any round of I 2 C address allocation), the first slave node will, based on the identification information of the first slave node, 2 The C bus sends a bit signal to the master node, and the first slave node will communicate with k after sending the bit signal. i The bit signals sent by the k slave nodes except the first slave node are arbitrated; if the first slave node is the k i The first slave node among the slave nodes that first sends the identification information to the master node will determine itself as the target slave node, that is, in the i-th round I 2 C address allocation, confirming that it is the slave node that has obtained priority. Then, the master node will allocate I 2 C address, and accordingly, the first slave node will obtain the first I C address assigned by the master node from the master node. 2 C address and exit I 2 C address allocation process. This is achieved in round i 2 C address allocation process, assigning I 2C address, so after N rounds of I 2 After the C address is assigned, an I 2 C address, so there is no need to add complex wiring between the master node and the slave node, and the slave node only needs to arbitrate based on the sent bit signal to achieve I 2 Dynamic allocation of I C addresses realizes 2 The universality of dynamic allocation of C addresses.

[0008] In one embodiment of the present application, N slave nodes are I 2 The slave nodes are the same type of slave nodes among all the slave nodes connected to the C bus, or the N slave nodes are all the slave nodes on the bus.

[0009] It can be seen that in the implementation mode of the present application, it is possible not to distinguish the slave nodes, and all the slave nodes on the bus are uniformly assigned I 2 C address, further increase the dynamic I 2 Alternatively, all slave nodes on the bus can be grouped based on the type of slave node, and then the slave nodes in each group are assigned I / O addresses in turn. 2 C address, so that the slave nodes of a group are assigned I 2 C address, that is, you can use an address segment's I 2 C addresses are assigned to slave nodes of the same type, making it easier for subsequent I 2 C address management.

[0010] In one embodiment of the present application, the method further comprises: Step S1: In the jth arbitration, the first slave node 2 The C bus sends the jth bit signal in the identification information to the master node; the first slave node is a slave node among the slave nodes that obtain a high priority during the j-1th arbitration; step S2: the first slave node obtains a high priority based on the jth bit signal and the jth arbitration. 2 The data on the C bus determines the priority of the first slave node at the jth arbitration, and the priority of the first slave node at the jth arbitration is a high priority or a low priority; 2 The data on the C bus is jointly determined by the bit signal sent by the slave node that obtains the high priority in the j-1 arbitration at the j arbitration; assign j=j+1, and repeat the above steps S1 to S2. After multiple arbitrations, if the priority of the first slave node in each arbitration is the high priority, the first slave node will first send the identification information to the master node.

[0011] It can be seen that in the embodiment of the present application, the slave node that obtained the priority in the previous arbitration will determine whether it is a priority slave node in the current arbitration based on the bit signal sent by the slave node and the data on the bus during the current arbitration. If it is, it will continue to participate in the next arbitration process, otherwise it will exit the arbitration. Since the identification information of the slave nodes is not exactly the same, the arbitration mechanism of the present application can ensure that the slave nodes are prioritized in each round. 2 When assigning I C addresses, only one slave node can first send the identification information to the master node, so that the master node can dynamically assign I C addresses to each slave node. 2 C address.

[0012] In one embodiment of the present application, the method further includes: if the priority of the first slave node in any arbitration among the multiple arbitrations is a low priority, the first slave node withdraws from the next arbitration.

[0013] It can be seen that in this embodiment, if the priority of a slave node is low in a certain arbitration, it will actively withdraw from the arbitration. In this way, with multiple arbitrations, many slave nodes with low priorities will gradually withdraw from the arbitration process, thus ensuring that the slave nodes that have always obtained high priorities always participate in the arbitration, and also ensuring that in each I 2 After multiple arbitrations in the process of C address, only one slave node can send the identification information completely to the master node, thereby realizing that the arbitration mechanism can be used in each round of I 2 When assigning C addresses, the master node dynamically assigns I 2 C address, the arbitration mechanism can be used to complete I 2 C address allocation, no need to design complex wiring structure.

[0014] In one embodiment of the present application, the first slave node is based on the j-th bit signal and the j-th arbitration time I 2 C bus, determine the priority of the first slave node at the jth arbitration, including: if the jth bit signal is equal to the jth arbitration I 2 C bus, the first slave node determines that the priority of the first slave node at the jth arbitration is high priority; if the jth bit signal is the same as the I 2 The data on the C bus are different, and the first slave node determines that the priority of the first slave node at the jth arbitration is a low priority.

[0015] If, in the jth arbitration cycle, a bit signal sent by a slave node is 0, the data on the bus is 0, where 0 represents a high priority; only when the bit signals sent by all slave nodes are 1, the data on the bus is 1. It can be seen that in this embodiment, in the jth arbitration cycle, the slave node can compare the bit signal sent by itself with the bit signal on the bus. 2 C bus, that is, the priority of the bit signal sent by itself is not lower than that of other slave nodes, it will be regarded as a high-priority slave node and continue to participate in arbitration; when the bit signal sent by itself is the same as that of I 2 C bus is not the same, that is, the priority of the bit signal sent by itself is lower than the priority of other slave nodes, it will automatically exit the arbitration process.

[0016] In one embodiment of the present application, the number of times a slave node arbitrates can be preset. For example, the slave node can be set to arbitrate M times, where M is determined based on the length of the identification information of the slave node. For example, the length of the longest identification information among N slave nodes can be used as M. It is understandable that the length of identification information of different slave nodes should be different, so that before the jth arbitration cycle, some slave nodes may have sent all the identification information, that is, some slave nodes may have no identification to send. In view of this situation, in the jth arbitration, the first slave node sends the identification information through I 2 The C bus sends the j-th bit signal in the identification information to the master node, including: if the length of the identification information of the first slave node is less than j, the first slave node sends a preset bit signal to the master node as the j-th bit signal of the identification information of the first slave node; if the length of the identification information of the first slave node is greater than or equal to j, the first slave node sends the j-th bit signal in the identification information to the master node.

[0017] It can be seen that in the embodiment of the present application, for the case where the length of the identification information is different, if a high-priority slave node has no identification information to send during a certain arbitration, it will continue to participate in the arbitration by sending bit 1. In this way, it is not necessary to pay attention to the length of the identification information of the slave node; in other words, the present application can complete I for all types of slave nodes. 2 Dynamic allocation of I C addresses further improves the 2 The universality of dynamic allocation of C addresses.

[0018] In one embodiment of the present application, the lengths of the identification information of the N slave nodes are in the same interval. It should be noted that the number of arbitration times is determined by the length of the longest identification information. 2Before C addresses are assigned, slave nodes whose identification information lengths are in the same range can be mounted on the same bus, or slave nodes whose identification information lengths are in the same range can be grouped in the same group. This can avoid the situation where some slave nodes with relatively short lengths need to resend a large number of bit 1s due to large differences in the lengths of the identification information, thereby increasing the power consumption and pressure of these slave nodes in sending bits.

[0019] In one embodiment of the present application, the first slave node is based on the identification information of the first slave node. 2 Before the C bus sends a bit signal to the master node, the method further includes: the first slave node obtains a first command from the master node, the first command including a first address and a read indication, the first address is used to address the first slave node; the read indication is used to instruct the first slave node to send identification information, so that the first slave node, based on the identification information of the first slave node, transmits the first command to the master node through the I 2 The C bus sends a bit signal to the master node.

[0020] If the N slave nodes are of the same type, the first address is the class address of the N slave nodes, and the class address is used to identify the type of the N slave nodes; if the N slave nodes are all slave nodes, the first address is a broadcast address. Specifically, the first command is I 2 C communication protocol. That is, in this application, the existing I 2 C command timing, to send the first command, and through the first command to instruct the slave node to send identification information, to complete I 2 C addresses are dynamically allocated, eliminating the need to construct new commands and 2 C communication protocol, and there is no need to add new interfaces, so the entire I 2 The C address allocation process is more feasible, more compatible, and simpler.

[0021] In one embodiment of the present application, the first slave node obtains the first I from the master node. 2 C address, including: the first slave node obtains a second command from the master node, wherein the second command includes a first I 2 C address and write instruction; the first slave node responds to the write instruction, and the first I 2 C address is used as the I assigned by the master node to the first slave node. 2 C address.

[0022] Among them, the second command is also I 2 C communication protocol under the command sequence. That is to say, the present application can also use the existing I 2 C command timing, to send the second command, and through the second command to the first I 2C address is assigned to the first slave node, thereby eliminating the need to construct a new command and to 2 C communication protocol, and there is no need to add new interfaces, so the entire I 2 The C address allocation process is more feasible, more compatible, and simpler.

[0023] In one embodiment of the present application, in the first round I 2 Before the I C address is allocated, the method further includes: the first slave node obtains an address allocation command from the master node, wherein the address allocation command is used to indicate that the master node is about to perform I 2 C address allocation, so that when the first slave node obtains the read instruction in the first command, based on the identification information of the first slave node, through I 2 The C bus sends a bit signal to the master node.

[0024] The address allocation command includes a second address and a third address, and the second address and the third address are the same address; or, they are different addresses. Specifically, when the N slave nodes are slave nodes of the same type, the second address and the third address are both class addresses of the N slave nodes, and the class address is used to indicate the type of the N slave nodes; when the N slave nodes are I 2 C bus, the second address and the third address are broadcast addresses.

[0025] It can be seen that in the implementation mode of the present application, in the first round I 2 Before assigning C addresses, first assign the master node to 2 The I / O address assignment is instructed to the slave node through the address assignment command. 2 When a read instruction is received in the C command sequence, a bit signal of identification information can be actively sent, and when a write instruction is received, the I after the write instruction is known. 2 The C address is the I assigned by the master node. 2 C address. For the master node based on the existing I 2 C command timing dynamically allocated I 2 C addresses provide the basis.

[0026] In one embodiment of the present application, the first command is sent by the master node during the i-th read process; the second command is sent by the master node during the i-th write process; the i-th read process is the same data transmission process or a different data transmission process; the address allocation command is sent by the master node during the first read process; wherein the i-th read process, the i-th write process and the first read process are in the same I 2 C command sequence, I 2 C command timing and I 2 C communication protocol command timing matching.

[0027] It can be seen that in this embodiment, the master node and the slave node can reuse the existing I 2 C command sequence completes the entire I 2 C address is dynamically allocated, without constructing new commands and I 2 C communication protocol needs no changes, and there is no need to add new interfaces. Therefore, the entire I2C address allocation process is more feasible, more compatible, and simpler.

[0028] In a second aspect, the present application embodiment provides a kind of I 2 C address allocation method, the method is applied to the master node, the method comprises: in the i-th round I 2 When C address is allocated, get k i The identification information of the slave nodes, where k i The slave nodes perform the first i-1 rounds of I 2 After the C address is allocated, N slave nodes are not allocated I 2 C address slave node; get k i The slave nodes are based on the identification information through I 2 The bit signal sent by the C bus; sending the first I 2 C address; among them, the first slave node is k i The slave node that first sends the identification information to the master node when the slave nodes arbitrate based on the sent bit signal.

[0029] In the implementation of this application, the master node allocates I 2 C address, it will go through N rounds of I 2 C address allocation, and each round of allocation allocates an I to each slave node 2 C address. Specifically, in the i-th round I 2 C address allocation (i.e. any round of I 2 C address allocation), the master node first indicates k i The master node will allocate addresses to obtain k slave nodes. i The identification information of the slave nodes; accordingly, k i Each of the k slave nodes will send a bit signal of identification information based on the instruction of the master node, and i When the slave nodes send the bit signal of the identification information, arbitration will be performed based on the sent bit signal, and finally only one slave node (i.e., the first slave node) will first send the identification information (complete identification information) to the master node. 2 C address. The first slave node obtains an I 2 C address, it will exit I 2C address allocation process, achieving the goal of 2 C address allocation process, assigning I 2 C address. Therefore, after N rounds of I 2 After the C address is assigned, an I 2 C address, so there is no need to add complex wiring between the master node and the slave node. The master node can implement I 2 Dynamic allocation of I C addresses realizes 2 The universality of dynamic allocation of C addresses.

[0030] In one embodiment of the present application, N slave nodes are I 2 The slave nodes are the same type of slave nodes among all the slave nodes connected to the C bus, or the N slave nodes are all the slave nodes on the bus.

[0031] It can be seen that in the implementation mode of the present application, it is possible not to distinguish the slave nodes, and all the slave nodes on the bus are uniformly assigned I 2 C address, further increase the dynamic I 2 Alternatively, all slave nodes on the bus can be grouped based on the type of slave node, and then the slave nodes in each group are assigned I / O addresses in turn. 2 C address, so that the slave nodes of a group are assigned I 2 C address, that is, you can use an address segment's I 2 C addresses are assigned to slave nodes of the same type, making it easier for subsequent I 2 C address management.

[0032] In one embodiment of the present application, k is obtained. i The identification information of a slave node includes: sending a first command, wherein the first command includes a first address and a read indication, and the first address is used to address k i slave nodes, the read indication is used to indicate k i The slave nodes send identification information so that k i The slave nodes are based on the identification information through I 2 C bus sends bit signals.

[0033] If the N slave nodes are of the same type, the first address is the category address of the N slave nodes, and the category address is used to identify the types of the N slave nodes; if the N slave nodes are all slave nodes, the first address is a broadcast address.

[0034] Furthermore, the first command is I 2C communication protocol under the command sequence. It can be seen that in this application, the master node can reuse the existing I 2 C command timing, to send the first command, and through the first command to instruct the slave node to send identification information, to complete I 2 C addresses are dynamically allocated, so there is no need to construct new commands, modify the communication protocol, or add new interfaces. I2 The C address allocation process is more feasible, more compatible, and simpler.

[0035] In one embodiment of the present application, a first I is sent to a first slave node. 2 C address, including: sending a second command, wherein the second command includes a first I 2 C address and write instruction, the write instruction is used to transfer the first I 2 The C address is assigned to the first slave node.

[0036] Among them, the second command is also I 2 C communication protocol under the command sequence. It can be seen that in this application, the master node can also reuse the existing I 2 C command timing, to send the second command, and through the second command to the first I 2 C address is assigned to the first slave node, thereby eliminating the need to construct a new command and to 2 C communication protocol, and there is no need to add new interfaces, so the entire I 2 The C address allocation process is more feasible, more compatible, and simpler.

[0037] In one embodiment of the present application, the method further includes: sending an address allocation command, the address allocation command is used to indicate that the master node is going to I 2 C address assignment to indicate k i When a slave node obtains the read instruction in the first command, based on the identification information, it sends the I 2 C bus sends bit signals.

[0038] The address allocation command includes a second address and a third address, and the second address and the third address are the same address; or, they are different addresses. Specifically, when the N slave nodes are slave nodes of the same type, the second address and the third address are both class addresses of the N slave nodes, and the class address is used to indicate the type of the N slave nodes; when the N slave nodes are I 2 C bus, the second address and the third address are broadcast addresses.

[0039] It can be seen that in the implementation mode of the present application, in the first round I 2 Before allocating C addresses, the master node first2 The I / O address assignment is instructed to the slave node through the address assignment command. 2 When a read instruction is received in the C command sequence, a bit signal of identification information can be actively sent, and when a write instruction is received, the I after the write instruction is known. 2 The C address is the I assigned by the master node. 2 C address. The master node reuses the existing I 2 C command timing to dynamically allocate I 2 C addresses provide the basis.

[0040] In one embodiment of the present application, the first command is sent by the master node during the i-th read process; the second command is sent by the master node during the i-th write process; the address allocation command is sent by the master node during the first read process; the i-th read process, the i-th write process and the first read process are in the same I 2 C command sequence; I 2 C command timing and I 2 C communication protocol command timing matching.

[0041] It can be seen that in this embodiment, the master node and the slave node can reuse the existing I 2 C command sequence completes the entire I 2 C address is dynamically allocated, without constructing new commands and I 2 C communication protocol needs no changes, and there is no need to add new interfaces. Therefore, the entire I2C address allocation process is more feasible, more compatible, and simpler.

[0042] In one embodiment of the present application, the method further includes: when the master node performs N rounds of I 2 After the C addresses are assigned, the master node sends an end signal, which is used to indicate that the master node has completed I for N slave nodes. 2 C address allocation.

[0043] It can be seen that in this embodiment, first, the master node pre-configures the waiting allocation I 2 The number of slave nodes at the C address is N, so that the master node perceives that N rounds of I 2 After the I C address is assigned, the end signal can be sent autonomously to end the entire I 2 C address allocation process to release the bus.

[0044] In one embodiment of the present application, the method further includes: if the master node does not obtain k i-1 slave node identification information, and when a negative confirmation is obtained, the master node sends an end signal, which is used to indicate that the master node has completed I for N slave nodes. 2 C address allocation, where k i -1 slave node is k i The slave nodes other than the first slave node among the slave nodes.

[0045] In actual applications, the master node may not know the number of slave nodes. For example, the number of slave nodes is not pre-configured. Or, even if the number of slave nodes is configured, the number of slave nodes currently participating in the address allocation may not be known due to some special circumstances. For example, some slave nodes are faulty or not powered on, so they do not participate in the arbitration and address allocation process. In this case, the number of slave nodes that actually need to be allocated addresses will be less than the pre-configured number. At this time, the master node cannot allocate addresses according to the configured number of slave nodes. Therefore, in this embodiment, after completing the i-th round of address allocation, that is, completing the current round of i, the master node will allocate addresses according to the configured number of slave nodes. 2 After the C address is allocated, the master node does not pay attention to whether an address is allocated to each slave node, but continues the next round of address allocation. If the device identifier is not obtained when instructing the slave node to send identification information in the next round of address allocation, it means that all slave nodes have been allocated addresses in the current round. Therefore, the master node perceives that all slave nodes have been allocated I 2 C address can end the address allocation process autonomously, so that the master node can complete the address allocation process without knowing the number of slave nodes in advance.

[0046] In a third aspect, the present application embodiment provides a kind of I 2 C address allocation method, the method is applied to a computing device, the computing device includes a master node and N slave nodes, the master node and the N slave nodes are connected via I 2 C bus connection; the method comprises: in the i-th round I 2 When C address is allocated, the master node obtains k i The identification information of the slave nodes; among them, k i The slave nodes perform the first i-1 rounds of I 2 After the C address is allocated, N slave nodes are not allocated I 2 C address slave node; k i Each slave node in the slave nodes is based on the identification information through I 2 C bus sends a bit signal of identification information to the master node; i Each of the slave nodes arbitrates with other slave nodes based on the transmitted bit signal; the master node allocates the first I 2 C address, the first slave node is k iThe slave node that first sends the identification information to the master node when the slave nodes arbitrate based on the sent bit signal.

[0047] First of all, the master node allocates I to N slave nodes. 2 C address, it will go through N rounds of I 2 C address allocation, and each round of allocation allocates an I to each slave node 2 C address. In the i-th round I 2 C address allocation (i.e. any round of I 2 C address allocation), the master node first indicates k i Each of the k slave nodes sends identification information, and then i Each slave node in the slave nodes is based on the identification information through I 2 The C bus sends a bit signal of identification information to the master node, and arbitrates with other slave nodes based on the sent bit signal. In this way, arbitration is performed through identification information, and only one slave node (i.e., the first slave node) will first send identification information (complete identification information) to the master node. Accordingly, the master node will assign the first I2C bus to the first slave node. 2 C address. The first slave node obtains an I 2 C address, it will exit I 2 C address allocation process, achieving the goal of 2 C address allocation process, assigning I 2 C address. Therefore, after N rounds of I 2 After the C address is assigned, an I 2 C address, so there is no need to add complex wiring between the master node and the slave node. The master node can implement I 2 Dynamic allocation of I C addresses realizes 2 The universality of dynamic allocation of C addresses.

[0048] In one embodiment of the present application, N slave nodes are I 2 The slave nodes are the same type of slave nodes among all the slave nodes connected to the C bus, or the N slave nodes are all the slave nodes on the bus.

[0049] It can be seen that in the implementation mode of the present application, it is possible not to distinguish the slave nodes, and all the slave nodes on the bus are uniformly assigned I 2 C address, further increase the dynamic I 2 Alternatively, all slave nodes on the bus can be grouped based on the type of slave node, and then the slave nodes in each group are assigned I / O addresses in turn. 2C address, so that the slave nodes of a group are assigned I 2 C address, that is, you can use an address segment's I 2 C addresses are assigned to slave nodes of the same type, making it easier for subsequent I 2 C address management.

[0050] In one embodiment of the present application, k i Each slave node in the slave nodes is based on the identification information through I 2 The C bus sends a bit signal to the master node, including: in the jth arbitration, the first slave node sends the jth bit signal of the identification information to the master node, wherein the first slave node is k i Any one of the slave nodes that obtains high priority in the j-1th arbitration among the slave nodes; k i Each slave node in the j slave nodes arbitrates with other slave nodes based on the transmitted bit signal, including: the first slave node arbitrates based on the j-th bit signal, and I 2 C bus, determines the priority of the first slave node at the jth arbitration, wherein the priority of the first slave node at the jth arbitration is high priority or low priority; after M arbitrations, if the priority of the first slave node at each arbitration is high priority, the first slave node first sends the identification information to the master node; if the priority of the first slave node at any arbitration in multiple arbitrations is low priority, the first slave node exits the next arbitration.

[0051] It can be seen that in the embodiment of the present application, the slave node that obtained the priority in the previous arbitration will determine whether it is a priority slave node in the current arbitration based on the bit signal sent by the slave node and the data on the bus during the current arbitration. If it is, it will continue to participate in the next arbitration process, otherwise it will exit the arbitration. Since the identification information of the slave nodes is not exactly the same, the arbitration mechanism of the present application can ensure that the slave nodes are prioritized in each round. 2 When C addresses are allocated, only one slave node can send identification information to the master node first. In this way, in the i-th round of address allocation, the first slave node will first send identification information to the master node. That is to say, in the i-th round of address allocation, only I will be allocated to the first slave node. 2 C address, realize the arbitration mechanism can be performed in each round 2 When assigning C addresses, the master node dynamically assigns I 2 C address, the arbitration mechanism can be used to complete I 2 C address allocation, no need to design complex wiring structure.

[0052] In one embodiment of the present application, the first slave node is based on the j-th bit signal and the j-th arbitration time I 2 C bus, determine the priority of the first slave node at the jth arbitration, including: if the jth bit signal is equal to the jth arbitration I 2 C bus, the first slave node determines that the priority of the first slave node at the jth arbitration is high priority; if the jth bit signal is the same as the I 2 The data on the C bus are different, and the first slave node determines that the priority of the first slave node at the jth arbitration is a low priority.

[0053] If, in the jth arbitration cycle, a bit signal sent by a slave node is 0, the data on the bus is 0, where 0 represents a high priority; only when the bit signals sent by all slave nodes are 1, the data on the bus is 1. It can be seen that in this embodiment, in the jth arbitration cycle, the slave node can compare the bit signal sent by itself with the bit signal on the bus. 2 C bus, that is, the priority of the bit signal sent by itself is not lower than that of other slave nodes, it will be regarded as a high-priority slave node and continue to participate in arbitration; when the bit signal sent by itself is the same as that of I 2 C bus is not the same, that is, the priority of the bit signal sent by itself is lower than the priority of other slave nodes, it will automatically exit the arbitration process.

[0054] In one embodiment of the present application, the number of times the slave node arbitrates can be preset, for example, the slave node can be set to arbitrate M times, where M is determined based on the length of the identification information of the slave node. For example, the length of the longest identification information among the N slave nodes can be taken as M. It is understandable that the length of the identification information of different slave nodes should be different, so that before the jth arbitration cycle, some slave nodes may have sent all the identification information, that is, some slave nodes may have no identification to send. In response to this situation, the first slave node sends the jth bit signal of the identification information to the master node, including: if the length of the identification information of the first slave node is less than j, the first slave node sends a preset bit signal to the master node as the jth bit signal of the identification information of the first slave node; if the length of the identification information of the first slave node is greater than or equal to j, the first slave node sends the jth bit signal in the identification information to the master node.

[0055] It can be seen that in the embodiment of the present application, for the case where the length of the identification information is different, if a high-priority slave node has no identification information to send during a certain arbitration, it will continue to participate in the arbitration by sending bit 1. In this way, it is not necessary to pay attention to the length of the identification information of the slave node; in other words, the present application can complete I for all types of slave nodes. 2 Dynamic allocation of I C addresses further improves the 2 The universality of dynamic allocation of C addresses.

[0056] In one embodiment of the present application, the identification information of N slave nodes is located in the same interval. It should be noted that the number of arbitrations is determined by the length of the longest identification information. 2 Before C addresses are assigned, slave nodes whose identification information lengths are in the same range can be mounted on the same bus, or slave nodes whose identification information lengths are in the same range can be grouped in the same group. This can avoid the situation where some slave nodes with relatively short lengths need to resend a large number of bit 1s due to large differences in the lengths of the identification information, thereby increasing the power consumption and pressure of these slave nodes in sending bits.

[0057] In one embodiment of the present application, the master node obtains k i The identification information of each slave node includes:

[0058] Send a first command, wherein the first command includes a first address and a read instruction, the first address is used to address k i slave nodes, the read indication is used to indicate k i The slave nodes send identification information so that k i The slave nodes are based on the identification information through I 2 C bus sends bit signals.

[0059] If the N slave nodes are of the same type, the first address is the class address of the N slave nodes, and the class address is used to identify the type of the N slave nodes; if the N slave nodes are all slave nodes, the first address is a broadcast address. Specifically, the first command is I 2 C communication protocol. That is, in this application, the existing I 2 C command timing, to send the first command, and through the first command to instruct the slave node to send identification information, to complete I 2 C addresses are dynamically allocated, eliminating the need to construct new commands and 2 C communication protocol, and there is no need to add new interfaces, so the entire I 2 The C address allocation process is more feasible, more compatible, and simpler.

[0060] In one embodiment of the present application, the master node allocates a first I 2 C address, including: sending a second command, wherein the second command includes a first I 2 C address and write instruction, the write instruction is used to transfer the first I 2 The C address is assigned to the first slave node.

[0061] Among them, the second command is also I 2 C communication protocol under the command sequence. That is to say, the present application can also use the existing I 2 C command timing, to send the second command, and through the second command to the first I 2 C address is assigned to the first slave node, thereby eliminating the need to construct a new command and to 2 C communication protocol, and there is no need to add new interfaces, so the entire I 2 The C address allocation process is more feasible, more compatible, and simpler.

[0062] In one embodiment of the present application, in the first round I 2 Before the I C address is allocated, the method further includes: sending an address allocation command, the address allocation command is used to indicate that the master node is going to I 2 C address assignment to indicate k i When a slave node obtains the read instruction in the first command, based on the identification information of the first slave node, the slave node 2 The C bus sends a bit signal to the master node.

[0063] The address allocation command includes a second address and a third address, and the second address and the third address are the same address; or, they are different addresses. Specifically, when the N slave nodes are slave nodes of the same type, the second address and the third address are both class addresses of the N slave nodes, and the class address is used to indicate the type of the N slave nodes; when the N slave nodes are I 2 C bus, the second address and the third address are broadcast addresses.

[0064] It can be seen that in the implementation mode of the present application, in the first round I 2 Before assigning C addresses, first assign the master node to 2 The I / O address assignment is instructed to the slave node through the address assignment command. 2 When a read instruction is received in the C command sequence, a bit signal of identification information can be actively sent, and when a write instruction is received, the I after the write instruction is known. 2 The C address is the I assigned by the master node. 2 C address. For the master node based on the existing I 2C command timing dynamically allocated I 2 C addresses provide the basis.

[0065] In one embodiment of the present application, the first command is sent by the master node during the i-th read process; the second command is sent by the master node during the i-th write process; the i-th read process is the same data transmission process or a different data transmission process; the address allocation command is sent by the master node during the first read process; wherein the i-th read process, the i-th write process and the first read process are in the same I 2 C command sequence, I 2 C command timing and I 2 C communication protocol command timing matching.

[0066] It can be seen that in this embodiment, the master node and the slave node can reuse the existing I 2 C command sequence completes the entire I 2 C address is dynamically allocated, without constructing new commands and I 2 C communication protocol needs no changes, and there is no need to add new interfaces. Therefore, the entire I2C address allocation process is more feasible, more compatible, and simpler.

[0067] In one embodiment of the present application, the method further includes: when the master node performs N rounds of I 2 After the C addresses are assigned, the master node sends an end signal, which is used to indicate that the master node has completed I for N slave nodes. 2 C address allocation.

[0068] It can be seen that in this embodiment, first, the master node pre-configures the waiting allocation I 2 The number of slave nodes at the C address is N, so that the master node perceives that N rounds of I 2 After the I C address is assigned, the end signal can be sent autonomously to end the entire I 2 C address allocation process to release the bus

[0069] In one embodiment of the present application, the method further includes: if the master node does not obtain k i -1 slave node identification information, and when a negative confirmation is obtained, the master node sends an end signal, which is used to indicate that the master node has completed I for N slave nodes. 2 C address allocation, where k i -1 slave node is k i The slave nodes other than the first slave node among the slave nodes.

[0070] In actual applications, the master node may not know the number of slave nodes. For example, the number of slave nodes is not pre-configured. Or, even if the number of slave nodes is configured, the number of slave nodes currently participating in the address allocation may not be known due to some special circumstances. For example, some slave nodes are faulty or not powered on, so they do not participate in the arbitration and address allocation process. In this case, the number of slave nodes that actually need to be allocated addresses will be less than the pre-configured number. At this time, the master node cannot allocate addresses according to the configured number of slave nodes. Therefore, in this embodiment, after completing the i-th round of address allocation, that is, completing the current round of i, the master node will allocate addresses according to the configured number of slave nodes. 2 After the C address is allocated, the master node does not pay attention to whether an address is allocated to each slave node, but continues the next round of address allocation. If the device identifier is not obtained when instructing the slave node to send identification information in the next round of address allocation, it means that all slave nodes have been allocated addresses in the current round. Therefore, the master node perceives that all slave nodes have been allocated I 2 C address can end the address allocation process autonomously, so that the master node can complete the address allocation process without knowing the number of slave nodes in advance.

[0071] In a fourth aspect, an embodiment of the present application provides a slave node, which is any one of N master nodes; the slave node includes: a transceiver unit and a processing unit;

[0072] The transceiver unit is used to perform the i-th round I 2 When assigning C addresses, based on the identification information of the first slave node, the I 2 The C bus sends a bit signal to the master node;

[0073] a processing unit, configured to determine the slave node as a target slave node if the slave node first sends identification information to the master node after arbitration between the bit signal sent by the slave node and the bit signals sent by other slave nodes;

[0074] The transceiver unit is also used to obtain the first I 2 C address.

[0075] In one embodiment of the present application, N slave nodes are I 2 The slave nodes are the same type of slave nodes among all the slave nodes connected to the C bus, or the N slave nodes are all the slave nodes on the bus.

[0076] In one embodiment of the present application, the processing unit is further configured to perform the following steps: Step S1: During the jth arbitration, the transceiver unit is controlled to receive the signal through I 2The C bus sends the jth bit signal in the identification information to the master node; the slave node is one of the slave nodes that obtain a high priority during the j-1th arbitration; step S2: based on the jth bit signal and I during the jth arbitration 2 The data on the C bus determines the priority of the slave node at the jth arbitration, and the priority of the slave node at the jth arbitration is high priority or low priority; 2 The data on the C bus is jointly determined by the bit signal sent by the slave node that obtains the high priority in the j-1th arbitration at the jth arbitration; assign j=j+1, and repeat the above steps S1 to S2. After multiple arbitrations, if the priority of the slave node in each arbitration is high, it is determined that the slave node sends the identification information to the master node first.

[0077] In one embodiment of the present application, the processing unit is further configured to: if the priority of the slave node in any arbitration among multiple arbitrations is a low priority, then the slave node withdraws from the next arbitration.

[0078] In one embodiment of the present application, based on the j-th bit signal and the j-th arbitration, 2 C bus, in determining the priority of the slave node at the jth arbitration, the processing unit is specifically used for:

[0079] If the j-th bit signal is equal to the j-th arbitration 2 C bus, the priority of the slave node at the jth arbitration is determined to be high priority; if the jth bit signal is the same as the I 2 The data on the C bus is different, and it is determined that the priority of the slave node in the jth arbitration is low priority.

[0080] In one embodiment of the present application, the number of times a slave node performs arbitration can be preset. For example, the slave node can be set to arbitrate M times, where M is determined based on the length of the identification information of the slave node. For example, the length of the longest identification information among N slave nodes can be used as M. It is understandable that the length of identification information of different slave nodes should be different, so that before the jth arbitration cycle, some slave nodes may have sent all the identification information, that is, some slave nodes may have no identification to send. In view of this situation, in I 2 In terms of sending the j-th bit signal in the identification information of the C bus to the master node, the processing unit is specifically configured to:

[0081] If the length of the identification information of the slave node is less than j, the control transceiver unit sends a preset bit signal to the master node as the j-th bit signal of the identification information of the slave node; if the length of the identification information of the slave node is greater than or equal to j, the control transceiver unit sends the j-th bit signal in the identification information to the master node.

[0082] In one embodiment of the present application, the lengths of the identification information of N slave nodes are in the same interval.

[0083] In one embodiment of the present application, the transceiver unit is further used to obtain a first command from the master node, the first command including a first address and a read indication, the first address is used to address the first slave node; the read indication is used to instruct the slave node to send identification information, so that the slave node, based on the identification information of the slave node, receives the first command from the master node through I 2 The C bus sends a bit signal to the master node.

[0084] In one embodiment of the present application, after obtaining the first I from the master node 2 In terms of the C address, the transceiver unit is specifically used to: obtain a second command from the master node, wherein the second command includes a first I 2 C address and write instruction; processing unit, further used to respond to the write instruction, the first I 2 C address is used as the I assigned by the master node to the first slave node. 2 C address.

[0085] In one embodiment of the present application, in the first round I 2 Before the I C address is allocated, the transceiver unit is also used to obtain an address allocation command from the master node, wherein the address allocation command is used to indicate that the master node is about to perform I 2 C address allocation, so that when the slave node obtains the read instruction in the first command, based on the identification information of the slave node, through I 2 The C bus sends a bit signal to the master node.

[0086] In one embodiment of the present application, the first command is sent by the master node during the i-th read process; the second command is sent by the master node during the i-th write process; the i-th read process is the same data transmission process or a different data transmission process; the address allocation command is sent by the master node during the first read process; wherein the i-th read process, the i-th write process and the first read process are in the same I 2 C command sequence, I 2 C command timing and I 2 C communication protocol command timing matching.

[0087] In a fifth aspect, an embodiment of the present application provides a master node, the master node comprising: a transceiver unit and a processing unit;

[0088] Processing unit, used for performing the i-th round I 2 When C address is allocated, get k i The identification information of the slave nodes, where k i The slave nodes perform the first i-1 rounds of I 2 After the C address is allocated, N slave nodes are not allocated I 2 The slave node of C address;

[0089] Transceiver unit, used to obtain k i The slave nodes are based on the identification information through I 2 The bit signal sent by the C bus; sending the first I 2 C address; among them, the first slave node is k i The slave node that first sends the identification information to the master node when the slave nodes arbitrate based on the sent bit signal.

[0090] In one embodiment of the present application, N slave nodes are I 2 The slave nodes are the same type of slave nodes among all the slave nodes connected to the C bus, or the N slave nodes are all the slave nodes on the bus.

[0091] In one embodiment of the present application, when obtaining k i In terms of identification information of a slave node, the processing unit is specifically used to: control the transceiver unit to send a first command, wherein the first command includes a first address and a read indication, and the first address is used to address k i slave nodes, the read indication is used to indicate k i The slave nodes send identification information so that k i The slave nodes are based on the identification information through I 2 C bus sends bit signals.

[0092] In one embodiment of the present application, when sending a first I to the first slave node 2 In terms of the C address, the transceiver unit is specifically used to: send a second command, wherein the second command includes a first I 2 C address and write instruction, the write instruction is used to transfer the first I 2 The C address is assigned to the first slave node.

[0093] In one embodiment of the present application, the transceiver unit is further used to: send an address allocation command, the address allocation command is used to indicate that the master node is going to perform I 2 C address assignment to indicate k i When a slave node obtains the read instruction in the first command, based on the identification information, it sends the I 2 C bus sends bit signals.

[0094] In one embodiment of the present application, the first command is sent by the master node during the i-th read process; the second command is sent by the master node during the i-th write process; the address allocation command is sent by the master node during the first read process; the i-th read process, the i-th write process and the first read process are in the same I 2 C command sequence; I 2 C command timing and I 2 C communication protocol command timing matching.

[0095] In one embodiment of the present application, the transceiver unit is further configured to: when the master node performs N rounds of I 2 After the C address is assigned, an end signal is sent to indicate that the master node has completed I for N slave nodes. 2 C address allocation.

[0096] In one embodiment of the present application, the transceiver unit is further configured to: if k is not obtained i -1 slave node identification information, and when a negative confirmation is obtained, an end signal is sent, which is used to indicate that the master node has completed I for N slave nodes. 2 C address allocation, where k i -1 slave node is k i The slave nodes other than the first slave node among the slave nodes.

[0097] In a sixth aspect, an embodiment of the present application provides a computing device; the computing device includes a master node and N slave nodes, and the master node and the N slave nodes are connected via I 2 C bus connection;

[0098] The master node is used to perform the i-th round of 2 When C address is allocated, get k i The identification information of the slave nodes; among them, k i The slave nodes perform the first i-1 rounds of I 2 After the C address is allocated, N slave nodes are not allocated I 2 The slave node of C address;

[0099] k i Each slave node in the slave nodes is used to transmit the information based on the identification information through I 2 The C bus sends a bit signal of identification information to the master node; based on the sent bit signal, it arbitrates with other slave nodes;

[0100] The master node is also used to allocate the first I 2 C address, the first slave node is k i The slave node that first sends the identification information to the master node when the slave nodes arbitrate based on the sent bit signal.

[0101] In one embodiment of the present application, N slave nodes are I 2 The slave nodes are the same type of slave nodes among all the slave nodes connected to the C bus, or the N slave nodes are all the slave nodes on the bus.

[0102] In one embodiment of the present application, based on the identification information, through I 2 C bus sends bit signals to the master node, k i Each of the slave nodes is specifically used for: in the jth arbitration, the first slave node sends the jth bit signal of the identification information to the master node, wherein the first slave node is k i Any one of the slave nodes that obtains the high priority in the j-1th arbitration among the slave nodes; in terms of arbitration with other slave nodes based on the transmitted bit signal, k i Each slave node in the slave nodes is specifically configured to: the first slave node is based on the j-th bit signal, and at the j-th arbitration 2 C bus, determines the priority of the first slave node at the jth arbitration, wherein the priority of the first slave node at the jth arbitration is high priority or low priority; after M arbitrations, if the priority of the first slave node at each arbitration is high priority, the first slave node first sends the identification information to the master node; if the priority of the first slave node at any arbitration in multiple arbitrations is low priority, the first slave node exits the next arbitration.

[0103] In one embodiment of the present application, the first slave node is based on the j-th bit signal and the j-th arbitration. 2 C bus, determine the priority of the first slave node in the jth arbitration, the first slave node is specifically used to: if the jth bit signal is equal to the jth arbitration I 2 C bus, the first slave node determines that the priority of the first slave node at the jth arbitration is high priority; if the jth bit signal is the same as the I 2 The data on the C bus are different, and the first slave node determines that the priority of the first slave node at the jth arbitration is a low priority.

[0104] In one embodiment of the present application, in terms of the j-th bit signal of identification information sent by the first slave node to the master node, the first slave node is specifically used to: if the length of the identification information of the first slave node is less than j, the first slave node sends a preset bit signal to the master node as the j-th bit signal of the identification information of the first slave node; if the length of the identification information of the first slave node is greater than or equal to j, the first slave node sends the j-th bit signal in the identification information to the master node.

[0105] In one embodiment of the present application, identification information of N slave nodes is located in the same interval.

[0106] In one embodiment of the present application, the master node obtains k i In terms of identification information of a slave node, the master node is specifically used to: send a first command, wherein the first command includes a first address and a read indication, and the first address is used to address k i slave nodes, the read indication is used to indicate k i The slave nodes send identification information so that k i The slave nodes are based on the identification information through I 2 C bus sends bit signals.

[0107] In one embodiment of the present application, the master node allocates a first I to the first slave node. 2 In terms of the C address, the master node is specifically used to: send a second command, wherein the second command includes the first I 2 C address and write instruction, the write instruction is used to transfer the first I 2 The C address is assigned to the first slave node.

[0108] In one embodiment of the present application, in the first round I 2 Before the I C address is allocated, the master node is also used to: send an address allocation command, which is used to indicate that the master node is about to perform I 2 C address assignment to indicate k i When a slave node obtains the read instruction in the first command, based on the identification information of the first slave node, the slave node 2 The C bus sends a bit signal to the master node.

[0109] In one embodiment of the present application, the first command is sent by the master node during the i-th read process; the second command is sent by the master node during the i-th write process; the i-th read process is the same data transmission process or a different data transmission process; the address allocation command is sent by the master node during the first read process; wherein the i-th read process, the i-th write process and the first read process are in the same I 2 C command sequence, I 2 C command timing and I 2 C communication protocol command timing matching.

[0110] In one embodiment of the present application, the master node is further used to: when the master node performs N rounds of I 2 After the C address is assigned, an end signal is sent to indicate that the master node has completed I for N slave nodes. 2 C address allocation.

[0111] In one embodiment of the present application, the master node is further used to: if the master node does not obtain k i -1 slave node identification information, and when a negative confirmation is obtained, an end signal is sent, which is used to indicate that the master node has completed I for N slave nodes. 2 C address allocation, where k i -1 slave node is k i The slave nodes other than the first slave node among the slave nodes.

[0112] In the seventh aspect, an embodiment of the present application provides an electronic device, comprising: a memory for storing programs; a processor for executing the programs stored in the memory; when the program stored in the memory is executed, the processor is used to implement the method in the first aspect or the second aspect above.

[0113] In an eighth aspect, an embodiment of the present application provides a computer-readable medium, which stores a program code for execution by a device, and the program code is used to implement the method of the first aspect or the second aspect mentioned above.

[0114] In a ninth aspect, an embodiment of the present application provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to implement the method in the first or second aspect above.

[0115] In a tenth aspect, an embodiment of the present application provides a computing device, which includes the first slave node as in the first aspect; or the computing device includes the master node as in the second aspect; or the computing device includes the computing device as in the third aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0116] Figure 1 A schematic diagram of a command timing for data reading and writing between a master node and a slave node;

[0117] Figure 2 A schematic diagram of a server provided in an embodiment of the present application;

[0118] Figure 3 A method I provided in the embodiment of the present application 2 C. Flow chart of the address allocation method;

[0119] Figure 4 A method for providing a method for 2 All slave nodes on the C bus perform I 2 Schematic diagram of C address allocation;

[0120] Figure 5 A method for performing I on slave nodes of the same type provided in an embodiment of the present application 2 Schematic diagram of C address allocation;

[0121] Figure 6 The embodiment of the present application provides an I in the i-th reading process. 2 Schematic diagram of C command timing;

[0122] Figure 7 A schematic diagram of addressing all slave nodes through a broadcast address provided in an embodiment of the present application;

[0123] Figure 8 A schematic diagram of addressing N slave nodes corresponding to a class address through a class address provided in an embodiment of the present application;

[0124] Fig. 9 The first reading process provided by the embodiment of the present application is 2 Schematic diagram of C command timing;

[0125] Fig.10 A schematic diagram of an embodiment of the present application providing a method of instructing a master node to allocate addresses by broadcasting addresses twice;

[0126] Fig.11 A schematic diagram of an embodiment of the present application providing a method of allocating addresses by indicating a master node twice through a class address;

[0127] Fig.12 A slave node provided in an embodiment of the present application is connected to the I 2 C is a schematic diagram of sending identification information;

[0128] Fig.13 A schematic diagram of sending identification information based on an arbitration mechanism provided in an embodiment of the present application;

[0129] Fig.14 A method for allocating a first I provided in an embodiment of the present application 2 Schematic diagram of C address;

[0130] Fig.15 Another method for allocating a first I provided in an embodiment of the present application 2 Schematic diagram of C address;

[0131] Fig.16 The present application provides a method for completing I between a master node and N slave nodes through a complete command sequence. 2 C address allocation process;

[0132] Fig.17 Another embodiment of the present application provides a master node and N slave nodes to complete I through a complete command timing 2 C address allocation process;

[0133] Fig.18Another method provided in the embodiment of the present application is to complete I between a master node and N slave nodes through a complete command timing sequence. 2 C address allocation process;

[0134] Fig.19 Another method provided in the embodiment of the present application is to complete I between a master node and N slave nodes through a complete command timing sequence. 2 C address allocation process;

[0135] Fig. 20 A schematic diagram of a slave node provided in an embodiment of the present application;

[0136] Fig.21 A schematic diagram of a master node provided in an embodiment of the present application;

[0137] Fig. 22 A schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0138] In order to understand the present application, various professional terms involved in the present application are first introduced.

[0139] S: Start bit, indicating the start of the command sequence, the full name is Start, abbreviated as S;

[0140] Slave Address: slave node address, commonly used in the data reading and writing process of the master node;

[0141] R / W: Read / write indication bit, indicating that the master node reads or writes data. 2 A bit indication in the C command sequence; when the value of this bit is 1, it indicates data reading, the full name is Read, abbreviated as R; when the value of this bit is 0, it indicates data writing, the full name is Write, abbreviated as W;

[0142] A / NACK: confirmation or negative confirmation indication bit, through I 2 A bit indication in the C command sequence. When the value of this bit is 0, it indicates confirmation, the full name is Acknowledge, abbreviated as A; when the value of this bit is 1, it indicates negative confirmation, the full name is Negative-Acknowledgment, abbreviated as NACK;

[0143] Sr: Repeat start bit, indicating that the command sequence is restarted, the full name is Repeat Start, abbreviated as Sr;

[0144] P: Indicates the stop bit, indicating the end of the command sequence.

[0145] First, it is explained that the data transmission between the master node and the slave node is in bytes, that is, 8 bits are transmitted each time. The following is a description of the manner in which the master node reads and writes data based on the command sequence in conjunction with the accompanying drawings.

[0146] like Figure 1 As shown, when the master node and the slave node transmit data, the master node first transmits 2 C bus sends the start bit S to activate the I 2 Each slave node on the C bus. The master node sends the slave node's 7-bit I 2 C address (i.e. Slave Adress) and 1-bit read / write indication, where Slave Adress is used to indicate the slave node addressed by the master node, and 1-bit read / write indication indicates the master node to read or write data. If the master node reads data, the addressed slave node replies with an ACK after receiving the byte and takes over I 2 The C bus transmits data to the master node; the master node replies an ACK to the slave node for each byte of data it receives, and after obtaining the expected number of bytes, it sends a NACK to the slave node; if the master node writes data, the addressed slave node replies an ACK after receiving the byte. After that, the master node writes data to the slave node. The slave node replies an ACK for each byte it obtains. When the data transmission is completed, the master node sends a stop signal P to end the data transmission and release the bus.

[0147] It should be noted that the master node and N slave nodes of the present application can be hardware modules in any computing device. Among them, the computing device can be a user device, a vehicle-mounted device, a computing device, and the like. The present application is mainly explained by taking the computing device as a server as an example. Accordingly, the master node is a device management module in the server, for example, a baseboard management controller (Baseboard Management Controller, BWC) in the server; or, iLO in an HPE server, iDRAC in a Dell server. The slave node can be a hardware module in the server, such as a sensor, a memory, a controller, and the like. For example, the sensor can be a temperature sensor or a light sensor.

[0148] For the convenience of description, the I 2 C address allocation, also known as address allocation, for example, the master node allocates I 2 C address, which can be referred to as the master node to allocate addresses to slave nodes; or the master node allocates I 2 C address, which can be referred to as the master node address allocation; I 2 C command timing, also referred to as command timing; I 2 C bus can also be referred to as bus.

[0149] See also Figure 2 , Figure 2 A schematic diagram of a server provided in an embodiment of the present application. The server includes a master node 10, N slave nodes 20 and I 2 C bus 30. The master node 10 and N slave nodes 20 are connected via I 2 C bus 30 is connected.

[0150] In the i-th round I 2 When C address is allocated, the master node obtains k i The identification information of the slave nodes is obtained from k in the i-th round of address allocation. i A slave node obtains the complete identification information of a slave node; among them, k i The slave nodes perform the first i-1 rounds of I 2 After the C address is allocated, N slave nodes are not allocated I 2 C address slave node, N slave nodes are waiting for the bus to be assigned I 2 C address of the slave node. Accordingly, k i Each slave node in the slave nodes is based on the identification information through I 2 The C bus 30 sends a bit signal to the master node, that is, when the slave node of the present application sends a bit signal, it can send the bit position in the identification information one bit at a time; i Each of the k slave nodes arbitrates with other slave nodes based on the bit signal sent; i When the first slave node among the slave nodes first sends the identification information (complete identification information) to the master node based on the transmitted bit signal, the master node allocates the first I 2 C address, thus completing round i 2 C address allocation.

[0151] Furthermore, the master node in round i 2 C address allocation is the first slave node allocation I 2 C address, the first slave node will exit I 2 C address allocation process, and the master node will perform the i+1th round of I 2 C address allocation, so after N rounds of I 2 After the C addresses are allocated, the master node can allocate I addresses to all N slave nodes. 2 C address, so as to dynamically allocate I to each slave node without changing the connection mode between the master and slave nodes. 2 C address, which means that it can be used in any I 2 In the C communication scenario, each slave node is dynamically assigned an address, realizing I 2 The universality of dynamic allocation of C addresses.

[0152] See also Figure 3 , Figure 3 A method I provided in the embodiment of the present application 2 C is a flowchart of the address allocation method. The method is applied to the above-mentioned server. The method includes but is not limited to the following steps:

[0153] 301. In the i-th round I 2 When C address is allocated, the master node obtains k i The identification information of a slave node.

[0154] Among them, the above k i The slave nodes perform the first i-1 rounds of I 2 After the C address is allocated, N slave nodes are not allocated I 2 C address of the slave node, N is an integer greater than 1. N slave nodes are I 2 C bus waiting for the assignment of I 2 C address of the slave node.

[0155] This application is in progress 2 When C address is assigned, Figure 4 As shown, the master node can 2 All slave nodes on the C bus perform I 2 C address allocation; such as Figure 5 As shown, the master node can also allocate slave nodes of the same type first and then allocate slave nodes of the same type according to the types of the slave nodes. 2 All slave nodes on the C bus can also be I 2 C bus of all slave nodes of a certain type.

[0156] It should be noted that when the master node is I 2 When allocating C addresses, the present application does not limit which type of slave node is assigned the address first and which type of slave node is assigned the address later, that is, the allocation order when allocating addresses according to the type of slave node is not limited. Optionally, the allocation order can be pre-configured in the master node, and the subsequent master node allocates addresses according to the type of slave node. 2 C When allocating addresses, addresses can be allocated according to the pre-configured allocation order.

[0157] It should be noted that the I 2 C address allocation is achieved through multiple rounds of address allocation, and each round of address allocation is a slave node allocation I 2 C address, so for N slave nodes, N rounds of address allocation are required to allocate an I 2C address. And the current round is assigned to I 2 The slave node with address C will no longer participate in the subsequent rounds of allocation of I 2 C address process.

[0158] Among them, the identification information of each slave node in the N slave nodes in this application is the unique identification of each slave node, and the identification information of different slave nodes is different. Exemplarily, the identification information of each slave node can be the device identification of each slave node, etc. The identification information and device identification mentioned later are essentially the same and do not need to be distinguished. Further, the device identification can be the serial number (Serial Number, SN) of each slave node, etc. This application is mainly explained by taking the identification information of each slave node as the SN of each slave node as an example, and does not limit the identification information of each slave node. Therefore, the device identification and identification information mentioned later can be understood as serial numbers and are no longer distinguished.

[0159] Further explanation: the device identification in the present application is represented by a binary bit string. For example, when the device identification of the slave node is SN, the device identification of the slave node can be a 128-bit bit string.

[0160] Optionally, the master node obtains k by command instruction i Specifically, the master node sends a first command, wherein the first command includes a first address and a read indication, the first address is used to address N slave nodes, and the read indication is used to instruct the slave node to send identification information. In this application, the length of the first command is mainly described as one byte, so the first byte and the first command mentioned later are essentially the same and do not need to be distinguished.

[0161] Specifically, the master node sends the first command to I 2 C bus, then I 2 Each slave node on the C bus can obtain the first command, because in the first i-1 rounds I 2 When C addresses are allocated, some slave nodes (i.e. Nk i slave nodes) are assigned to the corresponding I 2 C address, so in the i-th round of address allocation, although the first address is used to address N slave nodes, there will only be the above k i The slave nodes will respond to the first command, so the first address can also be understood as being used to address the k i There are only k slave nodes. i A slave node responds to the read instruction in the first command and sends identification information, that is, the master node obtains k through the command instruction. i Each slave node sends identification information.

[0162] Optionally, the master node may send the first command during the i-th reading process. 2 C command timing is performed, the I 2 C command timing and I 2 C communication protocol command timing matching, that is, the I 2 C command timing is achieved by multiplexing the existing I 2 C communication protocol command sequence.

[0163] For example, Figure 6 As shown, I in the i-th reading process 2 The C command sequence includes a repeated start bit, a first command (a first address and a read indication), a first confirmation character A, identification information, and a second confirmation character A. Figure 6 In the i-th reading process shown in the figure, the master node first sends a repeated start bit, which indicates the i-th round I 2 The master node sends the first command after sending the repeated start bit Sr. i After the slave node obtains the first address and the read instruction in the first command, it determines that the master node needs to obtain the identification information, k i The slave node will first reply with the first confirmation character A; then send the identification information, and then describe k i The process of a slave node sending a device identification is not described in detail here. After the master node obtains the identification information, it sends a second confirmation character A to indicate that the identification information of the slave node has been obtained.

[0164] Optionally, if the N slave nodes are all the slave nodes on the bus, the first address is a broadcast address, for example, the broadcast address is 7'h7F (ie, 7 1s). Figure 7 As shown in Figure 1, when the first address is a broadcast address, the master node sends a broadcast address to address all slave nodes during the i-th read process. i slave nodes respond to this addressing, so only k i A slave node responds to the read instruction in the i-th read process and sends identification information.

[0165] Optionally, if the N slave nodes are of the same type, the first address is the class address of the N slave nodes, and the class address is used to identify the type of the N slave nodes. It should be understood that each slave node is pre-configured with the class address of each slave node, and the master node is pre-configured with I 2 The master node determines the class address of the slave node on the I C bus. 2C address, and obtains the corresponding class address, and uses the class address as the first address. Then, the master node sends the first command, and the slave nodes on the bus will obtain the first address (i.e., class address) contained in the first command, and compare the first address with their pre-configured class addresses. Only the class address is the same as the class address sent by the master node, and it has not been assigned to I in the previous i-1 rounds. 2 The slave node with address C (i.e. the k i The first address can be understood as a slave node for addressing the k slave nodes. i slave nodes. Figure 8 As shown, when the first address is a class address, the master node sends the class address in the i-th reading process to address the N slave nodes corresponding to the class address. i slave nodes respond to this addressing, so only k i A slave node responds to the read instruction in the i-th read process and sends identification information.

[0166] Since the command timing for address allocation is not specified in the existing protocol, and the read indication or write indication in the existing command timing is indicated by a bit of 0 or 1, if the master node only sends the above-mentioned first command, the slave node cannot know the function of the read indication in the first command after receiving the first command. In other words, according to the existing command timing, after the slave node obtains the read indication in the first command, it is not clear that the function of the read indication is to let the slave node send identification information. Therefore, in an embodiment of the present application, before the slave node obtains the read indication in the first command, the master node will first indicate that the purpose of the above-mentioned read indication sent by the master node is to instruct the slave node to send identification information. In summary, before sending the first command, the master node will first indicate to the N slave nodes that the master node is going to perform address allocation.

[0167] Optionally, in each round I 2 Before allocating C addresses, the master node sends an address allocation command so that the slave node can receive each round of I 2 When a read instruction is sent by the master node in C address allocation, it is determined that the read instruction is used to instruct the slave node to send identification information.

[0168] Exemplarily, the master node sends an address allocation command through the first reading process, wherein the address allocation command includes a second address and a third address, and the second address and the third address cooperate with each other to indicate that the master node is going to perform address allocation.

[0169] Optionally, the i-th reading process and the first reading process are performed in the same 2 C command timing, and the I 2 C command timing and I2 C communication protocol. Furthermore, the multi-round address allocation process of the present application can be performed in the same I 2 C command timing, so it can be performed in the first round 2 Before the I C address is assigned, the master node sends 2 C command sequence, then the master node sends the address assignment command in the I 2 The read instructions sent in the C command sequence are used to instruct the slave node to send identification information, so the master node does not need to send the address allocation command again in each round of address allocation. 2 Before allocating C addresses, you can send an address allocation command once. In this application, the master node performs I 2 The following takes sending the address allocation command before C address allocation as an example.

[0170] It should be noted that, in the first reading process, the master node will receive and send other commands in addition to sending the second address and the third address. Fig. 9 As shown, during the first reading process, I 2 The C command sequence includes a start bit, a second address, a write indication, a third confirmation character, a third address, and a fourth confirmation character.

[0171] Combination Fig. 9 The commands shown specifically illustrate the first reading process so as to understand how the master node instructs the slave node to perform address allocation.

[0172] Specifically, the master node first sends a start bit S to activate all slave nodes on the bus; then, the master node sends a second address and a write indication, wherein the second address is used to address the N slave nodes; accordingly, each of the N slave nodes sends a third confirmation character after obtaining the write indication; then, the master node sends the third address. In this way, each slave node can obtain the second address and the third address, and pre-configure them in the slave node. When the master node is in the same slave node, 2 The second address and the third address are obtained in the C command sequence, and it is determined that the master node is going to allocate addresses. Accordingly, after obtaining the behavior that the master node is going to allocate addresses, the slave node will respond and send the fourth confirmation character.

[0173] It can be seen that through Fig. 9 In the first reading process shown, the master node can indicate its upcoming address allocation behavior to each of the N slave nodes, so that in each subsequent round of address allocation, after the slave node obtains the read instruction, it sends identification information to the master node.

[0174] Optionally, the second address and the third address can be the same address or different addresses, as long as two addresses that cooperate with each other to instruct the master node to allocate addresses are pre-configured in the master node and the slave node. This application is mainly explained by taking the second address and the third address as the same address as an example.

[0175] For example, Fig.10 As shown in FIG. 1 , when the N slave nodes are all the slave nodes on the bus, the second address and the third address may be broadcast addresses. Optionally, when the master node is about to perform address allocation, two broadcast addresses may be sent during the first read process to indicate that the master node is about to perform address allocation. In order to reuse the existing command sequence, the slave node address in the existing command sequence may be set to the broadcast address, that is, the existing I 2 The location of the data in the C command sequence is set as the broadcast address, so that the master node sends two broadcast addresses in the first read process. Accordingly, after the slave node obtains the two broadcast addresses in the first read process, it can be determined that the master node is about to perform address allocation.

[0176] For example, Fig.11 As shown in FIG. 1 , when the N slave nodes are of the same type among all the slave nodes on the bus, the second address and the third address may be class addresses. Optionally, when the master node is about to perform address allocation, two class addresses may be sent in the first read process command to indicate that the master node is about to perform address allocation. In order to reuse the existing command sequence, the slave node address in the existing command sequence may be set to the class address, that is, the existing I 2 The location of the data in the C command sequence is set as the class address, so that the master node sends two class addresses in the first read process. Accordingly, after the slave node obtains the two class addresses in the first read process, it can be determined that the master node is about to perform address allocation.

[0177] 302, k i Each slave node in the slave nodes is based on the identification information through I 2 The C bus sends a bit signal to the master node.

[0178] For example, the above k i After each slave node obtains the command instruction from the master node, it will 2 The C bus sends a bit signal in the identification information to the master node. i After each of the slave nodes obtains the read instruction in the first command, it sends the command to the slave node through I 2The C bus sends a bit signal of identification information to the master node. In the present application, when the slave node sends the bit signal of identification information, one bit of identification information is sent each time. Of course, in practical applications, the number of bit signals sent may not be limited, for example, two bits of identification information may be sent. In the present application, one bit of identification information sent by the slave node is mainly used as an example, and the bit signals mentioned subsequently may be understood as one bit.

[0179] 303, k i Each of the slave nodes arbitrates with other slave nodes based on the transmitted bit signal.

[0180] Optionally, the above k i Each slave node sends a bit signal of its own identification information based on the arbitration mechanism.

[0181] Specifically, when the jth arbitration cycle arrives, h j Each of the slave nodes sends the jth bit signal in the identification information, where h j The number of slave nodes is k i The slave nodes that obtain high priority after the first j-1 arbitration cycles among the slave nodes. When j=1, h1 slave nodes are the above k i slave nodes, wherein the j-th bit signal in the identification information sent by each slave node is 0 or 1; each slave node determines the priority of the slave node in the j-th arbitration cycle based on the j-th bit signal sent by the slave node in the j-th arbitration cycle and the data of the bus in the j-th arbitration cycle, wherein the priority of the slave node includes a high priority or a low priority.

[0182] The signal on the bus is composed of h j The j-th bit signal sent by the slave nodes in the j-th arbitration cycle is jointly determined. Specifically, the bus is a wired-AND structure, so h j When the j-th bit signal sent by each slave node in the j-th arbitration cycle contains 0, the data of the bus is 0; if and only if h j The data on the bus is 1 only when the j-th bit signal sent by each of the slave nodes is 1.

[0183] Specifically, if the j-th bit signal sent by a slave node in the j-th arbitration cycle is 0, the priority of the slave node is high priority; if the j-th bit signal sent by a slave node in the j-th arbitration cycle is 1, and the data of the bus in the j-th arbitration cycle is 1, the priority of the slave node is high priority; if the j-th bit signal sent by a slave node in the j-th arbitration cycle is 1, and the data of the bus in the j-th arbitration cycle is 0, the priority of the slave node is low priority. In other words, when the j-th bit signal sent by a slave node is the same as the data on the bus, the priority of the slave node is high priority; when the j-th bit signal sent by a slave node is different from the data on the bus, the priority of the slave node is low priority.

[0184] Furthermore, h j The slave node that obtains a high priority in the jth arbitration cycle among the slave nodes can send the j+1th bit signal of the identification information in the j+1th arbitration cycle; j A slave node that obtains a low priority in the j-th arbitration cycle no longer sends the j+1th bit signal and subsequent bits of the identification information from the j+1th arbitration cycle (including the j+1th arbitration cycle), that is, the slave node that obtains a high priority in the j-th arbitration cycle continues to participate in the arbitration process in the subsequent arbitration cycles, and the slave node that obtains a low priority in the j-th arbitration cycle no longer participates in the arbitration process in the subsequent arbitration cycles.

[0185] Further, according to the above arbitration mechanism, if the first slave node is a high-priority slave node in each arbitration cycle, then after M arbitration cycles, the first slave node is the first to send out all the identification information, that is, the first slave node is k i The slave node that first sends the identification information to the master node in the i-th round of address allocation among the slave nodes is selected, so that the master node first obtains the complete identification information of the first slave node after M arbitration cycles, where M is a preset value, and M can be the length of the identification information of the slave node, that is, the length of the bit string of the identification information of the slave node. It should be noted that if the lengths of the identification information of the N slave nodes are different, then M can be the maximum value of the length of the identification information of the slave node.

[0186] It should be noted that if the lengths of the identification information of N slave nodes are different, in a certain arbitration cycle, if the slave node that obtains high priority has no identification information to send, then in the subsequent arbitration cycle, if the slave node obtains high priority, it will continue to send bits by completion. For example, the slave node can send bit 1 in the subsequent arbitration cycle.

[0187] For example, if the value of M is set to 6, if the device identification of a slave node is 000, the slave node is a high-priority slave node in the third arbitration cycle, and the slave node will participate in the fourth arbitration cycle, but the slave node has no bits to send in the fourth arbitration cycle. The slave node will complete it by sending bit 1 in the fourth arbitration cycle.

[0188] In practical applications, in order to avoid a large difference in the length of identification information, the device identification with a smaller identification information length needs to be actively supplemented with more bits during the arbitration process. Therefore, before address allocation, slave nodes with lengths in the same preset range can be connected to the same I 2 C bus, that is, the lengths of the identification information of the N slave nodes are within the same preset interval. 2 C bus, which allocates I 2 C address, are all the same as the dynamic allocation of I 2 The C addresses are the same and will not be described one by one.

[0189] Furthermore, due to I 2 Under the C communication mechanism, the data transmission between the master node and the slave node is carried out in units of one byte. Fig.12 As shown in FIG. 1 , when the slave node sends identification information based on the arbitration mechanism, the master node will reply with a confirmation character A each time it obtains a byte of bit signal, instead of replying with a confirmation character only after obtaining the complete identification information of the first slave node. Fig.12 As shown, if the identification information of the first slave node is a 16-byte bit string, after the first slave node sends a byte, the master node will reply with a confirmation character A. In this way, after sending the sixteenth byte of the bit signal, that is, during the entire process of the first slave node sending the identification information, the master node replies with 16 confirmation characters.

[0190] The following describes the arbitration mechanism of slave nodes in detail by taking three slave nodes in the i-th round of address allocation as an example.

[0191] like Fig.13As shown, the device identification of slave node 1 is 0101xxx; the device identification of slave node 2 is 1011xxx; and the device identification of slave node 3 is 1101xxx. Therefore, in the i-th round of address allocation, in the first arbitration, slave node 1 sends a low level (i.e., sends 0), and slave nodes 2 and 3 send a high level (i.e., sends 1). Therefore, if the bus level is low, the level sent by slave node 1 is the same as the bus level, then slave node 1 is a high-priority slave node and will continue to participate in the data transmission of the next arbitration cycle. If the levels sent by slave nodes 2 and 3 are different from the bus level, they will exit arbitration and will not participate in subsequent arbitration cycles. In the second arbitration cycle, slave node 1 continues to send bits. At this time, only slave node 1 sends bits, so the bus level is the same as the level of slave node 1, and slave node 1 continues to be a high-priority slave node. In turn, after M arbitration cycles, slave node 1 will send all device identifications to the data bus, and the master node will obtain the complete device identification 0101xxx accordingly, so that in the i-th round of address allocation, the master node can allocate addresses to slave node 1. After allocating the address, slave node 1 will exit the address allocation. When it comes to the i+1th round of address allocation, in the first arbitration, slave nodes 2 and 3 both send 1, so that the bus level is high, and the levels sent by slave nodes 2 and 3 are the same as the bus level, then slave nodes 2 and 3 are both high-priority slave nodes, and will continue to participate in the next arbitration. In the second arbitration, slave node 2 will send 0 and slave node 3 will send 1. Slave node 2 is a high-priority slave node, and slave node 2 will continue to participate in the next arbitration, and slave node 3 will withdraw from the arbitration. Therefore, in the i+1th round of address allocation, slave node 2 will send all device identifiers to the master node. The master node will allocate an address to slave node 2. Then, it will allocate an address to slave node 3 in the i+2th round.

[0192] 304: The master node allocates the first I to the first slave node 2 C address, the first slave node is k i The slave node that first sends the identification information to the master node when the slave nodes arbitrate based on the sent bit signal.

[0193] Exemplarily, after M arbitration cycles, the master node first obtains the identification information of the first slave node, and then allocates the first I 2 C address.

[0194] Optionally, the master node may allocate addresses to the N slave nodes based on a preset allocation strategy, wherein the preset allocation strategy includes but is not limited to: increasing, decreasing, jumping, segmented or unified addressing.

[0195] Exemplarily, when the master node allocates addresses in an incremental manner, in the first round of address allocation, an I 2 C address, the I 2 The C address may be a starting address among all addresses that can be allocated from the slave node, or any address among all addresses, and so on; then, in the second round of address allocation, an I C address is allocated to the slave node corresponding to the identification information obtained in the second round of address allocation. 2 C address, which can be the I 2 C address is incremented, for example, by +1 until it is obtained; and so on, in the i-th round of address allocation, the first I can be allocated to the first slave node 2 In this way, after multiple rounds of address allocation, each slave node can be assigned an I 2 C address, and different slave nodes obtain I 2 It should be noted that when the master node adopts other preset allocation strategies (non-incremental allocation strategies) for I 2 When assigning C addresses, configure I 2 The process of C address is similar to the incremental allocation method and will not be described in detail.

[0196] Exemplarily, the master node sends a second command, wherein the second command includes the first I 2 C address and write indication, the write indication is used to indicate the first I 2 The C address is the I address that the master node assigns to the slave node in the i-th round of address allocation. 2 C address. Similarly, the length of the second command in this application is one byte, so the second command mentioned later can be understood as the second byte, and the two are essentially the same and no longer distinguished.

[0197] It can be understood that the master node sends the second command to the bus. At this time, only the first slave node responds to the bus. Then the master node sends the first I 2 C address is sent to the bus to 2 C address is assigned to the first slave node. Specifically, the master node assigns the first I 2 The C address is sent to the bus as the transmission data between the master node and the first slave node. Since the master node has indicated the address allocation before the first slave node sends the identification information, the first slave node obtains the first I 2 C address, we know that this part of data is the I allocated by the master node 2 C address. Further, the existing I 2 Data transmission under C communication is transmitted in one byte (eight bits), while I2 The C address is usually seven bits, in order to comply with the existing I 2 C communication process, which can be the first 2 C address is added with one bit to form one byte. In addition, since the first slave node is assigned the first I 2 The C address is essentially the first I 2 C address, can be regarded as a data writing process. 2 C address to add a first write instruction to obtain the second command. In this way, the master node can send the second command to the first I 2 The C address is assigned to the first slave node.

[0198] Optionally, the master node may send the first I during the i-th write process. 2 C address. Exemplarily, since the slave node sends identification information and allocates I 2 The C address can be regarded as a whole data transmission process. Therefore, the master node can continue to send the first I based on the i-th read process. 2 C address, or you can restart a write process by sending the first I 2 C address. Accordingly, the i-th read process and the i-th write process can be the same data transmission process or different data transmission processes. Similarly, the i-th read process, the i-th write process and the first read process are in the same I 2 C command sequence, I 2 C command timing and I 2 C communication protocol command timing matching.

[0199] Optionally, when the i-th reading process and the i-th writing process are the same data transmission process, the master node obtains the complete identification information of the first slave node, and after replying the second confirmation character, does not restart a writing process to send the first i-th slave node. 2 C address, that is, the master node will not restart a write process by repeating the start bit Sr, but will continue to send the first I in the i-th read process. 2 C address, that is, the i-th read process and the i-th write process are regarded as a data transmission process. In this case, the i-th read process and the i-th write process can be collectively referred to as the i-th data transmission process, that is, the master node obtains the identification information of the first slave node in the i-th data transmission process, and allocates the first I to the first slave node in the i-th data transmission process. 2 C address.

[0200] Specifically, compared to Figure 6 The sub-I shown 2 C command timing, such as Fig.14As shown, the i-th data transmission process includes not only the commands in the i-th read process, but also the commands in the i-th write process, that is, the first i 2 C address, write indication and third confirmation character. Fig.14 From the perspective of the master node, after obtaining the identification information of the first slave node during the i-th data transmission process and replying with a confirmation character, the master node can continue to send data, that is, in the i-th data transmission process, the first slave node 2 C address is sent as data, which only needs to be pre-configured at both the master node and the slave node. After the master node obtains the identification information and replies with the confirmation character, the data sent is the I assigned to the slave node. 2 C address, so that the master node can obtain the identification information of the first slave node during the i-th data transmission process and assign an address to the first slave node. 2 After receiving the C address, the third confirmation character will be sent to notify the master node that the data reception is complete, that is, to indicate that the master node has obtained the first I 2 C address, and the first slave node obtains the first I 2 After receiving the third confirmation character, the master node will no longer participate in the subsequent rounds of address allocation. Accordingly, after obtaining the third confirmation character, the master node can determine that the address allocation of the i-th round is completed, and then start the address allocation process of the i+1-th round.

[0201] Optionally, when the i-th reading process and the i-th writing process are different data transmission processes, since the first slave node is assigned I 2 The C address can essentially be regarded as a data writing process. In practical applications, after the master node obtains the identification information, it can follow the existing I 2 C command sequence restarts a write process, that is, the i-th write process, and sends the first I in the i-th write process. 2 C address.

[0202] like Fig.15 As shown, the command of the i-th write process includes a repeated start bit Sr, a broadcast address, a fourth confirmation character, a first I 2 C address and the fifth confirmation character. Fig.15 , in the distribution of the first I 2 C address, the master node first sends a repeated start bit Sr to start the i-th write process; then, the master node sends a broadcast address, and after obtaining the broadcast address, the first slave node can respond to the addressing in the i-th write process and reply with the fourth confirmation character; then, after obtaining the fourth confirmation character, the master node sends the first I 2 C address, that is, the master node allocates the first I 2C address. Accordingly, the first slave node obtains the first I 2 After the C address is received, the fifth confirmation character will be sent to notify the master node to obtain the first I 2 C address so that the master node ends the i-th round of address allocation and starts the i+1-th round of address allocation.

[0203] It should be noted that the above-mentioned address allocation command, the first command and the second command in each round of address allocation are in the same I 2 C command sequence, that is, the first reading process and each round of address allocation process are all sent in the same I 2 Specifically, the master node first starts the first read process with a start bit S, and then starts each round of address allocation process with a repeated start bit Sr, thereby completing each round of address allocation.

[0204] In one embodiment of the present application, if the master node is pre-configured with the number of N slave nodes, after the master node senses that N rounds of address allocation have been performed, it can be determined that address allocation has been completed for each of the N slave nodes. 2 After the C address, the master node can send an end signal P to indicate that the N slave nodes have completed I 2 For example, during the Nth round of address allocation, the slave node sends a message to the master node for I 2 After the confirmation character of address C is written, the master node can send an end signal P to indicate that N slave nodes have completed I 2 C address allocation.

[0205] In another embodiment of the present application, in actual applications, the master node may not be clear about the number of slave nodes. For example, the number of slave nodes is not pre-configured, or even if the number of slave nodes is configured, the number of slave nodes currently participating in the address allocation may not be known due to some special circumstances. For example, some slave nodes are faulty or the slave nodes are not powered on, so they do not participate in the arbitration and address allocation process. The actual number of slave nodes that need to be allocated addresses will be less than the pre-configured number. At this time, the master node cannot allocate addresses according to the configured number of slave nodes, but after allocating the actual number of addresses, it autonomously senses whether the allocation is completed, thereby deciding whether to end the command sequence.

[0206] Specifically, after completing the i-th round of address allocation, the master node will not pay attention to whether the address allocation process is completed, but will continue to perform the i+1th round of address allocation. Exemplarily, after completing the i-th round of address allocation, the master node sends a third command, wherein the third command includes the first address and a read indication, so as to indicate that the address not allocated to the i+1th round is read by the third command. 2C address of the slave node sends identification information; after the master node sends the third command, if the identification information of the slave node is not obtained, but a negative confirmation is obtained. For example, if the master node obtains a high level on the bus after sending the third command, that is, the data on the bus is always 0, then it can be determined that a negative confirmation is obtained, so the master node can determine that there is no slave node that needs to be assigned an address in the i+1th round of address allocation, that is, after completing the i-th round of address allocation, all slave nodes are assigned addresses, and the master node can send an end signal P at this time. If the master node obtains the identification information of the slave node after sending the third command, the address can be assigned to the slave node with the identification information. Then, continue with the next round of address allocation until the identification information of the slave node is not obtained in a certain round of address allocation, send an end signal P, and end i+1. 2 C command timing.

[0207] In general, after completing the current round of address allocation, the master node does not pay attention to whether an address is allocated to each slave node, but continues with the next round of address allocation. If the identification information of the slave node is not obtained in the next round of address allocation, it means that addresses have been allocated to all slave nodes in the current round, and the address allocation process can be ended.

[0208] Furthermore, in each round of address allocation, the master node only allocates an I address to the slave node whose identification information is obtained. 2 C address, but the master node does not know which slave node among the N slave nodes this slave node is, that is, the master node does not know where the slave node corresponding to this identification information is mounted on the bus. 2 C address, you can use the identification information with the I 2 C address is associated and stored. In this way, when the master node needs to communicate with a slave node, it can obtain the I of the slave node based on the device identification of the slave node. 2 C address, and based on the I 2 C address to communicate with the slave node.

[0209] Table 1 shows the identification information and the I of the slave nodes when the above N slave nodes are all the slave nodes on the bus. 2 C address correspondence.

[0210] Table 1:

[0211] Identification information 1 <![CDATA[I 2 C Address 1]]> Identification information 2 <![CDATA[I 2 C Address 2]]> …… …… Identification information <![CDATA[I 2 C Address N]]>

[0212] Table 2 shows the identification information of the above N slave nodes, which are the same type of slave nodes among all the slave nodes on the bus, and the I 2 C address correspondence.

[0213] Table 2:

[0214] Identification information 1_1 <![CDATA[I 2 C Address 1_1]]> Identification information 1_2 <![CDATA[I 2 C Address 1_2]]> …… …… Identification information 1_a1 <![CDATA[I 2 C address 1_a1]]> Identification information 2_1 <![CDATA[I 2 C Address 2_1]]> Identification information 2_2 <![CDATA[I 2 C Address 2_2]]> …… …… Identification information 2_a2 <![CDATA[I 2 C address 2_a2]]> …… …… Identification information N_1 <![CDATA[I 2 C Address N_1]]> Identification information N_2 <![CDATA[I 2 C Address N_2]]> …… …… Identification information N_aN <![CDATA[I 2 C address N_aN]]>

[0215] In general, when the above N slave nodes are all the slave nodes on the bus, they can be Fig.16 or Fig.17 The complete command sequence between the master node and N slave nodes is shown as 2 C address allocation process.

[0216] Combine the following Fig.16 or Fig.17 Describe the entire process of address allocation.

[0217] like Fig.16 or Fig.17 As shown, first the master node sends a start bit S to start the first read process, and then sends a broadcast address and a write indication during the first read process; then sends a broadcast address, and indicates that the master node will perform address allocation by sending the broadcast address twice during the first read process; after obtaining the broadcast address twice, the slave node replies with a confirmation character A, so that the master node completes the process of indicating address allocation. Then, the master node sends a repeated start bit Sr to start the first round of address allocation process, and then sends a byte during the first round of address allocation process. The byte contains a broadcast address and a read indication. Since the master node has been indicated to perform address allocation during the first read process, at this time, after each slave node obtains the read indication, it will send a bit of identification information in sequence in each arbitration cycle; when the slave node is a high-priority slave node, it will continue to send the next bit of identification information in the next arbitration cycle until after M arbitration cycles, a slave node will send the complete identification information to the data bus. Accordingly, the master node can obtain the identification information of this slave node through the bus, such as Fig.16 or Fig.17 As shown in the figure, the master node obtains the identification information of slave node 1 in the first round of address allocation, and replies with a confirmation character A, indicating that the master node has obtained a complete identification information. Then the master node assigns an I 2 C address, that is, sending a byte, which contains the I 2 C address and write instruction, through this byte to I 2 The C address is assigned to slave node 1. When slave node 1 obtains the byte, it sends a confirmation character A, which indicates that the master node has obtained I 2 C address, so that the master node can determine that the first round of address allocation is completed and start the next round of address allocation. Accordingly, after the master node obtains the confirmation character A, it will start the next round of address allocation. In the next round of address allocation, the above N slave node addresses are still addressed, but I2 The slave nodes with I C addresses will no longer participate in the next round of address allocation, and will not send identification information. 2 The slave node with the C address participates in the next round of address allocation. After N rounds of address allocation, each slave node can be assigned an I 2 C address.

[0218] Optionally, if the master node is pre-configured with the number of slave nodes, after the address allocation of N slave nodes is completed, Fig.16 As shown, the master node can directly send a stop signal P to release the bus and complete the entire process of address allocation.

[0219] Optionally, if the number of slave nodes is not configured in the master node, that is, the master node does not actively sense whether the address allocation is completed, such as Fig.17 As shown in the figure, after the master node allocates addresses in each round, it will continue to perform the address allocation process. When the address allocation is completed in the Nth round, the master node instructs the slave node to send identification information, and obtains a negative confirmation NACK. The master node then determines that all addresses have been allocated to the N slave nodes, and no slave node needs to participate in the address allocation process. Then the master node will send a stop signal P to release the bus and complete the entire process of address allocation.

[0220] In general, when the N slave nodes are of the same type, Fig.18 or Fig.19 The complete command sequence between the master node and N slave nodes is shown as 2 C address allocation process.

[0221] Combine the following Fig.18 or Fig.19 Describe the entire process of address allocation.

[0222] like Fig.17 or Fig.18As shown, first the master node sends a start bit S to start the first read process, and then sends a class address and a write indication during the first read process; then sends a class address, and indicates that the master node will perform address allocation by sending the class address twice during the first read process; after obtaining the class address twice, the slave node replies with a confirmation character A, so that the master node completes the process of indicating address allocation. Then, the master node sends a repeated start bit Sr to start the first round of address allocation process, and then sends a byte during the first round of address allocation. The byte contains the class address and the read indication. Since the master node has been indicated to perform address allocation during the first read process, at this time, after each slave node obtains the read indication, it will send a bit of identification information in sequence in each arbitration cycle; when the slave node is a high-priority slave node, it will continue to send the next bit of identification information in the next arbitration cycle until after M arbitration cycles, a slave node will send the identification information completely to the data bus. Accordingly, the master node can obtain the identification information of this slave node through the bus, such as Fig.17 or Fig.18 As shown in Figure 1, the master node obtains the identification information of slave node 1 in the first round of address allocation and replies with a confirmation character A, indicating that the master node has obtained a complete identification information. Then the master node assigns an I 2 C address, that is, sending a byte, which contains the I 2 C address and write instruction, through this byte to I 2 The C address is assigned to slave node 1. When slave node 1 obtains the byte, it sends a confirmation character A, which indicates that the master node has obtained I 2 C address, so that the master node can determine that the first round of address allocation is completed and start the next round of address allocation. Correspondingly, after the master node obtains the confirmation character A, it can start the next round of address allocation. In the next round of address allocation, the above N slave node addresses are still addressed, but I 2 The slave nodes with I C addresses will no longer participate in the next round of address allocation, and will not send identification information. 2 The slave node with the C address participates in the next round of address allocation. In this way, after N rounds of addresses, each slave node can be assigned an I2C address.

[0223] Optionally, if the master node is pre-configured with the number of slave nodes, after the address allocation of N slave nodes is completed, Fig.18 As shown, the master node can directly send a stop signal P to release the bus and complete the entire process of address allocation.

[0224] Optionally, if the number of slave nodes is not configured in the master node, that is, the master node does not actively sense whether the address allocation is completed, such as Fig.19 As shown in the figure, after the master node allocates addresses in each round, it will continue to perform the address allocation process. When the address allocation is completed in the Nth round, the master node instructs the slave node to send identification information, and obtains a negative confirmation. Only then does the master node determine that all the N slave nodes have been allocated addresses, and no slave node needs to participate in the address allocation process. Then the master node will send a stop signal P to release the bus and complete the entire process of address allocation.

[0225] See also Fig. 20 , Fig. 20 A schematic diagram of a slave node provided in an embodiment of the present application. The slave node 2000 includes a transceiver unit 2001 and a processing unit 2002.

[0226] The transceiver unit 2001 is used to perform the i-th round I 2 When assigning C addresses, based on the identification information of the first slave node, the I 2 The C bus sends a bit signal to the master node;

[0227] The processing unit 2002 is configured to determine the slave node as the target slave node if the slave node first sends the identification information to the master node after the bit signal sent by the slave node and the bit signals sent by other slave nodes are arbitrated;

[0228] The transceiver unit 2001 is also used to obtain the first I 2 C address.

[0229] For a more detailed description of the transceiver unit 2001 and the processing unit 2002, reference may be made to the related description of the slave node in the above method embodiment, which will not be described again here.

[0230] See also Fig.21 , Fig.21 A schematic diagram of a master node provided in an embodiment of the present application. The master node 2100 includes a transceiver unit 2101 and a processing unit 2102 .

[0231] Processing unit 2102, for performing the i-th round I 2 When C address is allocated, get k i The identification information of the slave nodes, where k i The slave nodes perform the first i-1 rounds of I 2 After the C address is allocated, N slave nodes are not allocated I 2 The slave node of C address;

[0232] The transceiver unit 2101 is used to obtain k i The slave nodes are based on the identification information through I 2 The bit signal sent by the C bus; sending the first I 2C address; among them, the first slave node is k i The slave node that first sends the identification information to the master node when the slave nodes arbitrate based on the sent bit signal.

[0233] For a more detailed description of the above-mentioned transceiver unit 2101 and the processing unit 2102, please refer to the relevant description of the master node in the above-mentioned method embodiment, which will not be described again here.

[0234] See also Fig. 22 , Fig. 22 A schematic diagram of an electronic device provided in an embodiment of the present application. The electronic device 2200 may be the slave node 2000 described above, or a chip or chip system in the slave node 2000; or, the electronic device 2200 may be the master node 2100 or a chip or chip system in the master node 2100.

[0235] The electronic device 2200 includes a memory 2201 , a processor 2202 , a communication interface 2203 and a bus 2204 . The memory 2201 , the processor 2202 , and the communication interface 2203 are connected to each other through the bus 2204 .

[0236] The memory 2201 may be a read-only memory (ROM), a static storage device, a dynamic storage device or a random access memory (RAM). The memory 2201 may store programs; when the program stored in the memory 2201 is executed by the processor 2202, the processor 2202 and the communication interface 2203 are used to execute the embodiment I of the present application. 2 The individual steps in the C allocation method.

[0237] Processor 2202 can adopt a general central processing unit (CPU), a microprocessor, an application specific integrated circuit (ASIC), a graphics processing unit (GPU) or one or more integrated circuits to execute relevant programs to implement the multi-data remote reading method or the data remote writing method of the method embodiment of the present application.

[0238] The processor 2202 may also be an integrated circuit chip with signal processing capabilities. In the implementation process, each step in the data remote reading method or data remote writing method of the present application may be completed by the hardware integrated logic circuit or software instructions in the processor 2202. The above-mentioned processor 2202 may also be a general-purpose processor, a digital signal processor (Digital Signal Processing, DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (Field Programmable Gate Array, FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The methods, steps and logic block diagrams disclosed in the embodiments of the present application may be implemented or executed. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. The steps of the method disclosed in the embodiments of the present application may be directly embodied as being executed by a hardware decoding processor, or executed by a combination of hardware and software modules in a decoding processor. The software module may be located in a mature storage medium in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory 2201, and the processor 2202 reads the information in the memory 2201 to execute each step of the multi-data remote reading method or the data remote writing method.

[0239] The communication interface 2203 may be a transceiver or other transceiver to realize the communication between the electronic device 2200 and other devices or communication networks; the communication interface 2203 may also be an input-output interface to realize the data transmission between the electronic device 2200 and the input-output device, wherein the input-output device includes but is not limited to a keyboard, a mouse, a display screen, a USB flash drive, and a hard disk. The bus 2204 may include a path for transmitting information between the various components of the electronic device 2200 (e.g., the memory 2201, the processor 2202, and the communication interface 2203).

[0240] It should be noted that although Fig. 22 The electronic device 2200 shown only shows a memory, a processor, and a communication interface, but in the specific implementation process, those skilled in the art should understand that the electronic device 2200 also includes other devices necessary for normal operation. At the same time, according to specific needs, those skilled in the art should understand that the electronic device 2200 may also include hardware devices for implementing other additional functions. In addition, those skilled in the art should understand that the electronic device 2200 may also only include the devices necessary to implement the embodiments of the present application, and does not necessarily include Fig. 22 All devices shown in .

[0241] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0242] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0243] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0244] In this application, "at least one" means one or more, and "more than one" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. In the text description of this application, the character " / " generally indicates that the previous and next associated objects are in an "or" relationship; in the formula of this application, the character " / " indicates that the previous and next associated objects are in a "division" relationship.

[0245] It is understood that the various numbers involved in the embodiments of the present application are only for the convenience of description and are not used to limit the scope of the embodiments of the present application. The size of the sequence number of the above-mentioned processes does not mean the order of execution, and the execution order of each process should be determined by its function and internal logic.

[0246] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application can be essentially or partly embodied in the form of a software product that contributes to the prior art. The computer software product is stored in a storage medium and includes several instructions for a computing device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0247] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A kind of I 2 C address allocation method, applied to slave nodes, It is characterized in that The method comprises: In the i-th round I 2 When allocating a C address, the first slave node allocates the I 2 The C bus sends a bit signal to the master node; including: Step S1: In the jth arbitration, the first slave node sends the jth bit signal in the identification information to the master node through the I2C bus; the first slave node is one of the slave nodes that obtain a high priority in the j-1th arbitration; Step S2: if the j-th bit signal is the same as the data on the I2C bus during the j-th arbitration, the first slave node determines that the priority of the first slave node during the j-th arbitration is a high priority; if the j-th bit signal is different from the data on the I2C bus during the j-th arbitration, the first slave node determines that the priority of the first slave node during the j-th arbitration is a low priority; the data on the I2C bus is obtained by the bit signal sent by the slave node that obtains the high priority during the j-1-th arbitration during the j-th arbitration and the operation; Assign j=j+1, and repeat the above steps S1 to S2. After multiple arbitrations, if the priority of the first slave node in each arbitration is high, the first slave node first sends the identification information to the master node; If, after arbitration between the bit signal sent by the first slave node and the bit signals sent by other slave nodes, the first slave node first sends identification information to the master node, the first slave node is determined as the target slave node; The first slave node obtains the first I from the master node 2 C address.

2. The method according to claim 1, It is characterized in that The method further comprises: If the priority of the first slave node in any arbitration of the multiple arbitrations is a low priority, the first slave node withdraws from the next arbitration.

3. The method according to claim 1 or 2, It is characterized in that The first slave node, based on the identification information of the first slave node, 2 Before the C bus sends a bit signal to the master node, the method further includes: The first slave node obtains a first command from the master node, the first command including a first address and a read indication, the first address being used to address the first slave node; the read indication being used to instruct the first slave node to send identification information so that the first slave node reads the first command based on the identification information of the first slave node through the I 2 The C bus sends a bit signal to the master node.

4. The method according to claim 3, It is characterized in that The first slave node obtains a first I2C address from the master node, including: The first slave node obtains a second command from the master node, wherein the second command includes the first I2C address and a write indication; in response to the write indication, the first slave node uses the first I2C address as the I2C address allocated by the master node to the first slave node.

5. The method according to claim 4, It is characterized in that In the first round of I 2 Before the C address is allocated, the method further includes: The first slave node obtains an address allocation command from the master node, wherein the address allocation command is used to indicate that the master node is to perform I 2 C address allocation, so that when the first slave node obtains the read instruction in the first command, based on the identification information of the first slave node, through I 2 The C bus sends a bit signal to the master node.

6. The method according to claim 5, It is characterized in that The first command is sent by the master node during the i-th reading process; the second command is sent by the master node during the i-th writing process; the i-th reading process is the same data transmission process or different data transmission processes; The address allocation command is sent by the master node during the first reading process; The i-th reading process, the i-th writing process and the first reading process are performed in the same I 2 C command timing, the I 2 C command timing and I 2 C communication protocol command timing matching.

7. A kind of I 2 C address allocation method, It is characterized in that The method is applied to a master node, and the method comprises: In the i-th round I 2 When C address is allocated, get k i The identification information of k slave nodes, wherein the i The slave nodes perform the first i-1 rounds of I 2 After the C address is allocated, N slave nodes are not allocated I 2 The slave node of C address; Get the k i The slave nodes are based on the identification information through I 2 The bit signal sent by the C bus; Send the first I to the first slave node 2 C address; wherein the first slave node is the k i The first slave node sends identification information to the slave node of the master node first when performing arbitration based on the sent bit signal, wherein the first slave node first sends identification information to the slave node of the master node comprises the following steps: Step S1: In the jth arbitration, the first slave node sends the jth bit signal in the identification information to the master node through the I2C bus; the first slave node is one of the slave nodes that obtain a high priority in the j-1th arbitration; Step S2: if the j-th bit signal is the same as the data on the I2C bus during the j-th arbitration, the first slave node determines that the priority of the first slave node during the j-th arbitration is a high priority; if the j-th bit signal is different from the data on the I2C bus during the j-th arbitration, the first slave node determines that the priority of the first slave node during the j-th arbitration is a low priority; the data on the I2C bus is obtained by the bit signal sent by the slave node that obtains the high priority during the j-1-th arbitration during the j-th arbitration and the operation; Assign j=j+1, and repeat the above steps S1 to S2. After multiple arbitrations, if the priority of the first slave node in each arbitration is high, the first slave node first sends the identification information to the master node.

8. The method according to claim 7, It is characterized in that The acquisition k i The identification information of each slave node includes: Send a first command, wherein the first command includes a first address and a read instruction, the first address is used to address the k i The read indication is used to indicate the k slave nodes. i The k slave nodes send identification information so that the i The slave nodes are based on the identification information through I 2 C bus sends bit signals.

9. The method according to claim 8, It is characterized in that The method further comprises: Send an address allocation command, the address allocation command is used to indicate that the master node is going to I 2 C address is assigned to indicate the k i When a slave node obtains the read instruction in the first command, based on the identification information, it sends the I 2 C bus sends bit signals.

10. The method according to claim 9, It is characterized in that The sending a first I2C address to the first slave node comprises: A second command is sent, wherein the second command includes the first I2C address and a write indication, and the write indication is used to assign the first I2C address to the first slave node.

11. The method according to claim 10, It is characterized in that The first command is sent by the master node during the i-th reading process; The second command is sent by the master node during the i-th write process; The address allocation command is sent by the master node during the first reading process; The i-th reading process, the i-th writing process and the first reading process are performed in the same 2 C command sequence; I 2 C command timing and I 2 C communication protocol command timing matching.

12. The method according to any one of claims 7 to 11, It is characterized in that The method further comprises: If the master node does not obtain k i -1 slave node identification information, and when a negative confirmation is obtained, an end signal is sent, wherein the end signal is used to indicate that the master node has completed I for the N slave nodes. 2 C address allocation, where the k i -1 slave node for the k i A slave node among the slave nodes except the first slave node.

13. A kind of I 2 C address allocation method, It is characterized in that The method is applied to a computing device, wherein the computing device includes a master node and N slave nodes, wherein the master node and the N slave nodes are connected via I 2 C bus connection; the method comprises: In the i-th round I 2 When C address is allocated, the master node obtains k i The identification information of k slave nodes; wherein the i The slave nodes perform the first i-1 rounds of I 2 After the C addresses are allocated, the N slave nodes that are not allocated I 2 The slave node of C address; The k i Each of the slave nodes is based on the identification information through the I 2 The C bus sends a bit signal of identification information to the master node; including: In the jth arbitration, the first slave node sends the jth bit signal of the identification information to the master node, wherein the first slave node is any one of the ki slave nodes that obtains a high priority in the j-1th arbitration; The k i Each slave node in the slave nodes arbitrates with other slave nodes based on the transmitted bit signal; including: If the j-th bit signal is the same as the data on the I2C bus during the j-th arbitration, the first slave node determines that the priority of the first slave node during the j-th arbitration is a high priority; if the j-th bit signal is different from the data on the I2C bus during the j-th arbitration, the first slave node determines that the priority of the first slave node during the j-th arbitration is a low priority; after multiple arbitrations, if the priority of the first slave node during each arbitration is a high priority, the first slave node first sends the identification information to the master node; The master node allocates a first I 2 C address, the first slave node is the k i The slave node that first sends the identification information to the master node when the slave nodes perform arbitration based on the sent bit signal.

14. The method according to claim 13, It is characterized in that The method further comprises: If the priority of the first slave node in any arbitration among the multiple arbitrations is a low priority, the first slave node withdraws from the next arbitration.

15. A computing device, It is characterized in that The computing device comprises the first slave node as claimed in any one of claims 1 to 6; or the computing device comprises the master node as claimed in any one of claims 7 to 12; or the computing device comprises the computing device as claimed in any one of claims 13 to 14.

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