Semiconductor device and method of forming the same

Abstract

A semiconductor device and a method of forming the same are provided. The method includes forming a bottom electrode layer over a substrate. A magnetic tunnel junction (MTJ) layer is formed over the bottom electrode layer. A top electrode layer is formed over the MTJ layer. The top electrode layer is patterned. After the top electrode layer is patterned, one or more process cycles are performed on the MTJ layer and the bottom electrode layer. The patterned top electrode layer, the patterned MTJ layer, and the patterned bottom electrode layer form an MTJ structure. Each of the one or more process cycles includes performing an etch process on the MTJ layer and the bottom electrode layer for a first duration, and performing a magnetic treatment on the MTJ layer and the bottom electrode layer for a second duration.

Description

[0001] This application is a divisional application of patent application No. 201911205480.4, filed on November 29, 2019, entitled "Semiconductor Device and Method of Forming the Same". Technical Field

[0002] The embodiments of this application relate to the field of semiconductors, and more specifically, to semiconductor devices and methods of forming the same. Background Technology

[0003] As an example, semiconductor memories are used in integrated circuits for electronic applications, including radios, televisions, mobile phones, and personal computing devices. One type of semiconductor memory device is magnetoresistive random access memory (MRAM), which involves spintronics that combines semiconductor technology with magnetic materials and devices. Electrons spin through their magnetic moment rather than their electric charge; the electron's spin is used to indicate its potential value.

[0004] A typical MRAM cell may include a magnetic tunnel junction (MTJ) stack comprising a pinned layer, a pinned layer above the pinned layer, a tunnel layer above the pinned layer, and a free layer above the tunnel layer. During the formation of the MRAM cell, multiple capping layers are first deposited. The capping layers are then patterned using photolithography to form the MTJ stack. A cap dielectric layer is then formed to include portions on the sidewalls of the MTJ stack and other portions that may be located above the top surface. The cap dielectric layer protects the MTJ stack. Summary of the Invention

[0005] According to embodiments of this application, a method for forming a semiconductor device is provided, comprising: forming a bottom electrode layer over a substrate; forming a magnetic tunnel junction layer over the bottom electrode layer; forming a top electrode layer over the magnetic tunnel junction layer; patterning the top electrode layer; and after patterning the top electrode layer, performing one or more process cycles on the magnetic tunnel junction layer and the bottom electrode layer, wherein the patterned top electrode layer, the patterned magnetic tunnel junction layer, and the patterned bottom electrode layer form a magnetic tunnel junction structure, and wherein each of the one or more process cycles comprises: performing an etching process on the magnetic tunnel junction layer and the bottom electrode layer for a first duration; and performing a magnetic processing on the magnetic tunnel junction layer and the bottom electrode layer for a second duration.

[0006] According to an embodiment of this application, a method for forming a semiconductor device is provided, comprising: introducing a wafer into a process chamber, the wafer including: a bottom electrode layer located above a substrate; a magnetic tunnel junction layer located above the bottom electrode layer; and a patterned top electrode layer located above the magnetic tunnel junction layer; and performing one or more process cycles on the wafer while the wafer is in the process chamber, wherein each of the one or more process cycles includes: performing an ion beam etching process on the magnetic tunnel junction layer and the bottom electrode layer for a first duration using an ion beam etching system of the process chamber; and performing a magnetic treatment on the magnetic tunnel junction layer and the bottom electrode layer for a second duration using a magnetic system of the process chamber.

[0007] According to an embodiment of this application, a semiconductor device is provided, comprising: a substrate; a magnetic tunnel junction structure located above the substrate, wherein the magnetic tunnel junction structure includes: a bottom electrode; a magnetic tunnel junction stack located above the bottom electrode; and a top electrode located above the magnetic tunnel junction stack; an oxide layer located on the sidewall of the magnetic tunnel junction stack; and a spacer located on the sidewall of the magnetic tunnel junction structure, wherein the spacer is in physical contact with the sidewall of the bottom electrode, the sidewall of the top electrode, and the oxide layer.

[0008] This application provides magnetic tunnel junction devices and methods for forming them. Attached Figure Description

[0009] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0010] Figures 1 to 9 This is a cross-sectional view of an intermediate stage in the formation of a semiconductor device according to some embodiments;

[0011] Figure 10 Systems used in various stages of semiconductor device fabrication according to some embodiments are illustrated;

[0012] Figure 11 An etching / magnetic treatment chamber during the etching stage is shown according to some embodiments;

[0013] Figure 12 An etching / magnetic processing chamber during the magnetic processing stage is shown according to some embodiments;

[0014] Figure 13 The process flow of the etching / magnetic processing according to some embodiments is shown;

[0015] Figure 14 The process flow of a method for forming a semiconductor device in some embodiments is shown. Detailed Implementation

[0016] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or structures discussed.

[0017] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower part," "above," and "upper part" may be used herein to readily describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientations shown in the figure, spatial relative terms are intended to encompass different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0018] Embodiments of the present invention are discussed in the context of semiconductor devices such as magnetic tunnel junction (MTJ) devices and methods for forming the same. In some embodiments, the MTJ device may be a magnetoresistive random access memory (MRAM) device. According to some embodiments, intermediate stages of forming an MTJ device are shown. According to some embodiments, when performing an etching process to pattern the MTJ layer, a magnetic treatment is performed on the MTJ layer to avoid electrical short circuits caused by re-sputtering of metal elements on the sidewalls of the patterned MTJ layer during the etching process. According to some embodiments, various layers are formed on the sidewalls of the patterned MTJ layer to reduce or avoid electron flow along the sidewalls of the patterned MTJ layer and to reduce or avoid moisture (H2O) diffusion into the patterned MTJ layer.

[0019] Figures 1 to 9 This is a cross-sectional view of an intermediate stage in the formation of a semiconductor device 100 according to some embodiments. Reference Figure 1The semiconductor device 100 includes a memory region 100A and a logic region 100B located above the same substrate 101. One or more memory devices (e.g., MRAM devices) are formed in the memory region 100A, and one or more logic devices (e.g., logic circuits) are formed in the logic region 100B. In some embodiments, electrical components 103A and 103B are formed in or on the substrate 101, and an interconnect structure including multiple dielectric layers and conductive components (e.g., metal lines and vias) formed in the dielectric layers is formed above the substrate 101 to connect the electrical components 103A and 103B, thereby forming the functional circuitry of the semiconductor device 100.

[0020] Substrate 101 may be a semiconductor substrate, such as doped or undoped silicon, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate may include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates may also be used, such as multilayer substrates or gradient substrates. Electrical components 103A and 103B may be transistors, diodes, capacitors, resistors, etc., formed by any suitable forming method.

[0021] In some embodiments, the interconnect structure includes a plurality of metallization layers formed over the substrate 101 and electrical components 103A and 103B. The metallization layers are denoted as M. x Where x = 0, 1, 2, ..., and M0 represents the lowest (e.g., closest to substrate 101) metallization layer, and the exponent x increases by 1 for each additional metallization layer. The metallization layer M0 includes one or more interlayer dielectric (ILD) layers, and conductive components within the ILD layers, such as contact plugs, for electrical connection to electrical components 103A and 103B. x (x greater than or equal to 1) includes an intermetallic dielectric (IMD) layer and conductive components (e.g., metal wires and vias) within the IMD layer. In some embodiments, conductive components such as conductive wires and vias provide electrical connections to the underlying conductive components.

[0022] Some ILD and IMD layers can be formed using any suitable dielectric material, such as nitrides (e.g., silicon nitride), oxides (e.g., silicon oxide), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or similar materials. Some ILD and IMD layers can be formed using any acceptable deposition process, such as spin coating, physical vapor deposition (PVD), chemical vapor deposition (CVD), or combinations thereof. Conductive components in some ILD and IMD layers can be formed using any suitable process, such as deposition, damascene, dual damascene, or combinations thereof.

[0023] Figure 1 The metallization layer M above the substrate 101 is shown. x and metallization layer M x+1 In some embodiments, the metallization layer M x It can be a metallization layer M0, and it can contact the substrate 101. In other embodiments, other metallization layers can be inserted into the metallization layer M. x Between and substrate 101. For simplicity, substrate 101 and electrical components 103A and 103B may not be shown in the following figures.

[0024] In some embodiments, the metallization layer M x The system includes a dielectric layer 105 and conductive components 107 within the dielectric layer 105. In some embodiments, for example, the dielectric layer 105 is a low-k dielectric layer having a k value less than about 3.0. The dielectric layer 105 may also be formed using another dielectric material such as silicon oxide, silicon nitride, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc. The conductive components 107 may be formed using metals such as copper, aluminum, tungsten, cobalt, and their metal alloys. In some embodiments, wherein the metallization layer M... x It is a metallization layer M0, and the conductive component 107 is a contact plug. In other embodiments, the metallization layer M... x It is a metallization layer with x greater than 1, and the conductive component 107 can be a metal line (such as a word line or bit line), a metal via, a doped semiconductor strip, etc.

[0025] In some embodiments, the metallization layer M x+1The dielectric layer 111 includes a dielectric layer 111 and conductive components 113 within the dielectric layer 111, such as conductive vias 113. In some embodiments, the dielectric layer 111 can be formed using TEOS oxide (silicon oxide deposited using, for example, a chemical vapor deposition (CVD) method employing tetraethyl orthosilicate (TEOS) as a precursor). In other embodiments, the dielectric layer 111 can be formed using PSG, BSG, BPSG, undoped silicate glass (USG), fluorosilicate glass (FSG), SiOCH, flowable oxides, porous oxides, etc., or combinations thereof. The dielectric layer 111 can also be formed using, for example, a low-k dielectric material with a k value less than about 3.0.

[0026] In some embodiments, the conductive via 113 includes a conductive region 117 and a conductive barrier layer 115 serving as the inner lining sidewall and bottom surface of the conductive region 117. The conductive barrier layer 115 can be formed of titanium, titanium nitride, tantalum, tantalum nitride, cobalt, combinations thereof, etc. The conductive region 117 can be formed of metals such as copper, aluminum, tungsten, cobalt, alloys thereof, etc. The formation of the via 113 may include: etching a dielectric layer 111 to form a via opening, forming a covering conductive barrier layer extending into the via opening, depositing a metal material over the covering conductive barrier layer, and performing a planarization process such as chemical mechanical polishing (CMP) or mechanical grinding to remove excess portions of the covering conductive barrier layer and the metal material.

[0027] In some embodiments, an etch stop layer 109 is formed between dielectric layer 105 and dielectric layer 111. In some embodiments, the etch stop layer 109 is formed by a dielectric layer different from the dielectric layer 111 above. For example, the etch stop layer 109 can be formed by aluminum nitride, aluminum oxide, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or combinations thereof. The etch stop layer 109 can also be a composite layer formed by multiple dielectric layers. For example, the etch stop layer 109 may include a metal oxide layer, a metal nitride layer above the metal oxide layer, and may or may not include a metal oxynitride layer or a metal carbonitride layer above the metal nitride layer. In these embodiments, the formation of the via 113 also includes etching the etch stop layer 109 when forming the via opening.

[0028] Further reference Figure 1A bottom electrode (BE) layer 119 is formed over the dielectric layer 111 and the via 113, a magnetic tunnel junction (MTJ) layer 127 is formed over the BE layer 119, and a top electrode (TE) layer 129 is formed over the MTJ layer 127. In some embodiments, the BE layer 119 is formed as a capping layer and can be formed using CVD, physical vapor deposition (PVD), electrochemical plating (ECP), electroless plating, etc. The material of the BE layer 119 may include Cu, Al, Ti, Ta, W, Pt, Ni, Cr, Ru, TiN, TaN, combinations thereof, multilayers thereof, etc. In embodiments where the BE layer 119 includes multiple layers, the BE layer 119 includes a first layer 119A and a second layer 119B located above the first layer 119A, the first layer 119A being made of TaN and the second layer 119B being made of TiN. In some embodiments, the first layer 119A has a thickness between about 20 angstroms and about 150 angstroms. In some embodiments, the second layer 119B has a thickness between about 30 angstroms and about 150 angstroms. In some embodiments, the BE layer 119 has a thickness between about 50 angstroms and about 300 angstroms.

[0029] In some embodiments, the MTJ layer 127 includes a bottom magnetic electrode layer 121, a tunnel barrier layer 123 above the bottom magnetic electrode layer 121, and a top magnetic electrode layer 125 above the tunnel barrier layer 123. The bottom magnetic electrode layer 121 may include a pinning layer 121A and a pinned layer 121B located above and in contact with the pinning layer 121A. The top magnetic electrode layer 125 may include a free layer. The bottom magnetic electrode layer 121, the tunnel barrier layer 123, and the top magnetic electrode layer 125 may be deposited using one or more deposition methods such as CVD, PVD, ALD, or combinations thereof.

[0030] The pinning layer 121A can be formed by a metal alloy, including manganese (Mn) and another (or several) metals such as platinum (Pt), iridium (Ir), rhodium (Rh), nickel (Ni), palladium (Pd), iron (Fe), and osmium (Os). Therefore, the pinning layer 121A can be formed by PtMn, IrMn, RhMn, NiMn, PdPtMn, FeMn, Os, Mn, etc. The pinning layer 121A can have a thickness in the range of about 50 angstroms to about 200 angstroms.

[0031] The pinned layer 121B can be formed of a ferromagnetic material with a larger coercive field than the top magnetic electrode layer 125, such as cobalt-iron (CoFe), cobalt-iron-boron (CoFeB), or combinations thereof. The pinned layer 121B can have a thickness in the range of about 50 angstroms to about 200 angstroms. In some embodiments, the pinned layer 121B has a synthetic ferromagnetic (SFM) structure, wherein the coupling between the magnetic layers is ferromagnetic coupling. The bottom magnetic electrode layer 121 can also employ a synthetic antiferromagnetic (SAF) structure, which includes multiple magnetic metal layers spaced apart by multiple non-magnetic spacer layers. Magnetic metal layers can be formed using Co, Fe, Ni, etc. Non-magnetic spacer layers can be formed using Cu, Ru, Ir, Pt, W, Ta, Mg, etc. For example, the bottom magnetic electrode layer 121 can have a Co layer and repeating (Pt / Co) layers above the Co layer. x A layer, where x represents the number of repetitions and can be any integer equal to or greater than 1.

[0032] The tunnel barrier layer 123 can be formed using dielectric materials such as MgO, AlO, AlN, or combinations thereof. The tunnel barrier layer 123 can have a thickness in the range of about 1 nm to about 10 nm.

[0033] The top magnetic electrode layer 125 can be formed using ferromagnetic materials such as CoF, NiFe, CoFeB, CoFeBW, and combinations thereof. The top magnetic electrode layer 125 can also employ a synthetic ferromagnetic structure similar to a SAF structure, wherein the thickness of the spacer layers is adjusted to achieve ferromagnetic coupling between the spaced magnetic metals, i.e., magnetic moment coupling is induced along the same direction. The magnetic moment of the top magnetic electrode layer 125 is programmable, thus the resistance of the resulting MTJ structure can be varied between high and low resistance. It has been recognized that the material and structure of the MTJ layer 127 can have many variations, which are also within the scope of this invention. For example, the pinning layer 121A, the pinned layer 121B, the tunnel barrier layer 123, and the top magnetic electrode layer 125 can be combined with… Figure 1 The reverse order is shown. Therefore, the free layer can be the bottom layer of MTJ layer 127, while the pinned layer can be the top layer.

[0034] Further reference Figure 1 A TE layer 129 is formed above the MTJ layer 127. In some embodiments, the TE layer 129 is formed as a capping layer and can be formed using CVD, PVD, ECP, electroless plating, etc. The material of the TE layer 129 may include aluminum, titanium, tantalum, tungsten, alloys thereof, multilayers thereof, etc. In some embodiments, the TE layer 129 may be used as a hard mask in subsequent patterning of the MTJ layer 127 and may include a conductive layer formed by TiN, Ta, TaN, Ti, Ru, W, Si, alloys thereof, multilayers thereof, etc.

[0035] In embodiments where the TE layer 129 comprises multiple layers, the TE layer 129 may include a first layer 129A, a second layer 129B above the first layer 129A, and a third layer 129C above the second layer 129B, wherein the first layer 129A is made of Ta, the second layer 129B is made of TaN, and the third layer 129C is made of Ta. In some embodiments, the first layer 129A has a thickness between about 50 angstroms and about 200 angstroms. In some embodiments, the second layer 129B has a thickness between about 50 angstroms and about 200 angstroms. In some embodiments, the third layer 129C has a thickness between about 50 angstroms and about 200 angstroms. In some embodiments, the TE layer 129 has a thickness between about 100 angstroms and about 600 angstroms. In some embodiments, the thickness of the TE layer 129 is greater than the thickness of the BE layer 119.

[0036] After forming the TE layer 129, one or more masks are formed over the TE layer 129. In some embodiments, the one or more masks may include one or more hard masks, three-layer masks, combinations thereof, etc. In some embodiments, a hard mask layer 131 is formed over the TE layer 129, and a three-layer mask 133 is formed over the hard mask layer 131. In some embodiments, the hard mask layer 131 may include TiO, TEOS oxide, combinations thereof, etc. In some embodiments, the hard mask layer 131 has a thickness between about 50 angstroms and about 300 angstroms.

[0037] The three-layer mask 133 includes a bottom layer 133A, an intermediate layer 133B above the bottom layer 133A, and a top layer 133C above the intermediate layer 133B. In some embodiments, the bottom layer 133A is formed by photoresist. In some embodiments, the bottom layer 133A is cross-linked, and therefore different from the ordinary photoresist used for exposure. In other embodiments, the bottom layer 133A comprises amorphous carbon (aC). When the top layer 133C is exposed, the bottom layer 133A can serve as a bottom anti-reflective coating (BARC). The intermediate layer 133B can comprise, for example, a material comprising silicon and oxygen, which can be SiON, but other similar materials can also be used. The top layer 133C can comprise photoresist. In some embodiments, the top layer 133C is coated as a capping layer and then patterned in a photolithography process using a photomask. In a top view of the semiconductor device 100, the remaining portion of the top layer 133C can be arranged as an array.

[0038] refer to Figure 2 Patterned top layer 133C (see Figure 1The top layer 133C is used as an etching mask to etch and pattern the intermediate layer 133B and the bottom layer 133A of the three-layer mask 133. In some embodiments, the patterned top layer 133C may be consumed during the etching process (see [link to image]). Figure 1 In some embodiments, the etching process may include anisotropic dry etching processes, such as reactive ion etching (RIE), ion beam etching (IBE), or combinations thereof.

[0039] refer to Figure 3 Patterned intermediate layer 133B (see Figure 2 The patterned bottom layer 133A is used as an etching mask to etch the hard mask layer 131 and the TE layer 129, thereby forming the top electrode (TE) 129'. The etching method may include a plasma etching method, which may include reactive ion beam etching (IBE). Etching can be performed using glow discharge plasma (GDP), capacitively coupled plasma (CCP), inductively coupled plasma (ICP), etc. The patterned intermediate layer 133B (see [link to etching process]) may be consumed during the etching process. Figure 2 In some embodiments, the etching process may not completely etch the first layer 129A of the TE layer 129. In such embodiments, after the etching process is performed, a portion of the first layer 129A of the TE layer 129 remains covering the MTJ layer 127. In some embodiments, the portion of the first layer 129A of the TE layer 129 remaining above the MTJ layer 127 has a thickness between about 10 angstroms and about 50 angstroms.

[0040] refer to Figure 4 Using a patterned underlying layer 133A (see Figure 3 ), patterned hard mask layer 131 (see Figure 3 Using MTJ layer 127 and BE layer 119 as an etching mask, one or more etching processes are used to pattern MTJ layer 127 and BE layer 119. The patterning process forms MTJ 127' and BE 119'. In some embodiments, the patterning process may partially etch dielectric layer 111. In such embodiments, dielectric layer 111 includes etched portion 111A and unetched portion 111B. In some embodiments, the top surface of etched portion 111A is above the top surface of unetched portion 111B. In some embodiments, etched portion 111A has sloping sidewalls. In some embodiments, etched portion 111A has a trapezoidal shape in the cross-section shown. In some embodiments, the patterned underlayer 133A (see [reference]) may be consumed during the patterning process. Figure 3 ) and patterned hard mask layer 131 (see Figure 3 In other embodiments, for example, a suitable removal process such as a suitable etching process is used to remove the remaining patterned underlayer 133A after the patterning process has been performed (see...). Figure 3) and patterned hard mask layer 131 (see Figure 3 TE129', MTJ127', and BE119' form an MTJ structure 401 located above the substrate 101. In some embodiments, TE129', MTJ127', and BE119' have sloping sidewalls, such that the MTJ structure 401 has sloping sidewalls. In some embodiments, the width of TE129' is smaller than the width of BE119'.

[0041] In some embodiments, one or more etching processes may include plasma etching methods, such as IBE processes. In some embodiments, the IBE process may be implemented in conjunction with magnetic treatment, which allows for the avoidance of electrical short circuits caused by re-sputtering of metal elements on the sidewalls of the MTJ127' during the IBE process. In some embodiments, magnetic treatment removes metal particles from the sidewalls of the MTJ127'. In some embodiments, the following references are used Figures 10-12 The system 1000 described is used to implement the IBE process and the magnetic treatment process, and a detailed description of the IBE process and the magnetic treatment will be provided at that time.

[0042] refer to Figure 5 After performing the IBE process and magnetic treatment process, various protective layers are formed on the sidewalls and top surface of the MTJ structure 401. In some embodiments, an oxide layer 501 is formed on the sidewall of MTJ127'. In some embodiments, the oxide layer 501 comprises an oxide of the metal element forming MTJ127' and can be formed using an oxidation process. In some embodiments, the oxide layer 501 prevents electrons from flowing along the sidewall of MTJ127', which could adversely affect the magnetic properties of MTJ127'. In some embodiments, the oxide layer 501 may have a thickness between about 5 angstroms and about 15 angstroms.

[0043] After forming the oxide layer 501, a passivation layer 503 is formed over the MTJ structure 401. In some embodiments, the passivation layer 503 may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, combinations thereof, etc., and may be formed using CVD, PECVD, ALD, PELAD, PVD, combinations thereof, etc. In some embodiments, the passivation layer 503 may reduce or prevent the diffusion of moisture (H2O) into the MTJ structure 401. In some embodiments, the passivation layer 503 may have a thickness between about 100 angstroms and about 800 angstroms. In some embodiments, the following references are used... Figure 10 The system 1000 described herein is used to implement the processes for forming oxide layer 501 and passivation layer 503, and a detailed description of these processes will be provided at that time.

[0044] refer to Figure 6A dry etching process is performed to etch the passivation layer 503 to expose the top of the MTJ structure 401 (e.g., the top of TE129'). In some embodiments, the dry etching process is an anisotropic etching process and removes the horizontal portion of the passivation layer 503. Subsequently, a passivation layer 601 is formed over the MTJ structure 401, and then an oxide layer 603 is formed over the passivation layer 601. In some embodiments, the referenced above can be used. Figure 5 The passivation layer 601 is formed using similar materials and methods to the described passivation layer 503, and therefore will not be described again here. In some embodiments, the oxide layer 603 may include silicon oxide, etc., and may be formed using CVD, PECVD, ALD, PELAD, combinations thereof, etc. Subsequently, one or more dry etching processes are performed to etch the passivation layer 601 and the oxide layer 603 to expose the top of the MTJ structure 401 (e.g., a portion of TE129'). In some embodiments, the one or more dry etching processes are anisotropic etching processes and remove the horizontal portions of the passivation layer 601 and the oxide layer 603. On the sidewalls of the MTJ structure 401, the remaining portions of the passivation layer 503, the passivation layer 601, and the oxide layer 603 form spacers 605.

[0045] Further reference Figure 6 A dielectric layer 607 is formed over the MTJ structure 401 and the spacer 605, and a nitrogen-free antireflective layer (NFARL) 609 is formed over the dielectric layer 607. In some embodiments, the dielectric layer 607 comprises a low-k oxide, such as TEOS oxide (silicon oxide deposited using, for example, a CVD method utilizing tetraethyl orthosilicate (TEOS) as a precursor). Subsequently, the dielectric layer 607 and the NFARL 609 are patterned to expose the etch stop layer 109 in the logic region 100B of the semiconductor device 100. In some embodiments, the patterning process may include suitable photolithography and etching processes.

[0046] refer to Figure 7 A dielectric layer 701 is formed above an etch stop layer 109 in the logic region 100B of the semiconductor device 100, and a nitrogen-free antireflective layer (NFARL) 703 is formed above the dielectric layer 701. In some embodiments, the above-referenced... Figure 1 The dielectric layer 701 is formed using similar materials and methods to the dielectric layer 105 described herein, and therefore will not be repeated here. In some embodiments, when the dielectric layer 701 and NFARL 703 are formed in the logic region 100B of the semiconductor device 100, the memory region 100A of the semiconductor device 100 can be protected by a mask. Subsequently, a mask layer 705 is formed over the semiconductor device 100. In some embodiments, the mask layer 705 may include TiN, TaN, etc.

[0047] refer to Figure 8 Conductive components 801 are formed in dielectric layer 701. Conductive components 801 may include conductive lines 801L and vias 801V formed using suitable formation methods such as damascene, double damascene, deposition, plating, or combinations thereof. In some embodiments, mask layer 705 and NFARL 703 (reference) Figure 7 This facilitates the formation of conductive component openings in dielectric layer 701 and etch stop layer 109. In some embodiments, the conductive component openings are formed using a via-first process. In other embodiments, the conductive component openings are formed using a trench-first process. Subsequently, the conductive component openings are filled with a suitable conductive material. Next, a planarization process, such as CMP, is performed to remove excess material above MTJ structure 401 and expose the topmost surface of MTJ structure 401. In some embodiments, the topmost surface of MTJ structure 401 is flush with the topmost surface of conductive component 801. In some embodiments, the planarization process completely removes mask layer 705 and NFARL 703 (see reference). Figure 7 ).

[0048] refer to Figure 9 After the conductive component 801 is formed, a metallization layer M is formed on the MTJ structure 401, the dielectric layer 701, and the conductive component 801. x+2 In some embodiments, the metallization layer M x+2 The formation includes forming an etch stop layer 901 over the MTJ structure 401, the dielectric layer 701, and the conductive component 801. Subsequently, a dielectric layer 903 is formed over the etch stop layer 901. In some embodiments, the above-referenced... Figure 1 The etch stop layer 901 is formed using materials and methods similar to those described for the etch stop layer 109, and therefore will not be repeated here. In some embodiments, materials and methods similar to those referenced above can be used. Figure 1 The dielectric layer 903 is formed using materials and methods similar to those described for dielectric layer 105, and therefore will not be described again here. Subsequently, conductive components 905 (e.g., conductive lines 905L and vias 905V) are formed in the dielectric layer 903. The conductive components 905 extend through the etch stop layer 901 and are electrically connected to the conductive components 801 and the MTJ structure 401. In some embodiments, materials and methods similar to those described above can be used. Figure 8 The conductive component 801 is formed using similar materials and methods to the conductive component 905, and therefore will not be described again here. It is provided for illustrative purposes only. Figure 9 The specific number of MTJ structures 401, conductive components 801, and conductive components 905 shown are as described. Other numbers of MTJ structures 401, conductive components 801, and conductive components 905 are also possible and are fully intended to be included within the scope of this invention.

[0049] As will be readily understood by those skilled in the art, it can be Figure 9 The processing shown is followed by additional processing to complete the fabrication of the semiconductor device 100, so details are not discussed here. For example, additional processing can be performed on the metallization layer M. x+2 One or more additional metallization layers are formed on top until the interconnect structure is completed.

[0050] Figure 10 A system 1000 is illustrated for use in various formation stages of a semiconductor device 100 according to some embodiments. In some embodiments, the system 1000 may be used to implement a reference system. Figure 4 and Figure 5 The described process steps. In some embodiments, system 1000 includes an etching / magnetic processing station 1001, an oxidation / deposition station 1003, a loading and locking chamber 1005, and a transfer chamber 1007. In some embodiments, reference is implemented using the etching / magnetic processing station 1001. Figure 4 The process steps are described. In some embodiments, the oxidation / deposition station 1003 is used to implement the reference. Figure 5 The described process steps. In some embodiments, Figure 3 The semiconductor device 100 shown is loaded into the system 1000 to implement the above reference. Figure 4 and Figure 5 The described process steps.

[0051] In some embodiments, the etching / magnetic processing station 1001 is configured to perform a magnetic processing process in conjunction with an IBE process by implementing one or more process cycles. In some embodiments, each cycle includes an IBE phase followed by a magnetic processing phase. In some embodiments, the one or more process cycles may include one to six cycles. In some embodiments, the oxidation / deposition station 1003 is configured to perform oxidation and deposition processes.

[0052] In some embodiments, the loading locking chamber 1005 is open to the outside atmosphere and contains... Figure 3The semiconductor device 100 is shown. Once the semiconductor device 100 is placed in the loading lock chamber 1005, the loading lock chamber 1005 can be closed, thereby isolating the semiconductor device 100 from the outside atmosphere. Once isolated, any remaining outside atmosphere in the loading lock chamber 1005 can then be vented to prepare for the semiconductor device 100 to be moved to other parts of the system 1000 via, for example, a transfer chamber 1007. The transfer chamber 1007 may include one or more robotic arms 1009 that can grip, move, and transfer the semiconductor device 100 from the loading lock chamber 1005 to, for example, an etching / magnetic processing station 1001. In some embodiments, the robotic arm 1009 may extend into the loading lock chamber 1005, grip the semiconductor device 100, and transfer the semiconductor device 100 into the transfer chamber 1007. Once inside transfer chamber 1007, transfer chamber 1007 may have a closed door to isolate transfer chamber 1007 from loading lock chamber 1005, allowing loading lock chamber 1005 to reopen to the outside atmosphere without contaminating other parts of system 1000. Once isolated from loading lock chamber 1005, transfer chamber 1007 can be opened to etching / magnetic processing station 1001, where robotic arm 1009, still holding semiconductor device 100, extends into etching / magnetic processing station 1001 and places semiconductor device 1000 for further processing. Once semiconductor device 1000 is placed in etching / magnetic processing station 1001, the etching / magnetic processing station 1001 performs the above-mentioned procedures. Figure 4 The described process steps are as follows. Subsequently, the semiconductor device 100 is transferred to the oxidation / deposition station 1003 via transfer chamber 1007. Once the semiconductor device 100 is placed in the oxidation / deposition station 1003, the oxidation / deposition station 1003 performs the above-described process. Figure 5 The described process steps.

[0053] Figure 11 An etching / magnetic processing station 1001 during an etching phase is illustrated according to some embodiments. In some embodiments, the etching / magnetic processing station 1001 includes a plasma chamber 1101. The plasma chamber 1101 may also be referred to as a discharge chamber. A gas inlet 1103 supplies a suitable process gas to the plasma chamber 1101. In some embodiments, the suitable process gas includes inert gases such as He, Ne, Ar, Kr, Xe, Ra, combinations thereof, etc. A plasma generator 1105 generates plasma 1107 from the process gas. In some embodiments, the plasma generator 1105 is connected to a radio frequency (RF) power supply (not shown). In some embodiments, the plasma generator 1105 may be a transformer-coupled plasma generator, an inductively coupled plasma system, a magnetically enhanced reactive ion etching system, an electron cyclotron resonance system, a remote plasma generator, etc. In some embodiments, the RF power supply operates at a power between about 50 W and about 500 W.

[0054] In some embodiments, the etching / magnetic processing station 1001 further includes a grid optics device 1109. In some embodiments, the grid optics device 1109 includes an electrostatic aperture through which ions from plasma 1107 are extracted and an ion beam 1113 is formed. In some embodiments, the grid optics device 1109 includes one or more grids. In some embodiments, each grid includes an electrode having multiple apertures. The multiple apertures in different grids are aligned to allow the extraction of ions from plasma 1107. In some embodiments, the grid optics device 1109 includes a screen (S) grid 1109A, an accelerator (A) grid 1109B, and a decelerator (D) grid 1109C. The S grid 1109A is positioned closest to the plasma chamber 1101. The A grid 1109B is inserted between the S grid 1109A and the D grid 1109C. The S grid 1109A is biased by a positive voltage (beam voltage) relative to ground. In some embodiments, the beam voltage can be between approximately 100V and approximately 1000V. A grid 1109B is biased with a negative voltage relative to ground. A grid 1109C is grounded. Ions generated in plasma chamber 1101 are accelerated to high speed using grid optics 1109 to form an ion beam 1113. In some embodiments, a neutralizer 1115 is placed downstream of plasma 1107. The neutralizer 1115 emits electrons 1117 to balance the number of ions in the ion beam 1113. The electrons 1117 provide charge balance for the ions in the ion beam 1113, which allows for minimization or elimination of space or surface charges that may occur during the etching process.

[0055] In some embodiments, the etching / magnetic processing station 1001 further includes a chuck 1119 configured to hold the semiconductor device 100 during various process steps. In some embodiments, the chuck 1119 is a vacuum chuck, an electrostatic chuck, etc. In some embodiments, the chuck 1119 is configured to rotate about axis 1123 (by...). Figure 11 (As shown by arrow 1121 in the image), and tilted relative to the direction in which the ion beam 1113 strikes the semiconductor device 100 (by...). Figure 11(As indicated by arrow 1125 in the diagram). In some embodiments, the tilt angle θ of the chuck 1119 (the angle between the direction of the ion beam 1113 and the normal of the chuck 1119) is between approximately 90° and approximately -70°. In some embodiments, the rotational speed of the chuck 1119 is between approximately 5 rpm and approximately 100 rpm. In some embodiments, a mechanical shutter 1111 is positioned between the grating optics 1109 and the chuck 1119. In some embodiments, the mechanical shutter 1111 may be closed to prevent the ion beam 1113 from impacting the semiconductor device 100 positioned on the chuck 1119. The mechanical shutter 1111 is opened during the IBE phase. The mechanical shutter 1111 is closed during the magnetic processing phase.

[0056] In some embodiments, the etching / magnetic processing station 1001 further includes an endpoint detection system 1127 configured to detect byproducts of the IBE process (made by...). Figure 11 (As indicated by arrow 1129 in the diagram), and the IBE process is stopped when a desired byproduct is detected. In some embodiments, the etching / magnetic processing station 1001 further includes a pump 1131 configured to discharge byproducts of the IBE process from the etching / magnetic processing station 1001. In some embodiments, the etching / magnetic processing station 1001 further includes a magnetic system 1133 configured to generate a magnetic field during the magnetic processing phase.

[0057] In some embodiments, the magnetic system 1133 includes a conductive layer inner liner of an etching / magnetic processing station 1001 located around a chuck 1119 and a semiconductor device 100 placed on the chuck 1119. In other embodiments, the magnetic system 1133 may include a coil, solenoid, electromagnet, or other element for generating a magnetic field. In some embodiments, the conductive layer may include one or more layers of aluminum, iron, nickel, or combinations thereof. In some embodiments, the magnetic system 1133 generates a magnetic field by allowing current to flow through it.

[0058] Further reference Figure 11 During the IBE phase, the mechanical shutter 1111 is opened, and an ion beam 1113 emitted from the plasma 1107 generated by the plasma generator 1105 strikes the semiconductor device 100 placed on the chuck 1119. In some embodiments, the etching rate of the ion beam 1113 can be varied by changing the tilt angle θ of the chuck 1119. In some embodiments, the IBE phase can be implemented for a duration between approximately 10 seconds and 500 seconds.

[0059] Figure 12 An etching / magnetic processing station 1001 during a magnetic processing phase is illustrated according to some embodiments. In some embodiments, during the magnetic processing phase, the mechanical shutter 1111 is closed to prevent the ion beam 1113 (see reference) from entering the magnetic processing phase. Figure 11 The plasma is impacted by a semiconductor device 100 placed on a chuck 1119. In other embodiments, the plasma generator 1105 can be turned off, thereby preventing the generation of plasma 1107 and ion beam 1113 (see reference). Figure 11 In some embodiments, a magnetic field is generated by a magnetic system 1133 surrounding the semiconductor device 100 during the magnetic processing phase. In some embodiments, the magnetic system 1133 generates the magnetic field by allowing current to flow through it. In some embodiments, the current is between about 100 mA and 2000 mA. In some embodiments, the magnetic processing phase may be carried out in an inert gas atmosphere including He, Ne, Ar, Kr, Xe, Ra, and combinations thereof. In some embodiments, the magnetic processing phase may be carried out for a duration between about 10 seconds and 100 seconds. In some embodiments, the ratio of the duration of the IBE phase to the duration of the magnetic processing phase is between about 5:1 and about 1:3. In some embodiments, the magnetic processing removes metal particles re-sputtered onto the sidewalls of the MTJ127' during the IBE phase. In some embodiments, during the magnetic processing phase, the magnetic system 1133 generates a magnetic field that attracts the re-sputtered metal particles and removes them from the sidewalls of the MTJ127'. Therefore, electrical short circuits caused by metal particles are reduced or avoided.

[0060] Further reference Figure 5 and Figure 10 In implementing the above reference Figure 3 and Figures 10 to 12Following the IBE and magnetic processing processes, the semiconductor device 100 is transferred to an oxidation / deposition station 1003. In some embodiments, after the semiconductor device 100 is placed in the oxidation / deposition station 1003, an oxide layer 501 is formed on the sidewall of the MTJ127'. In some embodiments, an oxidation process including thermal oxidation, PECVD, or combinations thereof can be used to form the oxide layer 501. In some embodiments using PECVD to form the oxide layer 501, N2O can be used as the oxygen source. In some embodiments, PECVD can be performed with an RF power between about 10 W and about 100 W. In some embodiments with an RF power less than about 10 W, the oxidation process may be ineffective, and the desired thickness of the oxide layer 501 may not be achieved. In some embodiments with an RF power greater than about 100 W, the oxidation process may damage the MTJ127'. In some embodiments, the oxidation process is performed at a temperature between 20°C and about 200°C. In some embodiments, the oxidation process is performed at a pressure between about 0 Torr and about 10 Torr. In some embodiments, the oxidation process is performed for a duration between about 5 seconds and about 50 seconds. In some embodiments lasting longer than about 50 seconds, the oxide layer 501 may be too thick, potentially damaging the MTJ127' during the oxidation process. In some embodiments lasting less than about 5 seconds, the oxide layer 501 may be too thin, allowing electrons to flow along the sidewalls of the MTJ127' and adversely affecting device performance. In some embodiments, the thickness of the oxide layer 501 is between about 5 angstroms and about 15 angstroms. In some embodiments where the oxide layer 501 is thicker than about 15 angstroms, the oxidation process may damage the MTJ127'. In some embodiments where the oxide layer 501 is thinner than about 5 angstroms, electrons may flow along the sidewalls of the MTJ127' and adversely affect device performance.

[0061] Further reference Figure 5 and Figure 10After forming the oxide layer 501, the oxidation / deposition station 1003 forms a passivation layer 503 over the MTJ structure 401. In some embodiments, the passivation layer 503 can be formed using PECVD, PVD, ALD, PEALD, combinations thereof, etc. In some embodiments, SiH4 and NH3 are used as silicon and nitrogen precursors, respectively, to form a passivation layer 503 comprising silicon nitride via PECVD. In some embodiments, the flow rate of SiH4 can be between about 10 sccm and about 1000 sccm. In some embodiments, the flow rate of NH3 can be between about 1 sccm and about 100 sccm. In some embodiments, a carrier gas can be used in addition to the silicon and nitrogen precursors. The carrier gas can be He, N2, Ar, combinations thereof, etc. In some embodiments, PECVD can be performed at a temperature between about 50°C and about 250°C. In some embodiments, PECVD can be performed at a pressure between about 0 Torr and about 10 Torr. In some embodiments, the RF power of PECVD can be between about 50 W and about 600 W. In some embodiments where the temperature is above about 250°C and MTJ127' contains Mg, Mg ions may diffuse and may affect the magnetism of MTJ127'. In some embodiments where the temperature is below about 50°C, the magnetism of MTJ127' may be affected by moisture (H2O). In some embodiments, the passivation layer 503 may have a thickness between about 100 angstroms and about 800 angstroms. In some embodiments, the passivation layer 503 may have a refractive index (RI) between about 2.0 and about 2.3.

[0062] In some embodiments, a passivation layer 503 comprising silicon nitride is formed using PVD. In such embodiments, a Si target is sputtered in an Ar / N2 atmosphere. In some embodiments, PVD is performed at a temperature between about 50°C and about 400°C. In some embodiments, the RF power of the PVD is between about 100W and about 500W.

[0063] In some embodiments, a passivation layer 503 comprising silicon nitride is formed by using a PEALD with SiH4 and N2 as silicon and nitrogen precursors, respectively. In some embodiments, the RF power of the PEALD is between about 20 W and about 300 W. In some embodiments, the PEALD is implemented at a temperature between about 100 °C and about 400 °C.

[0064] Figure 13 A process flow diagram of an etching / magnetic processing process 1300 according to some embodiments is shown. In some embodiments, the etching / magnetic processing process 1300 begins at step 1301, wherein the wafer (e.g., Figure 3 The semiconductor device 100 shown is introduced into the process chamber (e.g., Figure 10 and Figure 11Etching / magnetic processing station 1001 shown). In step 1303, as referenced above. Figure 4 , Figure 10 ,and Figure 11 The process chamber performs the IBE process on the wafer. In step 1305, as described above... Figure 4 , Figure 10 ,and Figure 12 The process chamber performs magnetic processing on the wafer. In some embodiments, the cycle including step 1303 followed by step 1305 can be repeated N times. In some embodiments, N can be between 1 and 6.

[0065] Figure 14 A process flow for a method 1400 of forming a semiconductor device is illustrated in some embodiments. In some embodiments, method 1400 begins with step 1401, wherein, as referenced above... Figure 1 The bottom electrode layer is formed above the substrate (e.g., Figure 1 (BE layer 119 shown). In step 1403, as referenced above. Figure 1 The magnetic tunnel junction (MTJ) layer is formed above the bottom electrode layer (e.g., Figure 1 (MTJ layer 127 shown). In step 1405, as referenced above. Figure 1 As described above, a top electrode layer (e.g.) is formed above the MTJ layer. Figure 1 (TE layer 129 shown). In step 1407, as referenced above... Figure 2 and Figure 3 The top electrode layer is patterned. In step 1409, as referenced above... Figure 4 and Figures 10 to 12 The patterned MTJ layer and bottom electrode layer are used to form an MTJ structure (e.g., Figure 4 The MTJ structure 401 shown is illustrated. In some embodiments, implementing step 1409 includes the steps described above with reference to... Figure 13 The etching / magnetic processing process 1300 is implemented. In step 1411, as referred above... Figure 5 and Figure 10 The oxidation process is performed on the sidewalls of the patterned MTJ layer (e.g., the sidewalls of MTJ127'). In step 1413, as referenced above... Figure 5 and Figure 10 As described above, a passivation layer (e.g.) is formed on the sidewalls and top surface of the MTJ structure. Figure 5 (Passivation layer 503 shown).

[0066] In one embodiment, a method includes: forming a bottom electrode layer over a substrate; forming a magnetic tunnel junction (MTJ) layer over the bottom electrode layer; forming a top electrode layer over the MTJ layer; patterning the top electrode layer; and, after patterning the top electrode layer, performing one or more process cycles on the MTJ layer and the bottom electrode layer, wherein the patterned top electrode layer, the patterned MTJ layer, and the patterned bottom electrode layer form an MTJ structure, and wherein each of the one or more process cycles includes: performing an etching process on the MTJ layer and the bottom electrode layer for a first duration; and performing a magnetic treatment on the MTJ layer and the bottom electrode layer for a second duration. In one embodiment, performing the etching process includes performing an ion beam etching process. In one embodiment, the method further includes performing an oxidation process on the MTJ structure, wherein the oxidation process forms an oxide layer on the sidewalls of the patterned MTJ layer. In one embodiment, the method further includes forming a passivation layer along the sidewalls and top surface of the MTJ structure. In one embodiment, the oxide layer and the passivation layer are formed in the same process chamber. In one embodiment, the etching process and the magnetic treatment are performed in the same process chamber. In one embodiment, the ratio of the first duration to the second duration is between approximately 5:1 and approximately 1:3.

[0067] In another embodiment, a method includes: introducing a wafer into a process chamber, the wafer including: a bottom electrode layer above a substrate; a magnetic tunnel junction (MTJ) layer above the bottom electrode layer; and a patterned top electrode layer above the MTJ layer; while the wafer is in the process chamber, performing one or more process cycles on the wafer, wherein each of the one or more process cycles includes: performing an IBE process on the MTJ layer and the bottom electrode layer for a first duration using an ion beam etching (IBE) system of the process chamber; and performing a magnetic treatment on the MTJ layer and the bottom electrode layer for a second duration using a magnetic system of the process chamber. In one embodiment, the ratio of the first duration to the second duration is between about 5:1 and about 1:3. In one embodiment, the magnetic system generates a magnetic field around the wafer. In one embodiment, the magnetic treatment removes metal particles from the sidewalls of the patterned MTJ layer. In one embodiment, the one or more process cycles include between one and six process cycles. In one embodiment, the method further includes closing a mechanical shutter disposed between the IBE system and the magnetic system after performing the IBE process. In one embodiment, performing magnetic processing includes flowing an electric current through a magnetic system to generate a magnetic field.

[0068] In another embodiment, a device includes: a substrate; a magnetic tunnel junction (MTJ) structure located above the substrate, wherein the MTJ structure includes: a bottom electrode; an MTJ stack located above the bottom electrode; and a top electrode located above the MTJ stack; an oxide layer located on a sidewall of the MTJ stack; and a spacer located on a sidewall of the MTJ structure, wherein the spacer is in physical contact with the sidewall of the bottom electrode, the sidewall of the top electrode, and the oxide layer. In one embodiment, the device further includes a metallization layer located between the substrate and the MTJ structure, wherein the bottom electrode of the MTJ structure is electrically connected to a conductive component of the metallization layer. In one embodiment, the device further includes a metallization layer located above the MTJ structure, wherein the top electrode of the MTJ structure is electrically connected to a conductive component of the metallization layer. In one embodiment, the width of the bottom electrode is greater than the width of the top electrode. In one embodiment, the MTJ stack has sloping sidewalls. In one embodiment, the thickness of the top electrode is greater than the thickness of the bottom electrode.

[0069] According to embodiments of this application, a method for forming a semiconductor device is provided, comprising: forming a bottom electrode layer over a substrate; forming a magnetic tunnel junction layer over the bottom electrode layer; forming a top electrode layer over the magnetic tunnel junction layer; patterning the top electrode layer; and after patterning the top electrode layer, performing one or more process cycles on the magnetic tunnel junction layer and the bottom electrode layer, wherein the patterned top electrode layer, the patterned magnetic tunnel junction layer, and the patterned bottom electrode layer form a magnetic tunnel junction structure, and wherein each of the one or more process cycles comprises: performing an etching process on the magnetic tunnel junction layer and the bottom electrode layer for a first duration; and performing a magnetic processing on the magnetic tunnel junction layer and the bottom electrode layer for a second duration.

[0070] According to an embodiment of this application, the etching process includes performing an ion beam etching process.

[0071] According to embodiments of this application, an oxidation process is further performed on the magnetic tunnel junction structure, wherein the oxidation process forms an oxide layer on the sidewalls of the patterned magnetic tunnel junction layer.

[0072] According to embodiments of this application, a passivation layer is also formed along the sidewalls and top surface of the magnetic tunnel structure.

[0073] According to an embodiment of this application, an oxide layer and a passivation layer are formed in the same process chamber.

[0074] According to an embodiment of this application, the etching process and magnetic treatment are performed in the same process chamber.

[0075] According to an embodiment of this application, the ratio of the first duration to the second duration is between about 5:1 and about 1:3.

[0076] According to an embodiment of this application, a method for forming a semiconductor device is provided, comprising: introducing a wafer into a process chamber, the wafer including: a bottom electrode layer located above a substrate; a magnetic tunnel junction layer located above the bottom electrode layer; and a patterned top electrode layer located above the magnetic tunnel junction layer; and performing one or more process cycles on the wafer while the wafer is in the process chamber, wherein each of the one or more process cycles includes: performing an ion beam etching process on the magnetic tunnel junction layer and the bottom electrode layer for a first duration using an ion beam etching system of the process chamber; and performing a magnetic treatment on the magnetic tunnel junction layer and the bottom electrode layer for a second duration using a magnetic system of the process chamber.

[0077] According to embodiments of this application, a method for forming a semiconductor device is provided, comprising: introducing a wafer into a process chamber, the wafer including: a bottom electrode layer above a substrate; a magnetic tunnel junction layer above the bottom electrode layer; and a patterned top electrode layer above the magnetic tunnel junction layer; while the wafer is in the process chamber, performing one or more process cycles on the wafer, wherein each of the one or more process cycles includes: performing an ion beam etching process on the magnetic tunnel junction layer and the bottom electrode layer for a first duration using an ion beam etching system of the process chamber; and performing a magnetic treatment on the magnetic tunnel junction layer and the bottom electrode layer for a second duration using a magnetic system of the process chamber. The ratio of the first duration to the second duration is between 5:1 and 1:3.

[0078] According to an embodiment of this application, a magnetic system generates a magnetic field around a wafer.

[0079] According to an embodiment of this application, magnetic processing removes metal particles from the sidewalls of a patterned magnetic tunneling layer.

[0080] According to embodiments of this application, one or more process cycles include between one and six process cycles.

[0081] According to embodiments of this application, the method further includes closing the mechanical shutter located between the ion beam etching system and the magnetic system after the ion beam etching process is performed.

[0082] According to an embodiment of this application, performing magnetic processing includes causing an electric current to flow through a magnetic system to generate a magnetic field.

[0083] According to an embodiment of this application, a semiconductor device is provided, comprising: a substrate; a magnetic tunnel junction structure located above the substrate, wherein the magnetic tunnel junction structure includes: a bottom electrode; a magnetic tunnel junction stack located above the bottom electrode; and a top electrode located above the magnetic tunnel junction stack; an oxide layer located on the sidewall of the magnetic tunnel junction stack; and a spacer located on the sidewall of the magnetic tunnel junction structure, wherein the spacer is in physical contact with the sidewall of the bottom electrode, the sidewall of the top electrode, and the oxide layer.

[0084] According to embodiments of this application, a metallization layer is further included between the substrate and the magnetic tunnel junction structure, wherein the bottom electrode of the magnetic tunnel junction structure is electrically connected to a conductive component of the metallization layer.

[0085] According to embodiments of this application, a metallization layer is also included above the magnetic tunnel junction structure, wherein the top electrode of the magnetic tunnel junction structure is electrically connected to a conductive component of the metallization layer.

[0086] According to an embodiment of this application, the width of the bottom electrode is greater than the width of the top electrode.

[0087] According to an embodiment of this application, the magnetic tunnel junction stack has inclined sidewalls.

[0088] According to an embodiment of this application, the thickness of the top electrode is greater than the thickness of the bottom electrode.

[0089] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures for performing the same or similar purposes and / or achieving the same or similar advantages as this disclosure. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, comprising: Substrate; A magnetic tunnel junction structure is located above the substrate, wherein the magnetic tunnel junction structure includes: Bottom electrode; A magnetic tunnel junction stack is located above the bottom electrode; and The top electrode is located above the magnetic tunnel junction stack. An oxide layer is located on the sidewall of the magnetic tunnel junction stack; and A spacer is located on the sidewall of the magnetic tunnel junction structure, wherein the spacer is in physical contact with the sidewall of the bottom electrode, the sidewall of the top electrode, and the oxide layer. The oxide layer exposes the sidewalls of the bottom electrode, and the oxide layer has a bottom surface that is exposed compared to the bottom electrode. The portion of the spacer that physically contacts the sidewall of the bottom electrode has a top surface, and the bottom surface and the top surface face each other and are in physical contact.

2. The semiconductor device according to claim 1, further comprising a metallization layer located between the substrate and the magnetic tunnel junction structure, wherein, The bottom electrode of the magnetic tunnel junction structure is electrically connected to a conductive component of the metallization layer.

3. The semiconductor device according to claim 1, further comprising a metallization layer located above the magnetic tunnel junction structure, wherein, The top electrode of the magnetic tunnel junction structure is electrically connected to a conductive component of the metallization layer.

4. The semiconductor device according to claim 1, wherein, The width of the bottom electrode is greater than the width of the top electrode.

5. The semiconductor device according to claim 1, wherein, The magnetic tunnel junction stack has inclined sidewalls.

6. The semiconductor device according to claim 1, wherein, The thickness of the top electrode is greater than the thickness of the bottom electrode.

7. The semiconductor device according to claim 1, wherein, The magnetic tunnel junction stack comprises a metallic element, and wherein the oxide layer comprises an oxide of the metallic element.

8. The semiconductor device according to claim 1, wherein, The top surface of the top electrode is located above the top surface of the spacer.

9. The semiconductor device according to claim 1, wherein, The spacer includes multiple dielectric layers.

10. The semiconductor device according to claim 1, wherein, The oxide layer is located on the sidewall of the magnetic tunnel junction stack and exposes the sidewall of the top electrode.

11. A semiconductor device, comprising: Substrate; A dielectric layer is located above the substrate; A first conductive component is located within the dielectric layer; A magnetic tunnel junction structure is located above the dielectric layer, the magnetic tunnel junction structure having inclined sidewalls, wherein the magnetic tunnel junction structure includes: The bottom electrode is in physical contact with the first conductive component; A magnetic tunnel junction stack is located above the bottom electrode; and The top electrode is located above the magnetic tunnel junction stack. An oxide layer extends along the inclined sidewalls of the magnetic tunnel junction structure from the bottom surface of the magnetic tunnel junction stack to the top surface of the magnetic tunnel junction stack; and A spacer extends along the inclined sidewall of the magnetic tunnel junction structure, wherein the spacer is in physical contact with the bottom electrode, the top electrode, and the oxide layer, and a portion of the spacer extends into the dielectric layer. The oxide layer exposes the sidewalls of the bottom electrode, and the oxide layer has a bottom surface that is exposed relative to the bottom electrode. The portion of the spacer that is in physical contact with the bottom electrode has a top surface, and the bottom surface and the top surface face each other and are in physical contact.

12. The semiconductor device according to claim 11, wherein, The magnetic tunnel junction stack comprises a metallic element, and wherein the oxide layer comprises an oxide of the metallic element.

13. The semiconductor device according to claim 11, wherein, The spacer includes multiple dielectric layers.

14. The semiconductor device according to claim 11, wherein, The first conductive component has inclined sidewalls.

15. The semiconductor device according to claim 11, wherein, The top surface of the first conductive component is located above the bottom surface of the spacer.

16. The semiconductor device according to claim 11, wherein, The top surface of the top electrode is located above the top surface of the spacer.

17. The semiconductor device of claim 11, further comprising a metallization layer located above the magnetic tunnel junction structure, wherein, The top electrode of the magnetic tunnel junction structure is in physical contact with the second conductive component of the metallization layer.

18. The semiconductor device according to claim 11, wherein, The width of the bottom electrode is greater than the width of the top electrode.

19. The semiconductor device according to claim 11, wherein, The thickness of the top electrode is greater than the thickness of the bottom electrode.

20. The semiconductor device according to claim 11, wherein, The oxide layer exposes the sidewalls of the top electrode.

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