A chip detection method, device, apparatus and storage medium

Abstract

A chip detection method, device, equipment and storage medium are disclosed. The method is applied to a detection platform, and the chip detection method comprises: dynamically obtaining an excitation signal value sequence of a chip to be detected according to a scene requirement; updating a reference model according to the excitation signal value sequence, wherein the reference model comprises an expected signal value sequence of at least one detected signal corresponding to the chip to be detected; obtaining a current signal value sequence of the at least one detected signal output by the chip to be detected according to the excitation signal value sequence; and comparing the current signal value sequence and the expected signal value sequence of each detected signal to determine a target detection result of the chip to be detected. The embodiment of the present application can solve the problem that the static detection method for the clock and reset signals of the chip in the prior art cannot detect the dynamically changing clock and reset signals in real time.

Description

Technical Field

[0001] This invention relates to the field of chip verification technology, and in particular to a chip testing method, apparatus, device, and storage medium. Background Technology

[0002] Complex SOC (System-on-a-Chip) chips typically contain complex clock and reset networks. The correct transmission of clock and reset signals is crucial for the normal operation of the chip. Therefore, it is necessary to use an effective method and device to detect the correctness of clock and reset signal transmission before the chip is put into production.

[0003] The existing methods for detecting clock and reset signals of chips are static methods. The detection scenario is relatively fixed and the reference model cannot be changed in real time. Therefore, they cannot detect dynamically changing clock and reset signals in real time. Summary of the Invention

[0004] This invention provides a chip detection method, apparatus, device, and storage medium to solve the problem that existing static detection methods for chip clock and reset signals cannot detect dynamically changing clock and reset signals in real time.

[0005] According to one aspect of the present invention, a chip detection method is provided, the method comprising:

[0006] Based on the requirements of the scenario, dynamically acquire the excitation signal value sequence of the chip to be tested;

[0007] The reference model is updated according to the excitation signal value sequence, wherein the reference model includes the expected signal value sequence of at least one detected signal corresponding to the chip under test;

[0008] Obtain the current signal value sequence of at least one detected signal output by the chip under test according to the excitation signal value sequence;

[0009] The current signal value sequence of each detected signal is compared with the expected signal value sequence to determine the target detection result of the chip to be detected.

[0010] According to another aspect of the present invention, a chip inspection apparatus is provided, the apparatus comprising:

[0011] The first acquisition module is used to dynamically acquire the excitation signal value sequence of the chip to be tested according to the scenario requirements;

[0012] An update module is used to update a reference model, wherein the reference model includes a sequence of expected signal values ​​for at least one detected signal corresponding to the chip under test;

[0013] The second acquisition module is used to acquire the current signal value sequence of at least one detected signal output by the chip under test according to the excitation signal value sequence;

[0014] The first determining module is used to compare the current signal value sequence of each detected signal with the expected signal value sequence to determine the target detection result of the chip to be detected.

[0015] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising:

[0016] At least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores a computer program executable by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the chip detection method according to any embodiment of the present invention.

[0017] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions for causing a processor to execute and implement the chip detection method according to any embodiment of the present invention.

[0018] The technical solution of this invention dynamically acquires the excitation signal value sequence of the chip under test according to the scenario requirements, updates the reference model according to the excitation signal value sequence, wherein the reference model includes the expected signal value sequence of at least one detected signal corresponding to the chip under test, acquires the current signal value sequence of at least one detected signal output by the chip under test according to the excitation signal value sequence, compares the current signal value sequence and the expected signal value sequence of each detected signal, and determines the target detection result of the chip under test. This solves the problem that the static detection method for the clock and reset signals of the chip in the prior art cannot detect dynamically changing clock and reset signals in real time, and achieves the beneficial effect of being able to detect dynamically changing clock and reset signals in real time.

[0019] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a flowchart of a chip detection method provided according to Embodiment 1 of the present invention;

[0022] Figure 2 This is a flowchart of another chip detection method provided according to Embodiment 2 of the present invention;

[0023] Figure 3 This is a schematic diagram of the structure of a chip detection device according to Embodiment 3 of the present invention;

[0024] Figure 4 This is a schematic diagram of the structure of an electronic device that implements the chip detection method of this invention. Detailed Implementation

[0025] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0026] It should be noted that the terms "first," "target," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0027] Example 1

[0028] Figure 1 This is a flowchart of a chip testing method according to Embodiment 1 of the present invention. This embodiment is applicable to chip testing situations. The method can be executed by a chip testing device, which can be implemented in hardware and / or software. This chip testing device can be integrated into any electronic device that provides chip testing functionality. Figure 1 As shown, the method includes:

[0029] S101. Dynamically acquire the excitation signal value sequence of the chip to be tested according to the scenario requirements.

[0030] In this embodiment, the scenario requirement can be understood as a prerequisite for executing a certain use case, and the chip to be tested can be the SOC (System-on-a-Chip) chip to be tested.

[0031] It should be noted that the excitation signal value sequence can be the excitation signal value sequence input to the chip under test. Specifically, the excitation signal can be generated by a clock generator connected to the chip under test. The excitation signal generated by the clock generator can be, for example, a square wave signal. Therefore, the excitation signal value sequence can be, for example, in the form of 010101, where 0 represents a low-level signal value and 1 represents a high-level signal value. The frequency of the excitation signal can be determined by the configuration attributes of the clock generator.

[0032] Specifically, based on the scenario requirements, the excitation signal value sequence input from the clock generator to the chip under test is dynamically acquired, so that the excitation signal value sequence input to the chip under test can change dynamically.

[0033] S102. Update the reference model based on the excitation signal value sequence.

[0034] The reference model includes a sequence of expected signal values ​​for at least one detected signal corresponding to the chip under test.

[0035] It should be noted that the signal being detected can be a signal in the chip under test, such as a SOC chip. Preferably, the signal being detected can include a clock signal and a reset signal.

[0036] It should be explained that the expected signal value sequence can be a sequence of signal values ​​for at least one detected signal that the chip under test is expected to output, determined based on the excitation signal value sequence input to the chip under test. Specifically, the expected signal value sequence can be determined by the user based on practical experience or testing requirements. Preferably, the expected signal value sequence can include the expected signal value sequence of the detected clock signal and the expected signal value sequence of the detected reset signal.

[0037] Specifically, the reference model can be dynamically updated based on the excitation signal value sequence according to the scenario requirements. The reference model includes the expected signal value sequence of at least one detected signal corresponding to the chip under test.

[0038] S103. Obtain the current signal value sequence of at least one detected signal output by the chip under test based on the excitation signal value sequence.

[0039] The current signal value sequence can be the actual signal value sequence output by the chip under test based on the excitation signal value sequence input to the chip under test. Preferably, the current signal value sequence can include the current signal value sequence of the clock signal being detected and the current signal value sequence of the reset signal being detected.

[0040] Specifically, this chip detection method is applied to a detection platform, which connects to the detected signal of the chip under test through a parameterizable standardized interface. That is, a parameterized interface can be designed, which connects to the chip under test to obtain the current signal value sequence of at least one detected signal output by the chip under test based on the excitation signal value sequence. In the implementation process, to ensure the reusability of the current signal value sequence from the module verification platform to the system verification platform, the interface and the chip under test can be connected using macros.

[0041] S104. Compare the current signal value sequence and the expected signal value sequence of each detected signal to determine the target detection result of the chip to be detected.

[0042] In this embodiment, the target detection result can be either a successful or failed detection of the chip to be detected.

[0043] Specifically, there are two ways to determine the target detection result of the chip under test by comparing the current signal value sequence and the expected signal value sequence of each detected signal. One method is to compare the current signal value sequence and the expected signal value sequence of all detected signals of the chip under test one by one. If the current signal value sequence and the expected signal value sequence are exactly the same, the target detection result of the chip under test is considered successful; if they are not exactly the same, the target detection result is considered unsuccessful. The other method is to compare the duty cycle, frequency value, or level value of the current signal value sequence and the expected signal value sequence of each detected signal. If they are exactly the same, the target detection result of the chip under test is considered successful; if they are not exactly the same, the target detection result is considered unsuccessful.

[0044] The technical solution of this invention dynamically acquires the excitation signal value sequence of the chip under test according to the scenario requirements, updates the reference model according to the excitation signal value sequence, wherein the reference model includes the expected signal value sequence of at least one detected signal corresponding to the chip under test, acquires the current signal value sequence of at least one detected signal output by the chip under test according to the excitation signal value sequence, compares the current signal value sequence and the expected signal value sequence of each detected signal, and determines the target detection result of the chip under test. This solves the problem that the static detection method for the clock and reset signals of the chip in the prior art cannot detect dynamically changing clock and reset signals in real time, and achieves the beneficial effect of being able to detect dynamically changing clock and reset signals in real time.

[0045] Optionally, the current signal value sequence and the expected signal value sequence of each detected signal are compared to determine the target detection result of the chip to be detected, including:

[0046] If at least one of the detected signals has a different signal value at a corresponding position in the current signal value sequence and the expected signal value sequence, the target detection result will be determined as a detection failure.

[0047] In this embodiment, both the current signal value sequence and the expected signal value sequence of the detected signal can be periodic signals. For example, the signal value at the corresponding position in the current signal value sequence and the expected signal value sequence can be the signal value in the nth period of the same period in the current signal value sequence and the expected signal value sequence. For example, it can be the signal value in the 5th period in the current signal value sequence and the expected signal value sequence.

[0048] It should be noted that detection failure can occur when the current signal value sequence of the detected signal is different from the expected signal value sequence, in which case the target detection result can be determined as a detection failure.

[0049] Specifically, there can be multiple signals to be detected for the chip under test. If the signal value at the corresponding position in the current signal value sequence and the expected signal value sequence of at least one of the detected signals is different, the target detection result of the chip under test will be determined as a detection failure.

[0050] Optionally, the current signal value sequence and the expected signal value sequence of each detected signal are compared to determine the target detection result of the chip to be detected, including:

[0051] Obtain the first identification information carried by the chip to be tested.

[0052] In this embodiment, the first identification information carried by the chip to be tested may be identifying information such as the name, model and version of the chip to be tested.

[0053] Specifically, obtain the identification information such as the name, model, and version of the chip to be tested.

[0054] Based on the first identification information carried by the chip under test, obtain the second identification information carried by at least one detected signal of the chip under test.

[0055] The second identification information carried by the detected signal can be identification information such as the name and ID number of the detected signal.

[0056] In this embodiment, the detected signals of the chip under test can include two types: detected clock signals and detected reset signals. The number of detected clock signals can be at least one, and the number of detected reset signals can also be at least one. Therefore, it is necessary to distinguish the detected signals of the chip under test. Specifically, second identification information carried by at least one detected signal of the chip under test is obtained based on the first identification information carried by the chip under test. For example, the second identification information carried by the detected clock signals can be: clk1 for detected clock signal 1, clk2 for detected clock signal 2, clkn for detected clock signal n, etc.; the second identification information carried by the detected reset signals can be: reset1 for detected reset signal 1, reset2 for detected reset signal 2, resetn for detected reset signal n, etc.

[0057] The current signal value sequence and the expected signal value sequence of each detected signal are compared. If there is at least one first detected signal whose detection result is a failure, the target index table is queried according to the second identification information carried by the first detected signal to obtain the first identification information carried by the chip to be detected corresponding to the first detected signal.

[0058] It should be explained that the first detected signal can be a detected signal that indicates a detection failure. Specifically, the first detected signal can be a detected clock signal or a detected reset signal.

[0059] It should be noted that the target index table can be a directory-like index table that stores the correspondence between the first identification information carried by the chip under test and the second identification information carried by at least one detected signal.

[0060] At the start of the detection, the expected signal value sequence of each clock signal and the expected signal value sequence of each reset signal are determined based on the second identification information carried by the clock signal and the reset signal corresponding to the chip under test. The current signal value sequence of each clock signal and the current signal value sequence of each reset signal are then obtained. The current signal value sequence of each clock signal and the expected signal value sequence of each clock signal are compared, and the current signal value sequence of each reset signal is compared with the expected signal value sequence to determine the target detection result. Specifically, the current signal value sequence and the expected signal value sequence of each type of signal are compared. If the detection result of a certain first signal is a detection failure, the target index table is queried based on the second identification information carried by that first signal to obtain the first identification information carried by the chip under test corresponding to that first signal.

[0061] The target detection result of the chip to be tested corresponding to the first identification information carried by the chip to be tested is determined as a detection failure.

[0062] Specifically, the target detection result of the chip to be detected corresponding to the first identification information carried by the chip to be detected, obtained by querying the target index table based on the second identification information carried by the first detected signal, is determined as a detection failure.

[0063] Optionally, before comparing the current signal value sequence and the expected signal value sequence of each detected signal, and if there is at least one first detected signal whose detection result is a detection failure, the method further includes: querying the target index table based on the second identification information carried by the first detected signal to obtain the first identification information carried by the chip to be detected corresponding to the first detected signal.

[0064] The first identification information carried by the chip to be detected and at least one second identification information carried by the detected signal are encoded according to the preset encoding rules to obtain the encoding result.

[0065] In this embodiment, the preset encoding rule can be a rule set by the user according to the actual situation to encode the first identification information carried by the chip under test and the second identification information carried by at least one detected signal. The encoding operation can be an operation that establishes an association between the first identification information carried by the chip under test and the second identification information carried by at least one detected signal, and the encoding result can be an association between the first identification information carried by the chip under test and the second identification information carried by at least one detected signal.

[0066] Specifically, the first identification information carried by the chip to be detected and the second identification information carried by at least one detected signal are uniformly encoded according to a preset encoding rule to obtain the encoding result. For example, the first identification information carried by the chip to be detected, the second identification information carried by the detected clock signal, and the second identification information carried by the detected reset signal can be uniformly encoded according to the preset encoding rule.

[0067] A target index table is generated based on the first identification information carried by the chip to be tested, the second identification information carried by at least one detected signal, and the encoding result.

[0068] Specifically, a target index table can be generated based on the first identification information carried by the chip under test, the second identification information carried by the clock signal under test, the second identification information carried by the reset signal under test, and the encoding result. When it is necessary to test a certain clock signal or a certain reset signal under test, the second identification information carried by the clock signal or the reset signal under test can be obtained through the target index table. When the detection of a certain clock signal or a certain reset signal under test fails, the identification information of the DUT (Design Under Test, which in this embodiment can be the chip under test) can be efficiently located according to the preset encoding rules and the target index table.

[0069] The technical solution of this invention dynamically acquires the excitation signal value sequence of the chip under test according to the scenario requirements, updates the reference model according to the excitation signal value sequence, wherein the reference model includes the expected signal value sequence of at least one detected signal corresponding to the chip under test, acquires the current signal value sequence of at least one detected signal output by the chip under test according to the excitation signal value sequence, compares the current signal value sequence of each detected signal with the expected signal value sequence, and if the signal values ​​at corresponding positions in the current signal value sequence and the expected signal value sequence of at least one detected signal are different, the target detection result is determined as a detection failure. This solves the problem that the static detection method for the clock and reset signals of the chip in the prior art cannot detect dynamically changing clock and reset signals in real time, and achieves the beneficial effect of being able to detect dynamically changing clock and reset signals in real time.

[0070] Example 2

[0071] Figure 2 This is a flowchart of another chip detection method according to Embodiment 2 of the present invention. This embodiment is another way to determine the target detection result of the chip under test by comparing the current signal value sequence and the expected signal value sequence of each detected signal in the above embodiments. In this embodiment, the detected signals include: a detected clock signal and a detected reset signal. Figure 2 As shown, the method includes:

[0072] S201. Dynamically acquire the excitation signal value sequence of the chip to be tested according to the scenario requirements.

[0073] S202. Update the reference model based on the excitation signal value sequence.

[0074] The reference model includes a sequence of expected signal values ​​for at least one detected signal corresponding to the chip under test.

[0075] The signals being detected include: the clock signal being detected and the reset signal being detected.

[0076] S203. Obtain the current signal value sequence of at least one detected signal output by the chip under test based on the excitation signal value sequence.

[0077] The signals being detected include: the clock signal being detected and the reset signal being detected.

[0078] S204. Determine the expected duty cycle of the clock signal being detected, the expected frequency value of the clock signal being detected, and the expected level value of the reset signal being detected based on the expected signal value sequence.

[0079] It is known that a clock signal can have attributes such as duty cycle and frequency. The duty cycle refers to the proportion of high-level time relative to the total time within a pulse cycle. In this embodiment, the desired duty cycle can be the duty cycle of the clock signal to be output by the chip under test, determined based on the sequence of excitation signal values ​​input to the chip under test. The desired frequency value can be the frequency value of the clock signal to be output by the chip under test, determined based on the sequence of excitation signal values ​​input to the chip under test.

[0080] The desired level value can be the level value of the reset signal to be output by the chip under test, which is determined based on the sequence of excitation signal values ​​input to the chip under test.

[0081] Specifically, the expected signal value sequence of the clock signal to be detected and the expected signal value sequence of the reset signal to be detected are determined according to the excitation signal value sequence. The expected duty cycle and expected frequency of the clock signal to be detected are determined according to the expected signal value sequence of the clock signal to be detected. The expected level value of the reset signal to be detected is determined according to the expected signal value sequence of the reset signal to be detected.

[0082] S205. Determine the duty cycle of the clock signal being detected, the frequency value of the clock signal being detected, and the level value of the reset signal being detected based on the current signal value sequence.

[0083] In this embodiment, the duty cycle of the detected clock signal can be the duty cycle of the detected clock signal actually output by the chip under test according to the excitation signal value sequence input to the chip under test, the frequency value of the detected clock signal can be the frequency value of the detected clock signal actually output by the chip under test according to the excitation signal value sequence input to the chip under test, and the level value of the detected reset signal can be the level value of the detected reset signal actually output by the chip under test according to the excitation signal value sequence input to the chip under test.

[0084] Specifically, the current signal value sequence of the clock signal to be tested and the current signal value sequence of the reset signal to be tested corresponding to the chip under test are determined based on the excitation signal value sequence. The duty cycle and frequency value of the clock signal to be tested are determined based on the current signal value sequence of the clock signal to be tested. The level value of the reset signal to be tested is determined based on the current signal value sequence of the reset signal to be tested.

[0085] S206. Determine the first result based on the expected duty cycle of the clock signal being detected and the duty cycle of the clock signal being detected.

[0086] It should be noted that the first result can be whether the expected duty cycle of the clock signal being detected is the same as the duty cycle of the clock signal being detected, that is, whether the detection result is successful or unsuccessful.

[0087] Specifically, the expected duty cycle of the clock signal to be detected is compared with the duty cycle of the clock signal to be detected to determine the first result.

[0088] S207. Determine the second result based on the expected frequency value of the detected clock signal and the frequency value of the detected clock signal.

[0089] It should be explained that the second result can be whether the expected frequency value of the detected clock signal and the frequency value of the detected clock signal are the same, that is, the detection result is the result of successful detection or failure detection.

[0090] Specifically, the expected frequency value of the clock signal to be detected is compared with the frequency value of the clock signal to be detected to determine the second result.

[0091] S208. Determine the third result based on the expected level value of the detected reset signal and the level value of the detected reset signal.

[0092] The third result can be whether the expected level value of the detected reset signal and the level value of the detected reset signal are the same, that is, whether the detection result is successful or unsuccessful.

[0093] Specifically, the expected level value of the reset signal to be detected is compared with the level value of the reset signal to be detected to determine the third result.

[0094] S209. Determine the target detection result based on the first result, the second result, and the third result.

[0095] Specifically, if the first result, the second result, and the third result are all successful, then the target detection result is determined to be successful; if at least one of the first result, the second result, or the third result is failed, then the target detection result is determined to be failed.

[0096] In actual operation, when a detection failure is detected for a certain clock signal or a certain reset signal, the target index table can be queried according to the second identification information carried by the clock signal or the reset signal to obtain the first identification information carried by the chip to be tested corresponding to the clock signal or the reset signal, and the target detection result of the chip to be tested corresponding to the first identification information carried by the chip to be tested is determined as a detection failure.

[0097] The technical solution of this invention dynamically acquires the excitation signal value sequence of the chip under test according to scenario requirements, and updates the reference model based on the excitation signal value sequence. The reference model includes the expected signal value sequence of the clock signal to be tested and the expected signal value sequence of the reset signal to be tested corresponding to the chip under test. The current signal value sequence of the clock signal to be tested and the current signal value sequence of the reset signal to be tested, output by the chip under test according to the excitation signal value sequence, are obtained. The expected duty cycle, expected frequency, and expected level of the clock signal to be tested are determined based on the expected signal value sequence. The duty cycle of the clock signal to be tested is determined based on the current signal value sequence. The method compares the frequency value of the clock signal being detected with the level value of the reset signal being detected. Based on the expected duty cycle and the actual duty cycle of the clock signal being detected, a first result is determined. Based on the expected frequency value and the actual frequency value of the clock signal being detected, a second result is determined. Based on the expected level value and the actual level value of the reset signal being detected, a third result is determined. The target detection result is then determined based on the first, second, and third results. This method solves the problem in existing static detection methods for chip clock and reset signals that cannot detect dynamically changing clock and reset signals in real time, achieving the beneficial effect of real-time detection of dynamically changing clock and reset signals.

[0098] Example 3

[0099] Figure 3 This is a schematic diagram of a chip detection device according to Embodiment 3 of the present invention. Figure 3 As shown, the device includes: a first acquisition module 301, an update module 302, a second acquisition module 303, and a first determination module 304.

[0100] The first acquisition module 301 is used to dynamically acquire the excitation signal value sequence of the chip to be tested according to the scenario requirements.

[0101] The update module 302 is used to update the reference model according to the excitation signal value sequence, wherein the reference model includes the expected signal value sequence of at least one detected signal corresponding to the chip under test;

[0102] The second acquisition module 303 is used to acquire the current signal value sequence of at least one detected signal output by the chip under test according to the excitation signal value sequence;

[0103] The first determining module 304 is used to compare the current signal value sequence of each detected signal with the expected signal value sequence to determine the target detection result of the chip to be detected.

[0104] Optionally, the detection platform is connected to the detected signal of the chip under test through a parameterizable standardized interface.

[0105] Optionally, the first determining module 304 includes:

[0106] The first determining unit is configured to determine the target detection result as a detection failure if the signal values ​​at corresponding positions in the current signal value sequence of at least one detected signal are not the same as those in the expected signal value sequence.

[0107] Optionally, the first determining module 304 includes:

[0108] The first acquisition unit is used to acquire the first identification information carried by the chip to be detected;

[0109] The second acquisition unit is used to acquire at least one second identification information carried by a detected signal of the chip under test based on the first identification information carried by the chip under test.

[0110] The query unit is used to compare the current signal value sequence of each detected signal with the expected signal value sequence. If there is at least one first detected signal whose detection result is a detection failure, the target index table is queried according to the second identification information carried by the first detected signal to obtain the first identification information carried by the chip to be detected corresponding to the first detected signal.

[0111] The second determining unit is used to determine the target detection result of the chip to be detected corresponding to the first identification information carried by the chip to be detected as a detection failure.

[0112] Optionally, the first determining module 304 further includes:

[0113] The encoding unit is used to compare the current signal value sequence of each detected signal with the expected signal value sequence. If there is at least one first detected signal whose detection result is a detection failure, the unit queries the target index table based on the second identification information carried by the first detected signal to obtain the first identification information carried by the chip to be detected corresponding to the first detected signal. Before this, the unit encodes the first identification information carried by the chip to be detected and the second identification information carried by the at least one detected signal according to a preset encoding rule to obtain the encoding result.

[0114] The generation unit is used to generate a target index table based on the first identification information carried by the chip to be detected, the second identification information carried by the at least one detected signal, and the encoding result.

[0115] Optionally, the detected signal includes: a detected clock signal and a detected reset signal;

[0116] Accordingly, the chip detection device further includes:

[0117] The second determining module is used to determine the expected duty cycle of the detected clock signal, the expected frequency value of the detected clock signal, and the expected level value of the detected reset signal based on the expected signal value sequence after obtaining the current signal value sequence of at least one detected signal corresponding to the chip to be detected.

[0118] The third determining module is used to determine the duty cycle of the clock signal being detected, the frequency value of the clock signal being detected, and the level value of the reset signal being detected based on the current signal value sequence of at least one detected signal corresponding to the chip to be detected after acquiring the current signal value sequence.

[0119] Optionally, the first determining module 304 includes:

[0120] The third determining unit is used to determine a first result based on the expected duty cycle of the detected clock signal and the duty cycle of the detected clock signal;

[0121] The fourth determining unit is used to determine a second result based on the expected frequency value of the detected clock signal and the frequency value of the detected clock signal;

[0122] The fifth determining unit is used to determine a third result based on the expected level value of the detected reset signal and the level value of the detected reset signal;

[0123] The sixth determining unit is used to determine the target detection result based on the first result, the second result, and the third result.

[0124] The chip testing device provided in this embodiment of the invention can execute the chip testing method provided in any embodiment of the invention, and has the corresponding functional modules and beneficial effects of executing the method.

[0125] Example 4

[0126] Figure 4 A schematic diagram of an electronic device 40 that can be used to implement embodiments of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0127] like Figure 4 As shown, the electronic device 40 includes at least one processor 41 and a memory, such as a read-only memory (ROM) 42 or a random access memory (RAM) 43, communicatively connected to the at least one processor 41. The memory stores computer programs executable by the at least one processor. The processor 41 can perform various appropriate actions and processes based on the computer program stored in the ROM 42 or loaded into the RAM 43 from storage unit 48. The RAM 43 may also store various programs and data required for the operation of the electronic device 40. The processor 41, ROM 42, and RAM 43 are interconnected via a bus 44. An input / output (I / O) interface 45 is also connected to the bus 44.

[0128] Multiple components in electronic device 40 are connected to I / O interface 45, including: input unit 46, such as keyboard, mouse, etc.; output unit 47, such as various types of monitors, speakers, etc.; storage unit 48, such as disk, optical disk, etc.; and communication unit 49, such as network card, modem, wireless transceiver, etc. Communication unit 49 allows electronic device 40 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0129] Processor 41 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 41 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 41 performs the various methods and processes described above, such as chip detection methods:

[0130] Based on the requirements of the scenario, dynamically acquire the excitation signal value sequence of the chip to be tested;

[0131] The reference model is updated according to the excitation signal value sequence, wherein the reference model includes the expected signal value sequence of at least one detected signal corresponding to the chip under test;

[0132] Obtain the current signal value sequence of at least one detected signal output by the chip under test according to the excitation signal value sequence;

[0133] The current signal value sequence of each detected signal is compared with the expected signal value sequence to determine the target detection result of the chip to be detected.

[0134] In some embodiments, the chip detection method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 48. In some embodiments, part or all of the computer program may be loaded and / or installed on electronic device 40 via ROM 42 and / or communication unit 49. When the computer program is loaded into RAM 43 and executed by processor 41, one or more steps of the chip detection method described above may be performed. Alternatively, in other embodiments, processor 41 may be configured to perform the chip detection method by any other suitable means (e.g., by means of firmware).

[0135] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0136] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0137] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0138] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0139] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or computing systems that include middleware components (e.g., application servers), or computing systems that include frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0140] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0141] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0142] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A chip detection method, characterized in that, The chip testing method, applied to a testing platform, includes: Based on the requirements of the scenario, dynamically acquire the excitation signal value sequence of the chip to be tested; The reference model is updated according to the excitation signal value sequence, wherein the reference model includes the expected signal value sequence of at least one detected signal corresponding to the chip under test; Obtain the current signal value sequence of at least one detected signal output by the chip under test according to the excitation signal value sequence; The current signal value sequence of each detected signal is compared with the expected signal value sequence to determine the target detection result of the chip to be detected; The process involves comparing the current signal value sequence of each detected signal with the expected signal value sequence to determine the target detection result of the chip to be detected, including: Obtain the first identification information carried by the chip to be tested; Based on the first identification information carried by the chip under test, obtain the second identification information carried by at least one detected signal of the chip under test; The current signal value sequence of each detected signal is compared with the expected signal value sequence. If there is at least one first detected signal whose detection result is a detection failure, the target index table is queried according to the second identification information carried by the first detected signal to obtain the first identification information carried by the chip to be detected corresponding to the first detected signal. The target detection result of the chip to be tested corresponding to the first identification information carried by the chip to be tested is determined as a detection failure.

2. The method according to claim 1, characterized in that, The detection platform is connected to the detected signal of the chip under test through a parameterizable standardized interface.

3. The method according to claim 1, characterized in that, The current signal value sequence of each detected signal is compared with the expected signal value sequence to determine the target detection result of the chip to be detected, including: If at least one of the current signal value sequences of the detected signal is different from the corresponding signal value in the expected signal value sequence, the target detection result is determined to be a detection failure.

4. The method according to claim 1, characterized in that, Before comparing the current signal value sequence of each detected signal with the expected signal value sequence, and if there is at least one first detected signal whose detection result is a detection failure, the method further includes: querying the target index table based on the second identification information carried by the first detected signal to obtain the first identification information carried by the chip to be detected corresponding to the first detected signal. The first identification information carried by the chip to be detected and the second identification information carried by the at least one detected signal are encoded according to a preset encoding rule to obtain the encoding result; A target index table is generated based on the first identification information carried by the chip to be detected, the second identification information carried by the at least one detected signal, and the encoding result.

5. The method according to claim 1, characterized in that, The detected signal includes: a detected clock signal and a detected reset signal; Accordingly, after obtaining the current signal value sequence of at least one detected signal corresponding to the chip under test, the method further includes: The expected duty cycle of the detected clock signal, the expected frequency value of the detected clock signal, and the expected level value of the detected reset signal are determined based on the expected signal value sequence. The duty cycle of the detected clock signal, the frequency value of the detected clock signal, and the level value of the detected reset signal are determined based on the current signal value sequence.

6. The method according to claim 5, characterized in that, The current signal value sequence of each detected signal is compared with the expected signal value sequence to determine the target detection result of the chip to be detected, including: A first result is determined based on the expected duty cycle of the detected clock signal and the duty cycle of the detected clock signal; The second result is determined based on the expected frequency value of the detected clock signal and the frequency value of the detected clock signal; The third result is determined based on the expected level value of the detected reset signal and the level value of the detected reset signal; The target detection result is determined based on the first result, the second result, and the third result.

7. A chip detection device, characterized in that, include: The first acquisition module is used to dynamically acquire the excitation signal value sequence of the chip to be tested according to the scenario requirements; An update module is used to update a reference model, wherein the reference model includes a sequence of expected signal values ​​for at least one detected signal corresponding to the chip under test; The second acquisition module is used to acquire the current signal value sequence of at least one detected signal output by the chip under test according to the excitation signal value sequence; The first determining module is used to compare the current signal value sequence of each detected signal with the expected signal value sequence to determine the target detection result of the chip to be detected; The first determining module includes: The first acquisition unit is used to acquire the first identification information carried by the chip to be detected; The second acquisition unit is used to acquire at least one second identification information carried by a detected signal of the chip under test based on the first identification information carried by the chip under test. The query unit is used to compare the current signal value sequence of each detected signal with the expected signal value sequence. If there is at least one first detected signal whose detection result is a detection failure, the target index table is queried according to the second identification information carried by the first detected signal to obtain the first identification information carried by the chip to be detected corresponding to the first detected signal. The second determining unit is used to determine the target detection result of the chip to be detected corresponding to the first identification information carried by the chip to be detected as a detection failure.

8. An electronic device, characterized in that, The electronic device includes: At least one processor; and A memory communicatively connected to the at least one processor; wherein, The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the chip detection method according to any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that are used to cause a processor to execute the chip detection method according to any one of claims 1-6.

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