Reference power generator and circuit system

Abstract

The present invention provides a reference power generator and circuit system, which has a current mirror unit and a current mode temperature compensation unit. The current mirror unit is used to generate a first current, a first sum current and a second sum current flowing out of its first to third terminals, wherein the first current, the first sum current and the second sum current are multiples of each other. The current mode temperature compensation unit is electrically connected to the second and third terminals of the current mirror unit, and is used to make the first sum current generated by the current mirror unit a sum current of a current proportional to the absolute temperature and a current complementary to the absolute temperature when the voltages of the second and third terminals are the same. The first terminal of the current mirror unit is the output terminal of the reference power generator, so as to output the first current as a reference current. The reference current output by the embodiment of the present invention is not affected by temperature, and the reference voltage generated by the reference current is also not affected by temperature.

Description

Technical Field

[0001] The present invention relates to a reference power generator, and in particular to a reference power generator that is not affected by temperature variation and a circuit system using the reference power generator. Background Art

[0002] Most of the known reference voltage generators use a bandgap reference circuit to generate a bandgap reference voltage (V BG ). Due to the characteristics of the bandgap reference circuit, the range of the bandgap reference voltage is limited. When a higher reference voltage is required, the bandgap reference voltage is output through an additional operational amplifier, and then the required reference voltage is generated based on the output bandgap reference voltage through a voltage divider resistor string. However, operational amplifiers are not only very power-consuming, but also require a considerable chip area when implemented.

[0003] In low voltage circuit systems, although a higher reference voltage is not required (the bandgap reference voltage (V BG ), the bandgap reference voltage (V BG ) as the output reference voltage), but the reference voltage output by the known reference voltage generator may change due to temperature changes and power supply changes. Therefore, in response to this technical problem, some technicians in this field provide a feedback circuit, so that the feedback circuit generates a corresponding control signal according to the output reference voltage change to control the switching of the switch in the reference voltage generator to suppress the influence of temperature changes and power supply changes on the output reference voltage. However, this approach senses the output reference voltage to generate a feedback signal, and requires the setting of a comparator and a switch, which will reduce the operating bandwidth and operating speed, and increase the chip area and power consumption. Summary of the invention

[0004] According to the purpose of the present invention, an embodiment of the present invention proposes a reference power generator, which has a current mirror unit and a current mode temperature compensation unit. The current mirror unit has first to third terminals, and the current mirror unit is used to receive a supply voltage and to generate a first current, a first sum current and a second sum current flowing out of the first to third terminals, wherein the first current, the first sum current and the second sum current are multiples of each other. The current mode temperature compensation unit includes a bandgap circuit based on BJT and a first impedance circuit. The bandgap circuit based on BJT includes a first circuit and a second circuit. The two ends of the first circuit and the second circuit are electrically connected to the second terminal and the third terminal of the current mirror unit respectively. The first impedance circuit is electrically connected to the second terminal of the current mirror unit and is connected in parallel to the first circuit, wherein the connection point of the first impedance circuit and the first circuit receives the first sum current, and the two ends of the first circuit and the second circuit electrically connected to the second terminal and the third terminal of the current mirror unit are biased by the first voltage and the second voltage respectively. When the first voltage is the same as the second voltage, the first circuit generates a second current and the first impedance circuit generates a third current, wherein the second current is a current proportional to absolute temperature (PTAT) and the third current is a current complementary to absolute temperature (CTAT). The first terminal of the current mirror unit is the output terminal of the reference power generator, so as to output the first current as a reference current.

[0005] According to the above-mentioned reference power generator, the reference power generator further includes an impedance component, and the impedance component is electrically connected to the first terminal of the current mirror unit for receiving the first current to generate a reference voltage.

[0006] According to the above-mentioned reference power generator, the current mirror unit includes first to ninth transistors, wherein the sources of the first to fifth transistors are all used to receive the supply voltage, the gate of the third transistor is electrically connected to the gates of the fourth and fifth transistors and the drain of the first transistor, the gate of the second transistor is electrically connected to the gate of the first transistor and the drain of the second transistor, the drain of the eighth transistor is electrically connected to the drain of the third transistor, the gates of the seventh and eighth transistors, the drain of the sixth transistor is electrically connected to the drain of the first transistor, the drain of the ninth transistor is electrically connected to the drain of the fourth transistor, the gates of the ninth and sixth transistors, the drain of the seventh transistor is electrically connected to the drain of the second transistor, the sources of the sixth and eighth transistors are electrically connected to the second terminal of the current mirror unit, the sources of the seventh and ninth transistors are electrically connected to the third terminal of the current mirror unit, and the drain of the fifth transistor is electrically connected to the first terminal of the current mirror unit.

[0007] According to the reference power generator, the first to fifth transistors are P-type MOS transistors, and the sixth to ninth transistors are N-type MMOS transistors.

[0008] According to the above-mentioned reference power generator, the first circuit includes a tenth transistor and a first impedance component, the first impedance circuit includes a second impedance component, and the second circuit includes an eleventh transistor, the first end and the second end of the second impedance component are respectively electrically connected to the second end of the current mirror unit and the ground voltage, the base and the collector of the tenth transistor are electrically connected to the ground voltage, the first end and the second end of the first impedance component are respectively electrically connected to the second end of the current mirror unit and the emitter of the tenth transistor, the base and the collector of the eleventh transistor are electrically connected to the ground voltage, and the emitter of the eleventh transistor is connected to the third end of the current mirror unit.

[0009] According to the reference power generator, the current mode temperature compensation unit further includes a second impedance circuit, and the first end and the second end of the second impedance circuit are electrically connected to the third end of the current mirror unit and the ground voltage respectively. The second impedance circuit is connected in parallel with the second circuit, and the connection point between the second impedance circuit and the second circuit receives the second sum current.

[0010] According to the above-mentioned reference power generator, the tenth and eleventh transistors are PNP-type BJT transistors.

[0011] According to the above-mentioned reference power generator, the current mirror unit further includes first to fourth native transistors, the drains of the first to fourth native transistors are electrically connected to the drains of the first to fourth transistors respectively, the sources of the first to fourth native transistors are electrically connected to the sources of the sixth to ninth transistors respectively, the gates of the first and fourth native transistors are electrically connected to the gate of the sixth transistor, and the gates of the second and third native transistors are electrically connected to the gate of the seventh transistor.

[0012] According to the above-mentioned reference power generator, the first to fourth native transistors are N-type native MOS transistors.

[0013] According to the purpose of the present invention, an embodiment of the present invention provides a circuit system, which includes any of the aforementioned reference power generators and a load, wherein the load is electrically connected to an output end of the reference power generator.

[0014] In summary, the embodiments of the present invention provide a reference power generator that is not affected by temperature fluctuations. The reference current / voltage generated by the reference power generator is not affected by temperature fluctuations, that is, the reference current / voltage is a reference current / voltage with a zero temperature coefficient.

[0015] In order to further understand the technology, means and effects of the present invention, reference may be made to the following detailed description and accompanying drawings, so that the purpose, features and concepts of the present invention can be thoroughly and specifically understood. However, the following detailed description and accompanying drawings are only used for reference and explanation of the implementation of the present invention, and are not intended to limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The present invention can be more fully understood through the following detailed description of the embodiments in conjunction with the accompanying drawings, in which:

[0017] Figure 1 is a circuit diagram of a reference power generator according to an embodiment of the present invention;

[0018] Figure 2 is a circuit diagram of a current mode temperature compensation unit of a reference power generator according to an embodiment of the present invention;

[0019] Figure 3 is a circuit diagram of a reference power generator according to another embodiment of the present invention; and

[0020] Figure 4 FIG. 4 is a circuit diagram of a reference power generator according to another embodiment of the present invention.

[0021] The symbols indicated in the figure are explained as follows: 1, 2, 2' reference power generator; 11, 21, 21' current mirror unit; 12, 12', 22, 22' current mode temperature compensation unit; Mp1~Mp4, Mn1~Mn4, Q1, Q2 transistors; Mna1~Mna4 native transistors; R1~R4 impedance components; AVDD supply voltage; I1~I5 currents; Vx, Vy, VBG, VBN1, VBN2 voltages. DETAILED DESCRIPTION

[0022] Reference will now be made in detail to exemplary embodiments of the present invention, which are illustrated in the accompanying drawings. Where possible, the same component symbols are used in the drawings and the specification to refer to the same or similar components. In addition, the exemplary embodiments are only one of the implementations of the design concept of the present invention, and the following one or more exemplary embodiments are not intended to limit the present invention.

[0023] The embodiment of the present invention provides a reference power generator that is not affected by temperature changes. The reference power generator does not have a feedback circuit for sensing the reference voltage output, and does not need to set up an additional operational amplifier and switch, so it can solve the technical problems encountered in the above-mentioned prior art. The reference power generator of the embodiment of the present invention may include a reference current generator and a reference voltage generator, wherein the reference power generator determines to generate a reference current or a reference voltage according to whether there is an impedance element hanging on the output. The reference power generator of the embodiment of the present invention directly connects a current mirror unit and a current mode temperature compensation unit in cascode, and the design makes the voltages of the two terminals connected to the current mirror unit and the current mode temperature compensation unit the same, so that at least one of the two currents flowing through the two terminals connected to the current mirror unit and the current mode temperature compensation unit is the sum of a positive temperature coefficient current and a negative temperature coefficient current, wherein the positive temperature coefficient current is a current proportional to absolute temperature (PTAT), and the negative temperature coefficient current is a current complementary to absolute temperature (CTAT). Thus, the reference current output by the current mirror unit is a current that is independent of temperature (i.e., a current with a zero temperature coefficient). In addition, the voltage on the impedance element at the output end of the reference power generator is the product of the reference current and the resistance value of the impedance element, so this voltage can be used as a reference voltage that is independent of temperature. In addition, in one embodiment of the present invention, the current mirror unit is designed with a plurality of native transistors that are respectively located on the current flow path of the two terminals connected to the current mirror unit and the current mode temperature compensation unit, so as to reduce the influence of the supply power variation on the output reference current / voltage.

[0024] First, please refer to the present invention Figure 1 , Figure 1 1 is a circuit diagram of a reference power generator according to an embodiment of the present invention. The reference power generator 1 includes a current mirror unit 11, a current mode temperature compensation unit 12 and an impedance element R4. The current mirror unit 11 is used to receive a supply voltage AVDD and has first to third terminals corresponding to the voltages VBG, Vx and Vy, and is used to generate currents flowing out of the first to third terminals, wherein the current I5 flowing out of the first terminal, the sum current (I1+I2) flowing out of the second terminal and the sum current (I3+I4) flowing out of the third terminal are multiples of each other, such as 1:K:1, where K is any number greater than 0. The current mode temperature compensation unit 12 is electrically connected to the current mirror unit 11 through the second terminal and the third terminal, and is electrically connected in a stacked manner, so that the current mirror unit 11 is electrically connected to a low voltage, such as a ground voltage, through the current mode temperature compensation unit 12.

[0025] When the voltage Vx is equal to Vy, the current I1 and I2 generated by the current mode temperature compensation unit 12 flowing through itself at the second terminal will be a negative temperature coefficient current and a positive temperature coefficient current respectively, and through appropriate design, the total current (I1+I2) flowing out of the second terminal can be made into a zero temperature coefficient current. Because the current I5 flowing out of the first terminal, the total current (I1+I2) flowing out of the second terminal and the total current (I3+I4) flowing out of the third terminal are multiples of each other, therefore, the total current I3 and I4 generated by the current mode temperature compensation unit 12 flowing through itself at the third terminal will also be a zero temperature coefficient current, and the current I5 output by the current mirror unit 11 at the first terminal will also be a zero temperature coefficient current.

[0026] The two ends of the impedance component R4 are electrically connected between the first terminal and the low voltage, the first terminal serves as the output terminal of the reference power generator 1, the current I5 serves as the reference current output by the reference power generator 1, and the voltage VBG generated by the current I5 through the impedance component R4 serves as the reference voltage output by the reference power generator 1. In this way, the reference current and the reference voltage output by the reference power generator 1 are respectively the reference current and the reference voltage with zero temperature coefficient, so as to achieve the purpose that the reference current and the reference voltage are not affected by temperature changes. In addition, the impedance component R4 is a resistor in this embodiment, but the present invention is not limited to the type of the impedance component R4.

[0027] Further, the implementation of the current mirror unit 11 can be described as follows, but the present invention is not limited to the implementation of the current mirror unit 11. The current mirror unit 11 includes transistors Mp1-Mp5 and Mn1-Mn4, wherein the transistors Mp1-Mp5 are P-type MOS transistors, and the transistors Mn1-Mn4 are N-type MOS transistors. The sources of the transistors Mp1-Mp5 are all used to receive the supply voltage AVDD, the gate of the transistor Mp3 is electrically connected to the gates of the transistors Mp4 and Mp5 and the drain of the transistor Mp1, and the gate of the transistor Mp2 is electrically connected to the gate of the transistor Mp1 and the drain of the transistor Mp2. The drain of transistor Mn3 is electrically connected to the drain of transistor Mp3, the gates of transistors Mn3 and Mn2, the drain of transistor Mn1 is electrically connected to the drain of transistor Mp1, the drain of transistor Mn4 is electrically connected to the drain of transistor Mp4, the gates of transistors Mn4 and Mn1, and the drain of transistor Mn2 is electrically connected to the drain of transistor Mp2, wherein the electrical connection between the gates of transistors Mn1 to Mn4 presents a cross-coupled connection. The sources of transistors Mn1 and Mn3 are electrically connected to a second terminal, and a voltage Vx is generated at the second terminal, the sources of transistors Mn2 and Mn4 are electrically connected to a third terminal, and a voltage Vy is generated at the third terminal, and the drain of transistor Mp5 is electrically connected to a first terminal, and a voltage VBG is generated at the first terminal.

[0028] Further, the implementation of the current mode temperature compensation unit 12 can be described as follows, but the present invention is not limited to the implementation of the current mode temperature compensation unit 12. The current mode temperature compensation unit 12 includes transistors Q1, Q2 and impedance components R1~R3, wherein the transistors Q1 and Q2 are PNP type BJT transistors, and the impedance components R1~R3 ​​are resistors. The base and collector of the transistor Q1 are electrically connected to a low voltage, the emitter of the transistor Q2 is electrically connected to the third terminal of the current mirror unit 11, and the base and collector of the transistor Q2 are electrically connected to the low voltage. The first ends of the resistors R1 and R3 are electrically connected to the second terminal of the current mirror unit 11, the second end of the resistor R1 is electrically connected to the emitter of the transistor Q1, and the second end of the resistor R3 is electrically connected to the low voltage. The first end of the resistor R2 is electrically connected to the third terminal of the current mirror unit 11, and the second end of the resistor R2 is electrically connected to the low voltage.

[0029] Explained from another perspective, the current mode temperature compensation unit 12 includes a BJT-based bandgap circuit composed of transistors Q1, Q2 and an impedance component R3, a first impedance circuit composed of an impedance component R1 and a second impedance circuit composed of an impedance component R2. The BJT-based bandgap circuit includes a first circuit and a second circuit, the first circuit is composed of a transistor Q1 and an impedance component R3, and the second circuit is composed of a transistor Q2. The first circuit is connected in parallel with the first impedance circuit composed of the impedance component R1, and the connection point between the first circuit and the first impedance circuit composed of the impedance component R1 receives a first total current. The second circuit is connected in parallel with the second impedance circuit composed of the impedance component R2, and the connection point between the second circuit and the second impedance circuit composed of the impedance component R2 receives a second total current. Voltages Vx and Vy are used to bias the first and second circuits, and when the voltage Vx is equal to the voltage Vy, the current I1 generated by the first impedance circuit is a negative temperature coefficient current I that decreases as the temperature rises. CTAT The current I2 generated by the first circuit is a positive temperature coefficient current I that increases with the temperature rise. PTAT .

[0030] The current mode temperature compensation unit 12 is implemented in addition to Figure 1 In addition to the method, there are other methods. Please refer to Figure 2 , Figure 2 is a circuit diagram of a current mode temperature compensation unit of a reference power generator according to an embodiment of the present invention. Figure 1 The current mode temperature compensation unit 12, Figure 2 The current mode temperature compensation unit 12' lacks the impedance component R2, and the total current flowing out of the third terminal is I3. Figure 1 or Figure 2 When the voltage Vx is equal to the voltage VY, the current I1 = Vbe2 / R1, and the current I2 = (Vx-Vbe1) / R3 = (Vbe2-Vbe1) / R3 = V T lnK / R3, where Vbe1 and Vbe2 are the base-emitter voltages of transistors Q1 and Q2, respectively. T is the thermal voltage, and K is a constant. Therefore, the current I1 is a negative temperature coefficient current I that decreases as the temperature rises. CTAT , current I2 is a positive temperature coefficient current I that increases with temperature PTAT The total current flowing out of the second terminal of the current mirror unit 11 is I1+I2=I CTAT +I PTAT =V T lnK / R3+Vbe2 / R1=V T / R3(lnK+R3Vbe2 / V TR1). Therefore, through proper design, the total current flowing out of the second terminal of the current mirror unit 11 can be a zero temperature coefficient current. In addition, it should be noted that although the transistors Q1 and Q2 are described above using BJT transistors as an example, in other embodiments, the transistors Q1 and Q2 can be replaced by MOS transistors to achieve temperature compensation, and the present invention is not limited to the types of the transistors Q1 and Q2.

[0031] Please refer to Figure 3 , Figure 3 FIG. 4 is a circuit diagram of a reference power generator according to another embodiment of the present invention. Figure 3 The reference power generator 2 is substantially the same as Figure 1 The reference power generator 1 is approximated as follows: Figure 3 The current mode temperature compensation unit 22 and the impedance component R4 are the same as Figure 1 The current mode temperature compensation unit 12 and the impedance component R4 differ only in that Figure 3 The current mirror unit 21 has a plurality of additional native transistors Mna1-Mna4, wherein the native transistors Mna1-Mna4 are N-type native MOS transistors. The drains of the native transistors Mna1-Mna4 are electrically connected to the drains of the transistors Mp1-Mp4, respectively, and the sources of the native transistors Mna1-Mna4 are electrically connected to the sources of the transistors Mn1-Mn4, respectively. The gates of the native transistors Mna1 and Mna4 are electrically connected to the gate of the transistor Mn1 to receive the voltage VBN1 on the gate of the transistor Mn1, and the gates of the native transistors Mna2 and Mna3 are electrically connected to the gate of the transistor Mn2 to receive the voltage VBN2 on the gate of the transistor Mn2. The native transistors Mna1-Mna4 are stacked between the transistors Mp1-Mp4 and the transistors Mn1-Mn4, which can be used to reduce the influence of the supply voltage AVDD variation on the reference current / voltage generated by the reference power generator 2.

[0032] Please refer to Figure 4 , Figure 4 FIG. 4 is a circuit diagram of a reference power generator according to another embodiment of the present invention. Figure 4 The reference power generator 2' is substantially the same as Figure 3 The reference power generator 2 is similar, the difference is only Figure 4 The current mode temperature compensation unit 22' adopts Figure 2 The current mode temperature compensation unit 12', and compared with Figure 3, the current mirror unit 21' only has native transistors Mna1 and Mna2 (i.e., native transistors Mna3 and Mna4 are omitted), wherein native transistors Mna1 and Mna2 are N-type native MOS transistors. The drains of native transistors Mna1 and Mna2 are electrically connected to the drains of transistors Mp1 and Mp2, respectively, and the sources of native transistors Mna1 and Mna2 are electrically connected to the sources of transistors Mn1 and Mn2, respectively. The gate of native transistor Mna1 is electrically connected to the gate of transistor Mn2 to receive the voltage VBN2 on the gate of transistor Mn2, and the gate of native transistor Mna2 is electrically connected to the gate of transistor Mn1 to receive the voltage VBN1 on the gate of transistor Mn1. Native transistors Mna1 and Mna2 are stacked between transistors Mp2 and Mp4 and transistors Mn1 and Mn2, which can be used to reduce the influence of changes in supply voltage AVDD on the reference current / voltage generated by reference power generator 2'.

[0033] In addition, an embodiment of the present invention further provides a circuit system, which can be a low voltage circuit system, but the present invention is not limited thereto. The circuit system includes a reference power generator and a load according to any of the aforementioned embodiments and variations thereof, and the load is used to electrically connect to the output end of the reference power generator to receive the reference current and / or reference voltage output by the reference power generator, wherein the load can be various types of functional circuits, such as a memory unit, a controller unit, or a demodulator / modulator, etc., and the present invention is not limited to the type of load.

[0034] In summary, the embodiment of the present invention provides a reference power generator that is not affected by temperature fluctuations, which generates a sum current of a positive temperature coefficient current and a negative temperature coefficient current inside the generator, and mirrors the sum current as an output reference current, so that the output reference current is not affected by temperature, and the reference voltage generated by the reference current is also not affected by temperature. Compared with the prior art, the reference power generator of the embodiment of the present invention does not have a feedback circuit for sensing the output reference voltage, and does not need to set up additional operational amplifiers and switches, so there is no problem of reduced operating bandwidth and operating speed, and no problem of increased chip area and power consumption.

[0035] It should be understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in view thereof will be suggested to those skilled in the art and are to be included within the spirit and scope of the present application and the scope of the appended claims.

Claims

1. A reference power generator, characterized in that: The reference power generator comprises: a current mirror unit having a first terminal, a second terminal and a third terminal, receiving a supply voltage and used to generate a first current, a first sum current and a second sum current flowing out of the first terminal, the second terminal and the third terminal, wherein the first current, the first sum current and the second sum current are multiples of each other; and Current mode temperature compensation unit, including: A bandgap circuit based on a BJT, comprising a first circuit and a second circuit, wherein two ends of the first circuit and the second circuit are electrically connected to the second end point and the third end point of the current mirror unit respectively; and a first impedance circuit, electrically connected to the second terminal of the current mirror unit and connected in parallel to the first circuit, wherein a connection point between the first impedance circuit and the first circuit receives the first total current, the first circuit and the second circuit electrically connecting the second terminal and the third terminal of the current mirror unit are biased by a first voltage and a second voltage respectively, when the first voltage is the same as the second voltage, the first circuit generates a second current, and the first impedance circuit generates a third current, wherein the second current is a current proportional to the absolute temperature, and the third current is a current complementary to the absolute temperature; wherein the first terminal of the current mirror unit is an output terminal of the reference power generator, so as to output the first current as a reference current; The first circuit includes a tenth transistor and a first impedance component, the first impedance circuit includes a second impedance component, and the second circuit includes an eleventh transistor, the first end and the second end of the second impedance component are respectively electrically connected to the second end of the current mirror unit and a ground voltage, the base and the collector of the tenth transistor are electrically connected to the ground voltage, the first end and the second end of the first impedance component are respectively electrically connected to the second end of the current mirror unit and the emitter of the tenth transistor, the base and the collector of the eleventh transistor are electrically connected to the ground voltage, and the emitter of the eleventh transistor is connected to the third end of the current mirror unit.

2. The reference power generator as claimed in claim 1, wherein: The reference power generator further comprises: The impedance component is electrically connected to the first terminal of the current mirror unit and is used for receiving the first current to generate a reference voltage.

3. The reference power generator as claimed in claim 1, wherein: The current mirror unit includes first to ninth transistors, wherein sources of the first to fifth transistors are all used to receive the supply voltage, a gate of the third transistor is electrically connected to the gates of the fourth and fifth transistors and the drain of the first transistor, a gate of the second transistor is electrically connected to the gate of the first transistor and the drain of the second transistor, a drain of the eighth transistor is electrically connected to the drain of the third transistor and the gates of the seventh and eighth transistors, a drain of the sixth transistor is electrically connected to the drain of the first transistor, a drain of the ninth transistor is electrically connected to the drain of the fourth transistor and the gates of the ninth and sixth transistors, a drain of the seventh transistor is electrically connected to the drain of the second transistor, sources of the sixth and eighth transistors are electrically connected to the second terminal of the current mirror unit, sources of the seventh and ninth transistors are electrically connected to the third terminal of the current mirror unit, and a drain of the fifth transistor is electrically connected to the first terminal of the current mirror unit.

4. The reference power generator as claimed in claim 3, characterized in that: The first to fifth transistors are P-type MOS transistors, and the sixth to ninth transistors are N-type MOS transistors.

5. The reference power generator as claimed in claim 1, wherein: The current mode temperature compensation unit further includes a second impedance circuit, and the first end and the second end of the second impedance circuit are electrically connected to the third end of the current mirror unit and the ground voltage respectively, wherein the second impedance circuit is connected in parallel with the second circuit, and the connection point between the second impedance circuit and the second circuit receives the second total current.

6. The reference power generator as claimed in claim 1, wherein: The tenth and eleventh transistors are PNP-type BJT transistors.

7. The reference power generator as claimed in claim 3, wherein: The current mirror unit further includes first to fourth native transistors, the drains of the first to fourth native transistors are electrically connected to the drains of the first to fourth transistors, the sources of the first to fourth native transistors are electrically connected to the sources of the sixth to ninth transistors, the gates of the first and fourth native transistors are electrically connected to the gate of the sixth transistor, and the gates of the second and third native transistors are electrically connected to the gate of the seventh transistor.

8. The reference power generator as claimed in claim 7, characterized in that: The first to fourth native transistors are N-type native MOS transistors.

9. A circuit system, characterized in that: The circuit system comprises: The reference power generator according to any one of claims 1 to 8; and A load is electrically connected to the output terminal of the reference power generator.

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