Enable control circuit and semiconductor memory

Abstract

This application provides an enable control circuit and a semiconductor memory. The enable control circuit includes: a counting module for counting the current clock cycle and determining a clock cycle count value; a selection module for determining a clock cycle count target value based on a first setting signal; and a control module for controlling the ODT path to be in an enabled state and starting the counting module when the level state of the ODT pin signal flips; and controlling the ODT path to switch from an enabled state to a disabled state when the clock cycle count value reaches the clock cycle count target value and the level state of the ODT pin signal remains unchanged; and controlling the ODT path to remain in an enabled state when the clock cycle count value reaches the clock cycle count target value and the level state of the ODT pin signal flips again. This not only saves power but also solves the problem that the ODT path cannot be enabled when the ODT pin level flips a second time in some cases.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and more particularly to an enable control circuit and a semiconductor memory. Background Technology

[0002] With the continuous development of semiconductor technology, people have placed increasingly higher demands on data transmission speed when manufacturing and using devices such as computers. In order to obtain faster data transmission speeds, a series of devices such as memory that can transmit data at double data rate (DDR) have emerged.

[0003] In designs that enable double-data-rate transmission, specifications regarding on-die termination (ODT) are added. Simply put, the value of the termination resistance (RTT) can be switched, and the switching must follow a specific timing sequence. For example, the state of the ODT pin on the memory chip can control the value of the RTT.

[0004] However, current technologies cannot accurately control the enable state of the on-chip termination path (ODT Path), resulting in wasted current and increased power consumption. Furthermore, when the level of the ODT pin flips twice consecutively, in some cases, the ODT Path may fail to be enabled when the level of the second ODT pin flips. Summary of the Invention

[0005] This application provides an enable control circuit and a semiconductor memory, which can not only avoid current waste and achieve the purpose of saving power consumption, but also solve the problem that the enable of the ODT path cannot be turned on when the level of the second ODT pin is flipped in the related technology.

[0006] The technical solution of this application is implemented as follows:

[0007] In a first aspect, embodiments of this application provide an enable control circuit, which includes:

[0008] The counting module is used to count the current clock cycle and determine the clock cycle count value;

[0009] The selection module is used to determine the target value for clock cycle counting based on the first setting signal;

[0010] A control module, connected to the counting module and the selection module, is configured to: control the ODT path to be in an enabled state and start the counting module when the level state of the ODT pin signal flips; control the ODT path to change from the enabled state to the disabled state when the clock cycle count value reaches the clock cycle count target value and the level state of the ODT pin signal remains unchanged; and control the ODT path to remain in the enabled state when the clock cycle count value reaches the clock cycle count target value and the level state of the ODT pin signal flips again.

[0011] In some embodiments, the control module is further configured to, when the clock cycle count value has not reached the clock cycle count target value and the level state of the ODT pin signal flips again, control the ODT path to remain in the enabled state, control the counting module to be cleared, and restart the counting module; and when the clock cycle count value obtained by recounting reaches the clock cycle count target value, control the ODT path to change from the enabled state to the disabled state.

[0012] In some embodiments, the control module includes a first control submodule and a second control submodule; wherein,

[0013] The first control submodule is configured to generate a first intermediate signal based on the ODT pin signal; wherein the first intermediate signal includes: before the level state of the ODT pin signal flips, the first intermediate signal is at a first level; and within a preset time after the level state of the ODT pin signal flips, the first intermediate signal changes from the first level to a second level; and after the preset time, the first intermediate signal changes from the second level back to the first level.

[0014] The second control submodule is used to perform logical operations on the first intermediate signal to generate an ODT enable signal; wherein, the ODT enable signal includes: when the ODT enable signal is at a third level, controlling the ODT path to be in the enabled state; and when the ODT enable signal is at a fourth level, controlling the ODT path to be in the closed state.

[0015] In some embodiments, the first level is a high level, the second level is a low level, the third level is a high level, and the fourth level is a low level.

[0016] In some embodiments, the first control submodule includes a delay module and an XNOR gate module; wherein...

[0017] The delay module is used to delay the ODT pin signal by the preset time to obtain the ODT delayed signal;

[0018] The XOR gate module is used to perform an XOR operation on the ODT pin signal and the ODT delay signal to obtain the first intermediate signal.

[0019] In some embodiments, the control module further includes a two-input NOR gate; wherein,

[0020] The selection module is further configured to generate a target achievement signal, which indicates that the clock cycle count value has reached the clock cycle count target value.

[0021] The two-input NOR gate is used to perform NOR operation on the target achievement signal and the second setting signal to obtain a reset signal; wherein, the second setting signal is generated according to the setting of the mode register, and the second setting signal includes: when the second setting signal is at the fifth level, it indicates that the ODT function of the chip is turned off; when the second setting signal is at the sixth level, it indicates that the ODT function of the chip is turned on.

[0022] In some embodiments, the fifth level is a high level and the sixth level is a low level.

[0023] In some embodiments, the second control submodule includes a latch; wherein the latch is an SR type latch, and the SR type latch is composed of two two-input NAND gates.

[0024] In some embodiments, the first input terminal (S) of the latch is connected to the output terminal of the first control submodule for receiving the first intermediate signal; the second input terminal (R) of the latch is connected to the output terminal of the two-input NOR gate for receiving the reset signal; the output terminal (Q) of the latch is used to output the ODT enable signal; wherein, the ODT enable signal includes: when the first intermediate signal is low, the ODT enable signal must be high; when the first intermediate signal is high and the reset signal is low, the ODT enable signal must be low.

[0025] In some embodiments, the control module further includes a first NOT gate module, a second NOT gate module, and a three-input OR gate; wherein,

[0026] The first NOT gate module is used to receive the first intermediate signal and perform a NOT operation on the first intermediate signal to obtain the second intermediate signal;

[0027] The second NOT gate module is used to receive the ODT enable signal and perform a NOT operation on the ODT enable signal to obtain a third intermediate signal;

[0028] The three-input OR gate is used to perform an OR operation on the second setting signal, the second intermediate signal, and the third intermediate signal to generate a count reset signal.

[0029] In some embodiments, the counting module includes an asynchronous binary counter, which includes a plurality of flip-flops connected sequentially.

[0030] In some embodiments, the flip-flop is a D-type flip-flop; wherein the input terminal (D) of each flip-flop is connected to its own second output terminal (Q-NOT), and the second output terminal (Q-NOT) of each flip-flop is connected to the clock terminal (CK) of the next flip-flop.

[0031] In some embodiments, the trigger further includes a first output terminal (Q) and a reset terminal (RST); wherein,

[0032] The first output terminal of the trigger is used to output a counting signal;

[0033] The reset terminal of the trigger is used to receive the count reset signal, and when the count reset signal is high, to control the count signal to be low by resetting the trigger.

[0034] In some embodiments, the counting module further includes a clock control module, wherein,

[0035] The clock control module is used to receive the count reset signal and the clock signal, and generate an internal clock signal; wherein the internal clock signal is connected to the clock terminal (CK) of the first flip-flop among the plurality of flip-flops, and the internal clock signal includes: stopping the output of the internal clock signal when the count reset signal is at the seventh level; and outputting the internal clock signal when the count reset signal is at the eighth level.

[0036] In some embodiments, the seventh level is a high level and the eighth level is a low level.

[0037] In some embodiments, the clock control module includes a third NOT gate module and a two-input AND gate; wherein,

[0038] The third NOT gate module is used to receive the count reset signal and perform a NOT operation on the count reset signal to obtain a fourth intermediate signal;

[0039] The two-input AND gate is used to receive the fourth intermediate signal and the clock signal, and to perform an AND operation on the fourth intermediate signal and the clock signal to obtain the internal clock signal.

[0040] In some embodiments, the preset time is greater than the sum of the first delay, the second delay, and the third delay; wherein,

[0041] The first delay represents the time interval between the first intermediate signal changing from the first level to the second level and the counting reset signal changing from the second level to the first level.

[0042] The second delay represents the time interval between the change of the count reset signal from the second level to the first level and the change of the count signal from the first level to the second level.

[0043] The third delay refers to the time interval between the change of the counting signal from the first level to the second level and the change of the reset signal from the second level back to the first level.

[0044] In some embodiments, the selection module is further configured to receive the first setting signal and at least two characterization signals, and select one of the characterization signals from the at least two characterization signals as the target achievement signal according to the first setting signal; wherein the at least two characterization signals respectively characterize that the clock cycle count value has reached different clock cycle count target values.

[0045] In some embodiments, the selection module is specifically configured to select a first characterization signal as the target achievement signal and determine the clock cycle count target value as a first value when the first setting signal indicates that both the additional delay AL and the parity delay PL are not enabled; wherein the first value is greater than or equal to the column address write delay CWL minus 2; or...

[0046] The selection module is specifically configured to, when the first setting signal indicates that both the additional delay AL and the parity delay PL are enabled, select a second characterization signal as the target achievement signal, and determine the clock cycle count target value as a second value; wherein the second value is greater than or equal to the sum of the column address write delay CWL, the additional delay AL, and the parity delay PL, minus 2; or,

[0047] The selection module is specifically configured to, when the first setting signal indicates that the additional delay AL is enabled and the parity delay PL is not enabled, select a third characterization signal as the target achievement signal, and determine the clock cycle count target value as a third value; wherein the third value is greater than or equal to the sum of the column address write delay CWL and the additional delay AL minus 2; or,

[0048] The selection module is specifically used to select a fourth characterization signal as the target achievement signal when the first setting signal indicates that the additional delay PL is enabled and the parity delay AL is not enabled, and to determine the clock cycle count target value as the fourth value; wherein the fourth value is greater than or equal to the sum of the column address write delay CWL and the parity delay PL minus 2.

[0049] Wherein, the first characterization signal indicates that the clock cycle count value has reached the first value, the second characterization signal indicates that the clock cycle count value has reached the second value, the third characterization signal indicates that the clock cycle count value has reached the third value, and the fourth characterization signal indicates that the clock cycle count value has reached the fourth value.

[0050] In some embodiments, the counting module includes six triggers, and the six triggers are connected sequentially; wherein,

[0051] The first output terminal of the i-th flip-flop is used to output the i-th counting signal, where i is an integer greater than zero and less than or equal to six;

[0052] The selection module is specifically used to receive the first setting signal, the fifth counting signal, and the sixth counting signal, and select the fifth counting signal and the sixth counting signal according to the first setting signal to generate the target achievement signal; wherein, the two input terminals of the selection module are respectively connected to the first output terminal of the fifth flip-flop and the first output terminal of the sixth flip-flop.

[0053] In some embodiments, the selection module is further configured to, when the first setting signal indicates that both the additional delay AL and the parity delay PL are not enabled, determine that the target achievement signal is the fifth counting signal, and determine that the clock cycle count target value is the first value; or...

[0054] The selection module is further configured to determine the target achievement signal as the sixth counting signal and determine the clock cycle count target value as the second value when the first setting signal indicates that at least one of the additional delay AL and the parity delay PL is enabled.

[0055] In some embodiments, the first value is 32 and the second value is 64.

[0056] Secondly, embodiments of this application provide a semiconductor memory, which includes an enable control circuit as described in any one of the first aspects.

[0057] In some embodiments, the semiconductor memory is a dynamic random access memory (DRAM) chip.

[0058] In some embodiments, the dynamic random access memory (DRAM) chip conforms to the DDR4 memory specification.

[0059] This application provides an enable control circuit and a semiconductor memory. The enable control circuit includes a counting module, a selection module, and a control module. The counting module counts the current clock cycle to determine a clock cycle count value. The selection module determines a target clock cycle count value based on a first setting signal. The control module controls the ODT path to be in an enabled state and starts the counting module when the level state of the ODT pin signal flips. When the clock cycle count value reaches the target clock cycle count value and the level state of the ODT pin signal remains unchanged, the control module switches the ODT path from the enabled state to the disabled state. When the clock cycle count value reaches the target clock cycle count value and the level state of the ODT pin signal flips again, the control module keeps the ODT path in the enabled state. In this way, the enable state of the ODT path is controlled based on whether the clock cycle count value reaches the target clock cycle count value, so that the ODT path is turned off when it is not needed, thereby avoiding current waste and achieving the purpose of saving power consumption. In addition, when the level state of the ODT pin signal flips twice in a row, it can also solve the problem that the ODT path cannot be enabled when the ODT pin level flips for the second time in some cases. Attached Figure Description

[0060] Figure 1 A schematic diagram of the structure of an ODT functional circuit provided for related technologies;

[0061] Figure 2 A timing diagram of a synchronous ODT mode provided for related technologies;

[0062] Figure 3 A schematic diagram of a framework for controlling the operation of the ODT path is provided in an embodiment of this application;

[0063] Figure 4 A schematic diagram of the specific structure of an enable control circuit provided for related technologies;

[0064] Figure 5 A timing diagram of an enable control circuit provided for related technologies;

[0065] Figure 6 A timing diagram of another enable control circuit provided for related technologies;

[0066] Figure 7 A schematic diagram of the composition structure of an enable control circuit provided in an embodiment of this application;

[0067] Figure 8A schematic diagram of the composition structure of another enable control circuit provided in an embodiment of this application;

[0068] Figure 9 A timing diagram of an ODT pin signal, an ODT delay signal, and a first intermediate signal provided for an embodiment of this application;

[0069] Figure 10 A schematic diagram of the specific structure of an enable control circuit provided in an embodiment of this application;

[0070] Figure 11 A timing diagram of an enable control circuit provided in an embodiment of this application;

[0071] Figure 12 A timing diagram of another enable control circuit provided in an embodiment of this application;

[0072] Figure 13 A timing diagram of another enable control circuit provided in an embodiment of this application;

[0073] Figure 14 This is a schematic diagram of the composition structure of a semiconductor memory provided in an embodiment of this application. Detailed Implementation

[0074] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are merely for explaining the relevant application and not for limiting the application. Furthermore, it should be noted that, for ease of description, only the parts relevant to the application are shown in the accompanying drawings.

[0075] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0076] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0077] It should be noted that the terms "first, second, and third" used in the embodiments of this application are only used to distinguish similar objects and do not represent a specific order of objects. It is understood that "first, second, and third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0078] Before providing a further detailed description of the embodiments of this application, the nouns and terms used in the embodiments of this application will be explained. The nouns and terms used in the embodiments of this application shall be interpreted as follows:

[0079] Dynamic Random Access Memory (DRAM)

[0080] Double Data Rate (DDR)

[0081] Fourth generation DDR (DDR4)

[0082] On Die Termination (ODT)

[0083] Termination Resistance (RTT)

[0084] Column address write latency (CAS Write Latency, CWL)

[0085] Memory access latency (CAS Latency, CL)

[0086] Additional Latency (AL)

[0087] Parity Latency (PL)

[0088] Phase-locked loop (DLL)

[0089] Mode Register (MR)

[0090] Mode Register Set (MRS)

[0091] With the rapid development of semiconductor technology, signal transmission rates are getting faster and faster, leading to increasingly prominent issues related to signal integrity. To improve data signal integrity during high-speed signal propagation, DDR3 and DDR4 designs incorporate a separate ODT resistor. This ODT resistor performs impedance matching on the transmission line, reducing energy loss and reflection during transmission and thus ensuring the integrity of the signal received at the receiver.

[0092] Taking DDR4 DRAM as an example, DDR4 DRAM supports the ODT (Optical Detachment Transmission) function. This function allows adjustment of the termination resistors of the DQ, DQS_t / c, DM_n, and TDQS_t / c ports of each device via ODT pin control, write commands, or setting default resistance values ​​in the mode register. Furthermore, the purpose of the ODT function is to reduce reflections by independently controlling the termination resistors of all or any one of the DRAMs, thereby effectively improving signal integrity at the memory interface. Figure 1 As shown, it illustrates a schematic diagram of an ODT functional circuit provided by related technologies. Figure 1 The ODT (Optical Data Transmission) functional circuit can include at least a switch S1, a termination resistor RTT, and a power supply VDDQ. One end of switch S1 is connected to one end of the termination resistor RTT, the other end of the termination resistor RTT is connected to the power supply VDDQ, and the other end of switch S1 is connected to other circuitry like DQ, DQS, DM, and TDQS ports. It is important to note that DQS can be a pair of differential data strobe signals DQS_t and DQS_c, and TDQS can also be a pair of differential data strobe signals TDQS_t and TDQS_c; in other words, DDR4 DRAM only supports differential data strobe signals and does not support single-signal data strobe signals.

[0093] in addition, Figure 1 Switch S1 is controlled by the ODT control logic. The ODT control logic includes external ODT pin inputs, mode register configuration, and other control information. The value of RTT is controlled by the configuration information in the mode register. Furthermore, if RTT_NOM is disabled in self-refresh mode or MR1{A10,A9,A8}={0,0,0}, the control of the ODT pin is ignored.

[0094] Specifically, DDR4 DRAM's ODT (Optical Deployment Register) function has four states: termination resistor disabled, RTT_WR, RTT_NOM, and RTT_PARK. The ODT function is enabled when the configuration bits MR1{A10,A9,A8}, MR2{A10:A9}, or MR5{A8:A6} are not all zeros. In this case, the actual value of the ODT resistor is determined by these configuration bits. Upon entering self-refresh mode, DDR4 DRAM automatically disables the ODT function and sets all termination resistors to a high-impedance (Hi-Z) state to discard all mode register settings.

[0095] It should also be noted that this application embodiment provides a synchronous ODT mode. When the DLL is enabled and locked, the synchronous ODT mode can be selected. In synchronous ODT mode, RTT_NOM will be enabled after DODTLon clock cycles following the sampling of the ODT pin signal at the first rising edge of the clock when the ODT pin signal becomes high. RTT_NOM will be disabled after DODTLoff clock cycles following the sampling of the ODT pin signal at the first rising edge of the clock when the ODT pin signal becomes low. The parameters DODTLon and DODTLoff are related to WL (WL = CWL + AL + PL), where DODTLon = WL - 2 and DODTLoff = WL - 2.

[0096] In synchronous ODT mode, additional delay (AL) and parity delay (PL) also directly affect the delay of ODT (also known as "delay"), as shown in Table 1.

[0097] Table 1

[0098]

[0099] Furthermore, in synchronous ODT mode, the following timing parameters are applicable: DODTLon, DODTLoff, tADCmin, tADCmax, etc. When changing the ODT resistance value, such as from RTT_PARK to RTT_NOM, the maximum and minimum values ​​of the RTT time jitter value are tADCmax and tADCmin, respectively; these parameters are applicable to synchronous ODT mode and data termination resistor disabled mode. Figure 2 For example, it illustrates a timing diagram in a synchronous ODT mode provided by related technologies. Figure 2 As shown, assuming CWL = 9, AL = 0, PL = 0, then DODTLon = WL - 2 = 7, DODTLoff = WL - 2 = 7. Additionally, Figure 2 The black portion in the image represents the RTT (Reset Time) jitter value.

[0100] As you can understand, the above content refers to the ODT (Optical Depth Transmission) specifications in the DDR4 technical specifications. Simply put, the RTT (Resistance Tolerance) value can be switched, but the switching must follow a specific timing sequence. One mode is synchronous ODT mode. That is, the signal level at the ODT pin on the DRAM chip controls the RTT resistance value. When the signal level at the ODT pin changes from low to high, after waiting for DODTLon clock cycles, the DRAM chip's RTT resistance value changes from RTT_PARK to RTT_NOM. Alternatively, when the signal level at the ODT pin changes from high to low, after waiting for DODTLoff clock cycles, the DRAM chip's RTT resistance value changes from RTT_NOM to RTT_PARK.

[0101] It should be noted that the timing parameters DODTLon and DODTLoff, i.e., ODT latency, are related to the values ​​of CWL, AL, and PL. Therefore, a shift register needs to be set in the ODT path to shift by several clock cycles, thereby meeting the timing requirements related to CWL, AL, and PL. In addition, the shift register requires a clock signal (which can be represented by CLK).

[0102] like Figure 3 As shown, it illustrates a framework diagram for controlling the operation of the ODT path according to an embodiment of this application. Figure 3 The system can include a receiver, an ODT enable module, a shift register, a latency control module, and an RTT control module. The receiver receives ODT pin signals and the clock signal, while the RTT control module controls the switching of the RTT resistance value. Furthermore, the entire ODT path is very complex, including both physical delay (independent of the clock period) and clock delay (the delay is an integer multiple of the clock period). Because in... Figure 3 Ultimately, the delay of the entire path needs to be an integer multiple of the clock cycle, i.e., DODTLon and DODTLoff. Therefore, the function of this delay control module is to use the DLL to implement the signal at the end of the ODT path (i.e., Figure 1 The control signal of switch S1 is synchronized with the clock signal. This compensates for the physical delay, so that the delay of the entire path is an integer multiple of the clock cycle, thereby ultimately achieving resistance control of RTT.

[0103] In related technologies, the ODT enable module mainly employs simple logic control, as shown in Table 2. It controls the enabling or disabling of the CLK used by the ODT path by identifying whether the synchronous ODT mode is enabled in the MRS setting. For example, if MR1... <a10:a8>When set to the disabled state, the signal level at the ODT pin will not have any effect, and the ODT path and CLK will not be needed. Therefore, CLK can be disabled, and the ODT path will also be disabled, which can save power.

[0104] However, as shown in Table 2, there is another situation where the MRS setting is enabled, but the signal level at the ODT pin does not change. In this case, the ODT path does not need to work, but since CLK is not turned off, current is wasted and power consumption is increased.

[0105] Table 2

[0106]

[0107] For example, see Figure 4 It shows a schematic diagram of a specific structure of an enable control circuit provided by related technologies. For example... Figure 4 As shown, the enable control circuit may include: a delay module 401, an XOR gate 402, a first flip-flop 403, a first NOT gate 404, a three-input OR gate 405, a second NOT gate 406, a two-input AND gate 407, six second flip-flops 408, a selection module 409, and a two-input OR gate 410, etc. For detailed connection relationships, please refer to [link to details]. Figure 4 The signal output by the XOR gate 402 is represented by NET01; the signal output by the first NOT gate 404 is represented by ODT_CLK_EN; the signal output by the three-input OR gate 405 is represented by CNT_RST; and the six second flip-flops 408 can form an asynchronous binary counter, with the signals output from the first output (Q) of the six second flip-flops 408 sequentially represented by Q. <1> Q <2> Q <5> Q <6> The signal output of the two-input OR gate 410 is represented by SET. Additionally, ODT represents the ODT pin signal, CLK represents the clock signal, VSS! represents the global ground signal; and AL_DIST can be called the first setting signal, generated based on whether AL and / or PL are enabled; MRS_DIST can be called the second setting signal, generated based on the setting of the mode register.

[0108] according to Figure 4 The circuit structure shown has the following corresponding signal timing diagram: Figure 5 As shown. In Figure 5 In the diagram, the arrowed curves represent causal relationships. For example, when the ODT pin signal changes from low to high, the delay module 401 and the XOR gate 402 will cause the NET01 signal to change from low to high. The first flip-flop 403 (i.e., the D flip-flop) triggers the instant the NET01 signal changes from low to high, sampling the D input as the Q output, at which point the Q output is low; after passing through the first NOT gate 404, it becomes high, meaning the ODT_CLK_EN signal changes from low to high, enabling the ODT path. When the MRS_DIST signal is low, when the NET01 signal changes from high to low, since the Q output of the first flip-flop 403 is low, the three inputs to the three-input OR gate 405 will output low, meaning the CNT_RST signal changes from high to low. At this time, the asynchronous binary counter starts counting, and after the clock cycle count value satisfies 32 or 64 clock cycles (tCK), Q... <5> Or Q <6> When the signal changes from low to high, it is input to the two-input OR gate 410 along with the MRS_DIST signal, and the output SET signal changes from low to high. Furthermore, when the SET signal is high, the first flip-flop 403 is set, so that the Q output of the first flip-flop 403 is high. After passing through the first NOT gate 404, it becomes low, that is, the ODT_CLK_EN signal changes from high to low, so that the ODT path is closed, thereby achieving the purpose of power saving.

[0109] However, Figure 4 The circuit structure shown has a problem: when the ODT pin signal level changes twice consecutively, with an interval of approximately 32 or 64 tCK, a second ODT pin level change will occur, but the ODT path will not be enabled. See details... Figure 6 The timing diagram shown.

[0110] like Figure 6 As shown, approximately 32 or 64 clock cycles after the first change in the ODT pin signal level (depending on whether AL and / or PL are enabled), the ODT pin signal level changes a second time. This causes the rising edge of the NET01 signal to fall precisely in the middle of the SET signal pulse generated by the first change in the ODT pin signal level. This renders the rising edge of the NET01 signal ineffective, preventing the ODT_CLK_EN signal from going high, thus preventing the ODT path from starting. In short, at this specific moment, after the first change in the ODT pin signal level, the ODT path completion is delayed, and it is desirable to make the ODT_CLK_EN signal low to disable the ODT path. However, precisely at this moment, the ODT pin signal level changes a second time, and it is desired to make the ODT_CLK_EN signal high to enable the ODT path, but the enabling fails.

[0111] Based on this, the embodiments of this application provide an enable control circuit that can not only enable the ODT path for a certain period of time after detecting a change in the level state of the ODT pin, i.e., the ODT path is in an enabled state; but also disable the ODT path after ensuring that the resistance change of the RTT is completed, thereby achieving the purpose of saving power; in addition, when the level state of the ODT pin signal flips twice consecutively, it can also solve the problem that the ODT path cannot be enabled when the ODT pin level flips for the second time in some cases.

[0112] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0113] In one embodiment of this application, see Figure 7 This illustrates a schematic diagram of the composition of an enable control circuit 70 provided in an embodiment of this application. Figure 7 As shown, the enable control circuit 70 may include a counting module 71, a selection module 72, and a control module 73; wherein,

[0114] The counting module 71 is used to count the current clock cycle and determine the clock cycle count value;

[0115] Selection module 72 is used to determine the target value of clock cycle counting based on the first setting signal;

[0116] The control module 73, connected to the counting module 71 and the selection module 72, is used to control the ODT path to be in the enabled state and start the counting module when the level state of the ODT pin signal flips; and to control the ODT path to change from the enabled state to the disabled state when the clock cycle count value reaches the clock cycle count target value and the level state of the ODT pin signal does not change; and to control the ODT path to remain in the enabled state when the clock cycle count value reaches the clock cycle count target value and the level state of the ODT pin signal flips again.

[0117] It should be noted that the enable control circuit 70 in this embodiment is applied to Figure 3 The ODT enable module is used in this system. Here, if the signal level at the ODT pin flips, for example, from low to high or from high to low, the RTT resistance will change after a delay of DODTLon or DODTLoff clock cycles. During this process, the ODT path needs to be kept in the enabled state. Then, after the RTT resistance change is complete, to save power, the ODT path can be switched from the enabled state to the disabled state.

[0118] It should also be noted that, to ensure the completion of the RTT resistance change, this embodiment can set a clock cycle count target value, which is related to DODTLon or DODTLoff. Since both DODTLon and DODTLoff are related to CWL, AL, and PL, the setting of the clock cycle count target value is related to CWL, AL, and PL. In this embodiment, the first setting signal is generated based on whether AL and / or PL are enabled, allowing the selection module 72 to determine the clock cycle count target value based on whether AL and / or PL are enabled.

[0119] It should also be noted that for the enable control circuit 70, when the level state of the ODT pin signal flips twice consecutively, especially when the second flip occurs at certain times around the clock cycle count target value, the ODT path can still be guaranteed to be in the enabled state.

[0120] In this way, the counting module 71 can determine whether the clock cycle count value has reached the clock cycle count target value, and the selection module 72 can determine the clock cycle count target value. Then, the control module 73 can control the ODT path to be in the enabled state and start the counting module when the ODT pin signal level changes; and control the ODT path to change from the enabled state to the disabled state when the clock cycle count value reaches the clock cycle count target value and the ODT pin signal level remains unchanged; and control the ODT path to remain in the enabled state when the clock cycle count value reaches the clock cycle count target value and the ODT pin signal level changes again. This not only saves power but also solves the problem that the ODT path cannot be enabled when the ODT pin level changes for the second time in some cases.

[0121] In some embodiments, Figure 7 Based on the enable control circuit 70 shown, see... Figure 8 The control module 73 may include a first control submodule 731 and a second control submodule 732; wherein,

[0122] The first control submodule 731 is used to generate a first intermediate signal based on the ODT pin signal;

[0123] The second control submodule 732 is used to perform logical operations on the first intermediate signal to generate an ODT enable signal.

[0124] Here, the first intermediate signal can be represented by S. The first intermediate signal can include: a first level before the ODT pin signal's level state changes; a change from the first level to a second level within a preset time after the ODT pin signal's level state changes; and a change from the second level to the first level after the preset time.

[0125] The ODT enable signal can be represented by ODT_CLK_EN. Specifically, the ODT enable signal can be configured such that when it is at the third level, the ODT path is enabled; and when it is at the fourth level, the ODT path is disabled.

[0126] In a specific example, the first level can be high, the second level can be low, the third level can be high, and the fourth level can be low.

[0127] Furthermore, for the first control submodule 731, in some embodiments, such as Figure 8 As shown, the first control submodule 731 may include a delay module 7311 and an XNOR gate module 7312; wherein,

[0128] Delay module 7311 is used to delay the ODT pin signal for a preset time to obtain the ODT delayed signal;

[0129] The XOR gate module 7312 is used to perform an XOR operation on the ODT pin signal and the ODT delay signal to obtain the first intermediate signal.

[0130] Here, the preset time is the time the ODT pin signal is delayed by the delay module 7311, and this preset time can also control the pulse width of the first intermediate signal. In addition, the XOR gate module 7312 can also be called the XOR NOT gate module, which can be regarded as being composed of XOR gates and NOT gates.

[0131] For example, see Figure 9 This illustration shows a timing diagram of an ODT pin signal, an ODT delay signal, and a first intermediate signal provided in an embodiment of this application. Figure 9 In this context, ODT represents the ODT pin signal, ODT_delay represents the ODT delay signal, and S represents the first intermediate signal. According to... Figure 9 It can be seen that before the level state of the ODT pin signal flips, the first intermediate signal is at a high level; and within a preset time after the level state of the ODT pin signal flips, the first intermediate signal changes from a high level to a low level; and after the preset time, the first intermediate signal changes from a low level to a high level.

[0132] It should be noted that due to the physical delay introduced by the XOR gate module 7312, the moment when the level state of the ODT pin signal flips is not aligned with the moment when the first intermediate signal changes from high to low on the time axis.

[0133] Furthermore, regarding the second control submodule 732, in some embodiments, such as Figure 8 As shown, the second control submodule 732 may include a latch 7321.

[0134] In a specific example, latch 7321 can be an SR latch, and an SR latch is composed of two two-input NAND gates.

[0135] In this embodiment, the SR-type latch is a flip-flop, also known as a "reset / set flip-flop." It has two stable states, 1 and 0, and can also be called a "bistable flip-flop." Without an external trigger signal, it will remain in its original state, thus possessing a memory function. Only under the action of an external trigger signal can the flip-flop's output state change; the output state is directly controlled by the input signal.

[0136] It should also be noted that the SR type latch includes two input terminals (S and R) and two output terminals (Q and QN). The first input terminal (S) represents SET, i.e., the set terminal. When the S terminal is low, the first output terminal (Q) will definitely be high. The second input terminal (R) represents RST, i.e., the reset terminal. When the S terminal is high and the R terminal is low, the first output terminal (Q) will definitely be low.

[0137] Furthermore, in some embodiments, such as Figure 8 As shown, the control module 73 may further include a two-input NOR gate 733; wherein,

[0138] Selection module 72 is also used to generate a target achievement signal, which indicates that the clock cycle count value has reached the clock cycle count target value;

[0139] The two-input NOR gate 733 is used to perform NOR operation on the target achievement signal and the second setting signal to obtain the reset signal.

[0140] Here, the second setting signal is generated based on the setting of the mode register, and can be represented by MRS_DIST. Specifically, the second setting signal can include: when the second setting signal is at the fifth level, it indicates that the chip's ODT function is disabled; when the second setting signal is at the sixth level, it indicates that the chip's ODT function is enabled.

[0141] In one specific example, the fifth level is high and the sixth level is low.

[0142] In other words, if the second setting signal is high, it means that the chip's ODT function is off, and the enable control circuit 70 of this application is no longer required; if the second setting signal is low, it means that the chip's ODT function is on, and it is necessary to further combine the ODT pin signal to determine whether to enable the ODT path.

[0143] In this embodiment of the application, for the second control submodule 732, the first input terminal (S) of the latch 7321 is connected to the output terminal of the first control submodule 731 and is used to receive the first intermediate signal; the second input terminal (R) of the latch 7321 is connected to the output terminal of the two-input NOR gate 733 and is used to receive the reset signal; the output terminal (Q) of the latch 7321 is used to output the ODT enable signal.

[0144] Here, the ODT enable signal can be represented by ODT_CLK_EN. Specifically, the ODT enable signal can be: when the first intermediate signal is low, the ODT enable signal must be high; when the first intermediate signal is high and the reset signal is low, the ODT enable signal must be low.

[0145] It should also be noted that if the second setting signal is high, then the reset signal must be low. If the first intermediate signal is high, then the latch can be reset to control the ODT enable signal to be low, so that the ODT path is in the enabled-disabled state.

[0146] Furthermore, in some embodiments, such as Figure 8 As shown, the control module 73 may further include a first NOT gate module 734, a second NOT gate module 735, and a three-input OR gate 736; wherein,

[0147] The first NOT gate module 734 is used to receive the first intermediate signal and perform a NOT operation on the first intermediate signal to obtain the second intermediate signal;

[0148] The second NOT gate module 735 is used to receive the ODT enable signal and perform a NOT operation on the ODT enable signal to obtain the third intermediate signal;

[0149] The three-input OR gate 736 is used to perform an OR operation on the second setting signal, the second intermediate signal, and the third intermediate signal to generate a count reset signal.

[0150] Here, the count reset signal can be represented by CNT_RST. After obtaining the count reset signal, it can be input into the counting module 71. On the one hand, it can be directly used for the reset and clearing operation of the counting module 71. On the other hand, after performing logical operations on it, the clock signal of the counting module 71 can also be masked.

[0151] Furthermore, in some embodiments, such as Figure 8 As shown, the counting module 71 may include an asynchronous binary counter 711.

[0152] In one specific example, the asynchronous binary counter 711 may include a number of flip-flops 7111, which are connected sequentially.

[0153] In this embodiment of the application, the flip-flop 7111 is a D-type flip-flop; wherein, the input terminal (D) of each flip-flop is connected to its own second output terminal (Q-NOT, or represented by QN), and the second output terminal (Q-NOT) of each flip-flop is connected to the clock terminal (CK) of the next flip-flop.

[0154] In addition, the flip-flop 7111 may also include a first output terminal (Q) and a reset terminal (RST); wherein,

[0155] The first output terminal (Q) of the flip-flop is used to output a counting signal;

[0156] The reset terminal (RST) of the flip-flop is used to receive the count reset signal, and when the count reset signal is high, it controls the count signal to be low by resetting the flip-flop.

[0157] Specifically, the 7111 flip-flop belongs to the D-type flip-flop category. Here, a D-type flip-flop (Data Flip-Flop or Delay Flip-Flop, DFF) is an information storage device with memory function and two stable states. It is the most basic logic unit for constructing various sequential circuits and an important unit circuit in digital logic circuits. A D-type flip-flop has two stable states, "0" and "1," and can flip from one stable state to the other under the influence of a certain external signal.

[0158] In this embodiment, the flip-flop 7111 may include an input terminal (D), a clock terminal (CK), a reset terminal (RST), a first output terminal (Q), and a second output terminal (Q NOT), and may even include a set terminal (SET). Here, the set terminal may be connected to a ground terminal. In a specific example, the set terminal (SET) of the flip-flop is used to receive a set signal, which may be a global ground signal, denoted by VSS!.

[0159] Furthermore, in some embodiments, such as Figure 8 As shown, the counting module 71 may further include a clock control module 712, wherein,

[0160] The clock control module 712 is used to receive the count reset signal and the clock signal, and generate an internal clock signal.

[0161] Here, the internal clock signal is connected to the clock input (CK) of the first flip-flop among several flip-flops to provide a clock signal to the counting module 71. The internal clock signal may include: stopping the output of the internal clock signal when the counting reset signal is at level seven; and outputting the internal clock signal when the counting reset signal is at level eight.

[0162] In one specific example, the seventh level is high and the eighth level is low.

[0163] Furthermore, regarding the clock control module 712, in some embodiments, such as Figure 5 As shown, the clock control module 712 may include a third NOT gate module 7121 and a two-input AND gate 7122; wherein,

[0164] The third NOT gate module 7121 is used to receive the count reset signal and perform a NOT operation on the count reset signal to obtain the fourth intermediate signal;

[0165] The two-input AND gate 7122 is used to receive the fourth intermediate signal and the clock signal, and perform an AND operation on the fourth intermediate signal and the clock signal to obtain the internal clock signal.

[0166] It should be noted that since the count reset signal is related to the second setting signal, if the second setting signal is high, then it can be determined that the count reset signal is high. Thus, when the count reset signal is high, the asynchronous binary counter 711 can be turned off, achieving the technical effect of saving current.

[0167] It should also be noted that the internal clock signal used by the counting module 71 itself is also controlled by the counting reset signal. Thus, after the counting ends, since the counting reset signal is at a high level, the internal clock signal used by the counting module is also turned off, thereby further saving current.

[0168] Furthermore, in some embodiments, the selection module 72 is also configured to receive a first setting signal and at least two characterization signals, and select one of the characterization signals from the at least two characterization signals as a target achievement signal according to the first setting signal; wherein the at least two characterization signals respectively characterize that the clock cycle count value has reached different clock cycle count target values.

[0169] Here, for selection module 72, the first setting signal can be generated based on whether the additional delay AL and / or parity delay PL are enabled, and the first setting signal is represented by AL_DIST. The following will describe four cases: neither additional delay AL nor parity delay PL is enabled; both additional delay AL and parity delay PL are enabled; additional delay AL is enabled and parity delay PL is not enabled; and parity delay PL is enabled and additional delay AL is not enabled.

[0170] In one possible implementation, the selection module 72 is specifically configured to select the first characterization signal as the target achievement signal when the first setting signal indicates that neither the additional delay AL nor the parity delay PL is enabled, and to determine the clock cycle count target value as a first value; wherein the first value is greater than or equal to the column address write delay CWL minus 2.

[0171] In another possible implementation, the selection module 72 is specifically configured to select a second characterization signal as the target achievement signal when the first setting signal indicates that both the additional delay AL and the parity delay PL are enabled, and to determine the clock cycle count target value as a second value; wherein the second value is greater than or equal to the sum of the column address write delay CWL and the additional delay AL and the parity delay PL minus 2.

[0172] In another possible implementation, the selection module 72 is specifically configured to select a third characterization signal as the target achievement signal when the first setting signal indicates that the additional delay AL is enabled and the parity delay PL is not enabled, and to determine the clock cycle count target value as a third value; wherein the third value is greater than or equal to the sum of the column address write delay CWL and the additional delay AL minus 2.

[0173] In another possible implementation, the selection module 72 is specifically configured to select a fourth characterization signal as the target achievement signal when the first setting signal indicates that the parity delay PL is enabled and the additional delay AL is not enabled, and determine the clock cycle count target value as the fourth value; wherein the fourth value is greater than or equal to the sum of the column address write delay CWL and the parity delay PL minus 2.

[0174] Here, the first characterization signal indicates that the clock cycle count value has reached a first value, the second characterization signal indicates that the clock cycle count value has reached a second value, the third characterization signal indicates that the clock cycle count value has reached a third value, and the fourth characterization signal indicates that the clock cycle count value has reached the fourth value.

[0175] It should also be noted that the values ​​for CWL are shown in Table 3. Table 3 shows that the maximum value for CWL is 20. The values ​​for AL are shown in Table 4. Table 4 shows that the maximum value for AL is CL-1. The values ​​for CL are shown in Table 5. Table 5 shows that the maximum value for CL is 32, therefore the maximum value for AL is 31. The values ​​for PL are shown in Table 6. Table 6 shows that the maximum value for PL is 8.

[0176] Table 3

[0177]

[0178] Table 4

[0179]

[0180] Table 5

[0181] A12 A6 A5 A4 A2 CAS Latency (CL) 0 0 0 0 0 9 0 0 0 0 1 10 0 0 0 1 0 11 0 0 0 1 1 12 0 0 1 0 0 13 0 0 1 0 1 14 0 0 1 1 0 15 0 0 1 1 1 16 0 1 0 0 0 18 0 1 0 0 1 20 0 1 0 1 0 22 0 1 0 1 1 24 0 1 1 0 0 23 0 1 1 0 1 17 0 1 1 1 0 19 0 1 1 1 1 21 1 0 0 0 0 25 (3DS only available) 1 0 0 0 1 26 1 0 0 1 0 27 (3DS only available) 1 0 0 1 1 28 1 0 1 0 0 Reserved for 29 1 0 1 0 1 30 1 0 1 1 0 Reserved for 31 1 0 1 1 1 32 1 1 0 0 0 Reserved

[0182] Table 6

[0183]

[0184]

[0185] It should be noted that Tables 3 to 6 above are from relevant standard documents for DDR4 DRAM. A0, A1, A2, A3, A4, A5, A6, and A12 are bits in the corresponding mode registers. According to Tables 3 to 6, the maximum value of CWL is 20, the maximum value of AL is 31, and the maximum value of PL is 8. Then, according to selection module 72, when the first setting signal indicates that both the additional delay AL and the parity delay PL are not enabled, the first value is greater than or equal to 18; when the first setting signal indicates that both the additional delay AL and the parity delay PL are enabled, the second value is greater than or equal to 57; when the first setting signal indicates that the additional delay AL is enabled and the parity delay PL is not enabled, the third value is greater than or equal to 49; when the first setting signal indicates that the parity delay PL is enabled and the additional delay AL is not enabled, the fourth value is greater than or equal to 26. This allows us to determine the target value for the clock cycle count.

[0186] In addition, for the enable control circuit 70, the enable status of the ODT path when the ODT pin level flips for the second time can be described as follows, depending on whether the interval between two consecutive flips of the ODT pin signal level is greater than the clock cycle count target value.

[0187] In one possible implementation, assuming the interval between two consecutive toggles of the ODT pin signal's level state is greater than the clock cycle count target value, then control module 73 is configured to: enable the ODT path and start the counting module when the ODT pin signal's level state to toggle for the first toggle; and control the ODT path to switch from the enabled state to the disabled state when the clock cycle count value reaches the clock cycle count target value, and reset the counting module to zero. When the ODT pin signal's level state to toggle for the second toggle, the steps of enabling the ODT path and starting the counting module are executed normally, at which point the ODT path can be enabled normally.

[0188] In another possible implementation, assuming that the interval between two consecutive toggles of the ODT pin signal level is less than the clock cycle count target value, the control module 73 is further configured to control the ODT path to remain in the enabled state and control the counting module to be cleared and restarted when the clock cycle count value has not reached the clock cycle count target value and the ODT pin signal level to toggle again; and to control the ODT path to switch from the enabled state to the disabled state when the recounted clock cycle count value reaches the clock cycle count target value.

[0189] In another possible implementation, assuming that the interval between two consecutive toggles of the ODT pin signal level is approximately equal to the clock cycle count target value, the control module 73 is further configured to control the ODT path to change from the enabled state to the disabled state and clear the counting module when the clock cycle count value reaches the clock cycle count target value; and if the ODT pin signal level toggles again, immediately control the ODT path to be enabled again.

[0190] In other words, for the enable control circuit 70, when the level state of the ODT pin signal flips twice in a row, especially when the second flip occurs at certain times around the clock cycle count target value, the ODT path can still be guaranteed to be in the enabled state.

[0191] In short, this embodiment provides an enable control circuit, which includes a counting module, a selection module, and a control module. The counting module is used to count the current clock cycle and determine the clock cycle count value; the selection module is used to determine a target clock cycle count value based on a first setting signal; the control module is used to control the ODT path to be in an enabled state and start the counting module when the level state of the ODT pin signal flips; and when the clock cycle count value reaches the target clock cycle count value and the level state of the ODT pin signal remains unchanged, control the ODT path to switch from the enabled state to the disabled state; and when the clock cycle count value reaches the target clock cycle count value and the level state of the ODT pin signal flips again, control the ODT path to remain in the enabled state. In this way, by controlling the enable state of the ODT path based on whether the clock cycle count value reaches the target clock cycle count value, the ODT path can be enabled for a certain period of time after a change in the level state of the ODT pin is detected, that is, the ODT path is in the enabled state. After ensuring that the resistance value change of the RTT is completed, the ODT path can be turned off, which can reduce current and save power. In addition, when the level state of the ODT pin signal flips twice consecutively, it can also solve the problem that the ODT path cannot be enabled when the second ODT pin level flip occurs in some cases.

[0192] In another embodiment of this application, combined with Figure 8 For example, the counting module 71 includes six flip-flops and the selection module 72 only receives two characterization signals, and these two characterization signals are the counting signals output by the fifth flip-flop and the sixth flip-flop, respectively.

[0193] In some embodiments, the counting module 71 may include six flip-flops, which are connected sequentially; wherein,

[0194] The first output terminal (Q) of the i-th flip-flop is used to output the i-th counting signal, where i is an integer greater than zero and less than or equal to six;

[0195] The selection module 72 is specifically used to receive the first setting signal, the fifth counting signal, and the sixth counting signal, and select the fifth counting signal and the sixth counting signal according to the first setting signal to generate the target achievement signal; wherein, the two input terminals of the selection module are respectively connected to the first output terminal (Q) of the fifth flip-flop and the first output terminal (Q) of the sixth flip-flop.

[0196] It should be noted that the i-th counting signal is represented by Q. This can be represented by Q. Specifically, the fifth counting signal can be represented by Q. <5> This indicates that it is output from the first output (Q) of the fifth flip-flop; the sixth counting signal can be represented by Q. <6> This indicates that it is output from the first output terminal (Q) of the sixth flip-flop.

[0197] It should also be noted that since the selection module 72 only receives two characterization signals (the fifth counting signal and the sixth counting signal), the first setting signal either indicates that neither the additional delay AL nor the parity delay PL is enabled, or it is used to indicate that at least one of the additional delay AL and the parity delay PL is enabled. Thus, in a specific example, the selection module 72 is further configured to determine that the target achievement signal is the fifth counting signal and determine the clock cycle count target value as a first value when the first setting signal indicates that neither the additional delay AL nor the parity delay PL is enabled; or, the selection module 72 is further configured to determine that the target achievement signal is the sixth counting signal and determine the clock cycle count target value as a second value when the first setting signal indicates that at least one of the additional delay AL and the parity delay PL is enabled.

[0198] It should also be noted that when neither the additional delay AL nor the parity delay PL is enabled, the target clock cycle count (i.e., the first value) is greater than or equal to 18; when at least one of the additional delay AL and the parity delay PL is enabled, the target clock cycle count (i.e., the second value) is greater than or equal to 57. Furthermore, when the fifth counting signal goes high (i.e., "1"), the clock cycle count reaches 32; when the sixth counting signal goes high (i.e., "1"), the clock cycle count reaches 64. Therefore, in a specific example, the first value can be 32, and the second value can be 64.

[0199] For example, see Figure 10 This illustrates a schematic diagram of the specific structure of an enable control circuit 70 provided in an embodiment of this application. For example... Figure 10 As shown, the enable control circuit 70 may include a delay module 1001, an XNOR gate 1002, an SR latch 1003, a first NOT gate 1004, a second NOT gate 1005, a three-input OR gate 1006, a third NOT gate 1007, a two-input AND gate 1008, an asynchronous binary counter 1009, a selection module 1010, and a two-input NOR gate 1011. For detailed connection relationships, please refer to [link to details]. Figure 10 The asynchronous binary counter 1009 may include six flip-flops, which are D-type flip-flops. The input (D) of each flip-flop is connected to its own second output (QN), and the second output (QN) of each flip-flop is connected to the clock input (CK) of the next flip-flop.

[0200] exist Figure 10 In this diagram, the ODT pin signal is represented by ODT. The first intermediate signal output by the NAND gate 1002 is connected to the S terminal of the SR latch 1003, and can be represented by S. The reset signal output by the two-input NOR gate 1011 is connected to the R terminal of the SR latch 1003, and can be represented by R. The ODT enable signal output from the first output (Q) of the SR latch 1003 is represented by ODT_CLK_EN. The count reset signal output by the three-input OR gate 1006 is represented by CNT_RST. The count signals output from the first output (Q) of the six flip-flops are sequentially represented by Q. <1> Q <2> Q <5> Q <6> The symbols indicate the clock signal, AL_DIST, MRS_DIST, and VSS!. Additionally, CLK represents the clock signal, AL_DIST represents the first setting signal, MRS_DIST represents the second setting signal, and VSS! represents the global ground signal.

[0201] Thus, according to Figure 10 The circuit structure shown uses an SR-type latch. Whenever the level of the ODT pin signal changes, a low-level pulse will appear in S. At this time, ODT_CLK_EN will definitely be high to ensure that the ODT path can be enabled.

[0202] The following section will describe the working principle of the three cases in detail, using timing diagrams.

[0203] Case 1: Assuming the interval between two consecutive toggles of the ODT pin signal level is greater than the clock cycle count target value, i.e., when the time interval between two consecutive ODT pin level toggles is greater than 32 or 64 tCK, the timing diagram is as follows. Figure 11 As shown. In this case, both toggles of the ODT pin level will enable the ODT path normally.

[0204] The second scenario: Assuming the interval between two consecutive toggles of the ODT pin signal level is less than the clock cycle count target value, i.e., when the time interval between two consecutive ODT pin level toggles is less than 32 or 64 tCK, the timing diagram is as follows. Figure 12 As shown. Since the asynchronous binary counter 1009 has not yet counted to the target clock cycle count value, the second ODT pin level toggle occurs. Therefore, the counter will be reset to zero and start counting again. Only after the recounted clock cycle count value reaches the target clock cycle count value of 32 or 64tCK can ODT_CLK_EN be turned low to close the ODT path.

[0205] The third scenario: Assuming the interval between two consecutive toggles of the ODT pin signal level is approximately equal to the clock cycle count target value, that is, when the time interval between two consecutive ODT pin level toggles is approximately 32 or 64 tCK, the timing diagram is as follows. Figure 13 As shown. Although the first ODT pin level toggle causes the counter to count to 32 or 64tCK, and then sets R low to make ODT_CLK_EN low, the second ODT pin level toggle immediately sets S low, which in turn makes the SR latch output ODT_CLK_EN high, thus enabling the ODT path normally.

[0206] Whether it is Figure 11 ,still Figure 12 or Figure 13 The timeline diagram shown uses arrowed curves to represent causal relationships. Figure 13 For example, when the ODT pin signal flips (changes from low to high), after the delay module 1001, it is still low. Therefore, when both are input to the XOR gate 1002, the output will be low, meaning the S signal changes from high to low. The reason the ODT_CLK_EN signal changes from low to high is that when the S signal changes to low, the Q output of the SR latch 1003 must be high, meaning the ODT_CLK_EN signal becomes high, thus enabling the ODT path.

[0207] Additionally, when the MRS_DIST signal is low, the ODT pin signal outputs a high level after passing through the delay module 1001 and the XOR gate 1002, i.e., when the S signal changes from low to high. The S signal then changes from high to low through the first NOT gate 1004, and the Q output of the SR latch 1003 changes from high to low through the second NOT gate 1005. These three inputs are then fed into the three-input OR gate 1006, which outputs a low level, i.e., the CNT_RST signal changes from high to low. At this time, the asynchronous binary counter 1009 starts counting. Taking a clock cycle count target of 32tck as an example, after the clock cycle count reaches 32tck, the count value becomes 010000. At this point, Q... <5> The signal changes from low to high; with both the additional delay AL and the parity delay PL disabled and AL_DIST high, due to Q... <5> The signal is high, and the selection module 1010 outputs a high level. This high level, along with the MRS_DIST signal, is then input to the two-input NOR gate 1011, which outputs a low level, meaning the R signal becomes low. Alternatively, taking a clock cycle count target of 64 tck as an example, after the clock cycle count reaches 64 tck, the count value becomes 100000. At this point, Q... <6> The signal changes from low to high; when at least one of the additional delay AL and parity delay PL is enabled, and AL_DIST is low, due to Q <6> When the signal is high, the selection module 709 will output a high level. After inputting the high level signal and the MRS_DIST signal into the two-input NOR gate 1011, the output will be low, that is, the R signal will become low.

[0208] Furthermore, when the S signal is high and the R signal is low, resetting the SR latch 1003 ensures that its Q output is low, meaning the ODT_CLK_EN signal changes from high to low, thus disabling the ODT path and saving power. When the ODT pin signal flips again (from high to low), after a delay by the delay module 1001, it remains high. The inputs to the XOR gate 1002 will then output a low signal, meaning the S signal changes from high to low. When the S signal becomes low, the Q output of the SR latch 1003 will be high, meaning the ODT_CLK_EN signal changes from low to high again, enabling the ODT path once more.

[0209] In the above process, when the S signal changes from high to low, it passes through the first NOT gate 1004 and then through the three-input OR gate 1006, which causes the CNT_RST signal to change from low to high. This turns off and clears the asynchronous binary counter 1009 and disables its internal clock signal, thus enabling Q to... <5> Or Q <6> The signal changes from high level to low level; due to Q <5> Or Q <6> When both signals are at a low level and the MRS_DIST signal is at a low level, inputting them into a two-input NOR gate 1011 will cause the R signal to change from a low level to a high level.

[0210] Furthermore, when the ODT path is enabled again, with the MRS_DIST signal low, when the S signal changes from low to high, the S signal changes from high to low through the first NOT gate 1004, and the Q output of the SR latch 1003 changes from high to low through the second NOT gate 1005. These three inputs are then fed into a three-input OR gate 1006, which outputs a low level, meaning the CNT_RST signal changes from high to low. At this point, the asynchronous binary counter 1009 restarts counting until the recounted clock cycle count reaches the target clock cycle count value of 32tck (or 64tck). The count value then becomes 010000 (or 100000), i.e., Q... <5> signal (or Q) <6> The signal changes from low to high, which, after passing through the selection module 1010 and the two-input NOR gate 1011, causes the R signal to change from high to low again. Since the S signal is high and the R signal is low, the Q output of the SR latch 1003 must be low, meaning the ODT_CLK_EN signal changes from high to low, thus closing the ODT path again and achieving power saving.

[0211] It should be noted that the embodiments of this application also require controlling the preset time of the delay module 1001. In some embodiments, the preset time is greater than the sum of the first delay, the second delay, and the third delay; wherein,

[0212] The first delay represents the time interval between the first intermediate signal changing from the first level to the second level and the counting reset signal changing from the second level to the first level.

[0213] The second delay represents the time between the change of the count reset signal from the second level to the first level and the change of the count signal from the first level to the second level.

[0214] The third delay represents the time between the transition of the counting signal from the first level to the second level and the transition of the reset signal from the second level to the first level.

[0215] The second delay is the reset time of the asynchronous binary counter 1009. Specifically, the second delay represents the time between the change of the count reset signal from the second level to the first level and the change of the count signal from the first level to the second level.

[0216] Combination Figure 13 In this embodiment, it is necessary to control the delay of the delay module so that the pulse width of the S signal is greater than that of the delay module. Figure 13 The sum of the delays indicated by the bolded curved arrows. This ensures that when the reset signal R returns to high, the S signal remains low, thus preventing ODT_CLK_EN from being set low again and the ODT path from being closed again.

[0217] It is also important to note that, for Figure 13 In terms of Figure 13 Before the first arrow, in the initial state, the MRS_DIST signal is high, indicating that the chip's ODT function is disabled. At this time, the R signal is low and the ODT_CLK_EN signal is low. When the MRS_DIST signal changes from high to low, it indicates that the chip's ODT function is enabled, and only then will the R signal become high. When the ODT pin signal does not toggle, the S signal remains high, and the ODT_CLK_EN signal will continue to remain low, meaning the ODT path is in a disabled state.

[0218] Furthermore, in the embodiments of this application, Figure 10 The circuit structure shown is designed to generate the ODT path enable signal ODT_CLK_EN. When the ODT_CLK_EN signal is high, the clock signal for the ODT path is enabled, thus enabling the ODT path. When the ODT_CLK_EN signal is low, the clock signal for the ODT path is disabled, thus disabling the ODT path.

[0219] It's important to note the relationship between ODT delay and CWL, AL, and PL, as discussed above. To ensure ODT delay, the high level of ODT_CLK_EN must guarantee that the ODT path completes the ODT delay shift. If neither AL nor PL is enabled, CWL can be a maximum of 20 (DDR4 specification). Therefore, an asynchronous binary counter can be set to count to 32 clock cycles before setting ODT_CLK_EN low to disable the ODT path's clock signal. If at least one of AL and PL is enabled, considering a maximum of AL = 31, PL = 8, and CWL = 20, the counter can be set to count to 64 clock cycles before setting ODT_CLK_EN low to disable the ODT path's clock signal. This ensures the timing of the ODT path is achieved while reducing the clock signal oscillation time and current consumption.

[0220] It should also be noted that, in Figure 10 In the asynchronous binary counter 1009, the internal clock signal used by the asynchronous binary counter 1009 is also controlled by the CNT_RST signal. After the counting ends, since the CNT_RST signal is high, the internal clock signal used by the asynchronous binary counter 1009 is also turned off, and the current consumed by the two-input AND gate 1008 is also reduced, thereby further saving current.

[0221] This embodiment elaborates on the specific implementation of the aforementioned embodiments. It can be seen that the technical solution of the aforementioned embodiments controls the enable state of the ODT path based on whether the clock cycle count value reaches the clock cycle count target value, so that the ODT path is turned off when it is not needed, thereby avoiding current waste and achieving the purpose of saving power consumption. In addition, when the level state of the ODT pin signal flips twice consecutively, it can also solve the problem that the ODT path cannot be enabled when the ODT pin level flips for the second time in some cases.

[0222] In another embodiment of this application, see [link to application]. Figure 14 This illustrates a schematic diagram of the structural composition of a semiconductor memory 140 provided in an embodiment of this application. For example... Figure 14 As shown, the semiconductor memory 140 may include the enable control circuit 70 described in any of the foregoing embodiments.

[0223] In this embodiment, the semiconductor memory 140 can be a DRAM chip.

[0224] Furthermore, in some embodiments, the DRAM chip conforms to the DDR4 memory specification.

[0225] In this embodiment, the enable control circuit 70 specifically relates to the enable control of the ODT path in a DDR4 DRAM chip. This enable control circuit 70 can generate an enable signal, thereby controlling the clock signal of the ODT path to achieve power saving.

[0226] Specifically, since the semiconductor memory 140 includes an enable control circuit 70, the enable state of the ODT path is controlled according to whether the clock cycle count value reaches the clock cycle count target value. This allows the ODT path to be turned off when it is not needed, thereby avoiding current waste and saving power. In addition, when the level state of the ODT pin signal flips twice consecutively, it can also solve the problem that the ODT path cannot be enabled when the ODT pin level flips for the second time in some cases.

[0227] The above are merely preferred embodiments of this application and are not intended to limit the scope of protection of this application.

[0228] It should be noted that, in this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0229] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0230] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0231] The features disclosed in the several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0232] The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0233] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An enable control circuit, characterized in that, The enabling control circuit includes: The counting module is used to count the current clock cycle and determine the clock cycle count value; The selection module is used to determine the target value for clock cycle counting based on the first setting signal; A control module, connected to the counting module and the selection module, is configured to: control the ODT path to be in an enabled state and start the counting module when the level state of the ODT pin signal flips; control the ODT path to change from the enabled state to the disabled state when the clock cycle count value reaches the clock cycle count target value and the level state of the ODT pin signal remains unchanged; and control the ODT path to remain in the enabled state when the clock cycle count value reaches the clock cycle count target value and the level state of the ODT pin signal flips again.

2. The enable control circuit according to claim 1, characterized in that, The control module is further configured to, when the clock cycle count value has not reached the clock cycle count target value and the level state of the ODT pin signal flips again, control the ODT path to remain in the enabled state, control the counting module to be cleared, and restart the counting module. And when the clock cycle count value obtained by recounting reaches the clock cycle count target value, the ODT path is controlled to change from the enabled state to the disabled state.

3. The enable control circuit according to claim 1, characterized in that, The control module includes a first control submodule and a second control submodule; wherein... The first control submodule is configured to generate a first intermediate signal based on the ODT pin signal; wherein the first intermediate signal includes: before the level state of the ODT pin signal flips, the first intermediate signal is at a first level; and within a preset time after the level state of the ODT pin signal flips, the first intermediate signal changes from the first level to a second level; and after the preset time, the first intermediate signal changes from the second level back to the first level. The second control submodule is used to perform logical operations on the first intermediate signal to generate an ODT enable signal; wherein, the ODT enable signal includes: when the ODT enable signal is at a third level, controlling the ODT path to be in the enabled state; and when the ODT enable signal is at a fourth level, controlling the ODT path to be in the closed state.

4. The enable control circuit according to claim 3, characterized in that, The first level is high, the second level is low, the third level is high, and the fourth level is low.

5. The enable control circuit according to claim 3, characterized in that, The first control submodule includes a delay module and an XOR gate module; wherein, The delay module is used to delay the ODT pin signal by the preset time to obtain the ODT delayed signal; The XOR gate module is used to perform an XOR operation on the ODT pin signal and the ODT delay signal to obtain the first intermediate signal.

6. The enable control circuit according to claim 3, characterized in that, The control module further includes a two-input NOR gate; wherein... The selection module is further configured to generate a target achievement signal, which indicates that the clock cycle count value has reached the clock cycle count target value. The two-input NOR gate is used to perform NOR operation on the target achievement signal and the second setting signal to obtain a reset signal; wherein, the second setting signal is generated according to the setting of the mode register, and the second setting signal includes: when the second setting signal is at the fifth level, it indicates that the ODT function of the chip is turned off; when the second setting signal is at the sixth level, it indicates that the ODT function of the chip is turned on.

7. The enable control circuit according to claim 6, characterized in that, The fifth level is a high level, and the sixth level is a low level.

8. The enable control circuit according to claim 7, characterized in that, The second control submodule includes a latch; wherein the latch is an SR type latch, and the SR type latch is composed of two two-input NAND gates.

9. The enable control circuit according to claim 8, characterized in that, The first input terminal (S) of the latch is connected to the output terminal of the first control submodule and is used to receive the first intermediate signal; the second input terminal (R) of the latch is connected to the output terminal of the two-input NOR gate and is used to receive the reset signal. The output terminal (Q) of the latch is used to output the ODT enable signal; wherein, the ODT enable signal includes: when the first intermediate signal is low, the ODT enable signal must be high; when the first intermediate signal is high and the reset signal is low, the ODT enable signal must be low.

10. The enable control circuit according to claim 6, characterized in that, The control module further includes a first NOT gate module, a second NOT gate module, and a three-input OR gate; wherein... The first NOT gate module is used to receive the first intermediate signal and perform a NOT operation on the first intermediate signal to obtain the second intermediate signal; The second NOT gate module is used to receive the ODT enable signal and perform a NOT operation on the ODT enable signal to obtain a third intermediate signal; The three-input OR gate is used to perform an OR operation on the second setting signal, the second intermediate signal, and the third intermediate signal to generate a count reset signal.

11. The enable control circuit according to claim 10, characterized in that, The counting module includes an asynchronous binary counter, which includes several flip-flops connected sequentially.

12. The enable control circuit according to claim 11, characterized in that, The flip-flop is a D-type flip-flop; wherein, the input terminal (D) of each flip-flop is connected to its own second output terminal (Q-NOT), and the second output terminal (Q-NOT) of each flip-flop is connected to the clock terminal (CK) of the next flip-flop.

13. The enable control circuit according to claim 12, characterized in that, The trigger also includes a first output terminal (Q) and a reset terminal (RST); wherein, The first output terminal of the trigger is used to output a counting signal; The reset terminal of the trigger is used to receive the count reset signal, and when the count reset signal is high, to control the count signal to be low by resetting the trigger.

14. The enable control circuit according to claim 13, characterized in that, The counting module further includes a clock control module, wherein, The clock control module is used to receive the count reset signal and the clock signal, and generate an internal clock signal; wherein the internal clock signal is connected to the clock terminal (CK) of the first flip-flop among the plurality of flip-flops, and the internal clock signal includes: stopping the output of the internal clock signal when the count reset signal is at the seventh level; and outputting the internal clock signal when the count reset signal is at the eighth level.

15. The enable control circuit according to claim 14, characterized in that, The seventh level is a high level, and the eighth level is a low level.

16. The enable control circuit according to claim 14, characterized in that, The clock control module includes a third NOT gate module and a two-input AND gate; wherein... The third NOT gate module is used to receive the count reset signal and perform a NOT operation on the count reset signal to obtain a fourth intermediate signal; The two-input AND gate is used to receive the fourth intermediate signal and the clock signal, and to perform an AND operation on the fourth intermediate signal and the clock signal to obtain the internal clock signal.

17. The enable control circuit according to claim 13, characterized in that, The preset time is greater than the sum of the first delay, the second delay, and the third delay; wherein, The first delay represents the time interval between the first intermediate signal changing from the first level to the second level and the counting reset signal changing from the second level to the first level. The second delay represents the time interval between the change of the count reset signal from the second level to the first level and the change of the count signal from the first level to the second level. The third delay refers to the time interval between the change of the counting signal from the first level to the second level and the change of the reset signal from the second level back to the first level.

18. The enable control circuit according to claim 6, characterized in that, The selection module is further configured to receive the first setting signal and at least two characterization signals, and select one of the characterization signals from the at least two characterization signals as the target achievement signal according to the first setting signal; wherein the at least two characterization signals respectively characterize that the clock cycle count value has reached different clock cycle count target values.

19. The enable control circuit according to claim 18, characterized in that, The selection module is specifically configured to, when the first setting signal indicates that both the additional delay AL and the parity delay PL are not enabled, select the first characterization signal as the target achievement signal, and determine the clock cycle count target value as a first value; wherein the first value is greater than or equal to the column address write delay CWL minus 2; or... The selection module is specifically configured to, when the first setting signal indicates that both the additional delay AL and the parity delay PL are enabled, select a second characterization signal as the target achievement signal, and determine the clock cycle count target value as a second value; wherein the second value is greater than or equal to the sum of the column address write delay CWL, the additional delay AL, and the parity delay PL, minus 2; or, The selection module is specifically configured to, when the first setting signal indicates that the additional delay AL is enabled and the parity delay PL is not enabled, select a third characterization signal as the target achievement signal, and determine the clock cycle count target value as a third value; wherein the third value is greater than or equal to the sum of the column address write delay CWL and the additional delay AL minus 2; or, The selection module is specifically used to select a fourth characterization signal as the target achievement signal when the first setting signal indicates that the additional delay PL is enabled and the parity delay AL is not enabled, and to determine the clock cycle count target value as the fourth value; wherein the fourth value is greater than or equal to the sum of the column address write delay CWL and the parity delay PL minus 2. Wherein, the first characterization signal indicates that the clock cycle count value has reached the first value, the second characterization signal indicates that the clock cycle count value has reached the second value, the third characterization signal indicates that the clock cycle count value has reached the third value, and the fourth characterization signal indicates that the clock cycle count value has reached the fourth value.

20. The enable control circuit according to claim 19, characterized in that, The counting module includes six triggers, and the six triggers are connected sequentially; wherein, The first output terminal of the i-th flip-flop is used to output the i-th counting signal, where i is an integer greater than zero and less than or equal to six; The selection module is specifically used to receive the first setting signal, the fifth counting signal, and the sixth counting signal, and select the fifth counting signal and the sixth counting signal according to the first setting signal to generate the target achievement signal; wherein, the two input terminals of the selection module are respectively connected to the first output terminal of the fifth flip-flop and the first output terminal of the sixth flip-flop.

21. The enable control circuit according to claim 20, characterized in that, in, The selection module is further configured to, when the first setting signal indicates that both the additional delay AL and the parity delay PL are not enabled, determine that the target achievement signal is the fifth counting signal, and determine that the clock cycle count target value is the first value; or, The selection module is further configured to determine the target achievement signal as the sixth counting signal and determine the clock cycle count target value as the second value when the first setting signal indicates that at least one of the additional delay AL and the parity delay PL is enabled.

22. The enable control circuit according to claim 21, characterized in that, The first value is 32, and the second value is 64.

23. A semiconductor memory, characterized in that, Includes the enable control circuit as described in any one of claims 1 to 22.

24. The semiconductor memory according to claim 23, characterized in that, The semiconductor memory is a dynamic random access memory (DRAM) chip.

25. The semiconductor memory according to claim 24, characterized in that, The dynamic random access memory (DRAM) chip conforms to the DDR4 memory specification.

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