Interface chip, display module and display cabinet

Abstract

This invention discloses an interface chip, a display module, and a display enclosure. The interface chip includes, for example, a differential signal input circuit for connecting to the signal output circuit of a display control card, receiving an initial data signal and a clock signal, and parsing the initial data signal according to the clock signal; and a timing recovery circuit connected to the differential signal input circuit for receiving the parsed initial data signal and the clock signal, and performing data recovery processing on the parsed initial data signal based on the clock signal to obtain a recovery drive signal, wherein the recovery drive signal is used to control the display driver chip to illuminate the display unit array. This invention can solve the transmission problem existing between receiver cards and LED modules.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to an interface chip, a display module, and a display enclosure. Background Technology

[0002] LED displays are widely used in various fields due to their advantages such as low cost, low power consumption, high visibility, and flexible assembly. A common LED display control system mainly consists of a video source, a transmitting card, a receiving card, and the LED display itself. An LED display is generally composed of multiple LED modules spliced ​​together.

[0003] Currently, the connection between the receiver card and the LED module of the display screen is that the receiver card directly connects to the driver chip on the LED module. This connection method leads to many problems in the transmission between the receiver card and the LED module, such as: serious EMC issues, making it difficult to achieve low radiation; the transmission of signals requires a large number of IO pins in the FPGA of the receiver card. Since the number of FPGA IO pins is limited, it restricts the expansion capability of data signals, and limits data bandwidth and data transmission rate; in addition, too many signals will affect the selection of connectors and cables, and cannot reduce costs.

[0004] Therefore, providing a new transmission scheme between the receiver card and the LED module to avoid the aforementioned transmission problems between the existing receiver card and the LED module is a technical problem that this invention urgently needs to solve. Summary of the Invention

[0005] This invention discloses an interface chip, a display module, and a display enclosure, which can solve the transmission problem between existing receiver cards and LED modules, improve the EMC performance of transmitted signals, reduce the I / O pin consumption of the FPGA in the receiver card, improve data transmission bandwidth, and reduce the cost of connectors and cables.

[0006] To achieve the above objectives, this invention discloses an interface chip, comprising: a differential signal input circuit; and a timing recovery circuit connected to the differential signal input circuit; wherein the differential signal input circuit is used to connect to the signal output circuit of a display control card to receive an initial data signal and a clock signal input from the signal output circuit, and to perform parsing processing on the initial data signal according to the clock signal; the timing recovery circuit is used to receive the parsed initial data signal and the clock signal, and to perform data recovery processing on the parsed initial data signal based on the clock signal to obtain a recovery drive signal, wherein the recovery drive signal is used to control the display driver chip to light up the display unit array.

[0007] The above describes a method that connects the display driver chip and the display control card via an interface chip. This interface chip includes a differential signal input circuit and a timing recovery circuit. The differential signal input circuit directly connects to the display control card's signal output circuit to receive differential initial data signals and accompanying clock signals. Differential signal transmission improves EMC performance, enhances signal transmission quality, enables long-distance transmission, and offers good compatibility and scalability. The direct electrical connection of the interface chip to the display control card's signal output circuit reduces the I / O pin consumption of signal output circuits in the display control card, such as FPGAs, thus increasing data transmission bandwidth. Furthermore, the reduced number of signals does not affect the selection of connectors and cables, thereby lowering their cost. Therefore, this method can solve the transmission problems existing between the receiver card and the LED module.

[0008] In one embodiment of the present invention, the interface chip further includes: an output control circuit connected to the timing recovery circuit, for receiving the recovery drive signal and outputting a display drive signal to the display driver chip based on the recovery drive signal, so that the display driver chip can light up the display unit array based on the display drive signal.

[0009] By setting the output control circuit in the interface chip, the signal fine-tuning function is realized, which can cope with different transmission environments and has better applicability.

[0010] In one embodiment of the present invention, the timing recovery circuit includes: a control signal generation module electrically connected to the differential signal input circuit, configured to receive control signal generation information from the accompanying clock signal and the parsed initial data signal, and generate a recovery control signal based on the control signal generation information and the accompanying clock signal; and a data signal recovery module electrically connected to the differential signal input circuit, configured to receive data signal generation information from the accompanying clock signal and the parsed initial data signal, and recover a recovered data signal based on the accompanying clock signal and the data signal generation information; wherein, the recovery drive signal includes the recovery control signal and the recovered data signal.

[0011] By setting up a control signal generation module and a data signal recovery module in the timing recovery circuit, the LED driving signal recovery work can be completed in parallel, improving data processing efficiency. It can be adapted to different types of display driver chips and has a wider range of applications.

[0012] In one embodiment of the present invention, the differential signal input circuit is further configured to: perform frequency multiplication on the accompanying clock signal to obtain multiple clock signals; the control signal generation module includes: a drive clock signal generation unit, configured to receive the multiple clock signals and drive clock signal generation information from the control signal generation information, and select a target clock signal from the multiple clock signals to generate a drive clock signal based on the target clock signal and the drive clock signal generation information; and a drive control signal generation unit, configured to receive drive control signal generation information from the accompanying clock signal and the control signal generation information to generate a drive control signal based on the accompanying clock signal and the drive control signal generation information; wherein, the recovery control signal includes: the drive clock signal and the drive control signal.

[0013] By setting up a drive clock signal generation unit and a drive control signal generation unit in the control signal generation module, the recovery of the drive clock signal and the drive control signal can be completed in parallel, improving data processing efficiency.

[0014] In one embodiment of the present invention, the driving clock signal generation unit is further configured to: select a second target clock signal from the plurality of clock signals, and perform frequency division processing on the driving clock signal to obtain a frequency-divided driving clock signal, and perform register processing on the frequency-divided driving clock signal based on the second target clock signal to obtain a phase-adjusted driving clock signal.

[0015] The driving clock signal generation unit disclosed in this invention can perform phase adjustment on the driving clock signal, and has a wider range of applications.

[0016] In one embodiment of the present invention, the driving clock signal includes: a data clock signal, and the driving clock signal generating unit is further configured to: receive sampling mode information, and when the sampling mode information indicates that the sampling mode of the display driver chip is a single-edge sampling mode, use the data clock signal as a data sampling clock; when the sampling mode information indicates that the sampling mode of the display driver chip is a dual-edge sampling mode, perform frequency division processing on the data clock signal to obtain a frequency-divided data clock signal as a data sampling clock; and / or the driving clock signal includes: a grayscale clock signal, and the driving clock signal generating unit is further configured to: receive clock counting information to adjust the pulse width of the first clock cycle and the last clock cycle of the grayscale clock signal based on the clock counting information.

[0017] The driving clock signal generation unit disclosed in this invention can realize the configuration of sampling mode and / or grayscale clock pulse width modulation, and has a wider range of applications.

[0018] In one embodiment of the present invention, the driving clock signal generation unit includes: a clock selection subunit electrically connected to the differential signal input circuit, configured to receive the plurality of clock signals input by the differential signal input circuit, and select the target clock signal from the plurality of clock signals based on a selection instruction; a gating subunit electrically connected to the clock selection subunit and the differential signal input circuit, configured to receive the target clock signal and the driving clock signal generation information, and generate the driving clock signal by performing a logical AND operation on the driving clock signal generation information and the target clock signal; and / or the driving control signal generation unit includes: a clock counting subunit electrically connected to the differential signal input circuit. A path, used to receive the accompanying clock signal and count the accompanying clock signal to output a clock counting signal; an information selection subunit, electrically connected to the differential signal input circuit and the clock counting subunit, used to receive the drive control signal generation information and the clock counting signal, and select target control signal generation information from the drive control signal generation information based on the clock counting signal; a storage subunit, electrically connected to the differential signal input circuit and the information selection subunit, used to receive the accompanying clock signal and the target control signal generation information, and generate the drive control signal based on the accompanying clock signal and the target control signal generation information; and / or the data signal recovery module, including:

[0019] A counting unit, electrically connected to the differential signal input circuit, is used to receive the accompanying clock signal and count the accompanying clock signal to output a counting signal. A comparison unit, electrically connected to the differential signal input circuit and the counting unit, is used to receive the phase information and the counting signal in the data signal generation information, and compare the phase information and the counting signal to output a comparison signal. An output selection unit, electrically connected to the differential signal input circuit and the comparison unit, is used to receive the data content information and the comparison signal in the data signal generation information, and output the data content information when the comparison signal represents a target state. A register output unit, electrically connected to the differential signal input circuit and the output selection unit, is used to generate and output the data signal based on the accompanying clock signal and the data content information. The output selection unit is further used to receive the data signal output by the register output unit, and when the comparison signal represents a non-target state, output the data signal to the register output unit to control the register output unit to maintain the output of the data signal.

[0020] In one embodiment of the present invention, the timing recovery circuit includes: a data signal recovery module electrically connected to the differential signal input circuit, configured to receive SPI data signal generation information from the accompanying clock signal and the parsed initial data signal, and generate an SPI data signal as the recovery drive signal based on the accompanying clock signal and the SPI data signal generation information.

[0021] By incorporating a data signal recovery module into the timing recovery circuit, the recovery function of LED driving signals, such as SPI data signals, can be achieved, simplifying the device structure.

[0022] In one embodiment of the present invention, the data signal recovery module includes: a counting unit electrically connected to the differential signal input circuit, configured to receive the accompanying clock signal and count the accompanying clock signal to output a counting signal; a comparison unit electrically connected to the differential signal input circuit and the counting unit, configured to receive phase information and the counting signal in the SPI data signal generation information, and compare the phase information and the counting signal to output a comparison signal; an output selection unit electrically connected to the differential signal input circuit and the comparison unit, configured to receive SPI data content information and the comparison signal in the SPI data signal generation information, and output the SPI data content information when the comparison signal indicates a target state; and a register output unit electrically connected to the differential signal input circuit and the output selection unit, configured to generate and output the SPI data signal based on the accompanying clock signal and the SPI data content information; wherein, the output selection unit is further configured to receive the SPI data signal output by the register output unit, and output the SPI data signal to the register output unit when the comparison signal indicates a non-target state to control the register output unit to maintain the output of the SPI data signal.

[0023] In one embodiment of the present invention, the output control circuit includes: a delay adjustment module connected to the timing recovery circuit, configured to adjust the delay of the recovery drive signal according to a first control instruction to output a delay adjustment signal transmitted in the form of a TTL signal; and a current adjustment module connected to the delay adjustment module, configured to adjust the current intensity of the delay adjustment signal according to a second control instruction to output the display drive signal to the display driver chip.

[0024] By setting a delay adjustment module and a current adjustment module in the output control circuit, the signal delay fine-tuning function and current fine-tuning function can be realized, thus adapting to different transmission environments in the subsequent stage and having strong applicability.

[0025] In one embodiment of the present invention, the differential signal input circuit includes: a phase-locked loop (PLL) module; and a serial-to-parallel conversion module electrically connected to the PLL module and the timing recovery circuit; wherein the PLL module is configured to connect to the signal output circuit to receive the accompanying clock signal, perform frequency multiplication on the accompanying clock signal to obtain a reference clock signal, and output the reference clock signal and the accompanying clock signal; the serial-to-parallel conversion module is configured to connect to the signal output circuit to receive the initial data signal, the reference clock signal, and the accompanying clock signal, and perform serial-to-parallel conversion on the initial data signal based on the reference clock signal. The interface chip further includes: a signal input circuit for connecting to the display driver chip to receive return data; a signal processing circuit for processing the return data to generate a return data packet; and a differential signal output circuit for processing the return data packet to obtain a target return data packet, thereby outputting the target return data packet and the accompanying clock signal to the signal output circuit.

[0026] By incorporating a phase-locked loop (PLL) module and a serial-to-parallel conversion module into the differential signal input circuit, the signal output circuit of the display control card can be directly connected. This reduces the consumption of I / O pins in signal output circuits such as programmable logic devices, while ensuring high and stable signal quality, enabling long-distance transmission, and exhibiting good EMC performance. The PLL module can perform frequency multiplication on the accompanying clock signal as needed to adapt to different application environments. By incorporating a signal input circuit, signal processing circuit, and differential signal output circuit into the interface chip, the return data can be transmitted to the display control card, avoiding the need for an additional pair of LVDS transceivers in existing technologies to achieve data return. This reduces costs, simplifies board-level solutions, and improves applicability.

[0027] Furthermore, embodiments of the present invention disclose a display module, comprising: at least one of the aforementioned interface chips; and at least one display driver chip, which is electrically connected to the at least one interface chip.

[0028] Furthermore, embodiments of the present invention disclose a display cabinet, a display control card, including: a signal output circuit; and any of the aforementioned display modules, electrically connected to the signal output circuit.

[0029] The above technical solution has the following advantages or beneficial effects: By setting an interface chip connected between the display driver chip and the display control card, and the interface chip is equipped with a differential signal input circuit and a timing recovery circuit, the differential signal input circuit is directly connected to the signal output circuit of the display control card to receive the initial data signal and the accompanying clock signal in differential form. Since the signal is transmitted in differential form, the EMC effect of the transmitted signal can be improved, the signal transmission quality can be improved, long-distance transmission can be achieved, and the compatibility and scalability are good. The interface chip is directly electrically connected to the signal output circuit of the display control card through the differential signal input circuit, which can reduce the consumption of IO pins in the signal output circuit of the display control card, such as FPGA, which is conducive to improving the data transmission bandwidth. Moreover, the reduction in the number of signals does not affect the selection of connectors and wires, thereby reducing the cost of connectors and wires. Therefore, the transmission problem between the existing receiver card and LED module can be solved. Attached Figure Description

[0030] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1a This is a schematic diagram of a display module disclosed in one embodiment of the present invention.

[0032] Figure 1b This is a schematic diagram of another structure of the display module disclosed in one embodiment of the present invention.

[0033] Figure 2 This is a schematic diagram of an interface chip disclosed in one embodiment of the present invention.

[0034] Figure 3 This is a schematic diagram of another structure of the interface chip disclosed in one embodiment of the present invention.

[0035] Figure 4 This is a schematic diagram showing a connection between the differential signal input circuit and the timing recovery circuit in an interface chip disclosed in an embodiment of the present invention.

[0036] Figure 5 This is a schematic diagram illustrating another connection between the differential signal input circuit and the timing recovery circuit in an interface chip disclosed in an embodiment of the present invention.

[0037] Figure 6 This is another schematic diagram showing the connection of the differential signal input circuit and the timing recovery circuit in an interface chip disclosed in an embodiment of the present invention.

[0038] Figure 7 This is a schematic diagram of an example circuit structure of a drive clock signal generation unit in an interface chip disclosed in an embodiment of the present invention.

[0039] Figure 8 This is an example circuit diagram of a drive control signal generation unit in an interface chip disclosed in an embodiment of the present invention.

[0040] Figure 9 This is an example circuit diagram of a data signal recovery module in an interface chip disclosed in one embodiment of the present invention.

[0041] Figure 10 This is a schematic diagram of another structure of the interface chip disclosed in one embodiment of the present invention.

[0042] Figure 11 This is an example circuit diagram of a delay adjustment module in an interface chip disclosed in an embodiment of the present invention.

[0043] Figure 12 This is a schematic diagram of another structure of the display module disclosed in one embodiment of the present invention.

[0044] Figure 13 This is a schematic diagram of a display cabinet structure disclosed in one embodiment of the present invention. Detailed Implementation

[0045] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present invention can be combined with each other. The present invention will be described below with reference to the accompanying drawings and embodiments.

[0046] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0047] It should also be noted that the division of multiple embodiments in this invention is only for the convenience of description and should not constitute a special limitation. Features in various embodiments can be combined and referenced in each other without contradiction.

[0048] See Figure 1a One embodiment of the present invention discloses a display module. For example... Figure 1a As shown, the display module 100 includes, for example, an interface chip 10 and a display driver chip 20, with the display driver chip 20 electrically connected to the interface chip 10. The number of interface chips 10 is, for example, at least one, and the number of display driver chips 20 is, for example, at least one, with each interface chip 10 corresponding to at least one display driver chip 20. Figure 1a The interface chip 10 and display driver chip 20 shown are one in number, but this embodiment is not limited to this. Figure 1b As shown, the display module 100 includes multiple interface chips 10 and display driver chips 20, for example, three. Each interface chip 10 and each display driver chip 20 is electrically connected in a one-to-one correspondence. The display driver chips 20 are used to illuminate the display unit array 30; that is, multiple display driver chips 20 are electrically connected to the display unit array 30. Furthermore, it is worth mentioning that this invention does not limit one interface chip 10 to one display driver chip 20. One interface chip 10 can connect to multiple display driver chips 20, for example, connecting a string of display driver chips 20, where a string of display driver chips 20 includes multiple cascaded display driver chips 20; or connecting multiple strings of display driver chips 20, where each string of display driver chips 20 includes multiple cascaded display driver chips 20.

[0049] Specifically, the display module 100 is, for example, an LED module. The interface chip 10 is, for example, an ASIC (Application Specific Integrated Circuit) chip. The display driver chip 20 can be a chip integrating row decoding and column driving, or a separate column driver chip. When the display driver chip 20 is a separate column driver chip, the display module 100 also needs to include a row decoding chip. For example, the column driver chip is a 74HC595 chip or an SMT5026 chip, and the row decoding chip is, for example, a 3-to-8 decoder. The display unit array 30 is, for example, an LED dot array.

[0050] like Figure 2 As shown, one embodiment of the present invention discloses an interface chip 10, which includes, for example, a differential signal input circuit 11 and a timing recovery circuit 13, wherein the timing recovery circuit 13 is electrically connected to the differential signal input circuit 11.

[0051] The differential signal input circuit 11 is connected to the signal output circuit of the display control card, such as a programmable logic device, to receive the initial data signal and the accompanying clock signal input from the signal output circuit, and to perform parsing processing on the initial data signal according to the accompanying clock signal. The timing recovery circuit 13 receives the parsed initial data signal and the accompanying clock signal, and performs data recovery processing on the parsed initial data signal based on the accompanying clock signal to obtain a recovery drive signal, wherein the recovery drive signal is used to control the display driver chip 20 to light up the display unit array 30.

[0052] The display control card mentioned herein is, for example, a receiver card or scanner card in an LED display control system. For instance, in addition to signal output circuitry, the display control card includes a memory and network port electrically connected to the signal output circuitry. The signal output circuitry may be a programmable logic device, such as an FPGA (Field-Programmable Gate Array), a single-chip microcomputer, or a microcontroller; or other microprocessors with certain data processing and computing capabilities, such as ARM processors and DSP processors. The memory may be, for example, DDR memory. This embodiment of the invention does not limit the display control card to a receiver card or scanner card in an LED display control system; it can also be a transmitter card in the LED display control system, or other devices capable of processing video sources and outputting data and clock signals. Furthermore, the aforementioned programmable logic device can be replaced with an ASIC circuit or an integrated chip. It is worth noting that this embodiment does not limit the display control card to a single integrated structure; it may also include a hub adapter board.

[0053] The initial data signal and accompanying clock signal mentioned here are, for example, differential signals, such as LVDS signals, mini-LVDS signals, HDMI signals, etc. The LVDS signal mentioned can be understood as a signal transmitted using a standard LVDS transmission protocol, such as signals transmitted using a 4:1 LVDS transmission protocol, a 5:1 LVDS transmission protocol, a 6:1 LVDS transmission protocol, a 7:1 LVDS transmission protocol, or an 8:1 LVDS transmission protocol. Among these, the 7:1 LVDS transmission protocol is more widely used than other protocols. Furthermore, because it uses a standard LVDS transmission protocol, there is no need for the front-end display control card to have a paired LVDS transmitter, which can standardize the display module interface and improve the compatibility and scalability of the display module.

[0054] The mentioned recovery drive signals are, for example, TTL signal types. These recovery drive signals can be understood as LED drive signals used to drive LED dot arrays. For instance, they could be SPI-like signals, including: data clock signal DCLK, latch signal LAT, grayscale clock signal GCLK, decoder signals ABCDE, and RGB data signals. Alternatively, they could be SPI data signals, including: SPI data input signal SPI_mosi, SPI data output signal SPI_miso, SPI clock signal SPI_clk, and SPI chip select signal SPI_cs. SPI data signals could include, for example, calibration data, control signals, and interaction signals. Or, the mentioned recovery drive signals could include both the aforementioned SPI-like signals and SPI data signals, specifically: data clock signal DCLK, latch signal LAT, grayscale clock signal GCLK, decoder signals ABCDE, RGB data signals, SPI data input signal SPI_mosi, SPI data output signal SPI_miso, SPI clock signal SPI_clk, and SPI chip select signal SPI_cs.

[0055] The initial data signal mentioned above and the parsed initial data signal contain the same content, such as LED driver signal generation information, only the signal format differs. The LED driver signal generation information could be, for example, the aforementioned SPI-like signal generation information, or the aforementioned SPI data signal generation information, or both. For instance, the SPI-like signal generation information might include: clock signal generation information for generating the data clock signal DCLK and the grayscale clock signal GCLK; control signal generation information for generating the latch signal LAT and the decoder signals ABCDE; and RGB data signal information for recovering the RGB data signal. The SPI signal generation information might include, for example, SPI data signal generation information for generating the SPI data input signal SPI_mosi, the SPI data output signal SPI_miso, the SPI clock signal SPI_clk, and the SPI chip select signal SPI_cs.

[0056] The interface chip 10 is connected between the display driver chip 20 and the display control card. The interface chip 10 includes a differential signal input circuit and a timing recovery circuit. The differential signal input circuit is directly connected to the signal output circuit in the display control card to receive the initial data signal and the accompanying clock signal. These signals are, for example, LVDS signals. Due to the high bandwidth of LVDS, a single LVDS clock signal and a single LVDS data signal can transmit up to 1Gbps of data. Therefore, the signal output circuit of the display control card, such as an FPGA, only needs four I / O pins to output more data. For example, the maximum data transmission speed of the front-end can support 30Mbps, so it is estimated that 33 sets of DAT signals can be transmitted. A. This saves 29 data signals, significantly reducing the number of FPGA I / O pins used. This reduces the I / O pin consumption of the signal output circuit in the display control card, which helps improve data transmission bandwidth. At the same time, it avoids the use of paired LVDS transceivers between the receiver card and the LED module in existing related technologies, reducing the cost of connection cables between the display control card and the display module, improving the signal transmission quality between the display control card and the display module, enabling long-distance transmission, improving the EMC effect of signal transmission, avoiding the phase deviation of the recovery clock and recovery data that may occur due to oversampling required by using LVDS transceivers, and even leading to data loss. It has good compatibility, strong scalability, and reduces the design complexity of the display module.

[0057] In other embodiments of the present invention, based on Figure 2 The interface chip shown is, for example Figure 3 As shown, the interface chip 10 may also include, for example, an output control circuit 15 and a connection timing recovery circuit 13.

[0058] The output control circuit 15 is used to receive the recovery drive signal and output a display drive signal to the display driver chip based on the recovery drive signal, so that the display driver chip can light up the display unit array based on the display drive signal.

[0059] The content of the display drive signal mentioned is the same as that of the recovery drive signal mentioned, including, for example, SPI-like signals and / or SPI data signals.

[0060] Figure 3 The interface chip shown is compared to Figure 2 The interface chip shown also includes an output control circuit 15. The recovery drive signal generated by the timing recovery circuit 13 can be fine-tuned by the output control circuit, and then the output control circuit 15 outputs the display drive signal to the display driver chip. That is, the interface chip 10 can further realize the signal fine-tuning function, so as to cope with different transmission environments and have better applicability.

[0061] It is worth mentioning that when the recovery drive signal does not require fine-tuning, the timing recovery circuit 13 can directly output the recovery drive signal as the display drive signal to the display driver chip.

[0062] In other embodiments of the invention, such as Figure 4 As shown, the differential signal input circuit 11 disclosed in the foregoing embodiment includes, for example, a phase-locked loop module 111 and a serial-to-parallel conversion module 113, wherein the serial-to-parallel conversion module 113 is electrically connected to the phase-locked loop module 111 and the timing recovery circuit 13.

[0063] The phase-locked loop module 111 is connected to the signal output circuit to receive the accompanying clock signal, perform frequency multiplication on the accompanying clock signal to obtain a reference clock signal, and output the reference clock signal and the accompanying clock signal. The serial-to-parallel conversion module 113 is connected to the signal output circuit to receive the initial data signal, the reference clock signal, and the accompanying clock signal, perform serial-to-parallel conversion on the initial data signal based on the reference clock signal to generate the parsed initial data signal, and output the parsed initial data signal and the accompanying clock signal to the timing recovery circuit 13.

[0064] Specifically, the phase-locked loop module 111, or PLL, includes, for example, a phase comparator (PD), a low-pass filter electrically connected to the phase comparator, a voltage-controlled oscillator (VCO) electrically connected to the low-pass filter, and a frequency divider and a frequency multiplier electrically connected between the VCO and the phase comparator. The PLL module 111 mainly implements the reception of the accompanying clock signal and the frequency multiplication and division processing functions of the accompanying clock signal. The serial-to-parallel conversion module 113 includes, for example, a shift register. The serial-to-parallel conversion module 113 mainly implements the conversion of serial data into parallel data for output.

[0065] For example, if the frequency of the accompanying clock signal is 10MHz and the frequency of the initial data signal is 70MHz, the phase-locked loop module 111 performs frequency multiplication on the 10MHz accompanying clock signal to obtain a reference clock signal. The frequency of the reference clock signal is the same as the frequency of the initial data signal, which is 70MHz. Taking the 7:1 LVDS transmission protocol mentioned earlier as an example, the initial data signal and the reference clock signal received by the serial-to-parallel conversion module 113 have the same frequency. Therefore, a set of initial data signals, i.e., a differential signal pair, can be sampled based on the reference clock signal, and then a 7-bit parsed initial data signal, such as parallel data and the accompanying clock signal, can be output, thereby completing the serial-to-parallel conversion.

[0066] By setting a phase-locked loop module 111 and a serial-to-parallel conversion module 113 in the differential signal input circuit 11, the signal output circuit of the display control card can be directly connected, thereby reducing the consumption of IO pins in the signal output circuit, and the signal quality is high and stable, enabling long-distance transmission and having good EMC performance. The phase-locked loop module can perform frequency multiplication processing on the accompanying clock signal as needed to cope with different application environments.

[0067] In other embodiments of the invention, such as Figure 5 As shown, the timing recovery circuit 13 includes, for example, a control signal generation module 133 and a data signal recovery module 135.

[0068] The control signal generation module 133 is electrically connected to the differential signal input circuit 11 and is used to receive control signal generation information from the accompanying clock signal and the parsed initial data signal, and generate a recovery control signal based on the control signal generation information and the accompanying clock signal. The data signal recovery module 135 is electrically connected to the differential signal input circuit 11 and is used to receive data signal generation information from the accompanying clock signal and the parsed initial data signal, and recover a recovered data signal based on the accompanying clock signal and the data signal generation information. The recovered data signal includes, for example, RGB data signals and / or SPI data signals; wherein, the recovery drive signal includes the recovery control signal and the recovered data signal.

[0069] The control signal generation module 133 is, for example, connected to the phase-locked loop module 111 and the serial-to-parallel conversion module 113 of the differential signal input circuit 11. The data signal recovery module 135 is, for example, connected to the serial-to-parallel conversion module 113 of the differential signal input circuit 11. By setting the control signal generation module 133 and the data signal recovery module 135 in the timing recovery circuit 13, the recovery of the LED driving signal can be completed in parallel, improving data processing efficiency. This allows it to be adapted to different types of display driver chips, thus broadening its application range.

[0070] Furthermore, the differential signal input circuit 11, such as the phase-locked loop module 111, is also used to: perform frequency multiplication on the accompanying clock signal to obtain multiple clock signals. Figure 6 As shown, the control signal generation module 133 includes, for example, a drive clock signal generation unit 1331 and a drive control signal generation unit 1333.

[0071] The drive clock signal generation unit 1331 is electrically connected to the differential signal input circuit 11 and is used to receive the drive clock signal generation information from the plurality of clock signals and the control signal generation information, and select a target clock signal from the plurality of clock signals to generate a drive clock signal based on the target clock signal and the drive clock signal generation information. The drive clock signal includes, for example, a data clock signal and a grayscale clock signal. The drive control signal generation unit 1333 is electrically connected to the differential signal input circuit 11 and is used to receive the drive control signal generation information from the accompanying clock signal and the control signal generation information, and generate a drive control signal based on the accompanying clock signal and the drive control signal generation information. The drive control signal includes, for example, a latch signal and a decode signal. The recovery control signal includes the drive clock signal and the drive control signal.

[0072] For example, such as Figure 6 As shown, the drive clock signal generation unit 1331 is electrically connected to the phase-locked loop module 111 and the serial-to-parallel conversion module 113 of the differential signal input circuit 11. The drive control signal generation unit 1333 is electrically connected to the serial-to-parallel conversion module 113 of the differential signal input circuit 11. The target clock signal mentioned is, for example, one of multiple clock signals, selected by the user through a configuration register.

[0073] By setting a drive clock signal generation unit 1331 and a drive control signal generation unit 1333 in the control signal generation module 133, the recovery of the drive clock signal and the drive control signal can be completed in parallel, thereby improving data processing efficiency.

[0074] Specifically, the frequency of the aforementioned target clock signal and the frequency of the aforementioned reference clock signal may be the same or different. The aforementioned drive clock signal generation information includes, for example, grayscale clock signal generation information GCLK_EN (representing the on-time of the grayscale clock signal) and data clock signal generation information DCLK_EN (representing the on-time of the data clock signal). The aforementioned drive control signal generation information includes, for example, latch signal generation information DIN, decoder signal A generation information, decoder signal B generation information, decoder signal C generation information, decoder signal D generation information, and decoder signal E generation information. The mentioned data signal generation information is, for example, RGB signal information and / or SPI signal generation information. Correspondingly, the mentioned data signals are, for example, RGB data signals and / or SPI data signals. The RGB signal information is, for example, grayscale data content, and the SPI signal generation information is, for example, correction data generation information, control signal generation information, or interactive signal generation information, i.e., the SPI data signals are, for example, correction data, control signals, and interactive signals. The various signal generation information mentioned above can be understood as indicating when a rising edge and when a falling edge are generated, thereby generating corresponding signals.

[0075] Furthermore, the drive clock signal generation unit 1331 is also configured to: select a second target clock signal from the plurality of clock signals, and perform frequency division processing on the drive clock signal to obtain a frequency-divided drive clock signal, and perform registration processing on the frequency-divided drive clock signal based on the second target clock signal to obtain a phase-adjusted drive clock signal. The second target clock signal mentioned above is, for example, the highest frequency clock signal output by the phase-locked loop module 111. The drive clock signal generation unit 1331 disclosed in this invention can realize phase adjustment of the drive clock signal and has a wider range of applications.

[0076] Furthermore, the driving clock signal includes, for example, a data clock signal. The driving clock signal generation unit 1331 is further configured to: receive sampling mode information, and when the sampling mode information indicates that the sampling mode of the display driver chip is a single-edge sampling mode, use the data clock signal as a data sampling clock; when the sampling mode information indicates that the sampling mode of the display driver chip is a dual-edge sampling mode, perform frequency division processing on the data clock signal to obtain a frequency-divided data clock signal as a data sampling clock. The frequency division processing mentioned is, for example, a two-way frequency division. The driving clock signal generation unit disclosed in this invention can implement sampling mode configuration and has a wider range of applications.

[0077] Furthermore, the driving clock signal includes, for example, a grayscale clock signal. The driving clock signal generation unit 1331 is also configured to: receive clock counting information to adjust the pulse width of the first and last clock cycles of the grayscale clock signal based on the clock counting information. This can be understood as controlling the number of grayscale clock signals contained in the first and last clock cycles through the clock counting information, thereby enabling pulse width modulation. The clock counting information involved here is, for example, obtained from a configuration register. The driving clock signal generation unit disclosed in this invention can realize grayscale clock pulse width modulation and has a wider range of applications.

[0078] It is worth mentioning that the embodiments of the present invention do not limit the driving clock signal generation unit 1331 to simultaneously having the aforementioned functions. The driving clock signal generation unit 1331 may have any one of the aforementioned functions or any combination of the aforementioned functions.

[0079] Further, the driving clock signal generation unit 1331 includes, for example, a clock selection subunit and a gating subunit. The clock selection subunit is electrically connected to the differential signal input circuit 11 and is used to receive the plurality of clock signals input by the differential signal input circuit 11, and select the target clock signal from the plurality of clock signals based on a selection instruction. The gating subunit is electrically connected to the clock selection subunit and the differential signal input circuit 11, and is used to receive the target clock signal and the driving clock signal generation information, and generate the driving clock signal by performing a logical AND operation on the driving clock signal generation information and the target clock signal.

[0080] For example, such as Figure 7 As shown, the clock selection subunit includes a multiplexer (MUX), which is electrically connected, for example, to the phase-locked loop module 111 in the differential signal input circuit 11 to receive multiple clock signals. The gating subunit includes an AND gate, which is, for example, electrically connected to the serial-to-parallel conversion module 113 in the differential signal input circuit 11. The selection instruction mentioned comes, for example, from the configuration register. The driving clock signals include, for example, a data clock signal DCLK and a grayscale clock signal GCLK, wherein the grayscale clock signal GCLK can be used as an external reference clock for the display driver chip, or it can be used directly as the clock for the display circuit.

[0081] Further, the drive control signal generation unit 1333 includes, for example, a clock counting subunit, an information selection subunit, and a storage subunit. The clock counting subunit is electrically connected to the differential signal input circuit 11, for example, to the serial-to-parallel conversion module 113, and is used to receive the accompanying clock signal and count the accompanying clock signal to output a clock counting signal. The information selection subunit is electrically connected to the differential signal input circuit 11, for example, to the serial-to-parallel conversion module 113 and the clock counting subunit, and is used to receive the drive control signal generation information and the clock counting signal, and select target control signal generation information from the drive control signal generation information based on the clock counting signal to output. The storage subunit is electrically connected to the differential signal input circuit 11, for example, to the serial-to-parallel conversion module 113 and the information selection subunit, and is used to receive the accompanying clock signal and the target control signal generation information, and generate the drive control signal based on the accompanying clock signal and the target control signal generation information.

[0082] For example, the clock counting subunit includes a counter, the information selection subunit includes a multiplexer, and the storage subunit 1333 includes a DFF register. The drive control signal generation information includes latch signal generation information DIN[0]-DIN[3] for generating the latch signal LAT and decoding signal generation information for generating the decoding signal AE. The clock counting subunit 1331 counts the accompanying clock signal, for example, by counting the period of the accompanying clock signal. Initially, the clock counting signal is "0". After one period of the accompanying clock signal, the clock counting subunit 1331 counts the clock counting signal to "1", and so on.

[0083] The following is combined Figure 8 The example given is the generation of a latch signal LAT by the drive control signal generation unit 1333. However, this embodiment does not limit the structure of the drive control signal generation unit 1333 to any particular form. Figure 8 The structure shown.

[0084] like Figure 8As shown, the clock counting subunit, such as a counter, receives the input clock signal SCLK and then counts the clock signal SCLK to obtain a clock count signal, which is output to the information selection subunit, such as a multiplexer MUX. The multiplexer MUX receives latch signal generation information DIN[0]-DIN[3] and selects one from the latch signal generation information DIN[0]-DIN[3] as the target latch signal generation information output according to the clock count signal. For example, when the clock count signal is 0, DIN[0] is selected as the target latch signal generation information output, and when the clock count signal is 1, DIN[1] is selected as the target latch signal generation information output, and so on. The storage subunit, such as a DFF register, receives the clock signal and the target latch signal generation information to generate a latch signal LAT and outputs it.

[0085] Furthermore, the data signal recovery module 135 includes, for example, a counting unit, a comparison unit, an output selection unit, and a register output unit.

[0086] The counting unit is electrically connected to the differential signal input circuit 11, for example, to the serial-to-parallel conversion module 113, and is used to receive the accompanying clock signal and count the accompanying clock signal to output a counting signal. The comparison unit is electrically connected to the differential signal input circuit 11, for example, to the serial-to-parallel conversion module 113 and the counting unit, and is used to receive the phase information and the counting signal from the data signal generation information, and compare the phase information and the counting signal to output a comparison signal. The output selection unit is electrically connected to the differential signal input circuit 11, for example, to the serial-to-parallel conversion module 113 and the comparison unit, and is used to receive the data content information and the comparison signal from the data signal generation information, and output the data content information when the comparison signal represents a target state. The register output unit is electrically connected to the differential signal input circuit 11, for example, to the serial-to-parallel conversion module 113 and the output selection unit, and is used to generate and output the data signal based on the accompanying clock signal and the data content information. The output selection unit is further configured to receive the data signal output by the register output unit, and when the comparison signal indicates a non-target state, output the data signal to the register output unit to control the register output unit to maintain the output of the data signal.

[0087] For example, the counting unit may include a counter, the comparison unit may include a comparator, the output selection unit may include a multiplexer, and the register output unit may include a DFF register. The counting unit counts the accompanying clock signal, for example, by counting the period of the accompanying clock signal. Initially, the counting signal is "0", and after one period of the accompanying clock signal, the counting signal becomes "1", and so on. The data signal generation information includes, for example, RGB signal information and phase information for generating RGB data signals, and / or SPI data signal generation information and phase information for generating SPI data signals.

[0088] The following is combined Figure 9 This example illustrates the use of RGB data signals generated by the data signal recovery module 135, but this embodiment does not limit the data signal recovery module 135 to... Figure 9 The structure shown.

[0089] like Figure 9 As shown, the counting unit, such as a counter, is electrically connected to the differential signal input circuit 11 to receive the accompanying clock signal SCLK, and counts the accompanying clock signal SCLK to output a counting signal to the comparison unit, such as a comparator. The comparator is electrically connected to the differential signal input circuit 11, receives the phase information PHASE and the counting signal from the data signal generation information, and compares the phase information PHASE and the counting signal. When the two are the same, a comparison signal "1" is output, where "1" is the aforementioned target state. When the two are different, a comparison signal "0" is output, where "0" is the aforementioned non-target state. The output selection unit, such as a multiplexer MUX, is connected to the differential signal input circuit 11 and receives the input RGB signal information RGB_DATA[2:0]. When the multiplexer MUX receives a comparison signal of "1", it outputs the input RGB_DATA[2:0] to a register output unit, such as the DFF register. The DFF register then generates the RGB data signal TTL_RGB[2:0] based on the accompanying clock signal SCLK and RGB_DATA[2:0]. The multiplexer MUX also receives the RGB data signal TTL_RGB[2:0] output from the DFF register. When the multiplexer MUX receives a comparison signal of "0", it outputs the RGB data signal TTL_RGB[2:0] to the DFF register, thus maintaining the output of the RGB data signal TTL_RGB[2:0]. This can be understood as updating the RGB data signal when the counting signal equals the phase information PHASE, and otherwise maintaining the RGB data signal.

[0090] It is worth mentioning that the embodiments of the present invention do not limit the structure of the drive clock signal generation unit 1331, the drive control signal generation unit 1333, and the data signal recovery module 135. In other embodiments of the present invention, any one or any two of the drive clock signal generation unit 1331, the drive control signal generation module 1333, and the data signal recovery module 133 may adopt other structures that achieve the same functions as described above.

[0091] In other embodiments of the present invention, the parsed initial data signal may only include SPI data signal generation information. As can be seen from the foregoing description, the SPI data signal is generated in the data signal recovery module 135 of the timing recovery circuit 13. Therefore, when the parsed initial data signal only includes SPI data signal generation information, the timing recovery circuit 13 may also only include the data signal recovery module 135, electrically connected to the differential signal input circuit 11, for example, electrically connected to the serial-to-parallel conversion module 113, for receiving the accompanying clock signal and the SPI data signal generation information in the parsed initial data signal, and generating the SPI data signal as the recovery drive signal based on the accompanying clock signal and the SPI data signal generation information.

[0092] The data signal recovery module 135 mentioned here has the same structure as described above; it only requires replacing the RGB signal information with SPI data signal generation information. Figure 9 For example, simply put Figure 9 The RGB_DATA[2:0] shown can be replaced with SPI_DATA, and the phase information PHASE can be replaced with the phase information of the SPI data signal to generate the SPI data signal. By setting a data signal recovery module in the timing recovery circuit, the recovery function of LED driving signals such as SPI data signals can be realized, simplifying the device structure.

[0093] In other embodiments of the invention, such as Figure 10 As shown, the output control circuit 15 includes, for example, a delay adjustment module 151 and a current adjustment module 153.

[0094] The delay adjustment module 151 is connected to the timing recovery circuit 13 and is used to adjust the delay of the recovery drive signal according to a first control command, thereby outputting a delay adjustment signal, such as a TTL signal. The current adjustment module 153 is connected to the delay adjustment module 151 and is used to adjust the current intensity of the delay adjustment signal according to a second control command, thereby outputting the display drive signal to the display driver chip 20.

[0095] The first and second control instructions mentioned above can be understood as instructions issued through the configuration register. The delay adjustment signals and recovery drive signals are of the same type, except that some signals undergo delay processing. For example, the aforementioned delayed drive signals include: SPI-like signals: data clock signal DCLK, latch signal LAT, grayscale clock signal GCLK, decoder signals ABCDE, RGB data signals; and / or SPI data signals: SPI data input signal SPI_mosi, SPI data output signal SPI_miso, SPI clock signal SPI_clk, and SPI chip select signal SPI_cs.

[0096] The aforementioned delay adjustment of the recovery drive signal can be understood as adjusting the delay of at least one of the following: data clock signal DCLK, latch signal LAT, grayscale clock signal GCLK, decoder signal ABCDE, RGB data signal, SPI data input signal SPI_mosi, SPI data output signal SPI_miso, SPI clock signal SPI_clk, and SPI chip select signal SPI_cs.

[0097] The adjustment of the current intensity of the delay adjustment signal mentioned above can be understood as adjusting the current intensity of at least one of the following: data clock signal DCLK, latch signal LAT, grayscale clock signal GCLK, decoder signal ABCDE, RGB data signal, SPI data input signal SPI_mosi, SPI data output signal SPI_miso, SPI clock signal SPI_clk, and SPI chip select signal SPI_cs.

[0098] It should be noted that when the recovery drive signal does not require delay adjustment but requires current intensity adjustment, the delay adjustment module can be inactive, and the recovery drive signal can be directly output as the delay adjustment signal to the current adjustment module. When the recovery drive signal requires delay adjustment but not current intensity adjustment, the delay adjustment module operates, delaying the signal in the recovery drive signal that requires delay adjustment to obtain the delay adjustment signal. The current adjustment module does not operate and directly outputs the delay adjustment signal as the display drive signal. When the recovery drive signal requires neither delay adjustment nor current intensity adjustment, both the delay adjustment module and the current adjustment module can be inactive. That is, the delay adjustment module outputs the recovery drive signal as the delay adjustment signal, and the current adjustment module outputs the delay adjustment signal directly as the display drive signal.

[0099] For example, under normal circumstances, decoded signal A and decoded signal B are output simultaneously. However, due to external PCB routing issues, decoded signal A is output faster than decoded signal B. In order to achieve simultaneous output, the delay adjustment module 151 adjusts the delay of decoded signal A according to the first control instruction until it is output simultaneously with decoded signal B. Figure 11 As shown, the delay adjustment module 151 includes, for example, a delay adjustment unit corresponding to each signal. The delay adjustment unit consists of, for example, multiple cascaded D-type flip-flops (DFFs) and a multiplexer (MUX) connected to the output terminal Q of each D-type flip-flop (DFF). Each D-type flip-flop can achieve a fixed time delay, for example, 0.1us. The first control command tells the multiplexer (MUX) to use the output of the third-stage D-type flip-flop as the output signal. Then, the decoded signal A enters the first to third-stage D-type flip-flops to achieve a 0.3us delay. Based on the first control command, the multiplexer outputs the output signal of the third-stage D-type flip-flop as the delayed-adjusted decoded signal SDOUT.

[0100] For example, signal loss during transmission can weaken the signal. To improve the signal's anti-interference capability, the current regulation module 153 can enhance the signal current. The current regulation module 153 includes, for example, multiple regulation units corresponding to multiple signals. Each regulation unit includes, for example, multiple current sources and a switching element connected to each current source. The opening and closing of the switching element is controlled by a second control command, thereby regulating the current intensity of the signal received by the regulation unit.

[0101] By setting a delay adjustment module and a current adjustment module in the output control circuit, the signal delay fine-tuning function and current fine-tuning function can be realized, thus adapting to different transmission environments in the subsequent stage and having strong applicability.

[0102] In other embodiments of the invention, such as Figure 12 As shown, the interface chip 10 may also include, for example, a signal input circuit 171, a signal processing circuit 173, and a differential signal output circuit 175.

[0103] The signal input circuit 171 is connected to the display driver chip 20 and is used to receive the feedback data output by the display driver chip 20. The signal processing circuit 173 is connected to the signal input circuit 171 and is used to process the feedback data to generate a feedback data packet. The differential signal output circuit 175 is connected to the signal processing circuit 173 and is used to process the feedback data packet to obtain a target feedback data packet, thereby outputting the target feedback data packet and the accompanying clock signal to the signal output circuit, such as a programmable logic device.

[0104] The returned data mentioned includes, for example, inspection data output by the display driver chip 20. This inspection data includes information such as defective LEDs, open circuits, short circuits, and on-state voltage values. The returned data may also include SPI interface data from the display driver chip. The processing mentioned includes, for example, the process of assembling packets according to a protocol.

[0105] For example, the signal input circuit 171 includes a clock gating unit and multiple D-type flip-flops. The data input terminals of the multiple D-type flip-flops are connected to the display driver chip 20 to receive the input feedback data, i.e., multiple TTL signals. The data output terminals of the multiple D-type flip-flops are connected to the signal processing circuit 173. The clock gating unit is connected to the display driver chip to receive the data enable signal and the clock signal. The output terminal of the clock gating unit is connected to the clock input terminal of each D-type flip-flop. Through the cooperation of the clock gating unit and the multiple D-type flip-flops, the reception of feedback data transmitted in the form of TTL signals can be realized. The clock gating unit adopts existing clock gating technology.

[0106] For example, the signal processing circuit 173 includes, for instance, a counter and a multiplexer connected to the counter. One input of the multiplexer is connected to the signal input circuit 171 to receive the returned data. Another input of the multiplexer receives the packet header data, and yet another input of the multiplexer receives the packet tail data. Thus, the counter and the multiplexer work together to perform packet processing on the returned data, that is, to add packet headers and packet tails to complete the packaging process.

[0107] For example, the differential signal output circuit 175 includes, for instance, a D-type flip-flop and an LVDS driver connected to the D-type flip-flop, as well as a buffer and an LVDS driver connected to the buffer. The D-type flip-flop and the LVDS driver connected to the D-type flip-flop can realize the return of the target return data packet transmitted in the form of an LVDS signal, and the buffer and the LVDS driver connected to the buffer can realize the return of the accompanying clock signal transmitted in the form of an LVDS signal.

[0108] By setting a signal input circuit 171, a signal processing circuit 173, and a differential signal output circuit 175 in the interface chip 10, the return data can be transmitted to the display control card. This avoids the need for an additional pair of LVDS transceivers to achieve data return in existing related technologies, reducing costs and simplifying the board-level matching solution, thus improving applicability.

[0109] It is worth mentioning that the aforementioned interface chip 10 includes, for example, a printed circuit board, on which the differential signal input circuit 11 and the timing recovery circuit 13 are both disposed. The printed circuit board is, for example, a PCB.

[0110] Furthermore, the differential signal input circuit 11, the timing recovery circuit 13, and the output control circuit 15 are all mounted on the same printed circuit board.

[0111] Furthermore, the differential signal input circuit 11, timing recovery circuit 13, output control circuit 15, signal input circuit 171, signal processing circuit 173, and differential signal output circuit 175 are all disposed on the printed circuit board.

[0112] It is worth mentioning that the aforementioned interface chip 10 and display driver chip 20 are located on the same printed circuit board, such as a PCB, thereby increasing the integration of the display module and facilitating its miniaturization.

[0113] In addition, such as Figure 13 As shown, one embodiment of the present invention discloses a display enclosure 300, which includes, for example, a display control card 200 and a display module 100 disclosed in the aforementioned embodiment. The display control card 200 includes, for example, a signal output circuit 210, and the display module 100 is electrically connected to the signal output circuit 210. This can be understood as the display module 100 being, for example, directly electrically connected to the I / O pins of the signal output circuit.

[0114] The display control card 200 is, for example, a receiver card or scanner card in an LED display control system. For instance, in addition to the signal output circuit 210, the display control card 200 also includes a memory electrically connected to the signal output circuit and a network port. The signal output circuit 210 is, for example, a programmable logic device, an ASIC circuit, or an integrated chip. The programmable logic device is, for example, an FPGA (Field-Programmable Gate Array), a single-chip microcomputer, or a microcontroller; or other microprocessors with certain data processing and computing capabilities, such as ARM processors and DSP processors. The memory is, for example, DDR memory.

[0115] The embodiments of the present invention do not limit the display control card 200 to a receiving card or scanning card in the LED display control system. It can also be a sending card in the LED display control system, or other devices that can perform video source processing and output data signals and clock signals.

[0116] In summary, the aforementioned embodiments of the present invention, by setting an interface chip 10 to connect between the display driver chip 20 and the display control card, and the interface chip 10 is equipped with a differential signal input circuit 11 and a timing recovery circuit 13, directly connects to the signal output circuit of the display control card through the differential signal input circuit 11 to receive the initial data signal and the accompanying clock signal in differential form. Since the signal is transmitted in differential form, the EMC effect of the transmitted signal can be improved, the signal transmission quality can be improved, long-distance transmission can be achieved, and the compatibility and scalability are good. The interface chip 10 is directly electrically connected to the signal output circuit of the display control card through the differential signal input circuit 11, which can reduce the consumption of IO pins in the signal output circuit of the display control card, such as FPGA, which is conducive to improving the data transmission bandwidth. Moreover, the reduction of the number of signals does not affect the selection of connectors and wires, thereby reducing the cost of connectors and wires. Therefore, it can solve the transmission problem between the existing receiver card and LED module. In addition, the interface chip 10 is equipped with an output control circuit 15 to realize the signal fine-tuning function, so the interface chip 10 can cope with different transmission environments and has better applicability.

[0117] In the several embodiments provided by this invention, it should be understood that the disclosed systems and devices can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, or indirect coupling or communication connection between devices or units, and may be electrical, mechanical, or other forms.

[0118] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0119] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An interface chip, characterized by The application relates to a display control system, comprising: a differential signal input circuit; and a timing recovery circuit connected to the differential signal input circuit; wherein the differential signal input circuit is connected to a signal output circuit of a display control card to receive initial data signals and a clock signal input by the signal output circuit, and to perform parsing processing on the initial data signals according to the clock signal; the timing recovery circuit is used to receive the parsed initial data signals and the clock signal, and to perform data recovery processing on the parsed initial data signals based on the clock signal to obtain a recovery driving signal, wherein the recovery driving signal is used to control a display driving chip to light up a display unit array; wherein the recovery driving signal comprises a driving clock signal and a driving control signal which are adapted to the display driving chip, the driving clock signal comprises a data clock signal which can be adjusted according to a sampling mode of the display driving chip, and the driving control signal comprises a decoding signal and a latching signal.

2. The interface chip of claim 1, wherein, Further comprising: an output control circuit connected to the timing recovery circuit, used to receive the recovery driving signal, and to output a display driving signal to the display driving chip based on the recovery driving signal, so that the display driving chip lights up the display unit array based on the display driving signal.

3. The interface chip according to claim 1 or 2, characterized in that, The timing recovery circuit comprises: a control signal generation module electrically connected to the differential signal input circuit, used to receive control signal generation information in the parsed initial data signals and the clock signal, and to generate a recovery control signal based on the control signal generation information and the clock signal; and a data signal recovery module electrically connected to the differential signal input circuit, used to receive data signal generation information in the parsed initial data signals and the clock signal, and to recover a recovery data signal based on the clock signal and the data signal generation information; wherein the recovery driving signal comprises the recovery control signal and the recovery data signal.

4. The interface chip of claim 3, wherein, The differential signal input circuit is further used to perform frequency multiplication processing on the clock signal to obtain a plurality of clock signals; the control signal generation module comprises: a driving clock signal generation unit used to receive driving clock signal generation information in the plurality of clock signals and the control signal generation information, and to select a target clock signal from the plurality of clock signals to generate the driving clock signal based on the target clock signal and the driving clock signal generation information; and a driving control signal generation unit used to receive driving control signal generation information in the control signal generation information and the clock signal, and to generate the driving control signal based on the clock signal and the driving control signal generation information.

5. The interface chip of claim 4, wherein, The driving clock signal generation unit is further configured to: select a second target clock signal from the plurality of clock signals, perform frequency division processing on the driving clock signal to obtain a frequency-division-processed driving clock signal, and perform register processing on the frequency-division-processed driving clock signal based on the second target clock signal to obtain a phase-adjusted driving clock signal.

6. The interface chip of claim 4, wherein, The driving clock signal generation unit is further configured to: receive sampling mode information, and when the sampling mode information indicates that the sampling mode of the display driving chip is a single-edge sampling mode, use the data clock signal as a data sampling clock; when the sampling mode information indicates that the sampling mode of the display driving chip is a double-edge sampling mode, perform frequency division processing on the data clock signal to obtain a frequency-division-processed data clock signal as a data sampling clock; and / or The driving clock signal comprises a grayscale clock signal, and the driving clock signal generation unit is further configured to: receive clock count information, and adjust the pulse widths of a first clock period and a last clock period of the grayscale clock signal based on the clock count information.

7. The interface chip of any one of claims 4-6, wherein, The driving clock signal generation unit comprises: a clock selection subunit electrically connected to the differential signal input circuit and configured to receive the plurality of clock signals input by the differential signal input circuit, and select the target clock signal from the plurality of clock signals based on a selection instruction; a gate subunit electrically connected to the clock selection subunit and the differential signal input circuit, and configured to receive the target clock signal and the driving clock signal generation information, and generate the driving clock signal by performing logical AND processing on the driving clock signal generation information and the target clock signal; and / or The driving control signal generation unit comprises: a clock count subunit electrically connected to the differential signal input circuit and configured to receive the on-the-fly clock signal, and output a clock count signal by counting the on-the-fly clock signal; an information selection subunit electrically connected to the differential signal input circuit and the clock count subunit, and configured to receive the driving control signal generation information and the clock count signal, and select target control signal generation information from the driving control signal generation information based on the clock count signal; a storage subunit electrically connected to the differential signal input circuit and the information selection subunit, and configured to receive the on-the-fly clock signal and the target control signal generation information, and generate the driving control signal based on the on-the-fly clock signal and the target control signal generation information; and / or The data signal recovery module comprises: a count unit electrically connected to the differential signal input circuit and configured to receive the on-the-fly clock signal, and output a count signal by counting the on-the-fly clock signal; ​ The comparison unit is electrically connected with the differential signal input circuit and the counting unit, configured to receive phase information in the data signal generation information and the counting signal, and compare the phase information with the counting signal to output a comparison signal; The output selection unit is electrically connected with the differential signal input circuit and the comparison unit, configured to receive data content information in the data signal generation information and the comparison signal, and output the data content information when the comparison signal represents a target state; The register output unit is electrically connected with the differential signal input circuit and the output selection unit, configured to generate and output the data signal based on the on-the-way clock signal and the data content information. The output selection unit is further configured to receive the data signal output by the register output unit, and output the data signal to the register output unit to control the register output unit to maintain the output of the data signal when the comparison signal represents a non-target state.

8. The interface chip according to claim 1 or 2, wherein, The timing recovery circuit comprises: The data signal recovery module is electrically connected with the differential signal input circuit, configured to receive the on-the-way clock signal and SPI data signal generation information in the initial data signal after the analysis processing, and generate an SPI data signal as the recovery driving signal based on the on-the-way clock signal and the SPI data signal generation information.

9. The interface chip of claim 8, wherein, The data signal recovery module comprises: The counting unit is electrically connected with the differential signal input circuit, configured to receive the on-the-way clock signal, and count the on-the-way clock signal to output a counting signal; The comparison unit is electrically connected with the differential signal input circuit and the counting unit, configured to receive phase information in the SPI data signal generation information and the counting signal, and compare the phase information with the counting signal to output a comparison signal; The output selection unit is electrically connected with the differential signal input circuit and the comparison unit, configured to receive SPI data content information in the SPI data signal generation information and the comparison signal, and output the SPI data content information when the comparison signal represents a target state; and The register output unit is electrically connected with the differential signal input circuit and the output selection unit, configured to generate and output the SPI data signal based on the on-the-way clock signal and the SPI data content information. The output selection unit is further configured to receive the SPI data signal output by the register output unit, and output the SPI data signal to the register output unit to control the register output unit to maintain the output of the SPI data signal when the comparison signal represents a non-target state.

10. The interface chip of claim 2, wherein, The output control circuit comprises: The delay adjustment module is connected with the timing recovery circuit, configured to perform delay adjustment on the recovery driving signal according to a first control instruction to output a delay adjustment signal; and A current regulating module is connected to the delay adjusting module, and is configured to regulate the current intensity of the delay adjusting signal according to a second control instruction, so as to output the display driving signal to the display driving chip.

11. The interface chip according to claim 1 or 2, characterized in that, the differential signal input circuit comprises: a phase-locked loop module; a serial-to-parallel conversion module electrically connected to the phase-locked loop module and the timing recovery circuit; wherein the phase-locked loop module is configured to be connected to the signal output circuit to receive the on-the-fly clock signal, and to perform frequency multiplication on the on-the-fly clock signal to obtain a reference clock signal, and to output the reference clock signal and the on-the-fly clock signal; the serial-to-parallel conversion module is configured to be connected to the signal output circuit to receive the initial data signal, the reference clock signal and the on-the-fly clock signal, to perform serial-to-parallel conversion on the initial data signal based on the reference clock signal to generate the parsed initial data signal, and to output the parsed initial data signal and the on-the-fly clock signal to the timing recovery circuit; and / or the interface chip further comprises: a signal input circuit configured to be connected to the display driving chip to receive the feedback data; a signal processing circuit connected to the signal input circuit and configured to process the feedback data to generate a feedback data packet; and a differential signal output circuit connected to the signal processing circuit and configured to process the feedback data packet to obtain a target feedback data packet, so as to output the target feedback data packet and the on-the-fly clock signal to the signal output circuit.

12. A display module, characterized by comprising: at least one interface chip according to any one of claims 1-11; and at least one display driving chip electrically connected to the at least one interface chip.

13. A display cabinet, characterised in that, comprising: a display control card comprising a signal output circuit; and the display module according to claim 12 electrically connected to the signal output circuit. ​

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