Display panel driving method and display panel

Abstract

The present invention discloses a driving method of a display panel and a display panel, and relates to the field of display technology. The display panel includes a first pulse cycle and a second pulse cycle. In the first pulse cycle, the duty cycle of the light-emitting control signal in the light-emitting stage is the first duty cycle; in the second pulse cycle, the duty cycle of the light-emitting control signal in the light-emitting stage is the second duty cycle, wherein the first duty cycle is greater than the second duty cycle; in the first pulse cycle, the interval between the start time of the first reset stage and the start time of the data writing stage is t1; in the second pulse cycle, the interval between the start time of the first reset stage and the start time of the data writing stage is t2, wherein t1<t2. By extending the time interval between the start time of the first reset stage and the start time of the data writing stage in the second pulse cycle, it is beneficial to extend the time for the characteristic recovery of the driving transistor, so it is beneficial to improve the ghosting phenomenon.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and more specifically, to a driving method of a display panel and a display panel. Background Art

[0002] Organic light-emitting display devices have the advantages of self-luminescence, low driving voltage, high luminous efficiency, fast response speed, thinness, and high contrast, and are considered to be the next generation of display devices with the most development potential. Organic light-emitting display devices are increasingly widely used in mobile phones, computers, televisions, car display devices, wearable devices and other display devices with display functions.

[0003] The pixels in the organic light-emitting display device include a pixel driving circuit. The driving transistor in the pixel driving circuit can generate a driving current. The light-emitting element emits light in response to the driving current, wherein the driving current generated by the driving transistor is related to the potential of the gate of the driving transistor. Due to the characteristics of the driving transistor itself, during the screen switching process of the display device, the driving transistor will be affected by the data of the previous frame, resulting in the inability to quickly switch the display screen to the preset screen, resulting in a ghosting phenomenon, which affects the display effect. In particular, in high-frequency display, the refresh frequency is faster, and the ghosting phenomenon is more obvious. Summary of the invention

[0004] In view of this, the present invention provides a driving method of a display panel and a display panel, which improve the ghosting phenomenon by extending the threshold compensation and characteristic recovery time of a driving transistor.

[0005] In a first aspect, the present application provides a method for driving a display panel, characterized in that the display panel comprises a plurality of sub-pixels and a pixel driving circuit correspondingly connected to the sub-pixels, the pixel driving circuit comprises a driving transistor; the working phase of the pixel driving circuit comprises a first reset phase, a data writing phase and a light emitting phase, wherein the starting time of the data writing phase is after the starting time of the first reset phase and before the starting time of the light emitting phase, and the first reset phase is at least used to reset the gate of the driving transistor;

[0006] The display panel includes a first pulse cycle and a second pulse cycle, in which the duty cycle of the light-emitting control signal in the light-emitting stage is a first duty cycle in the first pulse cycle; in which the duty cycle of the light-emitting control signal in the light-emitting stage is a second duty cycle in the second pulse cycle, wherein the first duty cycle is greater than the second duty cycle;

[0007] In the first pulse cycle, the interval between the start time of the first reset phase and the start time of the data writing phase is t1; in the second pulse cycle, the interval between the start time of the first reset phase and the start time of the data writing phase is t2, where t1<t2.

[0008] In a second aspect, the present application provides a display panel, which is driven by the display panel driving method provided in the first aspect of the present application.

[0009] Compared with the related art, the display panel driving method and the display panel provided by the present invention achieve at least the following beneficial effects:

[0010] In the display panel driving method and display panel provided by the embodiment of the present invention, the working phases of the pixel driving circuit include a first reset phase, a data writing phase and a light emitting phase, wherein the first reset phase is used to reset the gate of the driving transistor in the pixel driving circuit. The display panel includes two pulse cycles with different duty cycles, and the first duty cycle corresponding to the first pulse cycle is greater than the second duty cycle corresponding to the second pulse cycle. At this time, the interval t2 between the starting moment of the first reset stage and the starting moment of the data writing stage in the second pulse cycle is set to be greater than the interval t1 between the starting moment of the first reset stage and the starting moment of the data writing stage in the first pulse cycle, which is equivalent to extending the duration between the first reset stage and the data writing stage in the second pulse cycle with a smaller duty cycle. Since the process of resetting the gate of the driving transistor, that is, the process of threshold compensation and characteristic recovery of the driving transistor, is between the starting moment of the first reset stage and the starting moment of the data writing stage, when this part of the duration is extended, it is equivalent to extending the time for threshold compensation and characteristic recovery of the driving transistor. The longer the threshold compensation and characteristic recovery time is, the more conducive it is to adjust the characteristics of the driving transistor to the initial state, thereby helping to improve the ghosting phenomenon caused by the failure to restore the characteristics of the driving transistor well, and helping to improve the overall display effect of the display panel.

[0011] Of course, any product implementing the present invention does not necessarily need to achieve all of the technical effects described above at the same time.

[0012] Further features and advantages of the present invention will become apparent from the following detailed description of exemplary embodiments of the present invention with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0014] Figure 1FIG. 1 is a schematic diagram showing a structure of a pixel driving circuit in a display panel provided by an embodiment of the present invention;

[0015] Figure 2 FIG. 1 is a timing diagram of a method for driving a display panel provided by an embodiment of the present invention;

[0016] Figure 3 FIG. 1 is a flow chart of a method for driving a display panel provided by an embodiment of the present invention;

[0017] Figure 4 The figure shows a timing comparison diagram under the first pulse cycle and the second pulse cycle;

[0018] Figure 5 Another timing comparison diagram under the first pulse cycle and the second pulse cycle is shown;

[0019] Figure 6 FIG. 2 is another schematic diagram of the structure of a pixel driving circuit in a display panel provided by an embodiment of the present invention;

[0020] Figure 7 FIG. 2 is another schematic diagram of the structure of a pixel driving circuit in a display panel provided by an embodiment of the present invention;

[0021] Figure 8 Shown with Figure 7 A timing diagram corresponding to the pixel driving circuit in;

[0022] Fig. 9 Another timing comparison diagram under the first pulse cycle and the second pulse cycle is shown;

[0023] Fig.10 Another timing comparison diagram under the first pulse cycle and the second pulse cycle is shown;

[0024] Fig.11 FIG. 1 is a schematic diagram showing a potential change of the first node after three first reset stages and three data writing stages;

[0025] Fig.12 Another timing comparison diagram under the first pulse cycle and the second pulse cycle is shown;

[0026] Fig.13 FIG. 2 is another schematic diagram showing another potential change of the first node after three first reset stages and three data writing stages; FIG.

[0027] Fig.14 Another timing comparison diagram under the first pulse cycle and the second pulse cycle is shown;

[0028] Fig.15Shown is a timing diagram under the first pulse cycle or the second pulse cycle;

[0029] Fig.16 Another timing diagram under the first pulse cycle or the second pulse cycle is shown;

[0030] Fig.17 Another timing comparison diagram under the first pulse cycle and the second pulse cycle is shown;

[0031] Fig.18 Shown is a corresponding relationship diagram between control lines and pixel rows in a display panel;

[0032] Fig.19 FIG. 1 is a schematic diagram of the structure of a display panel provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0033] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present invention unless otherwise specifically stated.

[0034] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

[0035] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0036] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0037] It is obvious to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the present invention. Therefore, the present invention is intended to cover modifications and variations of the present invention that fall within the scope of the corresponding claims (technical solutions claimed for protection) and their equivalents. It should be noted that the implementation methods provided in the embodiments of the present invention can be combined with each other without contradiction.

[0038] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0039] In the related art, the brightness of the display panel in the first frame is relatively low, and, during the screen switching process, due to the hysteresis effect of the driving transistor itself, the driving transistor will be affected by the screen data of the previous frame, resulting in the threshold of the driving transistor not being well restored at the light-emitting moment of the current frame, and thus unable to generate a driving current corresponding to the preset switching screen, resulting in the display screen being unable to quickly switch to the preset switching screen. For example, assuming that the previous frame displays text, and the corresponding position of the text is black, and the other positions are white, in the current frame, assuming that the position of the text has changed and moved to other positions, the position corresponding to the text in the previous frame needs to display a white screen. Therefore, when the previous frame is converted to the current frame, the position corresponding to the text in the previous frame is the process of switching from a black screen to a white screen, and at least part of the position corresponding to the non-text in the previous frame is the process of switching from a white screen to a white screen. Due to the hysteresis effect of the driving transistor itself, the position corresponding to the text in the previous frame will be affected by the image data of the previous frame in the current frame, resulting in a gray screen between the black screen and the white screen when switching from a black screen to a white screen. Therefore, in the current frame, the white screen of the position corresponding to the text in the previous frame and the position corresponding to the non-text are not the same, and a residual image appears at the position corresponding to the text in the previous frame. In the process of sliding multiple frames continuously, a smear phenomenon will occur, affecting the display effect. At present, high-frequency display products are becoming more and more popular. As the frequency increases, the time for the threshold recovery of the driving transistor is also shortened accordingly, and the time for the threshold recovery of the driving transistor is the same under different duty cycles; in a low grayscale (e.g., 2nit) display mode, the driving current is small. When the duty cycle decreases, the time required to charge the light-emitting element will be longer, and the time for the driving transistor characteristics to recover is shorter, so the smear phenomenon will be more obvious.

[0040] To this end, the present application provides a method for driving a display panel, wherein the display panel includes a plurality of sub-pixels and a pixel driving circuit correspondingly connected to the sub-pixels, wherein the pixel driving circuit includes a driving transistor; the working phase of the pixel driving circuit includes a first reset phase, a data writing phase and a light emitting phase, wherein the starting time of the data writing phase is after the starting time of the first reset phase and before the starting time of the light emitting phase, and the first reset phase is at least used to reset the gate of the driving transistor; the display panel includes a first pulse period and a second pulse period, wherein in the first pulse period, the duty cycle of the light emitting control signal in the light emitting phase is the first duty cycle; in the second pulse period, the duty cycle of the light emitting control signal in the light emitting phase is the second duty cycle, wherein the first duty cycle is greater than the second duty cycle; in the first pulse period, the interval between the starting time of the first reset phase and the starting time of the data writing phase is t1; in the second pulse period, the interval between the starting time of the first reset phase and the starting time of the data writing phase is t2, wherein t1<t2. By extending the threshold compensation and characteristic recovery time of the driving transistor in the second pulse period with a smaller duty cycle, the smear phenomenon under low duty cycle conditions is improved, and the display effect is improved.

[0041] The above is the core idea of ​​the present invention. The technical scheme in the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiment of the present invention. Based on the embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work belong to the scope of protection of the embodiment of the present invention.

[0042] Figure 1 The figure is a schematic diagram of a structure of a pixel driving circuit in a display panel provided by an embodiment of the present invention. The figure is for illustration only and does not limit the structure of the pixel driving circuit actually included in the display panel. In some other embodiments of the present invention, the pixel driving circuit may also be embodied in other structures. The pixel driving circuit includes a driving transistor M0 and 6 switching transistors M1 to M6, wherein, except for the driving transistor M0, the remaining transistors are switching transistors, the gate of the driving transistor M0 is connected to the first node N1, the first electrode is connected to the second node N2, and the second electrode is connected to the third node N3. Optionally, the first transistor M1 in the first reset module 30 is connected to the gate of the driving transistor M0, and the gate of the first transistor M1 in the first reset module 30 is connected to the first control line SN1; the two electrodes of the second transistor M2 in the data writing module 10 are respectively connected to the data line Data and the second node N2, and the gate of the second transistor M2 in the data writing module 10 is connected to the second control signal line SN2; the two electrodes of the fifth transistor M5 in the light emitting control module 40 are respectively connected to the first power signal line PVDD and the second node N2, and the gate is connected to the light emitting control signal line EM. Figure 2The figure shows a timing diagram of the driving method of the display panel provided by the embodiment of the present invention, wherein within one frame time, the display panel performs a first reset phase T1, a data writing phase T2 and a light emitting phase T3, wherein in the first reset phase T1, the gate of the driving transistor M0 is reset and the threshold value of the driving transistor M0 is compensated. In the data writing phase T2, the data signal is written into the driving transistor M0; in the light emitting phase T3, the light emitting element D emits light in response to the driving signal of the driving transistor M0.

[0043] Figure 3 FIG. 1 is a flow chart of a method for driving a display panel provided by an embodiment of the present invention. It should be noted that: Figure 3 The flowchart of the illustrated embodiment only represents the sequence of the start times of the first resetting stage T1 , the data writing stage T2 and the light emitting stage T3 . Figure 4 The following is a timing comparison diagram of the first pulse period P1 and the second pulse period P2. Figures 1 to 4 An embodiment of the present invention provides a method for driving a display panel, wherein the display panel includes a plurality of sub-pixels and a pixel driving circuit correspondingly connected to the sub-pixels. The pixel driving circuit can be, for example, Figure 1 , the pixel driving circuit includes a driving transistor M0; the working stages of the pixel driving circuit include a first reset stage T1, a data writing stage T2 and a light emitting stage T3, wherein the starting time of the data writing stage T2 is after the starting time of the first reset stage T1 and before the starting time of the light emitting stage T3, and the first reset stage T1 is at least used to reset the gate of the driving transistor M0;

[0044] The display panel includes a first pulse period P1 and a second pulse period P2. In the first pulse period P1, the duty cycle of the light-emitting control signal in the light-emitting stage T3 is a first duty cycle; in the second pulse period P2, the duty cycle of the light-emitting control signal in the light-emitting stage T3 is a second duty cycle, wherein the first duty cycle is greater than the second duty cycle.

[0045] In the first pulse cycle P1, the interval between the start time of the first reset phase T1 and the start time of the data writing phase T2 is t1; in the second pulse cycle P2, the interval between the start time of the first reset phase T1 and the start time of the data writing phase T2 is t2, where t1<t2.

[0046] Due to the hysteresis effect of the driving transistor itself, if the first reset stage T1 is not introduced before the data writing stage T2, or the time of the first reset stage T1 executed before the data writing stage T2 is short, the characteristics of the driving transistor are difficult to recover, and the signal of the previous frame will affect the display of the current frame. In the current frame, the picture cannot be quickly switched to the current picture, resulting in display ghosting and affecting the display effect.

[0047] The larger the duty cycle of the pulse cycle of the display panel, the shorter the time between the start time of the first reset stage T1 and the end time of the data writing stage T2 in the same pulse cycle; the smaller the duty cycle of the pulse cycle, the longer the time between the start time of the first reset stage T1 and the end time of the data writing stage T2 in the same pulse cycle. In the related art, under different duty cycles, the time interval between the first reset stage T1 and the data writing stage T2 is the same, that is, the time for the driving transistor to perform threshold recovery is also the same, which results in that only the same threshold recovery time as that of the high duty cycle can be used under low duty cycles, resulting in more obvious ghosting under low grayscale and low duty cycles. To this end, in the driving method of the display panel provided in the embodiment of the present application, when the second duty cycle corresponding to the second pulse period P2 of the display panel is smaller than the first duty cycle corresponding to the first pulse period P1, the present application sets the interval t2 between the starting moment of the first reset stage T1 and the starting moment of the data writing stage T2 under the second pulse period P2 to be larger than the interval t1 between the starting moment of the first reset stage T1 and the starting moment of the data writing stage T2 under the first pulse period P1, which is equivalent to extending the duration between the first reset stage T1 and the data writing stage T2 under the second pulse period P2 with a smaller duty cycle. Since the gate of the driving transistor is reset between the starting moment of the first reset stage T1 and the starting moment of the data writing stage T2, that is, the process of threshold compensation and characteristic recovery of the driving transistor, when this part of the duration is extended, it is equivalent to extending the time for characteristic recovery of the driving transistor. The longer the threshold compensation time is, the more conducive it is to restore the characteristics of the driving transistor to the initial state, thereby helping to improve the ghosting phenomenon caused by the failure to restore the characteristics of the driving transistor well, and helping to improve the overall display effect of the display panel. The present application differentially sets the interval length between the start time of the first reset stage T1 and the start time of the data writing stage T2 according to pulse periods with different duty cycles, thereby extending the time interval between the first reset stage and the data writing stage under low duty cycle, thereby extending the characteristic recovery time of the driving transistor under low duty cycle, so that the characteristics of the driving transistor can be better restored before the light-emitting stage T3 under pulse periods with different duty cycles, and effectively improves the ghosting phenomenon caused by the failure to restore the characteristics of the driving transistor under low grayscale and low duty cycle, thereby helping to improve the display quality of the display panel under pulse periods with different duty cycles.

[0048] It should be noted that Figure 4 Only the timing diagrams corresponding to the pulse periods with different duty ratios are shown, and the types of pulse periods actually included in the display panel are not limited. In fact, the display panel may also include three or more pulse periods with different duty ratios. If the intervals between the first reset stage and the data writing stage in the pulse periods with different duty ratios are the same and are all set according to the intervals with larger duty ratios, the characteristic recovery time of the driving transistor under the pulse period with smaller duty ratio will be shorter. Since the driving current is smaller and the charging time of the light-emitting element is longer under the low duty ratio and low gray scale conditions, the phenomenon of dragging is more obvious during the screen switching process. If the threshold recovery time of the driving transistor is shorter under low gray scale, it is more unfavorable to improve the dragging phenomenon. Therefore, in the present embodiment, the time between the start time of the first reset stage T1 and the start time of the data writing stage T2 in the pulse period with smaller duty ratio is longer, and the threshold recovery time of the driving transistor under low duty ratio is extended, so as to improve the dragging phenomenon that may occur in the display panel under low duty ratio and improve the display effect of the display panel under different duty ratios.

[0049] Figure 5 Another timing comparison diagram under the first pulse period P1 and the second pulse period P2 is shown. Figure 4 Compared with the embodiment shown in FIG. 1 , the difference is that the effective pulse width corresponding to the single first reset stage T1 is different. Figure 5 In an optional embodiment of the present application, in the first pulse period P1, the effective pulse width corresponding to the single first reset stage T1 is t11; in the second pulse period P2, the effective pulse width corresponding to the single first reset stage T1 is t12, wherein t11<t12.

[0050] Specifically, please combine Figure 2 and Figure 5Since the second duty cycle of the second pulse period P2 is relatively low, the duration t2 from the start time of the first reset stage T1 to the start time of the light-emitting stage T3 under the second pulse period P2 is greater than the duration t1 from the start time of the first reset stage T1 to the start time of the light-emitting stage T3 under the first pulse period P1. At this time, the present embodiment extends the effective pulse width t12 corresponding to the single first reset stage T1 under the second pulse period P2 to make it greater than the effective pulse width t11 corresponding to the single first reset stage T1 under the first pulse period P1. This is equivalent to extending the time for writing the reset signal to the gate of the driving transistor under the second pulse period P2 with a relatively low duty cycle, thereby extending the time for recovering the characteristics of the driving transistor, so that the characteristics of the driving transistor can be better restored before the light-emitting stage T3, which is more conducive to improving the ghosting phenomenon caused by the failure to recover the characteristics of the driving transistor in the related art, and is conducive to improving the overall display effect of the display panel.

[0051] Continue to refer Figure 1 and Figure 2 In an optional embodiment of the present application, the data writing phase T2 includes a compensation phase T21 and a data writing phase T22, and the compensation phase T21 and the data writing phase T22 are performed simultaneously; the starting time of the data writing phase T2 is after the ending time of the first reset phase T1.

[0052] Specifically, the data writing stage T2 in this embodiment includes not only the data writing stage T22 for writing data, but also the compensation stage T21. The threshold voltage of the driving transistor in the compensation stage is different from the threshold voltage in the actual light-emitting stage, which will cause the actual light-emitting brightness to be different from the target light-emitting brightness. In the compensation stage T21, the driving transistor is in an on state. Writing a voltage to the driving first node in the compensation stage is equivalent to biasing the driving transistor in an on state, which is conducive to promoting the threshold recovery of the driving transistor. The introduction of the compensation stage is conducive to eliminating the influence of the threshold on the light-emitting current. Through the joint action of the first reset stage T1 and the compensation stage T21, it is more conducive to achieving reliable recovery of the characteristics of the driving transistor before the light-emitting stage T3, and is more conducive to improving the smear phenomenon. In this embodiment, the compensation stage T21 and the data writing stage T22 are carried out simultaneously, which is conducive to simplifying the control timing while realizing the threshold compensation of the driving transistor.

[0053] It should be noted that, for different pulse periods, one difference lies in the different duty cycles, and under different duty cycles, the duration between the start time of the first reset stage T1 and the start time of the data writing stage T2 is different, but the various working stages included in different pulse periods are the same. For example, in this embodiment, the first pulse period P1 and the second pulse period P2 both include the first reset stage T1, the compensation stage T21, the data writing stage T22 and the light emitting stage T3, wherein under different pulse periods, the compensation stage T21 and the data writing stage T22 are carried out simultaneously.

[0054] Please continue to refer to Figure 1 In an optional embodiment of the present application, the driving circuit includes a data writing module 10 and a compensation module 20. The data writing module 10 is connected to the first electrode of the driving transistor M0, and the compensation module 20 is connected between the second electrode and the gate of the driving transistor. In the data writing stage T2, the data writing module 10 and the compensation module 20 are turned on at the same time.

[0055] Optionally, the two electrodes of the transistor in the compensation module 20 are respectively connected between the second electrode and the gate of the driving transistor, that is, connected between the first node N1 and the third node N3 in the pixel driving circuit. Optionally, Figure 1 The second transistor M2 in the data writing module 10 and the third transistor M3 in the compensation module 20 are of the same type, and the gates of the two are connected to the same second control line SN2 as an example for description, but the types and connection relationship between the two are not limited. In some other embodiments of the present invention, the second transistor M2 in the data writing module 10 and the third transistor M3 in the compensation module 20 can also be set to different types, for example, please refer to Figure 6 , Figure 6 In the illustrated embodiment, the second transistor M2 in the data writing module 10 is a P-type transistor, and the third transistor M3 in the compensation module 20 is an N-type transistor, and the gates of the two are respectively connected to different control lines, for example, the gate of the second transistor M2 is connected to the control line Scan, and the gate of the third transistor M3 is connected to the control line SN2. In the compensation stage T21, the transistors in the data writing module 10 and the compensation module 20 can be provided with turn-on signals respectively through the aforementioned different control lines, and the two can also be turned on at the same time. Among them, Figure 6 FIG. 1 is another schematic diagram of the structure of a pixel driving circuit in a display panel provided by an embodiment of the present invention.

[0056] Figure 6In the illustrated embodiment, the third transistor M3 in the compensation module 20 is directly connected to the first node N1. If the third transistor M3 in the compensation module 20 is selected as an N-type transistor, since the leakage current of the N-type transistor is small, it is beneficial to reduce the influence of the leakage current of the transistor connected to the first node N1 on the gate potential of the driving transistor, which is beneficial to the recovery of the characteristic voltage of the driving transistor before the light-emitting stage T3. Optionally, the first transistor M1 in the first reset module 30 can also be an N-type transistor to further reduce the leakage current of the gate of the driving transistor through other transistors connected thereto. It should be noted that when the transistor in the first reset module is an N-type transistor, in the first reset stage T1, the effective level of the first transistor M1 in the first reset module 30 is a high level.

[0057] Figure 7 FIG. 2 is another schematic diagram of the structure of a pixel driving circuit in a display panel provided by an embodiment of the present invention. Figure 8 Shown with Figure 7 A timing diagram corresponding to the pixel driving circuit in . Please refer to Figure 7 and Figure 8 In an optional embodiment of the present application, the data writing stage T2 includes a first sub-stage T211 and a second sub-stage T212, the first sub-stage T211 is at least used to reset the second electrode of the driving transistor, and the second sub-stage T212 is at least used to compensate the gate potential of the driving transistor; the starting time of the first sub-stage T211 is between the starting time and the ending time of the first reset stage T1, and the ending time of the first sub-stage T211 is after the ending time of the first reset stage T1; the second sub-stage T212 is between the starting time and the ending time of the first sub-stage T211, and is after the ending time of the first reset stage T1.

[0058] Specifically, in the driving method of the display panel provided in the embodiment of the present invention, the data writing stage T2 may also include two sub-stages, namely, a first sub-stage T211 for at least resetting the second pole of the driving transistor and a second sub-stage T212 for at least compensating the gate of the driving transistor, wherein the starting time of the first sub-stage T211 is located in the first reset stage T1, that is, the starting time of the first sub-stage T211 is located between the starting time and the end time of the first reset stage T1, that is, the first sub-stage T211 and the first reset stage T1 are overlapped, and during the overlap period, the reset signal provided to the first node N1 by the first reset stage T1 will also be provided to the second pole of the driving transistor through the third node N3, and the reset signal can reset and compensate the potential of the second pole of the driving transistor, so that the characteristics of the driving transistor are restored as soon as possible. The termination time of the first sub-stage T211 is after the first reset stage T1, and the first sub-stage T211 after the first reset stage T1 also overlaps with the second sub-stage T212. During the overlap between the first sub-stage T211 and the second sub-stage T212, the data signal is written into the driving transistor, and the gate potential of the driving transistor can also be compensated to further promote the recovery of the characteristics of the driving transistor.

[0059] It should be noted that, for different pulse periods, one difference lies in the different duty cycles. Under different duty cycles, the duration between the start time of the first reset stage T1 and the start time of the data writing stage T2 is different, but the various working stages included in the different pulse periods are the same. For example, in the present embodiment, the first pulse period P1 and the second pulse period P2 both include the first reset stage T1, the first sub-stage T211, the second sub-stage T212 and the light-emitting stage T3. The start time of the first sub-stage T211 is located in the first reset stage T1, and the second sub-stage T212 overlaps with the first sub-stage T211, while the second sub-stage T212 does not overlap with the first reset stage T1.

[0060] Continue to refer Figure 7 and Figure 8 In an optional embodiment of the present application, the driving circuit includes a data writing module 10 and a compensation module 20, the data writing module 10 is connected to the first electrode of the driving transistor M0, and the compensation module 20 is connected between the second electrode and the gate of the driving transistor M0; the control ends of the data writing module 10 and the compensation module 20 are respectively connected to different control signal ends; the compensation module 20 is turned on in the first sub-stage T211 and the second sub-stage T212, and the data writing module 10 is turned on in the second sub-stage T212.

[0061] It should be noted that the control terminals of the first reset module, the data writing module 10, the compensation module 20 and other modules refer to the gates of the transistors in these modules. In this embodiment, the gate of the first transistor M1 in the first reset module 30, the gate of the second transistor M2 in the data writing module 10 and the gate of the third transistor M3 in the compensation module 20 are respectively connected to different control lines, and the conduction and cutoff of these modules can be controlled by signals on different control lines. In the first sub-stage T211 in the data writing stage T2, the first reset module 30 and the compensation module 20 are both in the on state. At this time, the reset signal transmitted by the first reset module 30 can be transmitted to the first node N1 of the pixel driving circuit, and can be transmitted to the third node N3 through the compensation module 20, thereby realizing the reset of the first node N1 and the third node N3, which is more conducive to the recovery of the characteristics of the driving transistor M0. In the second sub-stage T212, the first reset module 30 is turned off, the compensation module 20 and the data writing module 10 are turned on, the data signal is written into the driving transistor M0, and the threshold voltage of the driving transistor M0 is further compensated by the compensation module 20, so that the characteristics of the driving transistor M0 before the light-emitting stage T3 can be better restored. In addition, considering that the intervals from the first reset stage to the light-emitting stage are different under the first pulse period and the second pulse period of different duty cycles, the time when the first node N1 leaks from the reset voltage provided by the first reset module will be different, so that when the duty cycle dimming is adopted, the current deviates from the target current. The embodiment of the present application prolongs the time interval between the start time of the first reset stage and the start time of the data writing stage under the second pulse period of the lower duty cycle, while keeping the compensation module 20 turned on in the first sub-stage T211, so there is no problem of different leakage time, so that the actual driving current is closer to the target driving current, and the actual luminous brightness is also closer to the target luminous brightness, so it is more conducive to improving the smear phenomenon.

[0062] Optionally, refer to Figure 1 , Figure 6 and Figure 7 The pixel driving circuit in the embodiment of the present invention further includes a second reset module 50, wherein the two electrodes of the fourth transistor M4 in the second reset module 50 are respectively connected to the reset signal line Vref2 and the fourth node N4, and the anode of the light-emitting element D is connected to the fourth node N4. The second reset module 50 is used to reset the anode of the light-emitting element D. Optionally, the signal line connected to the anode of the fourth transistor M4 can be the same as any one of the control lines connected to the first reset module, the data writing module or the compensation module, and the present invention does not specifically limit this. Optionally, the light-emitting control module 40 further includes a sixth transistor M6 connected between the third node N3 and the fourth node N4.

[0063] Fig. 9 and Fig.10 Another timing comparison diagram under the first pulse period P1 and the second pulse period P2 is shown respectively, corresponding to the two situations where the data writing phase T2 and the first reset phase T1 have no overlap or overlap.

[0064] In an optional embodiment of the present application, at least N first reset stages T1 and N data writing stages T2 are performed under the first pulse period P1 and the second pulse period P2, wherein the starting time of the i-th data writing stage T2 is after the starting time of the i-th first reset stage T1, 1≤i≤N, i is an integer, and N is an integer greater than or equal to 2.

[0065] Fig. 9 The embodiment shows a scheme of performing three first reset phases T1 and three data writing phases T2 between two light emitting phases. Fig.10 The embodiment shows a scheme of executing two first reset stages T1 and two data writing stages T2 between two light-emitting stages, but does not limit the number of executions of the first reset stage T1 and the data writing stage T2 between the two light-emitting stages. In some other embodiments of the present invention, the number of first reset stages T1 and data writing stages T2 executed between two light-emitting stages T3 may be more than three times, and the present invention does not specifically limit this.

[0066] When two or more first reset stages T1 and data writing stages T2 are introduced between two light-emitting stages, the first reset stage T1 and the data writing stage T2 are executed alternately, that is, the i-th data writing stage T2 is executed after the start time of the i-th reset stage, and the i+1-th first reset stage T1 is executed after the i-th data writing stage T2. The embodiment of the present invention introduces at least two first reset stages T1 and data writing stages T2 before the light-emitting stage T3, and resets and writes data to the gate of the driving transistor multiple times, so that the characteristics of the driving transistor before the light-emitting stage T3 can be better restored, which can better improve the brightness of the first frame, avoid or reduce the problem of low brightness of the first frame when the screen is switched, and is conducive to weakening the difference between the brightness of the first frame and the brightness of subsequent frames, effectively improving the ghosting phenomenon, and improving the display quality of the display panel. At the same time, extending the interval between the start time of the first reset stage T1 and the start time of the data writing stage T2 in the pulse period with a small duty ratio can extend the threshold compensation and characteristic recovery time of the driving transistor, which is conducive to improving the display ghosting phenomenon under different pulse periods and improving the display effect. The following will be combined with Fig.11 The threshold recovery of the driving transistor when multiple first resetting stages and data writing stages are introduced is described.

[0067] Fig.11The figure shows the potential change of the first node after three first reset stages and three data writing stages, wherein Vn01 represents the voltage of the first node N1 when the black screen switches to the white screen, and Vn11 represents the voltage of the first node N1 when the white screen switches to the white screen. Ideally, the voltage of the N1 node is equal to the difference between the voltage provided by the data signal terminal and the absolute value of the threshold voltage of the driving transistor, that is, Vdata-|Vth|. Assuming that Vdata=3V, when the black screen switches to the white screen, after the first first reset stage, the potential of the N1 node becomes -4.5V, and after a data writing stage, the threshold voltage Vth of the driving transistor becomes -1.2V, and the voltage Vn01 of the first node becomes 1.8V. After the second first reset phase and data writing phase, the threshold voltage Vth of the driving transistor becomes -2.2V, and the voltage Vn01 of the first node becomes 0.8V; after the third first reset phase and data writing phase, the threshold voltage Vth of the driving transistor becomes -2.7V (closer to the threshold voltage -3V of the driving transistor when the white screen switches to the white screen), and the potential of the N1 node becomes 0.3V (closer to the potential of the first node when the white screen switches to the white screen). It can be seen that after multiple resets and data writing, the threshold voltage of the driving transistor gradually recovers, and when the black screen switches to the white screen, the threshold voltage of the driving transistor gradually approaches the threshold voltage of the driving transistor when the white screen switches to the white screen, and the potential of the first node N1 gradually approaches the voltage of the first node N1 when the white screen switches to the white screen; that is, after executing the first node reset stage and the data writing stage multiple times, the threshold voltage of the driving transistor gradually recovers, so that the potential of the first node when the black screen switches to the white screen is consistent with the potential of the first node when the white screen switches to the white screen, and then the color of the white screen when switching from the black screen to the white screen is consistent with the color of the white screen when switching from the white screen to the white screen, so that executing the first reset stage and the data writing stage multiple times is more conducive to improving the ghosting phenomenon during the screen switching process.

[0068] Continue to refer Fig. 9 and Fig.10 In an optional embodiment of the present application, in the first pulse period P1, the time interval between the start time of the mth first reset phase T1 and the start time of the mth data writing phase T2 is t01, and the time interval between the start time of the m+1th first reset phase T1 and the start time of the m+1th data writing phase T2 is t02, wherein 1≤m<N, t01=t02;

[0069] Under the second pulse period P2, the time interval between the starting moment of the mth first reset phase T1 and the starting moment of the mth data writing phase T2 is t21, and the time interval between the starting moment of the m+1th first reset phase T1 and the starting moment of the m+1th data writing phase T2 is t22, wherein t21=t22, t21>t01.

[0070] In this embodiment, when at least two first reset stages T1 and data writing stages T2 are introduced before the light-emitting stage T3, under the same pulse cycle, the time interval between the start time of each reset stage and the start time of the data writing stage T2 can be set to be equal, which is equivalent to the same time for each reset stage and the data writing stage T2 to restore the threshold of the driving transistor. Considering that when using a shift register to implement at least two first reset stages and at least two data writing stages, if the interval between the start time of the first reset extreme point and the start time of the data writing stage is different, the control difficulty of the shift register will be increased, and it is not conducive to the reuse of signals transmitted by shift registers of different levels. Therefore, the present application sets the time for each reset stage and the data writing stage T2 to restore the threshold of the driving transistor to be the same. This setting method can realize reliable recovery of the threshold of the driving transistor and improve the display ghosting phenomenon, and it is also conducive to simplifying the control difficulty of the shift register. In addition, for the second pulse period P2 with a smaller duty cycle, the time interval between each first reset stage T1 and the data writing stage T2 is greater than the time interval between each first reset stage T1 and the data writing stage T2 under the first pulse period P1, thereby making full use of the time before the light-emitting stage T3 to compensate for the threshold of the driving transistor, which is more conducive to the recovery of the characteristics of the driving transistor.

[0071] Fig.12 Another timing comparison diagram under the first pulse period P1 and the second pulse period P2 is shown. This embodiment shows a solution for differentially designing the time intervals between the start times of different first reset phases T1 and data writing phases T2 under the same pulse period.

[0072] Please refer to Fig.12 In an optional embodiment of the present application, in the first pulse period P1, the time interval between the start time of the first first reset phase T1 and the start time of the first data writing phase T2 is t31, and the time interval between the start time of the Mth first reset phase T1 and the start time of the Mth data writing phase T2 is t32, wherein 2≤M≤N, t31>t32;

[0073] Under the second pulse period P2, the time interval between the starting moment of the first first reset phase T1 and the starting moment of the first data writing phase T2 is t41, and the time interval between the starting moment of the Mth first reset phase T1 and the starting moment of the Mth data writing phase T2 is t42, wherein t41>t42≥t31.

[0074] During the display process of the display panel, in two adjacent data frames, after the previous frame is displayed, that is, at the moment when the light-emitting stage of the previous frame is completed, the characteristic drift of the driving transistor is more obvious. When multiple first reset stages T1 and data writing stages T2 are introduced before the light-emitting stage, for the same pulse cycle, this embodiment sets the time interval between the start time of the first first reset stage and the data writing stage T2 to be greater than the time interval between the start time of other reset stages and the data writing stage T2, so that a longer characteristic recovery time can be reserved for the driving transistor so that the characteristics of the driving transistor can be gradually restored. After the first first reset stage T1 and the data writing stage T2, the characteristics of the driving transistor have been well restored. After the first first reset stage T1 and the data writing stage T2 and before the light-emitting stage, the other reset stages and the data writing stage T2 executed can further restore the characteristics of the driving transistor. Therefore, the time of the other first reset extremes and the data writing stage T2 after the first first reset stage T1 and the data writing stage T2 can be appropriately reduced, and the characteristics of the driving transistor can also be well restored. The following will be combined with Fig.13 The threshold conditions of the driving transistor when the time intervals between the first resetting phase and the data writing phase are different are further described.

[0075] Fig.13 The figure shows another potential change schematic diagram of the first node after three first reset stages and three data writing stages, wherein Vn01 represents the voltage of the first node N1 when the black screen switches to the white screen, and Vn11 represents the voltage of the first node N1 when the white screen switches to the white screen. Ideally, the voltage of the N1 node is equal to the difference between the voltage provided by the data signal terminal and the absolute value of the threshold voltage of the driving transistor, that is, Vdata-|Vth|. Assuming that Vdata=3V, when the black screen switches to the white screen, after the first first reset stage, the potential of the N1 node becomes -4.5V. Since the interval between the first first reset stage and the data writing stage is large, the driving transistor is maintained for a longer time after being reset, which is more conducive to the recovery of the threshold of the driving transistor. After the first data writing stage, the threshold voltage Vth of the driving transistor becomes -1.6V. At this time, the voltage Vn01 of the first node becomes 1.4V, compared with Fig.11In the embodiment shown, the threshold recovery effect of the driving transistor is better after the first data writing stage is executed. After the second first reset stage and data writing stage are executed, the threshold of the driving transistor is restored to -2.5V, and the voltage of the first node becomes 0.5V; after the third first reset stage and data writing stage are executed, the threshold of the driving transistor is restored to -2.9V, and the voltage of the first node becomes 0.1V. It can be seen that at this time, the threshold voltage of the driving transistor is closer to the threshold voltage of the driving transistor when the white screen switches to the white screen, and the potential of the first node is also closer to the potential of the first node when the white screen switches to the white screen. Considering that the characteristic recovery of the driving transistor is not linear, but fast at first and then slow, therefore, when executing multiple first reset stages and data writing stages, extending the interval time between the first reset stage and the data writing stage executed first is more conducive to the recovery of the threshold of the driving transistor, and the color of the picture formed by the black screen switching to the white screen is closer to the color of the picture formed by the white screen switching to the white screen, which is more conducive to improving the ghosting phenomenon.

[0076] Fig.12 and Fig.13 The embodiment shows that when three first reset stages T1 and data writing stages T2 are introduced before the light-emitting stage T3, the time interval between the first first reset stage T1 and the start time of the first data writing stage T2 is the longest, and the time interval between the second first reset stage T1 and the start time of the second data writing stage T2 is the same as the time interval between the third first reset stage T1 and the start time of the third data writing stage T2. In addition to this implementation, the time intervals between the start times of different first reset stages T1 and the data writing stage T2 can also be set to be different. For example, please refer to Fig.14 , Fig.14 Another timing comparison diagram under the first pulse period P1 and the second pulse period P2 is shown.

[0077] Please refer to Fig.14 In an optional embodiment of the present application, under the first pulse period P1 or the second pulse period P2, the time interval between the starting moment of the Pth first reset phase T1 and the starting moment of the Pth data writing phase T2 is t03, and the time interval between the starting moment of the P+1th first reset phase T1 and the starting moment of the P+1th data writing phase T2 is t04, wherein 1≤P<N, t03>t04. Fig.14Only the time interval between the start time of the second first reset phase and the start time of the second data writing phase in the second pulse cycle is t03, and the time interval between the start time of the third first reset phase and the start time of the third data writing phase is t04 is taken as an example for explanation, but no specific limitation is imposed on the duration between the start time of each first reset phase and the data writing phase.

[0078] In this embodiment, the time intervals between the start time of each first reset stage T1 and the start time of the data writing stage T2 are different. Specifically, the time interval between the start time of the first first reset stage T1 and the start time of the first data writing stage T2 is the largest. Starting from the second time, the time interval between the start time of the first reset stage T1 and the start time of the data writing stage T2 gradually decreases. When the light-emitting stage T3 of the previous frame is completed, the characteristic deviation of the driving transistor is more obvious. Threshold compensation of the driving transistor is performed through the first first reset stage with a longer time, which is conducive to the continuous recovery of the characteristics of the driving transistor; each time the first reset stage T1 is performed, the characteristics of the driving transistor will be more inclined to the initial characteristic recovery. After the characteristics of the driving transistor are restored to a certain extent in the first first reset stage, the characteristics of the driving transistor can be better restored through one or more subsequent first reset stages T1 even if the time becomes shorter.

[0079] Fig.15 The figure shows a timing diagram under the first pulse period P1 or the second pulse period P2. In an optional embodiment of the present application, under the first pulse period P1 or the second pulse period P2, the effective pulse width of N first reset stages T1 shows an increasing or decreasing trend, and the width of the invalid pulse between two adjacent valid pulses is the same.

[0080] Fig.15The embodiment shown shows a scheme in which different effective pulse widths of the first reset stage T1 are different under the same pulse cycle. Specifically, the effective pulse width of the first reset pulse under the same pulse cycle is a decreasing trend. Specifically, the effective pulse width t111 of the first first reset stage is greater than the effective pulse width t112 of the second first reset stage. The effective pulse width t112 of the second first reset stage is greater than the effective pulse width t113 of the third first reset stage. The invalid pulse widths between two adjacent first reset stages are t001 and t002, respectively, and t001=t002. The first reset stage T1 is a stage in which a reset signal is written to the gate of the driving transistor. When the reset signal is written to the gate of the driving transistor, the threshold value of the driving transistor can be compensated. Within a certain time range, the longer the time for writing the reset signal to the driving transistor is, the more conducive it is to the recovery of the characteristics of the driving transistor. When the light-emitting stage of the previous frame is completed, the characteristic deviation of the driving transistor is more obvious. Threshold compensation of the driving transistor through the first first reset stage with a longer time is more conducive to the continuous recovery of the characteristics of the driving transistor. Of course, after the first reset stage and before the light-emitting stage, even if the reset signal is not written to the gate of the driving transistor, the driving transistor can also perform a certain degree of characteristic recovery during this time period. It should be noted that when the effective pulse width of the first reset stage T1 under the same pulse cycle is designed differently, the time interval between the start time of the first reset stage T1 and the start time of the data writing stage T2 in the pulse cycle with a smaller duty cycle is greater than the time interval between the start time of the first reset stage T1 and the start time of the data writing stage T2 in the pulse cycle with a larger duty cycle, and the time before the light-emitting stage T3 in the pulse cycle with a smaller duty cycle can still be better utilized to achieve characteristic recovery of the driving transistor.

[0081] Fig.16 Another timing diagram under the first pulse period P1 or the second pulse period P2 is shown. This embodiment shows a solution in which the effective pulse width of multiple first reset stages T1 under the same pulse period is the same. Fig.16 In an optional embodiment of the present application, in the first pulse period P1 or the second pulse period P2, the effective pulse widths of N first reset stages T1 are the same, and the width of the invalid pulse between two adjacent effective pulses shows an increasing or decreasing trend.

[0082] This embodiment shows that when three first reset stages and a data writing stage are introduced before the light-emitting stage, the widths of the valid pulses corresponding to the three first reset stages are set to be the same, that is, t111=t112=t113, and the widths of the invalid pulses between the valid pulses corresponding to adjacent first reset stages are set to different schemes, specifically taking the decreasing trend of the width of the invalid pulse as an example, that is, t001<t002. When the widths of valid pulses corresponding to multiple first reset stages 1 before the light-emitting stage are the same, the duration of each time the first reset extreme writes the reset signal to the gate of the driving transistor is fixed. By changing the width of the invalid pulse between the valid pulses, the time interval between the start time of the first reset stage and the start time of the data writing stage in different first reset stages and data writing stages can be adjusted. When the width of the invalid pulse decreases, the time interval between the start time of the first reset stage and the start time of the data writing stage shows an increasing trend. In this way, the time between the start time of the first reset stage and the data writing stage executed earlier can be used to fully restore the characteristics of the driving transistor, and the time between the start time of the first reset stage and the data writing stage executed later can be used to supplement the restoration of the characteristics of the driving transistor, so that the driving transistor can be restored to a better state before the light-emitting stage, effectively avoiding the display ghosting problem of the display panel.

[0083] In some other embodiments of the present invention, when the effective pulse widths of multiple first reset stages before the light-emitting stage are the same, the width of the invalid pulses between the effective pulses can also be set to an increasing trend. Correspondingly, in different first reset stages and data writing stages, the duration between the start time of the previous first reset stage and the start time of the data writing stage will be shorter than the duration between the start time of the subsequent first reset stage and the start time of the data writing stage, which can also achieve the recovery of the characteristics of the driving transistor.

[0084] Continue to refer Fig.14 In an optional embodiment of the present application, under the first pulse period P1, the time interval between the end moment of the last executed data writing stage T2 and the start moment of the light-emitting stage T3 is t10; under the second pulse period P2, the time interval between the end moment of the last executed data writing stage T2 and the start moment of the light-emitting stage T3 is t20, wherein t10=t20.

[0085] Specifically, when the duty cycles corresponding to different pulse periods are different, the present application makes a differentiated design for the time interval between the start time of the first reset stage T1 and the start time of the data write stage T2, and sets the time interval between the start time of the first reset stage T1 and the start time of the data write stage T2 under the second pulse period P2 with a smaller duty cycle to be larger, so as to extend the characteristic recovery time of the driving transistor under the second pulse period P2 with a smaller duty cycle. For pulse periods with different duty cycles, the time interval between the end time of the data write stage T2 adjacent to the light-emitting stage T3 and the start time of the light-emitting stage T3 is set to be the same, so that the time interval from the last data write before the completion of the light-emitting stage T3 to the start of light emission under pulse periods with different duty cycles is the same, which is conducive to improving the consistency of light-emitting conditions under pulse periods with different duty cycles.

[0086] Continue to refer Fig.14 In an optional embodiment of the present application, t10 is greater than or equal to 2H, where H is the time required to scan a row of sub-pixels in the display panel. When the time interval between the end time of the last executed data writing stage T2 and the start time of the light-emitting stage T3 under pulse periods of different duty cycles is set to be greater than or equal to 2H, sufficient margin can be left between the data writing stage and the light-emitting stage, effectively avoiding the burning phenomenon caused by the large current on the first power signal line passing through the driving transistor when the valid pulse of the light-emitting stage T3 appears during the data writing stage T2 (the data writing stage T2 overlaps with the light-emitting stage T3).

[0087] Optionally, between two light-emitting stages T3, the time interval between the start time of the first reset stage T1 executed for the first time and the end time of the light-emitting stage T3 adjacent to the first reset stage T1 is greater than or equal to 2H, which can also leave enough margin between the light-emitting stage and the first reset stage to avoid burns caused by a large current on the first power signal line passing through the driving transistor when a valid pulse of the light-emitting stage T3 appears in the first reset stage T1 (the first reset stage T1 overlaps with the light-emitting stage T3).

[0088] Fig.17 Another timing comparison diagram under the first pulse period P1 and the second pulse period P2 is shown. This embodiment shows a solution in which the effective pulse width of a single first reset phase T1 is larger than the effective pulse width of a single data writing phase T2 under the same pulse period.

[0089] Please refer to Fig.17In an optional embodiment of the present application, at least in the second pulse period P2, the width t010 of the effective pulse of the single first reset stage T1 is greater than the width t020 of the effective pulse of the single data writing stage T2. When the effective pulse width of the single first reset stage T1 is greater than the effective pulse width of the single data writing stage T2, it is equivalent to that the time for resetting the gate of the driving transistor is greater than the time for writing data, which is conducive to prolonging the characteristic recovery time of the driving transistor, so that the characteristics of the driving transistor before the light-emitting stage T3 can be better restored.

[0090] Continue to wipe the test Fig.17 In an optional embodiment of the present application, under the first pulse period P1 and the second pulse period P2, the width t010 of the effective pulse of the single first reset stage T1 is greater than or equal to 2H, where H is the time required to scan a row of sub-pixels in the display panel. When the width of the effective pulse of the single first reset stage T1 is set to be greater than or equal to 2H, the time for resetting the gate of the driving transistor at a single time, that is, the time for the driving transistor to recover its characteristics is greater than or equal to the time required to scan two rows of sub-pixels in the display panel, which is equivalent to effectively extending the time for the recovery of the characteristics of the driving transistor, which is more conducive to the recovery of the characteristics of the driving transistor before the next light-emitting stage T3, and weakening or avoiding the display smear phenomenon caused by the failure to recover the characteristics of the driving transistor.

[0091] Fig.18 FIG. 1 is a diagram showing a corresponding relationship between control lines and pixel rows in a display panel, wherein the sub-pixel row L0 is only for illustration. In fact, each sub-pixel row L0 corresponds to a plurality of pixel driving circuits. Fig.18 The connection relationship between the control line and the two sub-pixel rows L0 is shown. Figure 7 , Figure 8 and Fig.18 In an optional embodiment of the present application, the pixel driving circuits corresponding to at least two rows of sub-pixels in the display panel share the same first reset stage T1, that is, the same first reset module 30 is used to reset the gates of the driving transistors in the pixel driving circuits corresponding to at least two sub-pixel rows L0, which is beneficial to simplify the driving timing of the display panel, reduce the number of shift registers connected to the control lines, and further facilitate the realization of a narrow bezel design of the display panel.

[0092] Continue to combine Figure 7 and Fig.18Optionally, at least one of the first control line SN1, the second control line SN2, and the light emitting control line EMIT is electrically connected to the pixel driving circuits corresponding to the light emitting elements in N sub-pixel rows L0, N≥2; the third control line Scan is only electrically connected to the pixel driving circuits corresponding to the light emitting elements in the same sub-pixel row L0. It should be noted that Fig.18 The first control line SN1, the second control line SN2 and the light emitting control line EMIT are respectively electrically connected to the pixel driving circuits corresponding to the light emitting elements in two pixel rows for explanation, that is, one of the above control lines drives two pixel rows. In some other embodiments of the present invention, one of the above control lines can also drive three or more pixel rows, which is not specifically limited in the present invention. Fig.18 , the same shift register 90 is connected to the first reset module 30 in the pixel driving circuit of the two sub-pixel rows L0, and the first node N1 of the pixel driving circuit in the two sub-pixel rows L0 is reset through the control of the first control line SN1; the same shift register 90 is connected to the compensation module 20 of the pixel driving circuit in the two sub-pixel rows L0, and the threshold compensation in the pixel driving circuit corresponding to the two sub-pixel rows L0 is realized through the control of the second control line SN2; similarly, the same shift register 90 is connected to the light emitting control module 40 in the two sub-pixel rows L0, and the light emitting phase corresponding to the two sub-pixel rows L0 is controlled through the control of the light emitting control line EM. In this way, it is equivalent to using the same shift register 90 to provide signals to the pixel driving circuits in the two sub-pixel rows L0. Compared with the method in which one shift register 90 only corresponds to the pixel driving circuit in one sub-pixel row L0, the number of shift registers 90 included in the display panel is greatly reduced, and thus, due to the reduction of the space occupied by the shift register 90 in the border area of ​​the display panel, the narrow border design of the display panel is realized.

[0093] Based on the same inventive concept, the present invention also provides a display panel. Fig.19The structure diagram of a display panel provided by an embodiment of the present invention is shown, and the display panel is driven by the driving method provided by any of the above embodiments. In the driving method provided by the above embodiments, the duration between the first reset stage and the data writing stage in the second pulse cycle with a smaller duty cycle is extended. Since the gate of the driving transistor is reset between the start time of the first reset stage and the start time of the data writing stage, that is, the threshold compensation and characteristic recovery process of the driving transistor, when this part of the duration is extended, it is equivalent to extending the time for characteristic recovery of the driving transistor. The longer the threshold compensation time is, the more conducive it is to restore the characteristics of the driving transistor to the initial state, thereby helping to improve the ghosting phenomenon caused by the failure to restore the characteristics of the driving transistor. The present application adjusts the time for characteristic recovery of the driving transistor in different pulse cycles according to different duty cycles, which is conducive to improving the overall display effect of the display panel under different duty cycles.

[0094] The display panel provided in this embodiment can be a display panel using organic light-emitting diode display technology, that is, an OLED (Organic Light-Emitting Diode) display panel. Optionally, the basic structure of the light-emitting layer of the OLED display panel generally includes an anode, a light-emitting material layer and a cathode. When the power supply supplies an appropriate voltage, the holes of the anode and the electrons of the cathode will combine in the light-emitting material layer to produce bright light. Compared with thin-film field-effect transistor liquid crystal displays, OLED display devices have the characteristics of high visibility and high brightness, and are more power-saving, light in weight and thin in thickness. Of course, in some other embodiments of the present invention, the display panel may also be a display panel using inorganic light-emitting diode display technology, such as a Micro LED display panel, or a Mini LED display panel, etc.

[0095] It is understandable that the display panel provided in the embodiment of the present invention can be applied to other display devices with display functions such as computers, mobile phones, and tablets, and the present invention does not specifically limit this. The display panel provided in the embodiment of the present invention has the beneficial effects of the driving method of the display panel provided in the embodiment of the present invention. For details, please refer to the specific description of the display panel in the above embodiments, and this embodiment will not be repeated here.

[0096] In summary, the display panel driving method and the display panel provided by the present invention achieve at least the following beneficial effects:

[0097] In the display panel driving method and display panel provided by the embodiment of the present invention, the working phases of the pixel driving circuit include a first reset phase, a data writing phase and a light emitting phase, wherein the first reset phase is used to reset the gate of the driving transistor in the pixel driving circuit. The display panel includes two pulse cycles with different duty cycles, and the first duty cycle corresponding to the first pulse cycle is greater than the second duty cycle corresponding to the second pulse cycle. At this time, the interval t2 between the starting moment of the first reset stage and the starting moment of the data writing stage in the second pulse cycle is set to be greater than the interval t1 between the starting moment of the first reset stage and the starting moment of the data writing stage in the first pulse cycle, which is equivalent to extending the duration between the first reset stage and the data writing stage in the second pulse cycle with a smaller duty cycle. Since the gate of the driving transistor is reset between the starting moment of the first reset stage and the starting moment of the data writing stage, that is, the process of threshold compensation and characteristic recovery of the driving transistor, when this part of the duration is extended, it is equivalent to extending the time for characteristic recovery of the driving transistor. The longer the threshold compensation time is, the more conducive it is to restore the characteristics of the driving transistor to the initial state, thereby helping to improve the ghosting phenomenon caused by the failure to restore the characteristics of the driving transistor well, and helping to improve the overall display effect of the display panel.

[0098] Although some specific embodiments of the present invention have been described in detail by way of example, it will be appreciated by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It will be appreciated by those skilled in the art that the above embodiments may be modified without departing from the scope and spirit of the present invention. The scope of the present invention is defined by the appended claims.

Claims

1. A method for driving a display panel, characterized in that: The display panel comprises a plurality of sub-pixels and a pixel driving circuit correspondingly connected to the sub-pixels, wherein the pixel driving circuit comprises a driving transistor; the working phases of the pixel driving circuit comprise a first reset phase, a data writing phase and a light emitting phase, wherein the starting time of the data writing phase is after the starting time of the first reset phase and before the starting time of the light emitting phase, and the first reset phase is at least used to reset the gate of the driving transistor; The display panel includes a first pulse cycle and a second pulse cycle, in which the duty cycle of the light-emitting control signal in the light-emitting stage is a first duty cycle in the first pulse cycle; in which the duty cycle of the light-emitting control signal in the light-emitting stage is a second duty cycle in the second pulse cycle, wherein the first duty cycle is greater than the second duty cycle; In the first pulse cycle, the interval between the start time of the first reset phase and the start time of the data writing phase is t1; in the second pulse cycle, the interval between the start time of the first reset phase and the start time of the data writing phase is t2, where t1<t2.

2. The method for driving a display panel according to claim 1, wherein: In the first pulse cycle, the effective pulse width corresponding to a single first reset stage is t11; in the second pulse cycle, the effective pulse width corresponding to a single first reset stage is t12, wherein t11<t12.

3. The method for driving a display panel according to claim 1, wherein: The data writing phase includes a compensation phase and a data writing phase, and the compensation phase and the data writing phase are performed simultaneously; the starting time of the data writing phase is after the ending time of the first resetting phase.

4. The method for driving a display panel according to claim 3, wherein: The driving circuit includes a data writing module and a compensation module, the data writing module is connected to the first electrode of the driving transistor, and the compensation module is connected between the second electrode and the gate of the driving transistor. In the data writing stage, the data writing module and the compensation module are turned on at the same time.

5. The method for driving a display panel according to claim 1, wherein: The data writing phase includes a first sub-phase and a second sub-phase, the first sub-phase is at least used to reset the second pole of the driving transistor, and the second sub-phase is at least used to compensate for the gate potential of the driving transistor; the starting time of the first sub-phase is between the starting time and the ending time of the first reset phase, and the ending time of the first sub-phase is after the ending time of the first reset phase; the second sub-phase is between the starting time and the ending time of the first sub-phase, and is after the ending time of the first reset phase.

6. The method for driving a display panel according to claim 5, characterized in that: The driving circuit includes a data writing module and a compensation module, the data writing module is connected to the first electrode of the driving transistor, and the compensation module is connected between the second electrode and the gate of the driving transistor; the control ends of the data writing module and the compensation module are respectively connected to different control signal ends; the compensation module is turned on in both the first sub-stage and the second sub-stage, and the data writing module is turned on in the second sub-stage.

7. The method for driving a display panel according to claim 1, wherein: In the first pulse cycle and the second pulse cycle, the first reset phase and the data writing phase are performed at least N times, wherein the starting time of the i-th data writing phase is after the starting time of the i-th first reset phase, 1≤i≤N, i is an integer, and N is an integer greater than or equal to 2.

8. The method for driving a display panel according to claim 7, wherein: In the first pulse cycle, the time interval between the start time of the mth first reset phase and the start time of the mth data writing phase is t01, and the time interval between the start time of the m+1th first reset phase and the start time of the m+1th data writing phase is t02, wherein 1≤m<N, t01=t02; Under the second pulse cycle, the time interval between the starting moment of the mth first reset phase and the starting moment of the mth data writing phase is t21, and the time interval between the starting moment of the m+1th first reset phase and the starting moment of the m+1th data writing phase is t22, wherein t21=t22, t21>t01.

9. The method for driving a display panel according to claim 7, wherein: In the first pulse cycle, the time interval between the start time of the first reset phase for the first time and the start time of the first data writing phase is t31, and the time interval between the start time of the Mth first reset phase and the start time of the Mth data writing phase is t32, wherein 2≤M≤N, t31>t32; Under the second pulse cycle, the time interval between the starting moment of the first reset phase for the first time and the starting moment of the first data writing phase is t41, and the time interval between the starting moment of the Mth first reset phase and the starting moment of the Mth data writing phase is t42, wherein t41>t42≥t31.

10. The method for driving a display panel according to claim 7, wherein: In the first pulse cycle or the second pulse cycle, the time interval between the starting moment of the Pth first reset phase and the starting moment of the Pth data writing phase is t03, and the time interval between the starting moment of the P+1th first reset phase and the starting moment of the P+1th data writing phase is t04, where 1≤P<N, t03>t04.

11. The method for driving a display panel according to claim 7, wherein: In the first pulse period or the second pulse period, the effective pulse widths of N times in the first reset phase present an increasing or decreasing trend, and the widths of the invalid pulses between two adjacent effective pulses are the same.

12. The method for driving a display panel according to claim 7, wherein: In the first pulse period or the second pulse period, the effective pulse widths of N times in the first reset phase are the same, and the width of the invalid pulse between two adjacent effective pulses is increasing or decreasing.

13. The method for driving a display panel according to claim 1, wherein: Under the first pulse cycle, the time interval between the end moment of the last execution of the data writing phase and the start moment of the light-emitting phase is t10; under the second pulse cycle, the time interval between the end moment of the last execution of the data writing phase and the start moment of the light-emitting phase is t20, where t10=t20.

14. The method for driving a display panel according to claim 13, wherein: t10 is greater than or equal to 2H, where H is the time required to scan a row of sub-pixels in the display panel.

15. The method for driving a display panel according to claim 1, wherein: At least in the second pulse period, the width of a single effective pulse in the first reset phase is greater than the width of a single effective pulse in the data writing phase.

16. The method for driving a display panel according to claim 1, wherein: In the first pulse period and the second pulse period, the width of a single effective pulse in the first reset phase is greater than or equal to 2H, where H is the time required to scan a row of sub-pixels in the display panel.

17. The method for driving a display panel according to claim 16, wherein: The pixel driving circuits corresponding to at least two rows of sub-pixels in the display panel share the same first reset stage.

18. A display panel, characterized in that: The display panel is driven by the driving method of any one of claims 1 to 17.

Images