Pixel circuit and display panel comprising the same

Abstract

Disclosed in embodiments are pixel circuits and display panels including the same. A pixel circuit according to an embodiment includes a drive element including a gate connected to a first node to which a data voltage is applied, a first electrode connected to a high-potential voltage line, and a second electrode connected to a second node; a first switching element connected between the second node and a third node; a second switching element connected between the second node and a fourth node; a third switching element connected between the fourth node and a reference voltage line; a first capacitor connected between the first node and the third node; and a second capacitor connected between the third node and the fourth node.

Description

Technical Field

[0001] This disclosure relates to pixel circuits and display panels including therewith. Background Technology

[0002] Display devices include liquid crystal display (LCD) devices, electroluminescent display devices, field emission display (FED) devices, plasma display panels (PDP), etc.

[0003] Electroluminescent display devices are classified into inorganic and organic light-emitting display devices based on the material of their light-emitting layer. Active-matrix organic light-emitting display devices use self-emissive elements (e.g., organic light-emitting diodes, hereinafter referred to as "OLEDs") to reproduce input images. The advantages of organic light-emitting display devices include fast response times, high luminous efficiency, brightness, and wide viewing angles.

[0004] Some display devices, such as liquid crystal displays or organic light-emitting displays, include: a display panel comprising a plurality of subpixels; a driver outputting drive signals for driving the display panel; a power supply generating power to be supplied to the display panel or the driver, etc. The driver includes a gating driver that provides scan signals or gating signals to the display panel, and a data driver that provides data signals to the display panel.

[0005] Each of the multiple pixels includes a driving element that controls the driving current flowing through the organic light-emitting diode (OLED) based on the voltage (Vgs) between the gate electrode and the source electrode. The electrical characteristics of the driving element may degrade over time and therefore vary for each pixel. Therefore, OLED displays compensate for the degradation of the driving element through internal or external compensation schemes. Summary of the Invention

[0006] However, due to the effects of parasitic capacitance generated in the circuit wiring that constitutes pixels, data voltage loss may occur, which may reduce the data transmission rate.

[0007] This disclosure aims to address all the aforementioned needs and problems.

[0008] This disclosure provides a pixel circuit and a display panel including the pixel circuit.

[0009] It should be noted that the purpose of this disclosure is not limited to the above-described purposes, and other purposes of this disclosure will be apparent to those skilled in the art from the following description.

[0010] The pixel circuit according to this disclosure includes: a driving element comprising a gate connected to a first node to which a data voltage is applied, a first electrode connected to a high-potential voltage line, and a second electrode connected to a second node; a first switching element connected between the second node and a third node; a second switching element connected between the second node and a fourth node; a third switching element connected between the fourth node and a reference voltage line; a first capacitor connected between the first node and the third node; and a second capacitor connected between the third node and the fourth node.

[0011] According to this disclosure, the reduction caused by boosting loss can be fully compensated by sensing the threshold voltage of the driving element twice, thereby improving the compensation performance of the internal compensation.

[0012] This disclosure can improve image quality by adequately compensating for the reduction in threshold voltage deviation of the driving elements between pixels due to boost loss, and thus improving the image quality.

[0013] The effects of this disclosure are not limited to those described above, and other effects not mentioned will be clearly understood by those skilled in the art through the following description and the appended claims. Attached Figure Description

[0014] The above and other objects, features, and advantages of this disclosure will become more apparent to those skilled in the art from the detailed description of exemplary embodiments thereof with reference to the accompanying drawings, wherein:

[0015] Figure 1 This is a diagram illustrating a pixel circuit according to a first embodiment of the present disclosure;

[0016] Figures 2A to 3B This is a diagram illustrating the internal compensation principle of a pixel circuit according to a first embodiment of the present disclosure;

[0017] Figure 4 This is a diagram illustrating a pixel circuit according to a second embodiment of the present disclosure;

[0018] Figure 5 This is an example Figure 4 The diagram shows the driving timing of the pixel circuit.

[0019] Figures 6A to 10B This is an example Figure 4 The diagram shows the driving principle of the pixel circuit.

[0020] Figure 11 This is a diagram illustrating a pixel circuit according to a third embodiment of the present disclosure;

[0021] Figure 12 This is a diagram illustrating a pixel circuit according to a fourth embodiment of the present disclosure;

[0022] Figure 13 yes Figure 12 The diagram shows the driving timing of the pixel circuit.

[0023] Figures 14A to 17B This is an example Figure 12 The diagram shows the driving principle of the pixel circuit.

[0024] Figure 18 This is a diagram illustrating a pixel circuit according to a fifth embodiment of the present disclosure;

[0025] Figure 19 This is a diagram illustrating a pixel circuit according to a sixth embodiment of the present disclosure;

[0026] Figure 20 This is an example Figure 19 The diagram shows the driving timing of the pixel circuit.

[0027] Figure 21A and Figure 21B This is a diagram illustrating the simulation results of the compensation performance of the pixel circuit according to the implementation method;

[0028] Figure 22 This is a block diagram illustrating a display device according to an embodiment of the present disclosure; and

[0029] Figure 23 This is an example Figure 22 The diagram shows the cross-sectional structure of the display panel. Detailed Implementation

[0030] The advantages and features of this disclosure, and its implementation methods, will become clearer from the embodiments described below with reference to the accompanying drawings. However, this disclosure is not limited to the following embodiments, but can be implemented in various different forms. Rather, these embodiments will make the disclosure complete and allow those skilled in the art to fully understand its scope. This disclosure is limited only by the scope of the appended claims.

[0031] The shapes, dimensions, ratios, angles, quantities, etc., shown in the accompanying drawings to describe embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. Throughout this specification, similar reference numerals generally denote similar elements. Furthermore, in describing this disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure.

[0032] Terms such as “including,” “containing,” “having,” and “consisting of” as used herein are generally intended to allow for the addition of other components, unless these terms are used in conjunction with the term “only.” Unless otherwise expressly stated, any reference to the singular may include the plural.

[0033] Even if not explicitly stated, components are interpreted as including the normal error range.

[0034] When using terms such as “on,” “above,” “below,” and “next to” to describe the positional relationship between two components, one or more components may be located between the two components, unless these terms are used with the terms “immediately” or “directly.”

[0035] The terms “first”, “second”, etc., can be used to distinguish components from each other, but the function or structure of a component is not limited by the serial number or component name preceding the component.

[0036] Throughout this disclosure, the same reference numerals may refer to substantially the same elements.

[0037] The following implementations can be partially or wholly combined or integrated with each other, and can be linked and operated in various technical ways. These implementations can be performed independently of each other or in relation to each other.

[0038] In the following, various embodiments of this disclosure will be described in detail with reference to the accompanying drawings.

[0039] Figure 1 This is a diagram illustrating a pixel circuit according to a first embodiment of the present disclosure, and Figures 2A to 3B This is a diagram illustrating the internal compensation principle of a pixel circuit according to a first embodiment of the present disclosure.

[0040] Reference Figure 1 , Figure 2A , Figure 2B , Figure 3A and Figure 3B The pixel circuit according to embodiments of the present disclosure includes a light-emitting element EL, a driving element DT for supplying current to the light-emitting element EL, a plurality of switching elements M01, M02, and M03 for switching a current path connected to the driving element DT, a first capacitor Cst for storing the gate-source voltage of the driving element DT, and a second capacitor Cdual. The driving element DT and the switching elements M01, M02, and M03 can be implemented as an N-channel oxide TFT.

[0041] The light-emitting element EL emits light through a current applied through the channel of the driving element DT, which varies according to the data voltage Vdata. The light-emitting element EL can be implemented as an OLED comprising an organic compound layer formed between the anode and cathode. The organic compound layer may include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), an emissive layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). The anode of the light-emitting element EL is connected to the driving element DT via a third node n3, and the cathode of the light-emitting element EL is connected to a second power line that is supplied with a low-potential power supply voltage EVSS.

[0042] Organic light-emitting diodes (OLEDs) used as light-emitting elements can have a series structure with multiple stacked light-emitting layers. OLEDs with a series structure can improve pixel brightness and lifespan.

[0043] The driving element DT drives the light-emitting element EL by providing current to the light-emitting element EL according to the gate-source voltage Vgs. The driving element DT includes a gate electrode connected to the first node n1, a first electrode (or drain) connected to the first power supply line to which a high potential power supply voltage EVDD is applied, and a second electrode (or source) connected to the second node n2.

[0044] The first switching element M01 is turned on according to the selection voltage of the first gating signal GATE1, and connects the second electrode of the driving element DT to the anode of the light-emitting element EL. The first switching element M01 includes a gate connected to a first gating line to which the first gating signal GATE1 is applied, a first electrode connected to a second node n2, and a second electrode connected to a third node n3.

[0045] The second switching element M02 is turned on according to the selection voltage of the second strobe signal GATE2, and connects the second node n2 connected to the second electrode of the driving element DT to the fourth node n4. The second switching element M02 includes a gate connected to the second strobe line to which the second strobe signal GATE2 is applied, a first electrode connected to the second node n2, and a second electrode connected to the fourth node n4.

[0046] The third switching element M03 is turned on according to the selection voltage of the third gating signal GATE3, and connects the fourth node n4 to the reference voltage line. The third switching element M03 includes a gate connected to the third gating line to which the third gating signal GATE3 is applied, a first electrode connected to the fourth node n4, and a second electrode connected to the reference voltage line to which the reference voltage Vref is applied.

[0047] The first capacitor Cst is connected between the first node n1 and the third node n3. The first capacitor Cst charges the gate-source voltage Vgs of the driving element DT. Figure 2A and Figure 2B As shown, when the first switching element M01 and the third switching element M03 are turned on and the second switching element M02 is turned off during the first sensing period, the voltage of the third node n3 has a deviation of ΔVth, and the source voltage Vs of the driving element DT can rise to Vg-Vth, which is the difference between the gate voltage Vg and the threshold voltage Vth. At this time, the threshold voltage can be stored in the first capacitor Cst and compensated once.

[0048] In this case, the voltage at the third node n3 is indicated by solid and dashed lines. This is to indicate the deviation of the threshold voltage Vth of the driving element, for example, the deviation between the solid line (Vth = 0V) and the dashed line (Vth = 1V).

[0049] The second capacitor, Cdual, is connected between the third node n3 and the fourth node n4. The second capacitor, Cdual, transmits a predetermined compensation voltage α to the third node n3. For example... Figure 3A and Figure 3B As shown, when the first switching element M01 and the third switching element M03 are turned off and the second switching element M02 is turned on during the second sensing period, the voltage of the fourth node n4 also has a deviation of ΔVth, and the compensation voltage α is transmitted to the third node n3 through the second capacitor Cdual. Therefore, the source voltage Vs of the driving element DT can rise to Vg-(Vth+α), which is the difference between the gate voltage Vg and the threshold voltage Vth+α. At this time, the threshold voltage can be stored in the first capacitor Cst and compensated twice.

[0050] In this case, the compensation voltage α is a value used to compensate for the boost loss that occurs during the boost process. The compensation voltage α can vary depending on the duration of the second sensing period.

[0051] Figure 4 This is a diagram illustrating a pixel circuit according to a second embodiment of the present disclosure. Figure 5 This is an example Figure 4 The diagram shows the driving timing of the pixel circuit, and Figures 6A to 10B This is an example Figure 4 The diagram shows the driving principle of the pixel circuit.

[0052] Reference Figure 4The pixel circuit according to the second embodiment of this disclosure includes a light-emitting element EL, a driving element DT for providing current to the light-emitting element EL, a plurality of switching elements M01, M02, M03, M04, M05 and M06 for switching current paths connected to the driving element DT, a first capacitor Cst for storing the gate-source voltage of the driving element DT, and a second capacitor Cdual. The driving element DT and the switching elements M01, M02, M03, M04, M05 and M06 can be implemented as an N-channel oxide TFT.

[0053] The first switching element M01 is turned on according to the gating voltage of the EM signal EM and connects the second electrode of the driving element DT to the anode of the light-emitting element EL. The first switching element M01 includes a gate connected to the first gating line to which the EM signal is applied, a first electrode connected to the second node n2, and a second electrode connected to the third node n3.

[0054] The second switching element M02 is turned on according to the gating voltage of the first sensing signal SENSE1 and connects the second node n2, which is connected to the second electrode of the driving element DT, to the fourth node n4. The second switching element M02 includes a gate connected to the second gating line to which the first sensing signal SENSE1 is applied, a first electrode connected to the second node n2, and a second electrode connected to the fourth node n4.

[0055] The third switching element M03 is turned on according to the gating voltage of the second sensing signal SENSE2 and connects the fourth node n4 to the reference voltage line to apply a reference voltage. The third switching element M03 includes a gate connected to the third gating line to which the second sensing signal SENSE2 is applied, a first electrode connected to the fourth node n4, and a second electrode connected to the reference voltage line to which the reference voltage Vref is applied.

[0056] The fourth switching element M04 is turned on according to the gating voltage of the third sensing signal SENSE3 and connects the reference voltage line to the third node n3 to apply a reference voltage. The fourth switching element M04 includes a gate connected to the fourth gating line to which the third sensing signal SENSE3 is applied, a first electrode connected to the third node n3, and a second electrode connected to the reference voltage line to which the reference voltage Vref is applied.

[0057] The fifth switching element M05 applies an initialization voltage in response to the initialization signal INIT. In this case, the initialization voltage is applied to the first node n1 through the initialization voltage line. The fifth switching element M05 includes a gate to which the initialization signal INIT is applied, a first electrode connected to the initialization voltage line, and a second electrode connected to the first node n1.

[0058] The sixth switching element M06 is turned on according to the strobe voltage of the scan signal SCAN and connects the data voltage line to the first node n1 to apply a data voltage. The sixth switching element M06 includes a gate connected to the second strobe line to which the scan signal SCAN is applied, a first electrode connected to the data voltage line to which the data voltage is applied, and a second electrode connected to the first node n1.

[0059] Reference Figure 5 During the first sensing period, the first switching element M01, the third switching element M03, and the fifth switching element M05 are turned on, while the second switching element M02, the fourth switching element M04, and the sixth switching element M06 are turned off.

[0060] During the second sensing period, the second switching element M02 and the fifth switching element M05 are turned on, while the first switching element M01, the third switching element M03, the fourth switching element M04 and the sixth switching element M06 are turned off.

[0061] Reference Figure 6A and Figure 6B During the initialization period, the first switching element M01, the third switching element M03, the fourth switching element M04, and the fifth switching element M05 are turned on, while the second switching element M02 and the sixth switching element M06 are turned off. The initialization voltage is applied to the first node n1 through the fifth switching element M05. The reference voltage is applied to the third node n3 and the fourth node n4 through the third switching element M03 and the fourth switching element M04, respectively.

[0062] Reference Figure 7A and Figure 7B During the first sensing period, the first switching element M01, the third switching element M03, and the fifth switching element M05 are turned on, while the second switching element M02, the fourth switching element M04, and the sixth switching element M06 are turned off.

[0063] Due to the current flowing through the driving element DT, the voltage at the third node n3 has a deviation of ΔVth, and the source voltage Vs of the driving element DT can rise to the difference Vg-Vth, which is the difference between the gate voltage Vg and the threshold voltage Vth. At this time, the threshold voltage can be stored in the first capacitor Cst and compensated once.

[0064] Reference Figures 8A to 8B During the second sensing period, the second switching element M02 and the fifth switching element M05 are turned on, while the first switching element M01, the third switching element M03, the fourth switching element M04 and the sixth switching element M06 are turned off.

[0065] In this case, although the period during which the third switching element M03 is turned on partially overlaps with the period during which the second switching element M02 is turned on, it is not necessarily limited to this. When the period during which the third switching element M03 is turned on partially overlaps with the period during which the second switching element M02 is turned on, the fluctuation range of the compensation voltage α can be reduced.

[0066] The voltages at the second node n2 and the fourth node n4 also deviate by ΔVth due to the current flowing through the driving element DT, and the compensation voltage α is transmitted to the third node n3 through the second capacitor Cdual. Therefore, the source voltage Vs of the driving element DT can rise to Vg-(Vth+α), which is the difference between the gate voltage Vg and the threshold voltage Vth+α, and at this time the threshold voltage can be stored in the first capacitor Cst and compensated twice.

[0067] Reference Figure 9A and Figure 9B During the writing period, the sixth switching element M06 is turned on, and the first switching element M01, the second switching element M02, the third switching element M03, the fourth switching element M04 and the fifth switching element M05 are turned off.

[0068] The data voltage Vdata is applied to the first node n1 through the sixth switching element M06, thereby increasing the voltage of the first node n1. The voltage of the first node n1 rises from Vinit to Vdata.

[0069] Reference Figure 10A and Figure 10B During the boost and light emission periods, the first switching element M01 is turned on, while the second switching element M02, the third switching element M03, the fourth switching element M04, the fifth switching element M05, and the sixth switching element M06 are turned off.

[0070] As current flows through the driving element DT, the voltage at the third node increases, and the gate node of the driving element DT (i.e., the first node n1) is in a floating state. Therefore, the voltage change at the third node n3 is transmitted to the first node n1 through the first capacitor Cst. At this time, 100% of the voltage change at the third node n3 should be transmitted to the first node n1 through the first capacitor Cst, but due to the influence of the parasitic capacitor formed at the gate node, it is not transmitted to 100%, thus resulting in a boost loss. In the embodiment, a threshold voltage including compensation corresponding to the boost loss can be stored in the first capacitor to offset the boost loss. That is, the voltage at the third node becomes Vth + α - β.

[0071] The compensation voltage can vary depending on the ratio of the first capacitor to the second capacitor. The values ​​of the first and second capacitors can be preset. The principle behind setting the values ​​of the first and second capacitors will be described below.

[0072] The equation used to compensate for the boost loss of the threshold voltage Vth is Equation 1 below.

[0073] [Equation 1]

[0074]

[0075] Here, α is the compensation voltage, and B LOSS It is the boost loss rate.

[0076] In Equation 1, the compensation voltage α and the boost loss rate B LOSS As shown in Equations 2 and 3 below.

[0077] [Equation 2]

[0078]

[0079] [Equation 3]

[0080]

[0081] Here, Cst is the first capacitor, Cdual is the second capacitor, and Cpara is the parasitic capacitor.

[0082] Applying Equations 2 and 3 to Equation 1, it is arranged into Equation 4 below.

[0083] [Equation 4]

[0084]

[0085] Divide both sides of Equation 4 by Vth and rearrange them to obtain Equation 5 below.

[0086] [Equation 5]

[0087]

[0088] Calculate the second capacitor (i.e., Cdual) from Equation 5 to obtain Equation 6 below.

[0089] [Equation 6]

[0090]

[0091] Therefore, in the implementation, the value of the capacitor can be set based on Equation 6 above. As shown in Equation 6, the value of the second capacitor can vary depending on the value of the first capacitor. Using the values ​​of the first and second capacitors, the compensation voltage can be obtained from Equation 2.

[0092] Figure 11 This is a diagram illustrating a pixel circuit according to a third embodiment of the present disclosure.

[0093] Reference Figure 11 The pixel circuit according to the third embodiment of this disclosure includes a light-emitting element EL, a driving element DT for supplying current to the light-emitting element EL, a plurality of switching elements M01, M02, M03, M04, M05, M06 and M07 for switching current paths connected to the driving element DT, and a first capacitor Cst, a second capacitor Cdual and a third capacitor C3 for storing the gate-source voltage of the driving element DT. The driving element DT and the switching elements M01, M02, M03, M04, M05, M06 and M07 can be implemented as an N-channel oxide TFT.

[0094] The seventh switching element M07 is turned on according to the EM signal EM's gating voltage and connects the second electrode of the driving element DT to the anode of the light-emitting element EL. The seventh switching element M07 includes a gate connected to the first gating line to which the EM signal is applied, a first electrode connected to the third node n3, and a second electrode connected to the anode of the light-emitting element EL.

[0095] The seventh switching element M07, together with the first switching element M01, is turned off according to the gate cutoff voltage of the EM signal EM, thereby reducing the deviation of Coled shown in Equation 2 above.

[0096] The third capacitor C3 is connected between the third node n3 and the second high-potential voltage line. When a data voltage is applied, the third capacitor C3 can suppress the voltage increase at the source node of the driving element.

[0097] Figure 12 This is a diagram illustrating a pixel circuit according to a fourth embodiment of the present disclosure. Figure 13 yes Figure 12 The diagram shows the driving timing of the pixel circuit, and Figures 14A to 17B This is an example Figure 12 The diagram shows the driving principle of the pixel circuit.

[0098] Reference Figure 12The pixel circuit according to the fourth embodiment of this disclosure includes a light-emitting element EL, a driving element DT for providing current to the light-emitting element EL, a plurality of switching elements M01, M02, M03, M04, M05 and M06 for switching a current path connected to the driving element DT, a first capacitor Cst for storing the gate-source voltage of the driving element DT, and a second capacitor Cdual. The driving element DT and the switching elements M01, M02, M03, M04, M05 and M06 can be implemented as an N-channel oxide TFT.

[0099] The first switching element M01 is turned on according to the gating voltage of the EM signal EM and connects the second electrode of the driving element DT to the anode of the light-emitting element EL. The first switching element M01 includes a gate connected to the first gating line to which the EM signal is applied, a first electrode connected to the second node n2, and a second electrode connected to the third node n3.

[0100] The second switching element M02 is turned on according to the strobe voltage of the scan signal SCAN and connects the second node n2, which is connected to the second electrode of the driving element DT, to the fourth node n4. The second switching element M02 includes a gate connected to the second strobe line to which the scan signal SCAN is applied, a first electrode connected to the second node n2, and a second electrode connected to the fourth node n4.

[0101] The third switching element M03 is turned on according to the gating voltage of the initialization signal INIT and connects the fourth node n4 to the reference voltage line to apply a reference voltage. The third switching element M03 includes a gate connected to the third gating line to which the initialization signal INIT is applied, a first electrode connected to the fourth node n4, and a second electrode connected to the reference voltage line to which the reference voltage Vref is applied.

[0102] The fourth switching element M04 is turned on according to the gating voltage of the sensing signal SENSE and connects the reference voltage line to the third node n3 to apply a reference voltage. The fourth switching element M04 includes a gate connected to the fourth gating line to which the sensing signal SENSE is applied, a first electrode connected to the third node n3, and a second electrode connected to the reference voltage line to which the reference voltage Vref is applied.

[0103] The fifth switching element M05 applies an initialization voltage in response to the initialization signal INIT. In this case, the initialization voltage is applied to the first node n1 through the initialization voltage line. The fifth switching element M05 includes a gate to which the initialization signal INIT is applied, a first electrode connected to the initialization voltage line, and a second electrode connected to the first node n1.

[0104] The sixth switching element M06 is turned on according to the strobe voltage of the scan signal SCAN and connects the data voltage line to the first node n1 to apply a data voltage. The sixth switching element M06 includes a gate connected to the second strobe line to which the scan signal SCAN is applied, a first electrode connected to the data voltage line to which the data voltage is applied, and a second electrode connected to the first node n1.

[0105] Reference Figure 13 During the first sensing period, the first switching element M01, the third switching element M03, and the fifth switching element M05 are turned on, while the second switching element M02, the fourth switching element M04, and the sixth switching element M06 are turned off.

[0106] During the second sensing period, the second switching element M02 and the fifth switching element M05 are turned on, while the first switching element M01, the third switching element M03, the fourth switching element M04 and the sixth switching element M06 are turned off.

[0107] Reference Figure 14A and Figure 14B During the initialization period, the first switching element M01, the third switching element M03, the fourth switching element M04, and the fifth switching element M05 are turned on, while the second switching element M02 and the sixth switching element M06 are turned off. The initialization voltage is applied to the first node n1 through the fifth switching element M05. The reference voltages are applied to the third node n3 and the fourth node n4 through the third switching element M03 and the fourth switching element M04, respectively.

[0108] Reference Figure 15A and Figure 15B During the first sensing period, the first switching element M01, the third switching element M03, and the fifth switching element M05 are turned on, while the second switching element M02, the fourth switching element M04, and the sixth switching element M06 are turned off.

[0109] Due to the current flowing through the driving element DT, the voltage at the third node n3 has a deviation of ΔVth, and the source voltage Vs of the driving element DT can rise to the difference Vg-Vth, which is the difference between the gate voltage Vg and the threshold voltage Vth. At this time, the threshold voltage can be stored in the first capacitor Cst and compensated once.

[0110] Reference Figures 16A to 16B During the writing and second sensing periods, the second switching element M02 and the sixth switching element M06 are turned on, while the first switching element M01, the third switching element M03, the fourth switching element M04 and the fifth switching element M05 are turned off.

[0111] The data voltage Vdata is applied to the first node n1 through the sixth switching element M06, thereby increasing the voltage of the first node n1. The voltage of the first node n1 rises from Vinit to Vdata.

[0112] The voltages at the second node n2 and the fourth node n4 also deviate by ΔVth due to the current flowing through the driving element DT, and the compensation voltage α is transmitted to the third node n3 through the second capacitor Cdual. Therefore, the source voltage Vs of the driving element DT can rise to Vg-(Vth+α), which is the difference between the gate voltage Vg and the threshold voltage Vth+α. At this time, the threshold voltage Vth+α can be stored in the first capacitor Cst and compensated twice.

[0113] Reference Figure 17A and Figure 17B During the boost and light emission periods, the first switching element M01 is turned on, and the second switching element M02, the third switching element M03, the fourth switching element M04, the fifth switching element M05, and the sixth switching element M06 are turned off.

[0114] As current flows through the driving element DT, the voltage at the third node increases, and the gate node of the driving element DT (i.e., the first node n1) is in a floating state. Therefore, the voltage change at the third node n3 is transmitted to the first node n1 through the first capacitor Cst. At this time, 100% of the voltage change at the third node n3 should be transmitted to the first node n1 through the first capacitor Cst, but due to the influence of the parasitic capacitor formed at the gate node, it is not transmitted to 100%, thus resulting in a boost loss. In the embodiment, a threshold voltage including compensation corresponding to the boost loss can be stored in the first capacitor to offset the boost loss. That is, the voltage at the third node becomes Vth + α - β.

[0115] Figure 18 This is a diagram illustrating a pixel circuit according to a fifth embodiment of the present disclosure.

[0116] Reference Figure 18 The pixel circuit according to the fifth embodiment of this disclosure includes a light-emitting element EL, a driving element DT for providing current to the light-emitting element EL, a plurality of switching elements M01, M02, M03, M04, M05, M06 and M07 for switching current paths connected to the driving element DT, a first capacitor Cst for storing the gate-source voltage of the driving element DT, and a second capacitor Cdual. The driving element DT and the switching elements M01, M02, M03, M04, M05, M06 and M07 can be implemented as an N-channel oxide TFT.

[0117] The seventh switching element M07 is turned on according to the EM signal EM's gating voltage and connects the second electrode of the driving element DT to the anode of the light-emitting element EL. The seventh switching element M07 includes a gate connected to the first gating line to which the EM signal is applied, a second electrode connected to the third node n3, and a second electrode connected to the anode of the light-emitting element EL.

[0118] The seventh switching element M07, together with the first switching element M01, is turned off according to the gate cutoff voltage of the EM signal EM, thereby reducing the deviation of Coled shown in Equation 2 above.

[0119] The third capacitor C3 is connected between the third node n3 and the second high-potential voltage line. When a data voltage is applied, the third capacitor C3 can suppress the voltage increase at the source node of the driving element.

[0120] Figure 19 This is a diagram illustrating a pixel circuit according to a sixth embodiment of the present disclosure. Figure 20 This is an example Figure 19 The diagram shows the driving timing of the pixel circuit.

[0121] Reference Figure 19 The pixel circuit according to the sixth embodiment of this disclosure includes a light-emitting element EL, a driving element DT for supplying current to the light-emitting element EL, a plurality of switching elements M01, M02, M03, M05 and M06 for switching a current path connected to the driving element DT, a first capacitor Cst for storing the gate-source voltage of the driving element DT, and a second capacitor Cdual. The driving element DT and the switching elements M01, M02, M03, M05 and M06 can be implemented as an N-channel oxide TFT.

[0122] The first switching element M01 is turned on according to the gating voltage of the EM signal EM and connects the second electrode of the driving element DT to the anode of the light-emitting element EL. The first switching element M01 includes a gate connected to the first gating line to which the EM signal is applied, a first electrode connected to the second node n2, and a second electrode connected to the third node n3.

[0123] The second switching element M02 is turned on according to the strobe voltage of the scan signal SCAN and connects the second node n2, which is connected to the second electrode of the driving element DT, to the fourth node n4. The second switching element M02 includes a gate connected to the second strobe line to which the scan signal SCAN is applied, a first electrode connected to the second node n2, and a second electrode connected to the fourth node n4.

[0124] The third switching element M03 is turned on according to the gating voltage of the initialization signal INIT and connects the fourth node n4 to the reference voltage line to apply a reference voltage. The third switching element M03 includes a gate connected to the third gating line to which the initialization signal INIT is applied, a first electrode connected to the fourth node n4, and a second electrode connected to the reference voltage line to which the reference voltage Vref is applied.

[0125] The fifth switching element M05 applies an initialization voltage in response to the initialization signal INIT. In this case, the initialization voltage is applied to the first node n1 through the initialization voltage line. The fifth switching element M05 includes a gate to which the initialization signal INIT is applied, a first electrode connected to the initialization voltage line, and a second electrode connected to the first node n1.

[0126] The sixth switching element M06 is turned on according to the strobe voltage of the scan signal SCAN and connects the data voltage line to the first node n1 to apply a data voltage. The sixth switching element M06 includes a gate connected to the second strobe line to which the scan signal SCAN is applied, a first electrode connected to the data voltage line to which the data voltage is applied, and a second electrode connected to the first node n1.

[0127] Reference Figure 20 During the first sensing period, the first switching element M01, the third switching element M03 and the fifth switching element M05 are turned on, while the second switching element M02 and the sixth switching element M06 are turned off.

[0128] During the second sensing period, the second switching element M02 and the fifth switching element M05 are turned on, while the first switching element M01, the third switching element M03 and the sixth switching element M06 are turned off.

[0129] The pixel circuit according to the sixth embodiment has a configuration that removes the fourth switching element M04 from the pixel circuit according to the second embodiment, so the design area can be ensured by removing the switching element.

[0130] It should be noted that, although Figures 1 to 20 Some implementations of the pixel circuit structure and timing operation have been described, but this disclosure is not limited thereto. For example, the pixel circuit structure and timing operation can be modified in various ways, as long as the threshold voltage of the driving element can be sensed twice and / or the reduction due to boost loss can be compensated.

[0131] Figure 21A and Figure 21B This is a graph illustrating simulation results of the compensation performance of the pixel circuit according to an embodiment. More specifically, Figure 21A A diagram illustrating the pixel circuitry and driving timing of the compared pixels is shown. Figure 21BSimulation results of the deviation ΔIOLED of the current flowing through the light-emitting element relative to the threshold voltage ΔVth between the proposed pixel and the compared pixel according to the embodiment are illustrated.

[0132] Reference Figure 21A and Figure 21B As a result of the simulation of the compensation performance between the proposed pixel and the compared pixel according to the implementation method, it can be seen that the compensation performance of the proposed pixel is better than that of the compared pixel. Figure 21A The proposed pixels show more stable compensation performance. In other words, because the proposed pixels adequately compensate for the difference in threshold voltage, it can be seen that the current flowing through the light-emitting element does not change even when there is a difference in threshold voltage.

[0133] For example, using Figure 4 The simulation conditions are as follows: EVDD: 20V, EVSS: 0V, VGH: 18V, VGL: -6V, Cst: 200fF, Cdual: 10fF, Vdata: 4.8V, Vinit: 4.5V and Vref: 0.5V.

[0134] Therefore, by using the pixel circuit according to the embodiment, the threshold voltage deviation of the driving elements between pixels can be improved by sensing the threshold voltage twice, thereby improving image quality.

[0135] Figure 22 This is a block diagram illustrating a display device according to an embodiment of the present disclosure, and Figure 23 This is an example Figure 22 The diagram shows the cross-sectional structure of the display panel.

[0136] Reference Figure 22 The display device according to an embodiment of the present disclosure includes a display panel 100, a display panel driving circuit for writing pixel data to pixels of the display panel 100, and a power supply 140 for generating power required to drive the pixels and the display panel driving circuit.

[0137] The display panel 100 includes a pixel array AA for displaying an input image. The pixel array AA includes multiple data lines 102, multiple gate lines 103 intersecting the data lines 102, and pixels arranged in a matrix.

[0138] The pixel array AA comprises multiple pixel rows L1 to Ln. Each of the pixel rows L1 to Ln comprises a row of pixels arranged along the row direction X in the pixel array AA of the display panel 100. Pixels arranged in a pixel row share a gate line 103. Sub-pixels arranged in the column direction Y along the data line direction share the same data line 102. A horizontal time period 1H is the time obtained by dividing a frame time period by the total number of pixel rows L1 to Ln.

[0139] A touch sensor can be disposed on the display panel 100. Touch input can be sensed using a separate touch sensor or by means of pixels. The touch sensor can be disposed on the screen of the display panel as an on-cell type or an add-on type, or it can be implemented as an in-cell type touch sensor embedded in the pixel array AA.

[0140] The display panel 100 can be implemented as a flexible display panel. The flexible display panel can be made of a plastic OLED panel. An organic thin film can be disposed on the back of the plastic OLED panel, and the pixel array AA can be formed on the organic thin film.

[0141] The backsheet of a plastic OLED can be a polyethylene terephthalate (PET) substrate. An organic thin film is formed on the backsheet. The pixel array (AA) and touch sensor array can be formed on the organic thin film. The backsheet blocks moisture penetration, preventing the pixel array (AA) from being exposed to moisture. The organic thin film can be a thin polyimide (PI) film substrate. A multilayer buffer film can be formed on the organic thin film from an insulating material (not shown). Lines can be formed on the organic thin film to provide power or signals applied to the pixel array (AA) and touch sensor array.

[0142] To achieve color, each pixel can be divided into red subpixels (hereinafter referred to as "R subpixels"), green subpixels (hereinafter referred to as "G subpixels"), and blue subpixels (hereinafter referred to as "B subpixels"). Each pixel may also include a white subpixel. Each subpixel 101 includes pixel circuitry. The pixel circuitry is connected to data line 102 and gate line 103.

[0143] Each pixel is like Figure 1 , Figure 4 , Figure 11 , Figure 12 , Figure 18 and Figure 19 As shown, the threshold voltage of the driving element is compensated by two sensing operations, which can compensate for the reduction caused by boost loss.

[0144] In the following text, a pixel can be interpreted as having the same meaning as a subpixel.

[0145] like Figure 23 As shown, when viewed in cross-section, the display panel 100 may include a circuit layer 12, a light-emitting element layer 14, and an encapsulation layer 16 stacked on the substrate 10.

[0146] Circuit layer 12 may include pixel circuitry connected to wiring such as data lines, gating lines, and power lines; gating drivers (GIPs) connected to the gating lines; a demultiplexer array 112; circuitry (not shown) for automated probe inspection; and so on. The wiring and circuitry elements of circuit layer 12 may include multiple insulating layers, two or more metal layers separated by inter-insulating layers, and active layers comprising semiconductor material. All transistors formed in circuit layer 12 may be implemented as oxide TFTs with an n-channel oxide semiconductor.

[0147] The light-emitting element layer 14 may include light-emitting elements EL driven by pixel circuitry. The light-emitting elements EL may include red (R) light-emitting elements, green (G) light-emitting elements, and blue (B) light-emitting elements. The light-emitting element layer 14 may include white light-emitting elements and color filters. The light-emitting elements EL of the light-emitting element layer 14 may be covered by a protective layer comprising an organic film and a passivation film.

[0148] Encapsulation layer 16 covers light-emitting element layer 14 to seal circuit layer 12 and light-emitting element layer 14. Encapsulation layer 16 may have a multilayer insulating structure in which organic and inorganic films are alternately stacked. Inorganic films block the penetration of moisture and oxygen. Organic films planarize the surface of inorganic films. When organic and inorganic films are stacked in multiple layers, the movement path of moisture or oxygen becomes longer compared to a single layer, making it possible to effectively block the penetration of moisture and oxygen that affect light-emitting element layer 14.

[0149] A touch sensor layer may be disposed on the encapsulation layer 16. The touch sensor layer may include a capacitive touch sensor that senses touch input based on capacitance changes before and after the touch input. The touch sensor layer may include a metal wiring pattern forming the capacitor of the touch sensor and an insulating layer. The capacitor of the touch sensor may be formed between the metal wiring patterns. A polarizing plate may be disposed on the touch sensor layer. The polarizing plate can improve visibility and contrast by converting the polarized light reflected by the metal of the touch sensor layer and circuit layer 12. The polarizing plate may be implemented as a polarizing plate in which a linear polarizing plate and a phase retardation film are bonded, or a circular polarizing plate. A cover glass may be adhered to the polarizing plate.

[0150] The display panel 100 may further include a touch sensor layer and a color filter layer stacked on the encapsulation layer 16. The color filter layer may include red, green, and blue color filters, as well as a black matrix pattern. The color filter layer can replace a polarizing plate and improves color purity by absorbing a portion of the wavelengths of light reflected from the circuit layer and the touch sensor layer. In this embodiment, by applying a color filter layer 20 with a higher transmittance than a polarizing plate to the display panel, the transmittance of the display panel PNL can be improved, as can the thickness and flexibility of the display panel PNL. A cover glass may be adhered to the color filter layer.

[0151] Power supply 140 generates the DC power required to drive the pixel array AA and display panel driving circuitry of display panel 100 using a DC-DC converter. The DC-DC converter may include a charge pump, rectifier, buck converter, boost converter, etc. Power supply 140 can adjust the DC input voltage from a host system (not shown), thereby generating DC voltages such as the gamma reference voltage VGMA, gating on voltages VGH and VEH, gating off voltages VGL and VEL, pixel drive voltage EVDD, and pixel low-level power supply voltage EVSS. The gamma reference voltage VGMA is provided to data driver 110. The gating on voltages VGH and VEH, and the gating off voltages VGL and VEL are provided to gating driver 120. The pixel drive voltage EVDD and pixel low-level power supply voltage EVSS are typically provided to the pixels.

[0152] Under the control of the timing controller (TCON) 130, the display panel driving circuit writes the pixel data (digital data) of the input image to the pixels of the display panel 100.

[0153] The display panel driving circuit includes a data driver 110 and a strobe driver 120.

[0154] A demultiplexer array 112 can be positioned between the data driver 110 and the data lines 102. The demultiplexer array 112 sequentially connects one channel of the data driver 110 to multiple data lines 102 and distributes the data voltage output from one channel of the data driver 110 to the data lines 102 in a time-division manner, thereby reducing the number of channels of the data driver 110. The demultiplexer array 112 can be omitted. In this case, the output buffer AMP of the data driver 110 is directly connected to the data lines 102.

[0155] The display panel driving circuit may also include a touch sensor driver for driving the touch sensor. Figure 1 The touch sensor driver is omitted. In mobile devices, the timing controller 130, power supply 140, data driver 110, etc., can be integrated into a single driver integrated circuit (IC).

[0156] Data driver 110 generates a data voltage Vdata by converting pixel data of the input image received from timing controller 130 using a digital-to-analog converter (DAC) at each frame interval with a gamma-compensated voltage. A gamma reference voltage VGMA is divided for the corresponding grayscale level by a voltage divider circuit. The gamma-compensated voltage divided from the gamma reference voltage VGMA is provided to the DAC of data driver 110. The data voltage Vdata is output through the output buffer AMP in each channel of data driver 110.

[0157] In the data driver 110, the output buffer AMP included in one channel can be connected to the adjacent data line 102 via the demultiplexer array 112. The demultiplexer array 112 can be formed directly on the substrate of the display panel 100 or integrated into a driver IC together with the data driver 110.

[0158] The gating driver 120 can be implemented as an in-panel gating (GIP) circuit directly formed on the bezel BZ area of ​​the display panel 100 along with the TFT array of the pixel array AA. Under the control of the timing controller 130, the gating driver 120 sequentially outputs gating signals to the gating line 103. The gating driver 120 can also sequentially provide the gating signals to the gating line 103 by shifting the gating signals using a shift register.

[0159] The strobe signal may include a scan signal for selecting the pixel of the row in which data is written synchronously with the data voltage, and an EM signal for defining the emission time of the pixel charged with the data voltage.

[0160] The strobe driver 120 may include a scan driver 121, an EM driver 122, and an initialization driver 123.

[0161] Scan driver 121 outputs a scan signal SCAN in response to a start pulse and a shift clock from timing controller 130, and shifts the scan signal SCAN according to the shift clock timing. EM driver 122 outputs an EM signal EM in response to a start pulse and a shift clock from timing controller 130, and shifts the EM signal EM sequentially according to the shift clock. Initialization driver 123 outputs an initialization signal INIT in response to a start pulse and a shift clock from timing controller 130, and shifts the initialization signal INIT according to the shift clock timing. Therefore, the scan signal SCAN, the EM signal EM, and the initialization signal INIT are sequentially provided to the gating lines 103 of pixel rows L1 to Ln. In the borderless model, at least some of the transistors and clock wiring constituting the gating driver 120 can be distributed in the pixel array AA.

[0162] The timing controller 130 receives digital video data DATA of the input image and timing signals synchronized with it from the host system (not shown). The timing signals include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a master clock CLK, and a data enable signal DE. Since the vertical and horizontal time periods can be determined by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. The data enable signal DE has a period of one horizontal time period (1H).

[0163] The host system can be any of a television (TV) system, set-top box, navigation system, personal computer (PC), home theater system, vehicle system, and mobile device system.

[0164] The timing controller 130 multiplies the input frame frequency by i and controls the operation timing of the display panel drive circuit at a frame frequency of input frame frequency × i (i is a positive integer greater than 0) Hz. The input frame frequency is 60 Hz in the NTSC (National Television Standards Committee) scheme and 50 Hz in the PAL (Phase Alternating Line) scheme.

[0165] Based on the timing signals Vsync, Hsync, and DE received from the host system, the timing controller 130 generates data timing control signals for controlling the operation timing of the data driver 110, MUX signals MUX1 and MUX2 for controlling the operation timing of the demultiplexer array 112, and gating timing control signals for controlling the operation timing of the gating driver 120.

[0166] The voltage level of the gating timing control signal output from the timing controller 130 can be converted into gating on-state voltages VGH and VEH and gating off-state voltages VGL and VEL by a level shifter (not shown), and then provided to the gating driver 120. That is, the level shifter converts the low-level voltage of the gating timing control signal into the gating off-state voltages VGL and VEL, and converts the high-level voltage of the gating timing control signal into the gating on-state voltages VGH and VEH. The gating timing signal includes a start pulse and a shift clock.

[0167] Although embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed herein are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above embodiments are illustrative in all respects and are not limiting of the present disclosure. The scope of protection of the present disclosure should be interpreted based on the appended claims, and all technical concepts within the equivalent scope thereof should be interpreted as falling within the scope of the present disclosure.

[0168] Cross-references to related applications

[0169] This application claims priority and benefit to Korean Patent Application No. 10-2021-0090007, filed July 8, 2021; Korean Patent Application No. 10-2021-0174815, filed December 8, 2021; and Korean Patent Application No. 10-2022-0069554, filed June 8, 2022, the disclosures of which are incorporated herein by reference in their entirety.

Claims

1. A pixel circuit comprising: a drive element including a gate directly connected to a first node to which a data voltage is applied, a first electrode connected to a high potential voltage line, and a second electrode connected to a second node; a first switching element connected between the second node and a third node; a second switching element connected between the second node and a fourth node; a third switching element connected between the fourth node and a reference voltage line; a first capacitor directly connected between the first node and the third node; and a second capacitor directly connected between the third node and the fourth node, wherein the second switching element includes a gate configured to receive a first signal, and the third switching element includes a gate configured to receive a second signal different from the first signal. In a first sensing period, the drive element, the first switching element, and the third switching element are turned on, and the second switching element is turned off.

2. The pixel circuit of claim 1, wherein, In a second sensing period, the first switching element and the third switching element are turned off, and the drive element and the second switching element are turned on.

3. The pixel circuit of claim 2, wherein, In the first sensing period, a threshold voltage of the drive element is stored in the first capacitor and is once compensated, and 4. The pixel circuit of claim 3, wherein, wherein, in the second sensing period, the threshold voltage of the drive element is twice compensated to compensate for a voltage. The compensation voltage varies depending on a ratio of a capacitance of the first capacitor to a capacitance of the second capacitor.

5. The pixel circuit of claim 4, wherein, The capacitance of the second capacitor is determined in consideration of a parasitic capacitor and the capacitance of the first capacitor to compensate for a decrease due to a boost loss.

6. The pixel circuit of claim 5, wherein, 7. The pixel circuit according to claim 1, further comprising: a fifth switching element connected between the first node and an initialization voltage line; and a sixth switching element connected between the first node and a data voltage line.

8. The pixel circuit according to claim 7, further comprising: a fourth switching element connected between the third node and the reference voltage line, wherein the first node is connected to a gate of the drive element, the fifth switching element, the sixth switching element, and the first capacitor, the second node is connected to the drive element, the first switching element, and the second switching element, the third node is connected to the first switching element, the fourth switching element, the first capacitor, the second capacitor, and a light emitting element, and the fourth node is connected to the second switching element, the third switching element, and the second capacitor. In a first sensing period, the drive element, the first switching element, the third switching element, and the fifth switching element are turned on, and the second switching element, the fourth switching element, and the sixth switching element are turned off. ​ 9. The pixel circuit of claim 8, wherein, ​ 10. The pixel circuit of claim 9, wherein, In the second sensing period, the drive element, the second switch element, and the fifth switch element are turned on, and the first switch element, the third switch element, the fourth switch element, and the sixth switch element are turned off.

11. The pixel circuit of claim 9, wherein, In the second sensing period, the drive element, the second switch element, and the sixth switch element are turned on, and the first switch element, the third switch element, the fourth switch element, and the fifth switch element are turned off.

12. The pixel circuit of claim 10, wherein, The period in which the third switch element is turned on partially overlaps or does not overlap with the period in which the second switch element is turned on.

13. The pixel circuit according to claim 8, further comprising: a seventh switch element connected between the third node and the light emitting element; and a third capacitor connected between the third node and a second high potential voltage line, wherein the first node is connected to a gate of the drive element, the fifth switch element, the sixth switch element, and the first capacitor, the second node is connected to the drive element, the first switch element, and the second switch element, the third node is connected to the first switch element, the fourth switch element, the seventh switch element, the first capacitor, the second capacitor, and the third capacitor, and the fourth node is connected to the second switch element, the third switch element, and the second capacitor.

14. The pixel circuit of claim 13, wherein, In the first sensing period, the drive element, the first switch element, the third switch element, the fifth switch element, and the seventh switch element are turned on, and the second switch element, the fourth switch element, and the sixth switch element are turned off.

15. The pixel circuit of claim 14, wherein, In the second sensing period, the drive element, the second switch element, and the fifth switch element are turned on, and the first switch element, the third switch element, the fourth switch element, the sixth switch element, and the seventh switch element are turned off.

16. The pixel circuit of claim 14, wherein, In the second sensing period, the drive element, the second switch element, and the sixth switch element are turned on, and the first switch element, the third switch element, the fourth switch element, the fifth switch element, and the seventh switch element are turned off.

17. A display panel, comprising: a plurality of pixel circuits that display an input image corresponding to a data voltage, wherein each of the plurality of pixel circuits includes: a drive element including a gate directly connected to a first node to which the data voltage is applied, a first electrode connected to a high potential voltage line, and a second electrode connected to a second node; a first switch element connected between the second node and a third node; a second switch element connected between the second node and a fourth node; a third switch element connected between the fourth node and a reference voltage line; a first capacitor directly connected between the first node and the third node; and a second capacitor connected between the fourth node and the third node. a second capacitor directly connected between the third node and the fourth node, wherein the second switching element includes a gate configured to receive a first signal, and the third switching element includes a gate configured to receive a second signal different from the first signal.

18. The display panel of claim 17, wherein, In a first sensing period, the driving element, the first switching element, and the third switching element are turned on, and the second switching element is turned off.

19. The display panel of claim 18, wherein, In a second sensing period, the first switching element and the third switching element are turned off, and the driving element and the second switching element are turned on.

20. The display panel of claim 19, wherein, In the first sensing period, a threshold voltage of the driving element is stored in the first capacitor and is once compensated, and wherein, in the second sensing period, the threshold voltage of the driving element is twice compensated to compensate for a voltage.

21. The display panel of claim 20, wherein, The compensation voltage varies depending on a ratio of a capacitance of the first capacitor to a capacitance of the second capacitor.

22. The display panel of claim 21, wherein, The capacitance of the second capacitor is determined in consideration of a parasitic capacitor and the capacitance of the first capacitor to compensate for a decrease due to a boost loss.

23. The display panel of claim 17, wherein, Each of the plurality of pixel circuits further includes: a fifth switching element connected between the first node and an initialization voltage line, and a sixth switching element connected between the first node and a data voltage line.

24. The display panel of claim 23, wherein, Each of the plurality of pixel circuits further includes: a fourth switching element connected between the third node and the reference voltage line, wherein the first node is connected to a gate of the driving element, the fifth switching element, the sixth switching element, and the first capacitor, the second node is connected to the driving element, the first switching element, and the second switching element, the third node is connected to the first switching element, the fourth switching element, the first capacitor, the second capacitor, and a light emitting element, and the fourth node is connected to the second switching element, the third switching element, and the second capacitor.

25. The display panel of claim 24, wherein, In a first sensing period, the driving element, the first switching element, the third switching element, and the fifth switching element are turned on, and the second switching element, the fourth switching element, and the sixth switching element are turned off.

26. The display panel of claim 25, wherein, In a second sensing period, the driving element, the second switching element, and the fifth switching element are turned on, and the first switching element, the third switching element, the fourth switching element, and the sixth switching element are turned off.

27. The display panel of claim 25, wherein, In a second sensing period, the driving element, the second switching element, and the sixth switching element are turned on, and the first switching element, the third switching element, the fourth switching element, and the fifth switching element are turned off.

28. The display panel of claim 24, wherein, Each of the plurality of pixel circuits further includes: a seventh switching element connected between the third node and the light emitting element, and a third capacitor connected between the third node and a second high potential voltage line, and The first node is connected to a gate of the drive element, the fifth switch element, the sixth switch element, and the first capacitor, The second node is connected to the drive element, the first switch element, and the second switch element, The third node is connected to the first switch element, the fourth switch element, the seventh switch element, the first capacitor, the second capacitor, and the third capacitor, and The fourth node is connected to the second switch element, the third switch element, and the second capacitor.

29. The display panel of claim 28, wherein, In the first sensing period, the drive element, the first switch element, the third switch element, the fifth switch element, and the seventh switch element are turned on, and the second switch element, the fourth switch element, and the sixth switch element are turned off.

30. The display panel of claim 29, wherein, In the second sensing period, the drive element, the second switch element, and the fifth switch element are turned on, and the first switch element, the third switch element, the fourth switch element, the sixth switch element, and the seventh switch element are turned off.

31. The display panel of claim 29, wherein, In the second sensing period, the drive element, the second switch element, and the sixth switch element are turned on, and the first switch element, the third switch element, the fourth switch element, the fifth switch element, and the seventh switch element are turned off.

32. The display panel of claim 17, wherein, All the transistors in the panel including the plurality of pixel circuits are implemented using oxide thin film transistors (TFTs) including n-channel oxide semiconductors.

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