Delay cell layout structure, delay module layout structure and delay circuit

Abstract

The application provides a delay circuit, characterized in that the delay circuit comprises a decoder, a first bit line, a second bit line, a word line, a sensitive amplifier, a storage unit and a delay module circuit made of a delay unit module layout structure; the word line is electrically connected with the decoder and the storage unit respectively; the first bit line and the second bit line are electrically connected with the word line, the storage unit and the sensitive amplifier respectively; the sensitive amplifier is used for amplifying the potential difference of the first bit line and the second bit line and outputting an opening signal SE; the delay module circuit is used for delaying the opening signal SE; the application can better match the potential difference AV of the two bit lines BL and BLB; the function is realized by using the basic static random storage unit; the delay effect is better by using the stage amplification as the delay; the delay unit and other storage units are the same in the manufacturing process, so that the performance difference of the device caused by the process condition is avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a delay cell layout structure, a delay module layout structure and a delay circuit. BACKGROUND

[0002] With the chips being applied to various fields, as the data recording storage chip becomes one of the indispensable chip components of each electronic product, therefore the storage chip storage precision and storage speed become one of the key points of the storage chip, so at present it is needed to improve the precision of the existing storage circuit control circuit under the condition of not increasing additional cost through the existing process environment.

[0003] The most important thing of the static random access memory is to control the whole static random access memory control circuit, which is crucial to improve the speed of the static random access memory circuit, wherein the most important thing of the control circuit is to generate the opening signal SE of the sense amplifier and the opening control signal WL of the storage unit, and the timing signals generated by other circuits are derived from the two signals.

[0004] Due to the process conditions and device performance differences between the storage circuit and the logic circuit, the existing technology uses a stage amplification composed of inverters to control the generation of the opening signal SE of the sense amplifier, which brings the problem that using external logic devices as delay, then there will be a gap in the process, shape, size and other aspects between the storage unit and the process, which cannot be best matched, and the precision of the opening signal SE of the sense amplifier needs to be increased.

[0005] In order to solve the above problems, a new type of delay cell layout structure, delay module layout structure and delay circuit need to be proposed. SUMMARY

[0006] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a delay cell layout structure, a delay module layout structure and a delay circuit, which is used to solve the problem that the existing technology uses external logic devices as delay, then there will be a gap in the process, shape, size and other aspects between the storage unit and the process, which cannot be best matched, and the precision of the storage circuit control circuit needs to be improved without increasing additional cost.

[0007] To achieve the above-mentioned purposes and other related purposes, the present application provides a delay cell layout structure, comprising:

[0008] First and second PMOS layout structures and first to fourth NMOS layout structures;

[0009] The first and second PMOS layout structures and the first to fourth NMOS layout structures respectively comprise:

[0010] the first to fourth active area patterns and the first and second gate patterns are arranged in sequence, the first and fourth active area patterns are used by the first and second PMOS layout structures respectively, and the second and third active area patterns are used by the third and fourth NMOS layout structures respectively;

[0011] the first metal layer pattern is arranged across the first and second gate patterns of the first and second NMOS layout structures and is used to connect the first and second gate patterns;

[0012] the second metal layer pattern is arranged across the first and second gate patterns of the third and fourth NMOS layout structures and is used to connect the first and second gate patterns;

[0013] the third metal layer pattern is arranged on the second gate pattern of the first PMOS layout structure and is used as an output metal of the delay cell layout;

[0014] the fourth metal layer pattern is arranged on the first gate pattern of the second PMOS layout structure and is used as an input metal of the delay cell layout;

[0015] the first contact hole pattern is arranged on the first metal layer pattern and is located between the first and second NMOS layout structures;

[0016] the second contact hole pattern is arranged on the overlapping part of the first gate pattern and the second active area pattern and is used as an input terminal of the delay cell.

[0017] Preferably, the first and fourth active area patterns are symmetrically distributed with respect to each other, and the second and third active area patterns are symmetrically distributed with respect to each other.

[0018] Preferably, the size of the second contact hole pattern is less than or equal to the size of the overlapping part of the first gate pattern and the second active area pattern.

[0019] Preferably, the layout structure has a rectangular shape.

[0020] Preferably, the layout structure further comprises a memory cell layout structure, and the memory cell layout structure has the same parameters as the partial layout structure of the delay cell layout structure.

[0021] Preferably, the parameters include the shape, size and position of the pattern.

[0022] Preferably, the memory cell layout structure is a static random access memory cell layout structure.

[0023] A delay module layout structure comprises:

[0024] The delay module layout structure comprises n stage amplification layout structures connected in series, wherein n is greater than or equal to 2.

[0025] Each of the stage amplification layout structures is composed of a plurality of delay unit layout structures as described above.

[0026] Preferably, the n th stage amplification layout structure comprises 2 (n-1) delay unit layout structures connected in parallel.

[0027] Preferably, in the n th stage amplification layout structure, each of the delay unit layout structures is connected in parallel with the first contact pattern, i.e. an inverter usually connected in parallel in the prior art.

[0028] Preferably, in each of the two adjacent stage amplification layout structures, the third metal layer pattern in the n th stage amplification layout structure and the fourth metal layer pattern in the (n+1) th stage amplification layout structure are connected in series.

[0029] A delay circuit comprises:

[0030] A decoder, a first bit line, a second bit line, a word line, a sense amplifier, a memory cell, and

[0031] A delay module circuit made of the delay unit module layout structure as described above; wherein,

[0032] The word line is electrically connected with the decoder and the memory cell respectively, and the first and second bit lines are electrically connected with the word line, the memory cell and the sense amplifier respectively.

[0033] The sense amplifier is used to amplify the potential difference of the first and second bit lines and output an enable signal SE.

[0034] The delay module circuit is used to delay the enable signal SE.

[0035] Preferably, the memory cell is a static random memory.

[0036] As described above, the delay unit layout structure, the delay module layout structure and the delay circuit of the present application have the following beneficial effects:

[0037] The delay circuit obtained by the delay unit layout structure and the delay module layout structure of the present application can better match the potential difference AV of the BL and BLB bit lines; the function is realized by using the basic static random memory unit; the stage amplification is used as a delay, and the delay effect is better, and it is easier to form a delay; the delay unit and other memory units also remain the same in the manufacturing process, avoiding the performance difference of the device caused by the process conditions. BRIEF DESCRIPTION OF DRAWINGS

[0038] Figure 1 A schematic diagram of a delay cell layout structure of the present application is shown.

[0039] Figure 2 A schematic diagram of a delay module layout structure of the present application is shown.

[0040] Figure 3 A schematic diagram of a delay module circuit structure of the present application is shown.

[0041] Figure 4 A schematic diagram of a delay circuit of the present application is shown.

[0042] Reference signs:

[0043] First PMOS layout structure 100

[0044] Second PMOS layout structure 200

[0045] First NMOS layout structure 300

[0046] Second NMOS layout structure 400

[0047] Third NMOS layout structure 500

[0048] Fourth NMOS layout structure 600

[0049] Delay cell layout structure 700

[0050] First active region pattern 01

[0051] Second active region pattern 02

[0052] Third active region pattern 03

[0053] Fourth active region pattern 04

[0054] First gate pattern 05

[0055] Second gate pattern 06

[0056] First metal layer pattern 07

[0057] Second metal layer pattern 11

[0058] Third metal layer pattern 09

[0059] Fourth metal layer pattern 08

[0060] First contact hole pattern 11

[0061] Second contact hole pattern 10

[0062] Delay module circuit 20

[0063] sensitive amplifier 21

[0064] decoder 22

[0065] storage unit 23

[0066] word line 24

[0067] first bit line 25

[0068] second bit line 26 DETAILED DESCRIPTION

[0069] The present application is herein described, by way of example only, with the

[0070] Embodiment One

[0071] Referring to Figure 1 The present application provides a delay cell layout structure 700, comprising:

[0072] a first PMOS layout structure 100, a second PMOS layout structure 200, and a first NMOS layout structure 300, a second NMOS layout structure 400, a third NMOS layout structure 500, and a fourth NMOS layout structure 600;

[0073] The first PMOS layout structure 100, the second PMOS layout structure 200, and the first NMOS layout structure 300, the second NMOS layout structure 400, the third NMOS layout structure 500, and the fourth NMOS layout structure 600 respectively comprise:

[0074] a first active region pattern, a second active region pattern, a third active region pattern, and a fourth active region pattern arranged in sequence, and a first gate pattern and a second gate pattern crossing the first active region pattern, the second active region pattern, the third active region pattern, and the fourth active region pattern, the first NMOS layout structure 300 and the second NMOS layout structure 400 sharing the first active region pattern 01, the third NMOS layout structure 500 and the fourth NMOS layout structure 600 sharing the second active region pattern 02, the first active region pattern and the fourth active region pattern being arranged in the first PMOS layout structure 100 and the second PMOS layout structure 200 respectively;

[0075] a first metal layer pattern 07 crossing the first gate pattern and the second gate pattern in the first NMOS layout structure 300 and the second NMOS layout structure 400, and used for connecting the first NMOS layout structure 300 and the second NMOS layout structure 400;

[0076] a second metal layer pattern 11 crossing the first gate pattern and the second gate pattern in the third NMOS layout structure 500 and the fourth NMOS layout structure 600, and used for connecting the third NMOS layout structure 500 and the fourth NMOS layout structure 600;

[0077] a third metal layer pattern 09 arranged on the second gate pattern 06 in the first PMOS layout structure 100, and used as a delay cell layout output metal;

[0078] The fourth metal layer pattern 08 for inputting metal of the delay unit layout is arranged on the first gate pattern 05 in the second PMOS layout structure 200;

[0079] The first contact hole pattern 11 is arranged on the first metal layer pattern 07 and between the first and second NMOS layout structures.

[0080] The second contact hole pattern 10 is arranged on the overlapping part of the first gate pattern 05 and the second active area pattern 02, and is used as the input end of the delay unit, i.e., the layout structure of the inverter.

[0081] In the embodiment of the present application, the first and fourth active area patterns are symmetrically distributed, and the second and third active area patterns are symmetrically distributed.

[0082] In the embodiment of the present application, the size of the second contact hole pattern 10 is less than or equal to the overlapping part of the first gate pattern 05 and the second active area pattern 02.

[0083] In the embodiment of the present application, the layout structure is in the shape of a rectangle.

[0084] In the embodiment of the present application, the layout structure further comprises a storage unit layout structure, and the parameters of the storage unit layout structure are consistent with those of the partial pattern of the delay unit layout structure 700, i.e., the delay unit layout structure 700 is obtained by modifying the basic storage unit layout structure, and the original size, shape and metal connection level are kept as much as possible. For example, the manufacturing process of the delay unit is kept the same as that of the SRAM, so as to avoid the difference between the delay circuit and the storage process environment, so that the potential difference ΔV of the BL and BLB bit lines can be better matched, and since the potential difference ΔV is a relatively small value relative to VDD, the delay effect is better, and the calculation of ΔV is more accurate.

[0085] In the embodiment of the present application, the parameters include the shape, size and position of the pattern.

[0086] In the embodiment of the present application, the storage unit layout structure is a static random access memory unit layout structure.

[0087] Embodiment two

[0088] Please refer to Figure 2 The present application provides a delay module layout structure composed of a plurality of delay unit layout structures 700 as shown in embodiment one, which comprises:

[0089] The delay module layout structure comprises n stage amplification layout structures connected in series, and the stage amplification layout structure is used to manufacture a stage amplification inverter, wherein n is greater than or equal to 2, and the number n of stage amplification inverters is determined by the specific time of the potential difference AV of the two bit lines BL and BLB.

[0090] Each stage amplification layout structure is composed of a plurality of delay unit layout structures 700 as described above.

[0091] In an embodiment of the present application, the n th stage amplification layout structure comprises 2 (n-1) delay unit layout structures 700 connected in parallel.

[0092] In an embodiment of the present application, in the n th stage amplification layout structure, each delay unit layout structure 700 is connected in parallel by the first contact pattern.

[0093] In an embodiment of the present application, in each adjacent two stage amplification layout structures, the third metal layer pattern 09 in the n th stage amplification layout structure and the fourth metal layer pattern 08 in the (n+1) th stage amplification layout structure are connected in series, that is, the delay is performed by using the series connection of inverters instead of the parallel connection of inverters in the prior art.

[0094] Example three

[0095] Please refer to Figure 4 The present application also provides a delay circuit, comprising:

[0096] The decoder 22, the first and second bit lines (25, 26), the word line 24, the sensitive amplifier 21, the storage unit 23, and

[0097] The delay module circuit 20 manufactured by the delay unit module layout structure as shown in Example Two (as shown in Figure 3 , that is, the delay is performed by using the series connection of inverters instead of the parallel connection of inverters in the prior art; wherein,

[0098] The word line 24 is electrically connected with the decoder 22 and the storage unit 23 respectively, and the first and second bit lines (25, 26) are electrically connected with the word line 24, the storage unit 23 and the sensitive amplifier 21 respectively.

[0099] The sensitive amplifier 21 is used to amplify the potential difference of the first and second bit lines (25, 26) and output an enable signal SE.

[0100] The delay module circuit 20 is used to delay the enable signal SE.

[0101] In an embodiment of the present application, the storage unit 23 is a static random access memory.

[0102] It is to be noted that the drawings provided in the embodiments only schematically illustrate the basic concept of the present application, and only the components related to the present application are shown in the drawings, not the number, shape and size of the components when actually implemented. The shape, number and ratio of the components when actually implemented can be arbitrarily changed, and the layout pattern of the components can be more complex.

[0103] In summary, the delay circuit obtained by the delay unit layout structure and the delay module layout structure can better match the potential difference AV of the two bit lines BL and BLB, and the function is realized based on the basic static random memory unit. The delay effect is better and easier to form delay by using the class amplification as delay. The delay unit and other memory units also maintain the same in the manufacturing process, avoiding the performance difference of the device caused by the process conditions. Therefore, the present application effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0104] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought disclosed by the present application should be covered by the claims of the present application.

Claims

1. A delay cell layout structure, characterized in that, include: The first and second PMOS layout structures and the first to fourth NMOS layout structures; The first and second PMOS layout structures and the first to fourth NMOS layout structures respectively include: The first to fourth active region patterns are arranged sequentially, and the first and second gate patterns span the first to fourth active region patterns. The first and second NMOS layout structures share the first active region pattern, and the third and fourth NMOS layout structures share the second active region pattern. The first and second PMOS layout structures of the first and fourth active region patterns are respectively located in the third and fourth active region patterns. A first metal layer pattern that spans the first and second gate patterns in the first and second NMOS layout structures and is used to connect the two. A second metal layer pattern that spans the first and second gate patterns in the third and fourth NMOS layout structures and is used to connect the two; A third metal layer pattern, disposed on the second gate pattern in the first PMOS layout structure, for use as the output metal of the delay cell layout; A fourth metal layer pattern, which is disposed on the first gate pattern in the second PMOS layout structure, and is used as the layout input metal of the delay cell; A first contact hole pattern is disposed on the first metal layer pattern and located between the first and second NMOS layout structures; A second contact hole pattern is provided on the overlapping portion of the first gate pattern and the second active region pattern, which serves as the input terminal of the delay unit.

2. The delay cell layout structure according to claim 1, characterized in that: The first and fourth active regions are symmetrically distributed, and the second and third active regions are symmetrically distributed.

3. The delay cell layout structure according to claim 1, characterized in that: The size of the second contact hole pattern is less than or equal to the overlapping portion of the first gate pattern and the second active region pattern.

4. The delay cell layout structure according to claim 1, characterized in that: The shapes of the layout structures are all rectangular.

5. The delay cell layout structure according to claim 1, characterized in that: The layout structure also includes a storage cell layout structure, the parameters of which are consistent with those of the portion of the graphics in the delay cell layout structure.

6. The delay cell layout structure according to claim 5, characterized in that: The parameters include the shape, size, and position of the graphic.

7. The delay cell layout structure according to claim 5, characterized in that: The memory cell layout structure is a static random access memory (SRAM) cell layout structure.

8. A delay module layout structure, characterized in that, include: The delay module layout structure includes n sequentially connected hierarchical enlargement layout structures, where n is greater than or equal to 2; Each of the aforementioned hierarchical enlargement layout structures consists of a plurality of delay unit layout structures as described in any one of claims 1 to 7.

9. The delay module layout structure according to claim 8, characterized in that: The nth enlarged layout structure includes 2^(n-1) parallel delayed unit layout structures.

10. The delay module layout structure according to claim 9, characterized in that: In the nth enlarged layout structure, each of the delayed unit layout structures is connected in parallel with the first contact pattern.

11. The delay module layout structure according to claim 9, characterized in that: In each pair of adjacent enlarged layer patterns, the third metal layer pattern in the nth enlarged layer pattern and the fourth metal layer pattern in the (n+1)th enlarged layer pattern are connected in series.

12. A delay circuit, characterized in that, include: Decoder, first and second bit lines, word lines, sensitive amplifier, memory cell, and The delay module circuit is fabricated using the delay unit module layout structure as described in any one of claims 8 to 11; wherein, The word lines are electrically connected to one end of the decoder and the memory cell, respectively. The first and second bit lines are electrically connected to one end of the word lines, the memory cell, and the sensitive amplifier, respectively. The other end of the decoder is electrically connected to the other end of the sensitive amplifier. The sensitive amplifier is used to amplify the potential difference between the first and second bit lines and output an enable signal SE. The delay module circuit is used to delay the enable signal SE.

13. The delay circuit according to claim 12, characterized in that: The storage unit is a static random access memory.

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