A memory and a method of writing the same

Abstract

The application discloses a memory, comprising: a storage library; the storage library comprises a plurality of storage blocks, the storage block comprises a plurality of word lines, a plurality of bit lines and a plurality of storage units arranged in an array, each storage unit is connected to one of the word lines and one of the bit lines; wherein, the storage library is configured to: in a preset mode, in response to a control signal, activate each word line of at least one target storage block in the storage library, pull up or pull down the level on each bit line of the target storage block, and pull the complementary bit line of each bit line in the target storage block to the opposite level of the bit line, the complementary bit line is the bit line of the storage block adjacent to the target storage block.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuits, and in particular to a memory and a write method thereof. BACKGROUND

[0002] Memory is a memory device used for saving information in modern information technology. Memory is generally classified as volatile memory and non-volatile memory.

[0003] Because the reaction speed and running speed of dynamic random access memory (DRAM) are usually very fast, dynamic random access memory is widely used as the main memory or buffer memory of a system. Generally, a DRAM chip has to go through a series of tests after production before it can finally face the market, and the test phase will mainly test the DRAM storage matrix, which often needs to quickly detect the faulty storage unit and then repair it. Therefore, how to quickly and accurately check the bad points in the storage unit has become an important research direction in the field. SUMMARY

[0004] Therefore, the embodiments of the present application provide a memory and a write method thereof to solve at least one problem in the background art.

[0005] To achieve the above-mentioned purpose, the technical solution of the present application is as follows:

[0006] The embodiments of the present application provide a memory, characterized in that it comprises:

[0007] a storage library;

[0008] The storage library comprises a plurality of storage blocks, and each storage block comprises a plurality of word lines, a plurality of bit lines, and a plurality of storage units arranged in an array, each storage unit being connected to one of the word lines and one of the bit lines; wherein

[0009] The storage library is configured to, in a preset mode, in response to a control signal, activate each word line of at least one target storage block in the storage library, pull up or pull down the level on each bit line of the target storage block, and pull the complementary bit line of each bit line in the target storage block to the opposite level of the bit line, the complementary bit line being the bit line of a storage block adjacent to the target storage block.

[0010] In the above-mentioned solution, the memory further comprises a bit line write control module, and the bit line write control module pulls up or pulls down all the levels on the bit lines of the target storage block based on the control signal.

[0011] In the scheme, the bit line write control module comprises an enable module and a bit line write module, the enable module outputs a bit line write control signal to the bit line write module, the bit line write control signal is a high write control signal or a low write control signal; and the bit line write module pulls the bit line to a high level or a low level based on the bit line write control signal.

[0012] In the scheme, the enable module comprises a first AND gate, which outputs a bit line write control signal based on the memory block enable signal.

[0013] In the scheme, the bit line write module comprises a first transistor and a second transistor, the first transistor is turned on based on a low write control signal, and the second transistor is turned on based on a high write control signal; a source of the first transistor is coupled with a power supply end, a drain of the first transistor is coupled with a drain of the second transistor, and a source of the second transistor is grounded; a gate of the first transistor and a gate of the second transistor are connected and coupled with the first AND gate; or,

[0014] The first transistor and the second transistor are turned on based on a low write control signal, a source of the first transistor is coupled with a power supply end, a drain of the first transistor is coupled with the bit line, a source of the second transistor is coupled with the complementary bit line, a drain of the second transistor is grounded, and a gate of the first transistor and a gate of the second transistor are connected and coupled with the first AND gate; or,

[0015] The first transistor and the second transistor are turned on based on a high write control signal, a drain of the first transistor is coupled with a power supply end, a source of the first transistor is coupled with the bit line, a drain of the second transistor is coupled with the complementary bit line, a source of the second transistor is grounded, and a gate of the first transistor and a gate of the second transistor are connected and coupled with the first AND gate.

[0016] In the scheme, the bit line write control module further comprises a complementary bit line write module, which is used to pull the complementary bit line to a level opposite to that of the bit line in the target memory block.

[0017] In the scheme, the enable module further comprises a second AND gate, which outputs a complementary bit line write control signal to the complementary bit line write module based on the control signal, the complementary bit line write control signal is a high write control signal or a low write control signal; and the complementary bit line write module pulls the complementary bit line to a high level or a low level based on the complementary bit line write control signal.

[0018] In the above scheme, the second AND gate is configured such that when the first AND gate outputs a high write control signal, the second AND gate outputs a low write control signal; and when the second AND gate outputs a low write control signal, the first AND gate outputs a high write control signal.

[0019] In the above scheme, the complementary bit line writing module includes a third transistor and a fourth transistor. The third transistor is turned on based on a low write control signal, and the fourth transistor is turned on based on a high write control signal. The source of the third transistor is coupled to a power supply terminal, the drain of the third transistor is coupled to the drain of the fourth transistor, and the source of the fourth transistor is grounded. The gates of the third transistor and the fourth transistor are connected and coupled to the second AND gate; or,

[0020] The third and fourth transistors are turned on based on a low write control signal; the source of the third transistor is coupled to the complementary bit line, the drain of the third transistor is grounded, the source of the fourth transistor is coupled to the power supply, the drain of the fourth transistor is coupled to the complementary bit line, and the gates of the third and fourth transistors are connected and coupled to the second AND gate; or,

[0021] The third transistor and the fourth transistor are turned on based on a high write control signal. The drain of the third transistor is coupled to the complementary bit line, and the source of the third transistor is grounded. The drain of the fourth transistor is coupled to the power supply terminal, and the source of the fourth transistor is coupled to the complementary bit line. The gates of the third transistor and the fourth transistor are connected and coupled to the second AND gate.

[0022] In the above scheme, the repository further includes an isolation module, which includes a first switch connected between the bit line and the bit line writing module and a second switch connected between the complementary bit line and the complementary bit line writing module.

[0023] In the above scheme, when the preset mode is compressed write mode, the isolation module turns on the first switch and the second switch; when the preset mode is not compressed write mode, the isolation module turns off the first switch and the second switch.

[0024] In the above scheme, the gate of the first switch is connected to the gate of the second switch and coupled to the isolation signal terminal. When the preset mode is the compressed write mode, the isolation signal terminal outputs a high-level signal to the first switch and the second switch. When the preset mode is not the compressed write mode, the isolation signal terminal outputs a low-level signal to the first switch and the second switch.

[0025] The embodiment of the present application also provides a compressed write-in method, characterized in that,

[0026] The control memory enters a preset mode;

[0027] Each word line of at least one target memory block contained in the memory is activated;

[0028] The level of each bit line of the target memory block is pulled high or low, and the complementary bit line of each bit line in the target memory block is pulled to the opposite level of the bit line; wherein,

[0029] The memory comprises a memory bank, the memory bank comprises a plurality of memory blocks, the memory block comprises a plurality of word lines, a plurality of bit lines and a plurality of memory cells arranged in an array, each memory cell is connected to one word line and one bit line, and the complementary bit line is a bit line of a memory block adjacent to the target memory block.

[0030] In the above scheme, the activation of each word line of at least one target memory block contained in the memory comprises:

[0031] A control signal is received, and the control signal comprises a memory block enable signal;

[0032] Each word line in the target memory block is activated based on the memory block enable signal.

[0033] In the above scheme, the memory comprises a plurality of memory banks;

[0034] The control signal further comprises a memory bank enable signal;

[0035] When the memory bank enable signal is valid, each word line in the target memory block is activated based on the memory block enable signal; and when the memory bank enable signal is invalid, the word line is not activated.

[0036] In the above scheme, in a preset mode, the memory bank enable signals of a plurality of memory banks are simultaneously valid.

[0037] In the above scheme, the preset mode is a compressed write-in mode.

[0038] In the above scheme, the pulling of the level of each bit line of the target memory block high or low comprises:

[0039] The memory block enable signal is obtained;

[0040] A bit line write-in control signal is output, and the bit line write-in control signal is a high write-in control signal or a low write-in control signal;

[0041] pull up or pull down the level on the bit line based on the bit line write control signal.

[0042] In the above solution, pulling the complementary bit line to the opposite level of the bit line comprises:

[0043] obtaining the memory block enable signal;

[0044] outputting a complementary bit line write control signal, the complementary bit line write control signal being a high write control signal or a low write control signal;

[0045] pulling the complementary bit line to the opposite level of the bit line based on the complementary bit line write control signal.

[0046] Thus, the embodiments provided by the present application adopt the write mode of activating all word lines in a target memory block and adjusting the voltage on the bit line and the complementary bit line of the entire target memory block, which can realize the assignment of the entire memory block at one time, greatly shortens the test time compared with the normal write and general compression write mode, improves the test efficiency and reduces the test cost. In addition, compared with the normal write and general compression write mode, the mode of adjusting the voltage on the bit line and the complementary bit line by using the bit line write control module provided by the present application does not need to pass through the column selection module (CSEL), and does not need to provide data on the local data line (LIO), so that the target memory block can be assigned as a whole, without waiting for the timing time of tRCD and CWL, further saving the test time and test cost.

[0047] Additional aspects and advantages of the present application will be given in part in the following description, will become apparent from the following description, or will be learned by practice of the present application. BRIEF DESCRIPTION OF DRAWINGS

[0048] Figure 1 a circuit module schematic diagram of the memory in an embodiment of the present application;

[0049] Figures 2A-2B a module schematic diagram and a circuit schematic diagram of the storage amplification in an embodiment of the present application;

[0050] Figure 3 an amplification schematic diagram of the enable module and its surrounding circuit provided by an embodiment of the present application;

[0051] Figure 4 an amplification schematic diagram of the bit line write module and the complementary bit line write module provided by an embodiment of the present application;

[0052] Figure 5 an amplification schematic diagram of the bit line write module and the complementary bit line write module provided by another embodiment of the present application;

[0053] Figure 6 A circuit module schematic diagram is provided for another embodiment of the present application;

[0054] Figure 7 A flowchart schematic diagram of a compression write method is provided for the present application. DETAILED DESCRIPTION

[0055] Exemplary embodiments of the present application will be described herein below with reference to the accompanying drawings. While exemplary embodiments of the present application are illustrated, it should be understood that the present application can be embodied in many forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present application to those skilled in the art.

[0056] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be apparent to one skilled in the art that the present application can be practiced without one or more of these specific details. In other instances, well-known features have not been described in detail so as not to unnecessarily complicate the present application. In addition, it is to be understood that the terminology used herein is for the purpose of describing the particular embodiments only and is not intended to be limiting.

[0057] In the drawings, the size of layers, regions, elements, and the like can be exaggerated for clarity. Like reference numerals can represent like elements throughout the drawings.

[0058] It is to be understood that the terms "on", "adjacent", "connected to", or "coupled to" as used herein do not necessarily denote direct and immediate connections, but can also include connections through intervening elements or layers. On the contrary, the term "directly on", "directly adjacent", "directly connected to", or "directly coupled to" denotes no intervening elements or layers. It is to be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application. Conversely, a second element, component, region, layer or section discussed below could be termed a first element, component, region, layer or section without departing from the teachings of the present application.

[0059] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is inverted, then a dependent element or feature described as "below" or "beneath" another element or feature would then be oriented "above" and "over" the other element or feature. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0060] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0061] As used in the description below, the term "three-dimensional memory" refers to a semiconductor device having memory cells arranged vertically on a substrate oriented in a lateral direction, such that the number of memory cells is increased in a vertical direction relative to the substrate. As used herein, the term "vertically" means nominally perpendicular to a lateral surface of the substrate.

[0062] As described in the background section, a DRAM chip needs to go through a series of tests before it can be finally marketed, and among the series of tests, the checking test of the problematic memory cells in the memory is particularly important. Generally, the checking procedure of the problematic memory cells in the memory is as follows: first, all the memory cells in the memory are assigned values according to a predetermined rule, and then all the memory cells in the memory are read, and the read data is compared with the predetermined rule. The memory cells whose data is inconsistent with the predetermined rule are the problematic memory cells checked out. Therefore, the time used for the write operation directly affects the test time and test efficiency of the DRAM chip.

[0063] The test machine usually used in the test stage is not high in test frequency due to test items, so if the normal mode write operation is used in the test stage, the whole DRAM storage matrix is filled with data and then tested, which will waste a lot of test time and consume a lot of test cost. In the related art, a special test mode (or compression mode) is designed by a test designer to provide a test department for faster filling of the whole DRAM storage matrix, so as to test. However, in the compression write mode in the related art, 32 word lines in 16 storage banks in the DRAM chip are operated at one time, and 2048 bits of data can be written at one time through the MPR write-in mode. Although the compression write mode in the related art is much faster than the normal mode, it still consumes too much time and wastes a lot of test cost.

[0064] Therefore, an embodiment of the present application provides a memory, as shown in Figure 1 、 2A -2B, the memory comprises:

[0065] a storage bank;

[0066] The storage bank comprises a plurality of storage blocks, and each storage block comprises a plurality of word lines, a plurality of bit lines, and a plurality of storage units arranged in an array, each storage unit being connected to one of the word lines and one of the bit lines; wherein

[0067] The storage bank is configured to, in a preset mode, in response to a control signal, activate each word line of at least one target storage block in the storage bank, pull up or pull down the level on each bit line of the target storage block, and pull the complementary bit line of each bit line in the target storage block to the opposite level of the bit line, the complementary bit line being the bit line of a storage block adjacent to the target storage block.

[0068] In actual operation, the storage bank can be multiple, for example, as shown in Figure 1 The memory comprises 16 storage banks (bank) 0……15. Figure 2A is a module schematic diagram of the storage bank, as shown in Figure 2A Due to the limitation of the sensing amplifier array capability, a region of storage units within a range of every few hundred word lines (for example, 800-900) needs to be configured with one sensing amplifier array, and the signals on the bit lines and the complementary bit lines in the region are amplified by the one sensing amplifier array. The storage units, word lines and bit lines within the range of every few hundred word lines constitute a storage block (section). Figure 2B is a circuit schematic diagram of amplification of the storage bank, as shown in Figure 2BAs shown, the memory block includes multiple word lines WL, multiple bit lines BL, and multiple memory cells arranged in an array. Each memory cell is connected to one word line WL and one bit line BL. Furthermore, the bit lines of adjacent memory blocks become complementary bit lines within that memory block. A sense amplifier is connected between the bit lines and the complementary bit lines to amplify the signal between them.

[0069] like Figure 1 As shown, the control signal includes a storage block enable signal Section-EN; the repository is configured to: in a preset mode, in response to the control signal, activate each word line of at least one target storage block in the repository, including: the repository drives the activation of each word line within the target storage block based on the storage block enable signal Section-EN.

[0070] For details, see Figure 1 The storage block enable signal Section-EN is generated as follows: the address latch sends the target storage block address information to the storage block address decoder, the storage block address decoder decodes the storage block address information and generates the storage block enable signal Section-EN.

[0071] In one embodiment, the control signal further includes a repository enable signal Bank-EN (not shown in the figure); the repository is further configured to: when the repository enable signal Bank-EN is valid, drive activation of each word line within the target memory block based on the memory block enable signal Section-EN; and when the repository enable signal Bank-EN is invalid, not drive activation of the word lines.

[0072] When the memory includes multiple repositories, in a preset mode, the repository enable signals Bank-EN of the multiple repositories can be active simultaneously. That is, in the preset mode, each word line in the target repository within the multiple repositories can be activated. Here, the preset mode is a compressed write mode.

[0073] Here, in order to ensure that every word line in all repositories can be activated, in one embodiment, such as Figure 1 As shown, the control signals also include the All-bank-EN enable signal. When the All-bank-EN enable signal is active, all the Bank-EN enable signals are also active simultaneously, which will drive the activation of every word line within all repositories. Figure 1As shown, the all-bank enable signal All-bank-EN is generated by commanding a latch to send a command signal to a command decoder, which decodes the command signal to obtain the all-bank enable signal All-bank-EN.

[0074] To implement the overall assignment of the storage block, in addition to activating all word lines in the target storage block, the voltage on the bit line and the complementary bit line also needs to be adjusted to drive the voltage adjustment of the bit line to implement the assignment of the storage block.

[0075] To this end, as shown in Figure 1 The memory further includes a bit line write control module 110 capable of pulling up or pulling down the level of the bit line of the target storage block and pulling the complementary bit line of each bit line in the target storage block to the opposite level of the bit line based on the control signal.

[0076] In an embodiment, as shown in Figure 1 The bit line write control module 110 includes an enable module 111, a bit line write module 112 and a complementary bit line write module 113. The enable module 111 generates a bit line write control signal and a complementary bit line write control signal based on a control signal and sends the write control signal and the complementary bit line write control signal to the bit line write module 112 and the complementary bit line write module 113, respectively. The bit line write module 112 pulls up the bit line to a high level or pulls down the bit line to a low level based on the bit line write control signal. The complementary bit line write module 113 pulls the complementary bit line to the opposite level of the bit line based on the complementary bit line write control signal.

[0077] Specifically, Figure 3 An amplification schematic diagram of the enable module 111 and its surrounding circuit is shown in Figure 1 and Figure 3As shown, the control signal further includes a first trigger signal TMBLT1T and a second trigger signal TMBLT0T, the enable module 111 includes a first AND gate 151 and a second AND gate 152, the first AND gate 151 obtains the first trigger signal TMBLT1T in the control signal and the storage block enable signal Section-EN, generates a bit line write control signal based on the first trigger signal TMBLT1T and the storage block enable signal Section-EN, the second AND gate 152 obtains the second trigger signal TMBLT0T and the storage block enable signal Section-EN, generates a complementary bit line write control signal TMBLFORCEL based on the second trigger signal TMBLT0T and the storage block enable signal Section-EN. The bit line write control signal TMBLFORCEH and the complementary bit line write control signal TMBLFORCEL can be a high write control signal or a low write control signal, and the first AND gate 151 and the second AND gate 152 are configured to output a low write control signal when the first AND gate 151 outputs a high write control signal, and output a high write control signal when the first AND gate 151 outputs a low write control signal.

[0078] Specifically, when the first trigger signal TMBLT1T is 1, the second trigger signal TMBLT0T is 0, at this time the first AND gate 151 generates a high write control signal according to the first trigger signal TMBLT1T and the storage block enable signal Section-EN, and the second AND gate 152 generates a low write control signal according to the second trigger signal TMBLT0T and the storage block enable signal Section-EN. By controlling the first trigger signal TMBLT1T and the second trigger signal TMBLT0T to be opposite signals, when the first AND gate 151 outputs a high write control signal, the second AND gate 152 outputs a low write control signal, and when the first AND gate 151 outputs a low write control signal, the second AND gate 152 outputs a high write control signal.

[0079] Here, the first trigger signal TMBLT1T and the second trigger signal TMBLT0T are generated by the assignment control signal generation module. Specifically, the assignment control signal generation module obtains a preset mode signal from a mode register, when the preset mode is a compression write mode, the preset mode signal drives the assignment control signal generation module to send the first trigger signal TMBLT1T and the second trigger signal TMBLT0T to the first AND gate 151 and the second AND gate 152 respectively.

[0080] Figure 2 is an enlarged schematic view of the bit line write module 112 and the complementary bit line write module 113. Figure 4 is an enlarged schematic view of the bit line write module 112 and the complementary bit line write module 113. As shown in Figure 2, the bit line write module 112 includes a first transistor M1 and a second transistor M2, the first transistor M1 is connected between the bit line BL and the bit line write control signal TMBLFORCEH, the second transistor M2 is connected between the bit line BL and the complementary bit line write control signal TMBLFORCEL. The complementary bit line write module 113 includes a third transistor M3 and a fourth transistor M4, the third transistor M3 is connected between the bit line BL and the complementary bit line write control signal TMBLFORCEL, the fourth transistor M4 is connected between the bit line BL and the bit line write control signal TMBLFORCEH. Figure 4As shown, the input end of the bit line write module 112 is connected with the output end of the first AND gate 151, and the input end of the complementary bit line write module 113 is connected with the output end of the second AND gate 152. The bit line write module 112 pulls the level of the bit line in the target memory block to high or low based on the bit line write control signal, and the complementary bit line write module 113 pulls the complementary bit line in the target memory block to the opposite level of the bit line based on the complementary bit line write control signal.

[0081] In an embodiment, as shown in FIG. 2, the bit line write module 112 includes a first transistor 121 and a second transistor 122. The first transistor 121 is turned on based on a low write control signal, and the second transistor 122 is turned on based on a high write control signal. The source of the first transistor 121 is coupled with a power supply end, the drain of the first transistor 121 is coupled with the drain of the second transistor 122, and the source of the second transistor 122 is grounded. The gate of the first transistor 121 is connected with the gate of the second transistor 122 and coupled with the first AND gate 151. Figure 4 The complementary bit line write module 113 includes a third transistor 123 and a fourth transistor 124. The third transistor 123 is turned on based on a low write control signal, and the fourth transistor 124 is turned on based on a high write control signal. The source of the third transistor 123 is coupled with a power supply end, the drain of the third transistor 123 is coupled with the drain of the fourth transistor 124, and the source of the fourth transistor 124 is grounded. The gate of the third transistor 123 is connected with the gate of the fourth transistor 124 and coupled with the second AND gate 152. When the first AND gate 151 outputs a high write control signal to the bit line write module 112 and the second AND gate 152 outputs a low write control signal to the complementary bit line write module 113, the second transistor 122 is turned on and the third transistor 123 is turned on. Since the source of the second transistor 122 is grounded VSS and the source of the third transistor 123 is coupled with a power supply end, the level of the bit line is pulled low and the level of the complementary bit line is pulled high. Conversely, when the first AND gate 151 outputs a low write control signal to the bit line write module 112 and the second AND gate 152 outputs a high write control signal to the complementary bit line write module 113, the level of the bit line is pulled high and the level of the complementary bit line is pulled low.

[0082] In the above embodiments, since both the bit line write module 112 and the complementary bit line write module 113 are composed of two transistors of opposite types, there will always be one transistor in each of the bit line write module 112 and the complementary bit line write module 113 that cannot be completely turned off. However, after the memory is tested for practical applications, the main application scenarios are in the normal write mode of the non-compressed write mode. The normal write mode requires the use of the normal write module 140 (see Appendix). Figure 4 This is achieved through [method 1]. However, since one transistor in each of the bit line writing modules 112 and complementary bit line writing modules 113 will inevitably fail to turn off completely, this will cause the voltage on the bit line or complementary bit line to be pulled up or down from the normal voltage by the bit line writing module and complementary bit line writing module during normal write mode, thereby interfering with normal write operations. Therefore, in one embodiment, as [example of the solution is missing here]. Figure 4 As shown, the memory also includes an isolation module 130, such as... Figure 4 As shown, the isolation module 130 includes a first switch 131 connected between the bit line and the bit line writing module 112, and a second switch 132 connected between the complementary bit line and the complementary bit line writing module 113. The gate of the first switch 131 is connected to the gate of the second switch 132 and coupled to the isolation signal terminal ISO of the mode register. When the preset mode is compressed write mode, the isolation signal terminal ISO outputs a high-level signal to the first switch 131 and the second switch 132; when the preset mode is not compressed write mode, the isolation signal terminal ISO outputs a low-level signal to the first switch 131 and the second switch 132. That is, when the preset mode is compressed write mode, the isolation module 130 turns on the first switch 131 and the second switch 132; when the preset mode is not compressed write mode, the isolation module 130 turns off the first switch 131 and the second switch 132. Specifically, the high level here can be higher than VDD, and the low level here can be lower than 0V. The isolation signal can be output from the mode register, or it can be obtained by decoding from the command signal.

[0083] Thus, by setting the isolation module 130, in non-compression mode, the bit line and complementary bit line can be disconnected from the bit line and complementary bit line writing module 113 by controlling the isolation module 130. Therefore, even if there are transistors in the bit line writing module 112 and complementary bit line writing module 113 that cannot be turned off, normal writing will not be interfered with by the bit line writing module and complementary bit line writing module 112 and complementary bit line writing module 113 because the bit line and complementary bit line are disconnected from the bit line writing module 112 and complementary bit line writing module 113.

[0084] In another embodiment, the bit line write module 112 and the complementary bit line write module 113 can be as shown in another structure. As shown in another structure, the bit line write module 112 includes: a first transistor 121 and a second transistor 122 turned on based on a low write control signal, a source of the first transistor 121 coupled with a power supply end, a drain of the first transistor 121 coupled with the bit line, a source of the second transistor 122 coupled with the complementary bit line, a drain of the second transistor 122 grounded, a gate of the first transistor 121 and a gate of the second transistor 122 connected and coupled with the first AND gate 151; or, the first transistor 121 and the second transistor 122 turned on based on a high write control signal, a drain of the first transistor 121 coupled with the power supply end, a source of the first transistor 121 coupled with the bit line, a drain of the second transistor 122 coupled with the complementary bit line, a source of the second transistor 122 grounded, the gate of the first transistor 121 and the gate of the second transistor 122 connected and coupled with the first AND gate 151. Figure 5 Figure 5 As shown, the bit line write module 112 includes: a first transistor 121 and a second transistor 122 turned on based on a low write control signal, a source of the first transistor 121 coupled with a power supply end, a drain of the first transistor 121 coupled with the bit line, a source of the second transistor 122 coupled with the complementary bit line, a drain of the second transistor 122 grounded, a gate of the first transistor 121 and a gate of the second transistor 122 connected and coupled with the first AND gate 151; or, the first transistor 121 and the second transistor 122 turned on based on a high write control signal, a drain of the first transistor 121 coupled with the power supply end, a source of the first transistor 121 coupled with the bit line, a drain of the second transistor 122 coupled with the complementary bit line, a source of the second transistor 122 grounded, the gate of the first transistor 121 and the gate of the second transistor 122 connected and coupled with the first AND gate 151.

[0085] Correspondingly, the complementary bit line write module 113 includes: a third transistor 123 and a fourth transistor 124 turned on based on a low write control signal; a source of the third transistor 123 coupled with the bit line, a drain of the third transistor 123 grounded, a source of the fourth transistor 124 coupled with a power supply end, a drain of the fourth transistor 124 coupled with the complementary bit line, the gate of the third transistor 123 and the gate of the fourth transistor 124 connected and coupled with the second AND gate 152; or,

[0086] the third transistor 123 and the fourth transistor 124 turned on based on a high write control signal, a drain of the third transistor 123 coupled with the bit line, a source of the third transistor 123 grounded, a drain of the fourth transistor 124 coupled with the power supply end, a source of the fourth transistor 124 coupled with the complementary bit line, the gate of the third transistor 123 and the gate of the fourth transistor 124 connected and coupled with the second AND gate 152.

[0087] ​The first transistor 121, the second transistor 122, the third transistor 123 and the fourth transistor 124 are all turned on based on a low write control signal. When the first AND gate 151 outputs a high write control signal to the bit line write module 112 and the second AND gate 152 outputs a low write control signal to the complementary bit line write module 113, the third transistor 123 and the fourth transistor 124 are turned on, and the bit line is pulled to a low level and the complementary bit line is pulled to a high level due to the drain of the third transistor 123 being connected to the ground and the source of the fourth transistor 124 being connected to the power supply end. Conversely, when the first AND gate 151 outputs a low write control signal to the bit line write module 112 and the second AND gate 152 outputs a high write control signal to the complementary bit line write module 113, the bit line is pulled to a high level and the complementary bit line is pulled to a low level.

[0088] In this embodiment, the first transistor 121, the second transistor 122, the third transistor 123 and the fourth transistor 124 are the same type of transistors, and all of the first transistor 121, the second transistor 122, the third transistor 123 and the fourth transistor 124 can be turned off by applying an off signal to the bit line write module 112 and the complementary bit line write module 113. Therefore, in this embodiment, the bit line write module 112 and the complementary bit line write module 113 can avoid interfering with normal writing in the non-compression write mode by turning off all the transistors in the bit line write module 112 and the complementary bit line write module 113 by applying an off signal. Therefore, in this embodiment, as shown in Figures 5-6 It should be understood that this is not a limitation on the memory not having an isolation module 130 and an isolation signal terminal ISO when the bit line write module and the complementary bit line write module adopt the structure shown in Figure 5 In fact, to maximize the isolation interference, even if the bit line write module and the complementary bit line write module adopt the structure shown in Figure 5 The memory can also have an isolation module and an isolation signal terminal.

[0089] An embodiment of the present application provides a compression write method, as shown in Figure 7 The method comprises the following steps:

[0090] In step S701, the memory is controlled to enter a preset mode.

[0091] In step S702, each word line of at least one target storage block included in the memory is activated.

[0092] Step S703, pull up or pull down the level of each bit line of the target memory block, and pull the complementary bit line of each bit line in the target memory block to the opposite level of the bit line; wherein,

[0093] The memory comprises a memory bank, the memory bank comprises a plurality of memory blocks, the memory block comprises a plurality of word lines, a plurality of bit lines, and a plurality of memory cells arranged in an array, each memory cell is connected to one of the word lines and one of the bit lines, and the complementary bit line is a bit line of a memory block adjacent to the target memory block.

[0094] In actual operation, first, step S701 is performed, and the memory is controlled to enter a preset mode, which can be a compressed write mode.

[0095] Then, step S702 is performed, and each word line of at least one target memory block included in the memory is activated.

[0096] In an embodiment, the activation of each word line of at least one target memory block included in the memory comprises:

[0097] A control signal is received, and the control signal comprises a memory block enable signal Section-EN.

[0098] Each word line in the target memory block is driven and activated based on the memory block enable signal Section-EN.

[0099] Specifically, the memory block decoder obtains address information from the address latch and decodes it, obtains the memory block enable signal Section-EN after decoding, and sends the memory block enable signal Section-EN to the memory bank. The memory bank receives the memory block enable signal Section-EN and drives and activates each word line in the target memory block.

[0100] In some embodiments, as shown in Figure 1 The memory can comprise a plurality of memory banks;

[0101] The control signal further comprises a memory bank enable signal Bank-EN (not shown in the figure);

[0102] When the memory bank enable signal Bank-EN is valid, each word line in the target memory block is driven and activated based on the memory block enable signal Section-EN; when the memory bank enable signal Bank-EN is invalid, the word line is not driven and activated.

[0103] In a preset mode, the storage bank enable signals Bank-EN of the plurality of storage banks are enabled simultaneously. That is, in the preset mode, each word line in the target storage bank in the plurality of storage banks is activated. Specifically, the preset mode can be a compressed write mode for example.

[0104] Here, in order to enable each word line in all storage banks to be activated, in an embodiment, as shown in Figure 1 The control signals further include an all-bank enable signal All-bank-EN, when the all-bank enable signal All-bank-EN is enabled, all the storage bank enable signals Bank-EN are enabled simultaneously, at this time, each word line in all storage banks is driven to be activated. As shown in Figure 1 The all-bank enable signal All-bank-EN is generated by the following way: a command latch sends a command signal to a command decoder, the command decoder decodes the command signal to obtain the all-bank enable signal All-bank-EN.

[0105] After activating all the word lines of the target storage block, it is further needed to drive the level of all bit lines in the target storage block and the complementary bit lines of the bit lines to change the plate voltage on all storage units in the target storage block, so as to complete the assignment of the entire target storage block. That is, step S703 is performed, the level of each bit line of the target storage block is pulled high or low, and the complementary bit line of each bit line in the target storage block is pulled to the opposite level of the bit line.

[0106] In actual operation, pulling the level of each bit line of the target storage block high or low includes:

[0107] The storage block enable signal Section-EN is obtained;

[0108] The bit line write control signal TMBLFORCEH is output, the bit line write control signal TMBLFORCEH is a high write control signal or a low write control signal;

[0109] The level of the bit line is pulled high or low based on the bit line write control signal TMBLFORCEH.

[0110] The complementary bit line is pulled to the opposite level of the bit line, including:

[0111] The storage block enable signal Section-EN is obtained;

[0112] an output complementary bit line write control signal TMBLFORCEL, which is a high write control signal or a low write control signal;

[0113] based on the complementary bit line write control signal TMBLFORCEL, pulling the complementary bit line to a level opposite to the bit line.

[0114] Specifically, the mode register sends a preset mode signal to the assignment control signal generation module, when the preset mode is the compression write mode, the preset mode signal drives the assignment control signal generation module to send a first trigger signal TMBLT1T and a first trigger signal TMBLT0T to the first AND gate 151 and the second AND gate 152 respectively. The first AND gate 151 receives the storage block enable signal Section-EN and the first trigger signal TMBLT1T, and the first trigger signal TMBLT1T triggers the first AND gate to generate a bit line write control signal TMBLFORCEH based on the storage block enable signal Section-EN and the first trigger signal TMBLT1T. The second AND gate 152 receives the storage block enable signal Section-EN and the first trigger signal TMBLT0T, and the first trigger signal TMBLT0T triggers the second AND gate 152 to generate a complementary bit line write control signal TMBLFORCEL based on the storage block enable signal Section-EN and the first trigger signal TMBLT0T.

[0115] The bit line write control signal and the complementary bit line write control signal can be a high write control signal or a low write control signal, and the first AND gate 151 and the second AND gate 152 are configured to output a low write control signal when the first AND gate 151 outputs a high write control signal, and output a high write control signal when the first AND gate 151 outputs a low write control signal.

[0116] Specifically, when the first trigger signal TMBLT1T is 1, the first trigger signal TMBLT0T is 0, at this time the first AND gate 151 generates a high write control signal according to the first trigger signal TMBLT1T and the storage block enable signal Section-EN, and the second AND gate 152 generates a low write control signal according to the second trigger signal TMBLT0T and the storage block enable signal Section-EN. By controlling the first trigger signal TMBLT1T and the first trigger signal TMBLT0T to be opposite signals, when the first AND gate 151 outputs a high write control signal, the second AND gate 152 outputs a low write control signal, and when the first AND gate 151 outputs a low write control signal, the second AND gate 152 outputs a high write control signal.

[0117] The bit line write control signal TMBLFORCEH is received by the bit line write module, the complementary bit line write control signal TMBLFORCEL is received by the complementary bit line write module, the bit line write module pulls the level on the bit line high or low based on the bit line write control signal TMBLFORCEH, and the complementary bit line write module pulls the level on the complementary bit line to the opposite of the level on the bit line based on the complementary bit line write control signal TMBLFORCEL.

[0118] Through the above steps, the embodiment provided by the application adopts the write mode of activating all word lines in a target storage block and adjusting the voltage on the bit line and the complementary bit line of the entire target storage block, and can realize the assignment of the entire storage block at one time, greatly shortens the test time compared with the normal write and general compression write mode, improves the test efficiency and reduces the test cost. In addition, compared with the normal write and general compression write mode, the mode of adjusting the voltage on the bit line and the complementary bit line by the bit line write control module provided by the application does not need to pass through the column selection module (CSEL), and does not need to provide data on the local data line (LIO), so that the target storage block can be assigned as a whole, and the timing time of tRCD and CWL does not need to be waited, further saving the test time and test cost.

[0119] It needs at least 65536 times of ACTPRECHARGE command and 65536*128 times of write command to fill all the matrices in 1 bank by using the write mode in the related art, and the time of waiting for the intermediate inserted timing is needed. However, the compression write mode of the application only needs the time of 1 time of ACT PRECHARGE*the number of all sections in one bank and some related test mode commands, so that the time needed for assigning the storage matrix is greatly reduced, the test efficiency is improved, and the test cost is saved.

[0120] It should be noted that the three-dimensional phase change memory embodiment provided by the application and the preparation method embodiment of the three-dimensional phase change memory belong to the same concept; the technical features in the technical solutions recorded in each embodiment can be arbitrarily combined without conflict.

[0121] The above is only a preferred embodiment of the application, and is not used to limit the protection scope of the application, and any modification, equivalent replacement and improvement made within the spirit and principle of the application should be included in the protection scope of the application.

Claims

1. A memory, characterized in that, include: Repository; The repository includes multiple storage blocks, each storage block comprising multiple word lines, multiple bit lines, and multiple storage cells arranged in an array, each storage cell being connected to one word line and one bit line; wherein, The repository is configured to: in a preset mode, in response to a control signal, activate each word line of at least one target storage block in the repository; Without going through the column selection module and without providing data on the local data lines, the level on each bit line of the target memory block is pulled high or low, and the complementary bit line of each bit line in the target memory block is pulled to the opposite level to the bit line, wherein the complementary bit line is a bit line of a memory block adjacent to the target memory block.

2. The memory according to claim 1, characterized in that, The memory also includes a bit line write control module, which pulls all the levels on the bit lines of the target memory block high or low based on the control signal.

3. The memory according to claim 2, characterized in that, The bit line write control module includes an enable module and a bit line write module. The enable module outputs a bit line write control signal to the bit line write module. The bit line write control signal is either a high write control signal or a low write control signal. The bit line write module pulls the bit line high or low based on the bit line write control signal.

4. The memory according to claim 3, characterized in that, The enabling module includes a first AND gate, which outputs a bit line write control signal based on the memory block enable signal.

5. The memory according to claim 4, characterized in that, The bit line writing module includes a first transistor and a second transistor. The first transistor is turned on based on a low write control signal, and the second transistor is turned on based on a high write control signal. The source of the first transistor is coupled to a power supply terminal, the drain of the first transistor is coupled to the drain of the second transistor, and the source of the second transistor is grounded. The gates of the first transistor and the second transistor are connected and coupled to the first AND gate. or, The first transistor and the second transistor are turned on based on a low write control signal. The source of the first transistor is coupled to a power supply terminal, and the drain of the first transistor is coupled to the bit line. The source of the second transistor is coupled to the complementary bit line, and the drain of the second transistor is grounded. The gates of the first transistor and the second transistor are connected together and coupled to the first AND gate; or, The first transistor and the second transistor are turned on based on a high write control signal. The drain of the first transistor is coupled to the power supply terminal, the source of the first transistor is coupled to the bit line, the drain of the second transistor is coupled to the complementary bit line, the source of the second transistor is grounded, and the gates of the first transistor and the second transistor are connected together and coupled to the first AND gate.

6. The memory according to claim 4, characterized in that, The bit line write control module further includes a complementary bit line write module, which is used to pull the complementary bit line to a level opposite to that of the bit line in the target memory block.

7. The memory according to claim 6, characterized in that, The enabling module further includes: a second AND gate, which outputs a complementary bit line write control signal to the complementary bit line write module based on the control signal, wherein the complementary bit line write control signal is a high write control signal or a low write control signal; the complementary bit line write module pulls the complementary bit line high or low based on the complementary bit line write control signal.

8. The memory according to claim 7, characterized in that, The second AND gate is configured such that when the first AND gate outputs a high write control signal, the second AND gate outputs a low write control signal; and when the second AND gate outputs a low write control signal, the first AND gate outputs a high write control signal.

9. The memory according to claim 8, characterized in that, The complementary bit-line write module includes a third transistor and a fourth transistor. The third transistor is turned on based on a low write control signal, and the fourth transistor is turned on based on a high write control signal. The source of the third transistor is coupled to a power supply terminal, the drain of the third transistor is coupled to the drain of the fourth transistor, and the source of the fourth transistor is grounded. The gates of the third transistor and the fourth transistor are connected and coupled to a second AND gate; or... The third and fourth transistors are turned on based on a low write control signal; the source of the third transistor is coupled to the complementary bit line, the drain of the third transistor is grounded, the source of the fourth transistor is coupled to the power supply, the drain of the fourth transistor is coupled to the complementary bit line, and the gates of the third and fourth transistors are connected and coupled to the second AND gate; or, The third transistor and the fourth transistor are turned on based on a high write control signal. The drain of the third transistor is coupled to the complementary bit line, and the source of the third transistor is grounded. The drain of the fourth transistor is coupled to the power supply terminal, and the source of the fourth transistor is coupled to the complementary bit line. The gates of the third transistor and the fourth transistor are connected and coupled to the second AND gate.

10. The memory according to claim 6, characterized in that, The repository also includes an isolation module, which includes a first switch connected between the bit line and the bit line writing module and a second switch connected between the complementary bit line and the complementary bit line writing module.

11. The memory according to claim 10, characterized in that, When the preset mode is compressed write mode, the isolation module turns on the first switch and the second switch; when the preset mode is not compressed write mode, the isolation module turns off the first switch and the second switch.

12. The memory according to claim 11, characterized in that, The gate of the first switch is connected to the gate of the second switch and coupled to an isolation signal terminal. When the preset mode is compressed write mode, the isolation signal terminal outputs a high-level signal to the first switch and the second switch. When the preset mode is not compressed write mode, the isolation signal terminal outputs a low-level signal to the first switch and the second switch.

13. A compressed writing method, characterized in that, Control the memory to enter a preset mode; Activate each word line of at least one target memory block contained in the memory; Without going through the column selection module and without data being provided by the local data lines, the level of each bit line of the target memory block is pulled high or low, and the complementary bit line of each bit line in the target memory block is pulled to the opposite level to the bit line; wherein, The memory includes a repository, which includes a plurality of memory blocks. Each memory block includes a plurality of word lines, a plurality of bit lines, and a plurality of memory cells arranged in an array. Each memory cell is connected to one of the word lines and one of the bit lines. The complementary bit lines are bit lines of memory blocks adjacent to the target memory block.

14. The method according to claim 13, characterized in that, The activation of each word line of at least one target memory block in the memory includes: Receive control signals, including memory block enable signals; The memory block enable signal drives the activation of each word line within the target memory block.

15. The method according to claim 14, characterized in that, The memory includes multiple of the aforementioned repositories; The control signals also include a repository enable signal; When the repository enable signal is valid, each word line within the target storage block is activated based on the storage block enable signal. When the repository enable signal is invalid, the activation word line is not driven.

16. The method according to claim 15, characterized in that, In a preset mode, the repository enable signals of multiple repositories are active simultaneously.

17. The method according to claim 16, characterized in that, The preset mode is compressed write mode.

18. The method according to claim 14, characterized in that, Pulling up or down the level of each bit line of the target memory block, including: Obtain the enable signal of the memory block; Output a bit line write control signal, wherein the bit line write control signal is a high write control signal or a low write control signal; The bit line write control signal is used to pull the level on the bit line high or low.

19. The method according to claim 14, characterized in that, Pulling the complementary bit line to a level opposite to that of the bit line includes: Obtain the enable signal of the memory block; Output a complementary bit line write control signal, wherein the complementary bit line write control signal is a high write control signal or a low write control signal; Based on the complementary bit line write control signal, the complementary bit line is pulled to a level opposite to that of the bit line.

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