Input sampling system, method, storage medium and computer equipment

Abstract

This invention relates to an input sampling system, method, storage medium, and computer device, comprising: a signal processing module for receiving an initial chip select signal and a control / command signal, and subsequently widening the pulse width of the valid signal in the initial chip select signal to obtain a first chip select signal, thereby controlling the end time of the valid signal in the first chip select signal to be later than the end time of the valid signal in the control / command signal; and an input sampling module, connected to the signal processing module, for receiving the control / command signal, the first chip select signal, and a clock pulse signal, and sampling the control / command signal according to the first chip select signal and the clock pulse signal. The above-described input sampling system, method, storage medium, and computer device can prevent control / command signal sampling failure.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to an input sampling system, method, storage medium, and computer device. Background Technology

[0002] Currently, in the input sampling system of Double Data Rate (DDR) synchronous dynamic random access memory, the control / command (C / A) signal and the clock signal enter the sampling circuit through receivers. The C / A signal is then sampled based on the clock signal, and a synchronous C / A signal is output for subsequent logic operations. However, in the design of Dual Inline Memory Modules (DIMMs) for Dynamic Random Access Memory (DRAM), the C / A signal is shared by multiple DRAMs, and specific DRAM control is distinguished by the chip select (CS) signal. Different DRAMs share the C / A data bus to receive the same C / A signal but receive different CS signals. Therefore, it is necessary to determine the validity of the received C / A signal based on the chip select signal.

[0003] However, as the frequency of dynamic random access memory (DRAM) increases, the pulse widths of the C / A and CS signals continuously narrow. Because the C / A and CS signals follow different paths, a skew occurs at the logic circuit where the CS signal selects the C / A signal. This causes the end time of the valid signal in the C / A signal to be later than the end time of the valid signal in the CS signal. Considering the effects of process voltage and temperature variations (PVT), the effective pulse width of the selected C / A signal becomes even narrower, making it impossible to acquire the C / A signal after the end of the valid signal in the CS signal, potentially causing C / A sampling failure. Summary of the Invention

[0004] Therefore, it is necessary to provide an input sampling system, method, storage medium, and computer device to address the above problems.

[0005] To achieve the above objectives, in one aspect, the present invention provides an input sampling system, comprising:

[0006] The signal processing module is used to receive an initial chip select signal and a control / command signal, and then widen the pulse width of the valid signal in the initial chip select signal to obtain a first chip select signal, so as to control the end time of the valid signal in the first chip select signal to be later than the end time of the valid signal in the control / command signal;

[0007] An input sampling module, connected to the signal processing module, is used to receive the control / command signal, the first chip select signal, and the clock pulse signal, and to sample the control / command signal based on the first chip select signal and the clock pulse signal.

[0008] In one embodiment, it further includes:

[0009] A signal generation module, connected to the signal processing module, is used to send the initial chip select signal and the control / command signal. The initial chip select signal is sent earlier than the control / command signal, so as to control the arrival time of the valid signal in the initial chip select signal to be earlier than the arrival time of the valid signal in the control / command signal.

[0010] In one embodiment, the signal processing module is further configured to extend the pulse width of the valid signal in the initial chip select signal forward, so as to control the arrival time of the valid signal in the first chip select signal to be earlier than the arrival time of the valid signal in the control / command signal.

[0011] In one embodiment, the signal processing module includes:

[0012] An initial chip select signal receiving unit is configured to receive the initial chip select signal and output a second chip select signal after delaying the initial chip select signal.

[0013] A control / command signal receiving unit is configured to receive the control / command signal and output a first control / command signal after delaying the control / command signal. The absolute delay of the initial chip select signal receiving unit is less than the absolute delay of the control / command signal receiving unit.

[0014] A logic processing unit, connected to the initial chip select signal receiving unit and the control / command signal receiving unit, is used to delay the second chip select signal to obtain a third chip select signal, and to obtain the first chip select signal based on the second chip select signal and the third chip select signal. The arrival time of the valid signal in the first chip select signal is the same as the arrival time of the valid signal in the second chip select signal, and the end time of the valid signal in the first chip select signal is the same as the end time of the valid signal in the third chip select signal.

[0015] In one embodiment, the initial chip select signal receiving unit includes a first comparator. The initial chip select signal is input to the non-inverting input terminal of the first comparator, a first reference voltage is input to the inverting input terminal of the first comparator, and a second chip select signal is output from the output terminal of the first comparator. The second chip select signal is a high-level signal when the voltage of the initial chip select signal is greater than the first reference voltage, and a low-level signal when the voltage of the initial chip select signal is less than the first reference voltage. The low-level signal in the second chip select signal is the valid signal of the second chip select signal.

[0016] In one embodiment, the control / command signal receiving unit includes a second comparator. The control / command signal is input to the non-inverting input terminal of the second comparator, a second reference voltage is input to the inverting input terminal of the second comparator, and the first control / command signal is output to the output terminal of the second comparator. The first control / command signal is a high-level signal when the voltage of the control / command signal is greater than the second reference voltage, and a low-level signal when the voltage of the control / command signal is less than the second reference voltage.

[0017] In one embodiment, the logic processing unit includes:

[0018] The third comparator has a non-inverting input terminal for receiving a first clock signal and an inverting input terminal for receiving a second clock signal. The third comparator is used to compare the first clock signal and the second clock signal to output a clock pulse signal.

[0019] A trigger, wherein the first input terminal of the trigger is connected to the output terminal of the initial chip select signal receiving unit to receive the second chip select signal, and the second input terminal of the trigger is connected to the third comparator to receive the clock pulse signal, and the trigger is used to delay the second chip select signal according to the clock pulse signal to obtain the third chip select signal;

[0020] An AND gate is used to receive the second chip select signal by connecting its first input to the output of the initial chip select signal receiving unit and the third chip select signal by connecting its second input to the output of the flip-flop. The AND gate is used to perform a logical AND operation on the second chip select signal and the third chip select signal to obtain the first chip select signal.

[0021] In one embodiment, the trigger is a rising edge trigger, and the arrival time of the valid signal in the third chip select signal output by the rising edge trigger is the same as the arrival time of the first rising edge of the clock pulse signal after the arrival of the valid signal of the second chip select signal.

[0022] In one embodiment, the clock pulse signal is a periodic signal, and the effective signals of the initial chip select signal, the second chip select signal, the third chip select signal, and the first chip select signal are all low-level signals.

[0023] In one embodiment, the input sampling module includes:

[0024] An input signal acquisition unit is provided, wherein a first input terminal of the input signal acquisition unit is connected to the output terminal of the AND gate to receive the first chip select signal, and a second input terminal of the input signal acquisition unit is connected to the control / command signal receiving unit to receive the first control / command signal. The input signal acquisition unit is used to sample the first control / command signal during the valid signal period of the first chip select signal to obtain a control / command input signal.

[0025] An input sampling unit is provided, wherein a first input terminal of the input sampling unit is connected to the output terminal of the input signal acquisition unit to receive the control / command input signal, and a second input terminal of the input sampling unit is connected to the output terminal of the third comparator to receive the clock pulse signal. The input sampling unit is used to sample the control / command input signal based on the clock pulse signal to obtain a control / command output signal.

[0026] In one embodiment, the input signal acquisition unit includes:

[0027] The NOT gate is connected to the control / command signal receiving unit to receive the first control / command signal. The NOT gate is used to invert the first control / command signal to obtain a second control / command signal.

[0028] The NOR gate is configured such that its first input is connected to the output of the AND gate to receive the first chip select signal, and its second input is connected to the output of the NOT gate to receive the second control / command signal. The NOR gate is used to perform a logical OR-NOT operation on the second control / command signal and the first chip select signal to obtain the control / command input signal.

[0029] An input sampling method, the method comprising:

[0030] Obtain the initial chip select signal and control / command signals;

[0031] The pulse width of the valid signal in the initial chip select signal is widened backward to obtain the first chip select signal, so as to control the end time of the valid signal in the first chip select signal to be later than the end time of the valid signal in the control / command signal;

[0032] Obtain the clock pulse signal;

[0033] The control / command signal is sampled based on the first chip select signal and the clock pulse signal.

[0034] In one embodiment, it further includes:

[0035] The pulse width of the valid signal in the initial chip select signal is increased forward to control the arrival time of the valid signal in the first chip select signal to be earlier than the arrival time of the valid signal in the control / command signal.

[0036] A computer device includes a memory and a processor, the memory storing a computer program, the processor executing the computer program to implement the steps of the method as described in any one of the above.

[0037] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described in any of the preceding claims.

[0038] The aforementioned input sampling system, method, storage medium, and computer device obtain a first chip select signal by extending the pulse width of the valid signal in the initial chip select signal backward. When sampling the control command signal based on the first chip select signal and the clock signal, because the end time of the valid signal in the first chip select signal is later than the end time of the valid signal in the original initial chip select signal, even if the control / command signal deviates from the initial chip select signal, the duration of the valid signal in the control / command signal is still included within the duration of the valid signal in the first chip select signal. Therefore, control / command signal sampling failure can be avoided. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a structural block diagram of an input sampling system provided in one embodiment of this application;

[0041] Figure 2 This is a waveform diagram of each signal in an input sampling system provided in one embodiment of this application;

[0042] Figure 3 This is a structural block diagram of an input sampling system provided in another embodiment of this application;

[0043] Figure 4This is a structural block diagram of an input sampling system provided in another embodiment of this application;

[0044] Figure 5 This is a waveform diagram of each signal in an input sampling system provided in another embodiment of this application;

[0045] Figure 6 This is a circuit diagram of an input sampling system provided in one embodiment of this application;

[0046] Figure 7 This is a flowchart of an input sampling method provided in one embodiment of this application.

[0047] Explanation of reference numerals in the attached figures:

[0048] 11. Signal generation module; 12. Signal processing module; 13. Input sampling module; 121. Initial chip select signal receiving unit; 122. Control / command signal receiving unit; 123. Logic processing unit; 131. Input signal acquisition unit; 132. Input sampling unit. Detailed Implementation

[0049] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0051] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0052] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0053] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0054] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of the invention, thus allowing for variations in the illustrated shape due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the invention.

[0055] Please see Figure 1 This application provides an input sampling system. The input sampling system includes a signal processing module 12 and an input sampling module 13. The signal processing module 12 is used to receive an initial chip select signal and a control / command signal, and then widen the pulse width of the valid signal in the initial chip select signal to obtain a first chip select signal, so as to control that the end time of the valid signal in the first chip select signal is later than the end time of the valid signal in the control / command signal. The input sampling module 13 is connected to the signal processing module 12 and is used to receive the control / command signal, the first chip select signal, and a clock pulse signal, and to sample the control / command signal according to the first chip select signal and the clock pulse signal.

[0056] Please refer to the following for details. Figure 2 The signal processing module 12 receives the initial chip select signal CS_n and the control / command signal C / A. The signal processing modules 12 of different DRAM input sampling systems receive the same control / command signal C / A, but receive different initial chip select signals CS_n. The initial chip select signal CS_n received by each signal processing module 12 can be configured according to the operating time period of each DRAM. The initial chip select signal CS_n and the control / command signal C / A can be issued by a device external to the input sampling system and received by the signal processing module 12; alternatively, they can be configured to be generated by the input sampling system.

[0057] The signal processing module 12 improves the received initial chip select signal CS_n by widening the pulse width of the valid signal in the initial chip select signal CS_n to obtain the first chip select signal CS_1. In this embodiment, widening the pulse width of the valid signal in the initial chip select signal CS_n refers to widening the pulse width of the valid signal in the initial chip select signal CS_n based on time, so that the end time of the valid signal in the first chip select signal CS_1 is later than the end time of the valid signal in the initial chip select signal CS_n, and the pulse width of the valid signal in the first chip select signal CS_1 is greater than the pulse width of the valid signal in the initial chip select signal CS_n. The width of the initial chip select signal CS_n widened backward is configured according to actual needs to ensure that the end time of the valid signal in the first chip select signal CS_1 is later than the end time of the valid signal in the control / command signal C / A.

[0058] The input sampling module 13 is connected to the signal processing module 12 to obtain the control / command signal C / A and the first chip select signal CS_1 output by the signal processing module 12. The input sampling module 13 also receives clock pulse signals from external devices or generated by the input sampling system, and samples the control / command signal C / A according to the first chip select signal CS_1 and the clock pulse signal. When the input sampling module 13 samples the control / command signal C / A, since the end time of the valid signal in the first chip select signal CS_1 is later than the end time of the valid signal in the control / command signal C / A, when the control / command signal C / A deviates from the initial chip select signal CS_n, and the end time of the valid signal in the control / command signal C / A is later than the end time of the valid signal in the initial chip select signal CS_n, it can be guaranteed that the duration of the valid signal in the control / command signal C / A is within the duration of the valid signal in the first chip select signal CS_1, thus enabling the acquisition of the complete control / command signal C / A.

[0059] The aforementioned input sampling system improves the received initial chip select signal CS_n, enabling different DRAM input sampling systems to sample the control command signal C / A based on the corresponding improved initial chip select signal CS_n, i.e., the first chip select signal CS_1. When the input sampling system does not receive the initial chip select signal CS_n or the first chip select signal CS_1 is invalid, it will not execute the control / command signal C / A even if it receives it; that is, the control / command signal C / A is masked, thus preventing data flipping within the input sampling system and saving power. When the input sampling system receives a valid signal from the first chip select signal CS_1, it samples and executes the control command signal C / A. When sampling the control command signal C / A, because the first chip select signal CS_1 widens the pulse width of the effective signal compared to the initial chip select signal CS_n, even if the control / command signal C / A deviates from the initial chip select signal CS_n, and the end time of the effective signal in the control / command signal C / A is later than the end time of the effective signal in the initial chip select signal CS_n, it can be guaranteed that the duration of the effective signal in the control / command signal C / A is within the duration of the effective signal in the first chip select signal CS_1. Thus, the complete control / command signal C / A can be acquired, avoiding the failure of the control / command signal C / A.

[0060] In some examples, please refer to Figure 2 and Figure 3 The input sampling system also includes a signal generation module 11. The signal generation module 11 is connected to the signal processing module 12. The signal generation module 11 is used to issue an initial chip select signal CS_n and a control / command signal C / A, and the signal generation module 11 issues the initial chip select signal CS_n earlier than the control / command signal C / A, so as to control the arrival time of the valid signal in the initial chip select signal CS_n to be earlier than the arrival time of the valid signal in the control / command signal C / A.

[0061] Specifically, the signal generation module 11 controls the timing of sending the valid signal in the initial chip select signal CS_n and the valid signal in the control / command signal C / A to the processing module, so that the valid signal in the initial chip select signal CS_n is sent in advance. Then, the signal processing module 12 widens the received initial chip select signal CS_n backward, which is equivalent to widening the initial chip select signal CS_n both forward and backward. This ensures that no matter whether the control / command signal C / A deviates forward or backward (both forward and backward deviations are based on time), when sampling the control / command signal C / A based on the first chip select signal CS_1, the duration of the valid signal in the control / command signal C / A is within the duration of the valid signal in the first chip select signal CS_1, thereby ensuring that the complete control / command signal C / A is acquired.

[0062] In other examples, please refer to Figure 5 The signal processing module 12 is also used to widen the pulse width of the valid signal in the initial chip select signal CS_n so as to control the arrival time of the valid signal in the first chip select signal CS_1 to be earlier than the arrival time of the valid signal in the control / command signal C / A.

[0063] Specifically, the forward widening of the pulse width of the valid signal in the initial chip select signal CS_n refers to the time-wise widening of the pulse width of the valid signal in the initial chip select signal CS_n relative to the received chip select signal CS_4 in conventional technology. In conventional technology, after receiving the initial chip select signal CS_n and the control / command signal C / A, the input sampling system delays the initial chip select signal CS_n to obtain the chip select signal CS_4 and delays the control / command signal C / A. The arrival times of the valid signals in the delayed chip select signal CS_4 and the control / command signal C / A can be the same. The delayed control / command signal C / A is sampled based on the chip select signal CS_4. In this embodiment, the signal processing module 12 can delay both the received initial chip select signal CS_n and the control / command signal C / A. However, the delay time of the initial chip select signal CS_n can be less than the delay time of the initial chip select signal CS_n in the conventional technology, so that the arrival time of the valid signal in the initial chip select signal CS_n is earlier than the arrival time of the valid signal in the control / command signal C / A, thereby achieving the purpose of widening the pulse width of the valid signal in the initial chip select signal CS_n.

[0064] In this embodiment, the effective signal in the first chip select signal CS_1 is issued earlier and extended backward compared to the traditional chip select signal CS_4. This ensures that regardless of whether the control / command signal C / A deviates forward or backward (both forward and backward deviations are based on time), when sampling the control / command signal C / A based on the first chip select signal CS_1, the duration of the effective signal in the control / command signal C / A is within the duration of the effective signal in the first chip select signal CS_1, thereby ensuring that the complete control / command signal C / A is acquired.

[0065] In some examples, please refer to Figure 4 and Figure 5The signal processing module 12 includes an initial chip select signal receiving unit 121, a control / command signal receiving unit 122, and a logic processing unit 123. The initial chip select signal receiving unit 121 receives the initial chip select signal CS_n and outputs a second chip select signal CS_2 after delaying the initial chip select signal CS_n. The control / command signal receiving unit 122 receives the control / command signal C / A and outputs a first control / command signal C / A1 after delaying the control / command signal C / A1. The absolute delay of the initial chip select signal receiving unit 121 is less than the absolute delay of the control / command signal receiving unit 122. The absolute delay refers to the delay between the signal output by the initial chip select signal receiving unit 121 or the control / command signal receiving unit 122 and the received signal, thereby ensuring that the arrival time of the valid signal in the delayed second chip select signal CS_2 is earlier than the arrival time of the valid signal in the first control / command signal C / A1. The logic processing unit 123 is connected to the initial chip select signal receiving unit 121 and the control / command signal receiving unit 122. It is used to delay the second chip select signal CS_2 to obtain the third chip select signal CS_3, and obtain the first chip select signal CS_1 based on the second chip select signal CS_2 and the third chip select signal CS_3. The arrival time of the valid signal in the first chip select signal CS_1 is the same as the arrival time of the valid signal in the second chip select signal CS_2, and the end time of the valid signal in the first chip select signal CS_1 is the same as the end time of the valid signal in the third chip select signal CS_3.

[0066] In some examples, please refer to Figures 4 to 6 The initial chip select signal receiving unit 121 includes a first comparator A1. The non-inverting input of the first comparator A1 receives the initial chip select signal CS_n, the inverting input receives the first reference voltage V1, and the output outputs a second chip select signal CS_2. The second chip select signal CS_2 is high when the voltage of the initial chip select signal CS_n is greater than the first reference voltage V1, and low when the voltage of the initial chip select signal CS_n is less than the first reference voltage V1. The low-level signal in the second chip select signal CS_2 is the valid signal of the second chip select signal CS_2.

[0067] In some examples, please refer to Figures 4 to 6The control / command signal receiving unit 122 includes a second comparator A2. A control / command signal C / A is input to the non-inverting input of the second comparator A2, and a second reference voltage V2 is input to the inverting input. The output of the second comparator A2 outputs a first control / command signal C / A1. The first control / command signal C / A1 is high when the voltage of the control / command signal C / A is greater than the second reference voltage V2, and low when the voltage of the control / command signal C / A is less than the second reference voltage V2. The first reference voltage V1 and the second reference voltage V2 can be equal.

[0068] In some examples, please refer to Figures 4 to 6 The logic processing unit 123 includes a third comparator A3, a flip-flop A4, and an AND gate A5. The non-inverting input of the third comparator A3 is used to receive a first clock signal CKT, and the inverting input of the third comparator A3 is used to receive a second clock signal CKB. The third comparator A3 is used to compare the first clock signal CKT and the second clock signal CKB to output a clock pulse signal CLK. The first clock signal CKT and the second clock signal CKB can be differential forms of the same clock.

[0069] The first input of flip-flop A4 is connected to the output of the initial chip select signal receiving unit 121 to receive the second chip select signal CS_2. The second input of flip-flop A4 is connected to the third comparator A3 to receive the clock pulse signal CLK. Flip-flop A4 is used to delay the second chip select signal CS_2 according to the clock pulse signal CLK to obtain the third chip select signal CS_3. The delay time can be configured according to actual needs.

[0070] The first input of AND gate A5 is connected to the output of the initial chip select signal receiving unit 121 to receive the second chip select signal CS_2. The second input of AND gate A5 is connected to the output of flip-flop A4 to receive the third chip select signal CS_3. AND gate A5 is used to perform a logical AND operation on the second chip select signal CS_2 and the third chip select signal CS_3 to obtain the first chip select signal CS_1. Therefore, the arrival time of the valid signal in the first chip select signal CS_1 output by AND gate A5 is the same as the arrival time of the valid signal in the second chip select signal CS_2, and the end time of the valid signal in the first chip select signal CS_1 is the same as the end time of the valid signal in the third chip select signal CS_3.

[0071] In some examples, flip-flop A4 is a rising-edge flip-flop. The two inputs of flip-flop A4 are the second chip select signal CS_2 and the clock pulse signal CLK, respectively. The output of flip-flop A4 is the third chip select signal CS_3. Flip-flop A4 delays the second chip select signal CS_2 based on the clock pulse signal CLK, such that the arrival time of the valid signal in the output third chip select signal CS_3 is the same as the arrival time of the first rising edge of the clock pulse signal CLK after the arrival of the valid signal of the second chip select signal CS_2.

[0072] In some examples, the clock pulse signal CLK is a periodic signal. The specific delay can be configured according to the required rising edge delay time of the flip-flop A4. The valid signals for the initial chip select signal CS_n, the second chip select signal CS_2, the third chip select signal CS_3, and the first chip select signal CS_1 are all low-level signals. If the input sampling system does not receive the initial chip select signal CS_n, or if the first chip select signal CS_1 (derived from the modified initial chip select signal CS_n) is high-level, the control / command signal C / A will not be executed, even if it is received.

[0073] In some examples, please refer to Figures 4 to 6 The input sampling module 13 includes an input signal acquisition unit 131 and an input sampling unit 132. The first input terminal of the input signal acquisition unit 131 is connected to the output terminal of AND gate A5 to receive the first chip select signal CS_1. The second input terminal of the input signal acquisition unit 131 is connected to the control / command signal receiving unit 122 to receive the first control / command signal C / A1. The input signal acquisition unit 131 is used to sample the first control / command signal C / A1 during the valid signal period of the first chip select signal CS_1 to obtain the control / command input signal C / A1 Input.

[0074] The first input terminal of the input sampling unit 132 is connected to the output terminal of the input signal acquisition unit 131 to receive the control / command input signal C / A1 Input. The second input terminal of the input sampling unit 132 is connected to the output terminal of the third comparator A3 to receive the clock pulse signal CLK. The input sampling unit 132 is used to sample the control / command input signal C / A1 Input based on the clock pulse signal CLK to obtain the control / command output signal C / A1 Output.

[0075] In some examples, please refer to Figures 4 to 6 The input signal acquisition unit 131 includes NOT gates and NOR gates. Figure 6The NOT gate and NOR gate are drawn together (denoted as A6). The input of the NOT gate is connected to the control / command signal receiving unit 122 to receive the first control / command signal C / A1. The NOT gate is used to invert the first control / command signal C / A1 to obtain the second control / command signal. The first input of the NOR gate is connected to the output of the AND gate to receive the first chip select signal CS_1. The second input of the NOR gate is connected to the output of the NOT gate to receive the second control / command signal. The NOR gate is used to perform a logical OR-NOT operation on the second control / command signal and the first chip select signal CS_1 to obtain the control / command input signal C / A1 Input.

[0076] In some examples, please refer to Figures 4 to 6 The input sampling unit 132 may include a latch A7. The first input terminal of the latch A7 is connected to a NOR gate to obtain the control / command input signal C / A1Input output by A6, and is connected to a comparator A3 to obtain its output clock pulse signal CLK. The latch A7 is used to sample the control / command input signal C / A1Input based on the clock pulse signal CLK to obtain the control / command output signal C / A1Output.

[0077] This application also provides an input sampling method. Please refer to [link / reference]. Figure 7 Input sampling methods include:

[0078] Step S51: Obtain the initial chip select signal and control / command signal.

[0079] Step S52: Widen the pulse width of the valid signal in the initial chip select signal to obtain the first chip select signal, so as to control the end time of the valid signal in the first chip select signal to be later than the end time of the valid signal in the control / command signal.

[0080] Step S53: Obtain the clock pulse signal.

[0081] Step S54: Sample the control / command signal based on the first chip select signal and the clock pulse signal.

[0082] It should be understood that, although Figure 7 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 7At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0083] In some examples, the input sampling method further includes issuing an initial chip select signal and a control / command signal, with the initial chip select signal being issued earlier than the control / command signal, so that the arrival time of the valid signal in the initial chip select signal is earlier than the arrival time of the valid signal in the control / command signal.

[0084] In some examples, the input sampling method also includes forward widening of the pulse width of the valid signal in the initial chip select signal to control the arrival time of the valid signal in the first chip select signal to be earlier than the arrival time of the valid signal in the control / command signal.

[0085] In some examples, step S52 includes delaying the initial chip select signal and outputting a second chip select signal; delaying the control / command signal and outputting a first control / command signal, wherein the absolute delay of the initial chip select signal is less than the absolute delay of the control / command signal; delaying the second chip select signal to obtain a third chip select signal, and obtaining a first chip select signal based on the second and third chip select signals, wherein the arrival time of the valid signal in the first chip select signal is the same as the arrival time of the valid signal in the second chip select signal, and the end time of the valid signal in the first chip select signal is the same as the end time of the valid signal in the third chip select signal.

[0086] In some examples, the second chip select signal is a high-level signal when the voltage of the initial chip select signal is greater than the first reference voltage and a low-level signal when the voltage of the initial chip select signal is less than the first reference voltage. The low-level signal in the second chip select signal is the valid signal of the second chip select signal.

[0087] In some examples, the first control / command signal is a high-level signal when the voltage of the control / command signal is greater than the second reference voltage, and a low-level signal when the voltage of the control / command signal is less than the second reference voltage.

[0088] In some examples, the second chip select signal is delayed to obtain the third chip select signal, and the first chip select signal is obtained based on the second chip select signal and the third chip select signal, including delaying the second chip select signal based on a clock pulse signal to obtain the third chip select signal; and performing a logical AND operation on the second chip select signal and the third chip select signal to obtain the first chip select signal.

[0089] In some examples, the arrival time of the valid signal in the third chip select signal is the same as the arrival time of the first rising edge of the clock pulse signal after the arrival of the valid signal in the second chip select signal.

[0090] In some examples, the clock pulse signal is a periodic signal, and the valid signals of the initial chip select signal, the second chip select signal, the third chip select signal, and the first chip select signal are all low-level signals.

[0091] In some examples, step S53 includes receiving a first clock signal and a second clock signal, comparing the first clock signal and the second clock signal to output a clock pulse signal. Step S54 includes sampling a first control / command signal during the active signal period of the first chip select signal to obtain a control / command input signal; and sampling the control / command input signal based on the clock pulse signal to obtain a control / command output signal.

[0092] In some examples, during the active signal period of the first chip select signal, the first control / command signal is sampled to obtain the control / command input signal, including inverting the first control / command signal to obtain the second control / command signal; and performing a logical OR-NOT operation on the second control / command signal and the first chip select signal to obtain the control / command input signal.

[0093] The input signal sampling system can also perform any step of the input signal sampling method described above. Specific limitations of the input signal sampling system can be found in the limitations of the input signal sampling method above, and will not be repeated here. Each module in the above input signal sampling system can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in or independent of the processor in the computer device in hardware form, or stored in the memory of the computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0094] This application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the method as described in any one of the above.

[0095] This application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described in any of the preceding claims.

[0096] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0097] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. An input sampling system, characterized in that, include: The signal processing module is used to receive an initial chip select signal and a control / command signal, and then widen the pulse width of the valid signal in the initial chip select signal to obtain a first chip select signal, so as to control the end time of the valid signal in the first chip select signal to be later than the end time of the valid signal in the control / command signal; An input sampling module, connected to the signal processing module, is used to receive the control / command signal, the first chip select signal, and the clock pulse signal, and to sample the control / command signal according to the first chip select signal and the clock pulse signal; The signal processing module is further configured to extend the pulse width of the valid signal in the initial chip select signal forward, so as to control the arrival time of the valid signal in the first chip select signal to be earlier than the arrival time of the valid signal in the control / command signal.

2. The input sampling system according to claim 1, characterized in that, The signal processing module includes: An initial chip select signal receiving unit is configured to receive the initial chip select signal and output a second chip select signal after delaying the initial chip select signal. A control / command signal receiving unit is configured to receive the control / command signal and output a first control / command signal after delaying the control / command signal. The absolute delay of the initial chip select signal receiving unit is less than the absolute delay of the control / command signal receiving unit. A logic processing unit, connected to the initial chip select signal receiving unit and the control / command signal receiving unit, is used to delay the second chip select signal to obtain a third chip select signal, and to obtain the first chip select signal based on the second chip select signal and the third chip select signal. The arrival time of the valid signal in the first chip select signal is the same as the arrival time of the valid signal in the second chip select signal, and the end time of the valid signal in the first chip select signal is the same as the end time of the valid signal in the third chip select signal.

3. The input sampling system according to claim 2, characterized in that, The initial chip select signal receiving unit includes a first comparator. The initial chip select signal is input to the non-inverting input terminal of the first comparator, a first reference voltage is input to the inverting input terminal of the first comparator, and a second chip select signal is output from the output terminal of the first comparator. The second chip select signal is a high-level signal when the voltage of the initial chip select signal is greater than the first reference voltage, and a low-level signal when the voltage of the initial chip select signal is less than the first reference voltage. The low-level signal in the second chip select signal is the valid signal of the second chip select signal.

4. The input sampling system according to claim 2, characterized in that, The control / command signal receiving unit includes a second comparator. The control / command signal is input to the non-inverting input terminal of the second comparator, a second reference voltage is input to the inverting input terminal of the second comparator, and the first control / command signal is output to the output terminal of the second comparator. The first control / command signal is a high-level signal when the voltage of the control / command signal is greater than the second reference voltage, and a low-level signal when the voltage of the control / command signal is less than the second reference voltage.

5. The input sampling system according to claim 2, characterized in that, The logic processing unit includes: The third comparator has a non-inverting input terminal for receiving a first clock signal and an inverting input terminal for receiving a second clock signal. The third comparator is used to compare the first clock signal and the second clock signal to output a clock pulse signal. A trigger, wherein the first input terminal of the trigger is connected to the output terminal of the initial chip select signal receiving unit to receive the second chip select signal, and the second input terminal of the trigger is connected to the third comparator to receive the clock pulse signal, and the trigger is used to delay the second chip select signal according to the clock pulse signal to obtain the third chip select signal; An AND gate is used to receive the second chip select signal by connecting its first input to the output of the initial chip select signal receiving unit and the third chip select signal by connecting its second input to the output of the flip-flop. The AND gate is used to perform a logical AND operation on the second chip select signal and the third chip select signal to obtain the first chip select signal.

6. The input sampling system according to claim 5, characterized in that, The trigger is a rising edge trigger, and the arrival time of the valid signal in the third chip select signal output by the rising edge trigger is the same as the arrival time of the first rising edge of the clock pulse signal after the arrival of the valid signal of the second chip select signal.

7. The input sampling system according to claim 5, characterized in that, The clock pulse signal is a periodic signal, and the effective signals of the initial chip select signal, the second chip select signal, the third chip select signal, and the first chip select signal are all low-level signals.

8. The input sampling system according to claim 5, characterized in that, The input sampling module includes: An input signal acquisition unit is provided, wherein a first input terminal of the input signal acquisition unit is connected to the output terminal of the AND gate to receive the first chip select signal, and a second input terminal of the input signal acquisition unit is connected to the control / command signal receiving unit to receive the first control / command signal. The input signal acquisition unit is used to sample the first control / command signal during the valid signal period of the first chip select signal to obtain a control / command input signal. An input sampling unit is provided, wherein a first input terminal of the input sampling unit is connected to the output terminal of the input signal acquisition unit to receive the control / command input signal, and a second input terminal of the input sampling unit is connected to the output terminal of the third comparator to receive the clock pulse signal. The input sampling unit is used to sample the control / command input signal based on the clock pulse signal to obtain a control / command output signal.

9. The input sampling system according to claim 8, characterized in that, The input signal acquisition unit includes: The NOT gate is connected to the control / command signal receiving unit to receive the first control / command signal. The NOT gate is used to invert the first control / command signal to obtain a second control / command signal. The NOR gate is configured such that its first input is connected to the output of the AND gate to receive the first chip select signal, and its second input is connected to the output of the NOT gate to receive the second control / command signal. The NOR gate is used to perform a logical OR-NOT operation on the second control / command signal and the first chip select signal to obtain the control / command input signal.

10. An input sampling method, characterized in that, The method includes: Obtain the initial chip select signal and control / command signals; The pulse width of the valid signal in the initial chip select signal is widened backward to obtain the first chip select signal, so as to control the end time of the valid signal in the first chip select signal to be later than the end time of the valid signal in the control / command signal, and the pulse width of the valid signal in the initial chip select signal is widened forward to control the arrival time of the valid signal in the first chip select signal to be earlier than the arrival time of the valid signal in the control / command signal. Obtain the clock pulse signal; The control / command signal is sampled based on the first chip select signal and the clock pulse signal.

11. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method of claim 10.

12. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method of claim 10.

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