SPI communication circuit
By introducing a communication module and a pull-up signal circuit into the SPI communication circuit, the problem of the traditional SPI communication circuit being either single-function or complex is solved, realizing multi-slave functionality and low-cost circuit design.
Patent Information
- Application Number
- CN202423146037.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-19
- Publication Date
- 2025-12-02
- Estimated Expiration
- 2034-12-19
Smart Images
Figure CN223624604U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of communication circuit technology, specifically to an SPI communication circuit. Background Technology
[0002] Traditional SPI communication circuits often use a single master and a single slave circuit structure, resulting in limited communication capabilities and a lack of functionality. In addition, some traditional circuit structures that use one master and multiple slaves require the installation of signal chips, which complicates the circuit structure and increases manufacturing costs. Summary of the Invention
[0003] To overcome the above-mentioned shortcomings, the purpose of this application is to provide an SPI communication circuit, thereby effectively solving the above-mentioned technical problems.
[0004] To achieve the above objectives, this application adopts the following technical solution:
[0005] This application provides an SPI communication circuit, including:
[0006] The host module includes a main chip select unit, a main signal transmitting unit, and a main signal receiving unit.
[0007] At least one first slave module includes a first chip select unit, a first signal transmitting unit, and a first signal receiving unit, wherein,
[0008] The master chip select unit is electrically connected to the first chip select unit to form a first chip select signal circuit, and the master chip select unit sends a chip select signal to the first chip select unit.
[0009] The main signal transmitting unit is electrically connected to the first signal receiving unit to form a first signal transmitting circuit, and the main signal transmitting unit transmits communication signals to the first signal receiving unit.
[0010] The first signal transmitting unit is electrically connected to the main signal receiving unit to form a first signal feedback circuit, and the first signal transmitting unit sends a feedback signal to the main signal receiving unit;
[0011] At least one second slave module includes a second chip select unit, a second signal transmitting unit, and a second signal receiving unit, wherein,
[0012] The master chip select unit and the second chip select unit are electrically connected to form a second chip select signal circuit, and the master chip select unit sends a chip select signal to the second chip select unit.
[0013] The main signal transmitting unit is electrically connected to the second signal receiving unit to form a second signal transmitting circuit, and the main signal transmitting unit transmits communication signals to the second signal receiving unit.
[0014] The second signal transmitting unit is electrically connected to the main signal receiving unit to form a second signal feedback circuit, and the second signal transmitting unit sends a feedback signal to the main signal receiving unit;
[0015] The communication module includes a first signal feedback circuit and a second signal feedback circuit electrically connected via a first connection node, the first connection node being electrically connected to the communication module, and the communication module being configured to enable either the first slave module or the second slave module to communicate with the master module.
[0016] Furthermore, the host module includes a master chip, the first slave module includes at least one first slave chip, the second slave module includes at least one second slave chip, the master signal receiving unit includes a feedback signal receiving pin disposed on the master chip, the first signal transmitting unit includes a first feedback signal transmitting pin disposed on the first slave chip, and the second signal transmitting unit includes a second feedback signal transmitting pin disposed on the second slave chip.
[0017] The communication module includes a first transistor, a second transistor pull-up power supply, and a pull-up resistor, wherein...
[0018] The first feedback signal transmitting pin on the first slave chip and the feedback signal receiving pin on the master chip form the first signal feedback circuit.
[0019] The second feedback signal transmitting pin on the second slave chip and the feedback signal receiving pin on the master chip form the second signal feedback circuit.
[0020] The first transistor is disposed on the first signal feedback circuit, the second transistor is disposed on the second signal feedback circuit, the pull-up power supply and the pull-up resistor form a pull-up circuit, and the pull-up circuit is electrically connected to the first connection node connected to the first signal feedback circuit and the second signal feedback circuit.
[0021] Furthermore, the main chip select unit includes at least one chip select signal transmission pin one and at least one chip select signal transmission pin two disposed on the main chip, and the main signal transmission unit includes a main signal transmission pin disposed on the main chip.
[0022] The first chip select unit includes a first chip select signal receiving pin disposed on the first slave chip, and the first signal receiving unit includes a first signal receiving pin disposed on the first slave chip, wherein,
[0023] The chip select signal transmitting pin on the master chip is electrically connected to the first chip select signal receiving pin on the first slave chip, and the master signal transmitting pin on the master chip is electrically connected to the first signal receiving pin on the first slave chip.
[0024] Furthermore, the second chip select unit includes a second chip select signal receiving pin disposed on the second slave chip, and the second signal receiving unit includes a second signal receiving pin disposed on the second slave chip, wherein,
[0025] The chip select signal transmitting pin 2 on the master chip is electrically connected to the second chip select signal receiving pin on the second slave chip, and the master signal transmitting pin on the master chip is electrically connected to the second signal receiving pin on the second slave chip.
[0026] Furthermore, a second connection node is provided on the circuit where the chip select signal transmitting pin on the master chip is connected to the first chip select signal receiving pin on the first slave chip, and the second chip select signal receiving pin on the second slave chip is electrically connected to the second connection node.
[0027] Furthermore, the master chip also includes a clock signal transmitting pin, and the first slave chip includes a first clock signal receiving pin. The clock signal transmitting pin of the master chip is electrically connected to the first clock signal receiving pin of the first slave chip so that the master chip can transmit a clock signal to the first slave chip.
[0028] Furthermore, the second slave chip includes a second clock signal receiving pin, and the clock signal transmitting pin of the master chip is electrically connected to the second clock signal receiving pin of the second slave chip so that the master chip sends a clock signal to the second slave chip.
[0029] Furthermore, a third connection node is provided on the circuit connecting the clock signal transmitting pin of the master chip and the first clock signal receiving pin of the first slave chip, and the second clock signal receiving pin of the second slave chip is electrically connected to the third connection node.
[0030] Beneficial effects
[0031] This application provides an SPI communication circuit in which a communication module is set on the feedback circuit connecting the slave module and the master module. The master module can select one of the multiple slave modules to communicate through the communication module, realizing the one master and multiple slave functions in the SPI communication circuit. In addition, the communication module adopts a pull-up signal circuit structure composed of a transistor, a resistor and a power supply, which eliminates the need for additional chips, resulting in a simple structure and low manufacturing cost. Attached Figure Description
[0032] The accompanying drawings are provided to illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shapes and sizes of the components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this application.
[0033] Figure 1 This is a schematic diagram of the SPI communication circuit module of this application.
[0034] Figure 2 This is a schematic diagram of the SPI communication circuit structure in one embodiment of this application.
[0035] Figure 3 The equivalent circuit of the SPI communication circuit in one embodiment of this application. Figure 1 .
[0036] Figure 4 The equivalent circuit of the SPI communication circuit in one embodiment of this application. Figure 2 . Detailed Implementation
[0037] The above-described solution will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of this application. The implementation conditions used in the embodiments may be further adjusted according to the conditions of specific manufacturers, and the implementation conditions not specified are generally those in routine experiments.
[0038] Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the element or object listed following the word and its equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. In this document, "electrical connection" includes the situation where constituent elements are connected together by an element having some electrical function. There is no particular limitation on the "electrically functioning element," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. An "electrically functioning element" can be, for example, an electrode or wiring, a switching element such as a transistor, or other functional elements such as a resistor, inductor, or capacitor. "Up," "down," "left," and "right" are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.
[0039] In this application, the terms "upper," "lower," "inner," "middle," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for the purpose of better describing this application and its embodiments, and are not intended to limit the indicated device, element, or component to having a specific orientation, or to be constructed and operated in a specific orientation.
[0040] As described in the background section, traditional SPI communication circuits often use a circuit structure with only one master and one slave. Even with one master and multiple slaves, there are still problems such as complex circuit structure and high manufacturing cost.
[0041] In response to the above, the inventor provides an SPI communication circuit, such as... Figure 1 As shown, the SPI communication circuit includes a master module, which comprises a master chip select unit, a master signal transmitting unit, and a master signal receiving unit.
[0042] The SPI communication circuit also includes at least one first slave module. The first slave module includes a first chip select unit, a first signal transmitting unit, and a first signal receiving unit. The master chip select unit is electrically connected to the first chip select unit to form a first chip select signal circuit. The master chip select unit sends a chip select signal to the first chip select unit. The master signal transmitting unit is electrically connected to the first signal receiving unit to form a first signal transmitting circuit. The master signal transmitting unit sends a communication signal to the first signal receiving unit. The first signal transmitting unit is electrically connected to the master signal receiving unit to form a first signal feedback circuit. The first signal transmitting unit sends a feedback signal to the master signal receiving unit.
[0043] The SPI communication circuit also includes at least one second slave module. The second slave module includes a second chip select unit, a second signal transmitting unit, and a second signal receiving unit. The master chip select unit is electrically connected to the second chip select unit to form a second chip select signal circuit. The master chip select unit sends a chip select signal to the second chip select unit. The master signal transmitting unit is electrically connected to the second signal receiving unit to form a second signal transmitting circuit. The master signal transmitting unit sends a communication signal to the second signal receiving unit. The second signal transmitting unit is electrically connected to the master signal receiving unit to form a second signal feedback circuit. The second signal transmitting unit sends a feedback signal to the master signal receiving unit.
[0044] The SPI communication circuit also includes a communication module. The first signal feedback circuit and the second signal feedback circuit are electrically connected through a first connection node. The first connection node is electrically connected to the communication module. The communication module is configured to enable the first slave module or the second slave module to communicate with the master module.
[0045] This solution sets up a communication module on the feedback circuit connecting the slave module and the master module. The communication module enables the master module to select one of the multiple slave modules to communicate with, realizing the one master and multiple slave functions in the SPI communication circuit. In addition, the communication module adopts a pull-up signal circuit structure composed of a transistor, a resistor and a power supply, which eliminates the need for additional chips, resulting in a simple structure and low manufacturing cost.
[0046] Next, in conjunction with the appendix Figure 2-4 This application is described by way of example.
[0047] One embodiment of this application provides an SPI communication circuit, such as... Figure 2 As shown, the SPI communication circuit includes a master chip U1, a first slave chip U2, and a second slave chip U3.
[0048] The main chip U1 includes chip select signal transmission pin 1 (CS1), chip select signal transmission pin 2 (CS2), clock signal transmission pin (CLK-1), main signal transmission pin (MOS I-1), and feedback signal reception pin (MI SO-1).
[0049] The first slave chip U2 includes a first chip select signal receiving pin (CS-2), a first signal receiving pin (MOS I-2), a first clock signal receiving pin (CLK-2), and a first feedback signal transmitting pin (MI SO-2).
[0050] The second slave chip U3 includes a second chip select signal receiving pin (CS-3), a second signal receiving pin (MOS I-3), a second clock signal receiving pin (CLK-3), and a second feedback signal transmitting pin (MI SO-3).
[0051] It should be noted that the slave chips in this application include U2 and U3, but are not limited to only U2 and U3; there may be more slave chips.
[0052] The communication module includes a first transistor D1, a second transistor D2, and a pull-up signal circuit consisting of a power supply V and a resistor R. The specific connection structure of the SPI circuit is as follows:
[0053] The CS1 pin of the master chip U1 is electrically connected to the CS-2 pin of the slave chip U2. The CLK-1 pin of the master chip U1 is electrically connected to the CLK-2 pin of the slave chip U2. The MOS I-1 pin of the master chip U1 is electrically connected to the MOS I-2 pin of the slave chip U2. The MI SO-2 pin of the slave chip U2 is electrically connected to the MI SO-1 pin of the master chip U1.
[0054] The CS2 pin of the master chip U1 is electrically connected to the CS-3 pin of the slave chip U3. The CLK-1 pin of the master chip U1 is connected to the CLK-3 pin of the slave chip U3. The MOS I-1 pin of the master chip U1 is connected to the MOS I-3 pin of the slave chip U3. The MI SO-3 pin of the slave chip U3 is connected to the MI SO-1 pin of the master chip U1.
[0055] In some embodiments, the circuit connecting pin MISO-2 of chip U2 to pin MISO-1 of main chip U1 is a first signal feedback circuit, and the circuit connecting pin MISO-3 of chip U3 to pin MISO-1 of main chip U1 is a second signal feedback circuit. There is a connection node A between the first signal feedback circuit and the second signal feedback circuit. The first transistor D1 is disposed on the first signal feedback circuit, the second transistor D2 is disposed on the second signal feedback circuit, and the pull-up signal circuit composed of power supply V and resistor R is electrically connected to node A.
[0056] In some embodiments, a connection node B is provided on the circuit connecting pin MOSI-1 of the master chip U1 and pin MOSI-2 of the slave chip U2, and MOSI-3 of the slave chip U3 is electrically connected to node B. A connection node C is provided on the circuit connecting pin CLK-1 of the master chip U1 and pin CLK-2 of the slave chip U2, and CLK-3 of the slave chip U3 is electrically connected to node C.
[0057] The principle of the above SPI communication circuit is as follows:
[0058] like Figure 3 As shown, when the master chip U1 communicates with the slave chip U2, the master chip U1's pin CS1 sends a chip select signal to the slave chip U2's pin CS-2, the master chip U1's pin CLK-1 sends a clock signal to the slave chip U2's pin CLK-2, and the master chip U1's pin MOSI-1 sends a communication signal to the slave chip U2's pin MOS I-2. After receiving the signal, the slave chip U2 sends a low-level feedback signal through its pin MISO-2. The first signal feedback circuit receives the low-level feedback signal, the pull-up signal circuit is pulled low, and the voltage drop of the Schottky diode D1 drops to the range of 0.2V to 0.5V. The master chip U1's pin MISO-1 receives the low-level signal and establishes communication with the slave chip U2. Here, the master chip U1 does not communicate with the slave chip U3. The slave chip U3's pin MISO-3 outputs a high level or no output, and the second signal feedback circuit outputs a high level or no output.
[0059] like Figure 4As shown, when the master chip U1 communicates with the slave chip U3, the master chip U1's pin CS1 sends a chip select signal to the slave chip U3's pin CS-3, the master chip U1's pin CLK-1 sends a clock signal to the slave chip U3's pin CLK-3, and the master chip U1's pin MOSI-1 sends a communication signal to the slave chip U3's pin MOS I-3. After receiving the signal, the slave chip U3 sends a low-level feedback signal through its pin MI SO-3. The second signal feedback circuit inputs a low-level feedback signal, the pull-up signal circuit is pulled low, the Schottky diode D2 voltage drops, and the master chip U1's pin MI SO-1 receives the low-level signal and establishes communication with the slave chip U3.
[0060] The above embodiments are only for illustrating the technical concept and features of this application, and are intended to enable those skilled in the art to understand the content of this application and implement it accordingly. They should not be used to limit the scope of protection of this application. All equivalent changes or modifications made in accordance with the spirit and essence of this application should be included within the scope of protection of this application.
Claims
1. An SPI communication circuit, characterized in that: include: The host module includes a main chip select unit, a main signal transmitting unit, and a main signal receiving unit. At least one first slave module includes a first chip select unit, a first signal transmitting unit, and a first signal receiving unit, wherein, The master chip select unit is electrically connected to the first chip select unit to form a first chip select signal circuit, and the master chip select unit sends a chip select signal to the first chip select unit. The main signal transmitting unit is electrically connected to the first signal receiving unit to form a first signal transmitting circuit, and the main signal transmitting unit transmits communication signals to the first signal receiving unit. The first signal transmitting unit is electrically connected to the main signal receiving unit to form a first signal feedback circuit, and the first signal transmitting unit sends a feedback signal to the main signal receiving unit; At least one second slave module includes a second chip select unit, a second signal transmitting unit, and a second signal receiving unit, wherein, The master chip select unit and the second chip select unit are electrically connected to form a second chip select signal circuit, and the master chip select unit sends a chip select signal to the second chip select unit. The main signal transmitting unit is electrically connected to the second signal receiving unit to form a second signal transmitting circuit, and the main signal transmitting unit transmits communication signals to the second signal receiving unit. The second signal transmitting unit is electrically connected to the main signal receiving unit to form a second signal feedback circuit, and the second signal transmitting unit sends a feedback signal to the main signal receiving unit; The communication module includes a first signal feedback circuit and a second signal feedback circuit electrically connected via a first connection node, the first connection node being electrically connected to the communication module, and the communication module being configured to enable either the first slave module or the second slave module to communicate with the master module.
2. The SPI communication circuit as described in claim 1, characterized in that: The host module includes a master chip, the first slave module includes at least one first slave chip, the second slave module includes at least one second slave chip, the master signal receiving unit includes a feedback signal receiving pin disposed on the master chip, the first signal transmitting unit includes a first feedback signal transmitting pin disposed on the first slave chip, and the second signal transmitting unit includes a second feedback signal transmitting pin disposed on the second slave chip. The communication module includes a first transistor, a second transistor pull-up power supply, and a pull-up resistor, wherein... The first feedback signal transmitting pin on the first slave chip and the feedback signal receiving pin on the master chip form the first signal feedback circuit. The second feedback signal transmitting pin on the second slave chip and the feedback signal receiving pin on the master chip form the second signal feedback circuit. The first transistor is disposed on the first signal feedback circuit, the second transistor is disposed on the second signal feedback circuit, the pull-up power supply and the pull-up resistor form a pull-up circuit, and the pull-up circuit is electrically connected to the first connection node connected to the first signal feedback circuit and the second signal feedback circuit.
3. The SPI communication circuit as described in claim 2, characterized in that: The main chip select unit includes at least one chip select signal transmission pin 1 and at least one chip select signal transmission pin 2 disposed on the main chip, and the main signal transmission unit includes a main signal transmission pin disposed on the main chip. The first chip select unit includes a first chip select signal receiving pin disposed on the first slave chip, and the first signal receiving unit includes a first signal receiving pin disposed on the first slave chip, wherein, The chip select signal transmitting pin on the master chip is electrically connected to the first chip select signal receiving pin on the first slave chip, and the master signal transmitting pin on the master chip is electrically connected to the first signal receiving pin on the first slave chip.
4. The SPI communication circuit as described in claim 3, characterized in that: The second chip select unit includes a second chip select signal receiving pin disposed on the second slave chip, and the second signal receiving unit includes a second signal receiving pin disposed on the second slave chip, wherein, The chip select signal transmitting pin 2 on the master chip is electrically connected to the second chip select signal receiving pin on the second slave chip, and the master signal transmitting pin on the master chip is electrically connected to the second signal receiving pin on the second slave chip.
5. The SPI communication circuit as described in claim 4, characterized in that: A second connection node is provided on the circuit where the chip select signal transmitting pin on the master chip is connected to the first chip select signal receiving pin on the first slave chip, and the second chip select signal receiving pin on the second slave chip is electrically connected to the second connection node.
6. The SPI communication circuit as described in claim 2, characterized in that: The master chip further includes a clock signal transmitting pin, and the first slave chip includes a first clock signal receiving pin. The clock signal transmitting pin of the master chip is electrically connected to the first clock signal receiving pin of the first slave chip so that the master chip can transmit a clock signal to the first slave chip.
7. The SPI communication circuit as described in claim 6, characterized in that: The second slave chip includes a second clock signal receiving pin, and the clock signal transmitting pin of the master chip is electrically connected to the second clock signal receiving pin of the second slave chip so that the master chip can send a clock signal to the second slave chip.
8. The SPI communication circuit as described in claim 7, characterized in that: A third connection node is provided on the circuit connecting the clock signal transmitting pin of the master chip and the first clock signal receiving pin of the first slave chip, and the second clock signal receiving pin of the second slave chip is electrically connected to the third connection node.