Slew rate control circuit

Abstract

The present invention discloses a slew rate control circuit, comprising a slew rate control unit, a capacitor delay unit, a delay unit, a first output unit, a second output unit, and a third output unit. The slew rate control unit is configured to receive multiple control signals. The capacitor delay unit is coupled to the slew rate control unit and receives an input signal. The delay unit is coupled to the capacitor delay unit. The first output unit and the second output unit are coupled to the capacitor delay unit. The third output unit is coupled to the delay unit. The output signal of the first output unit is a signal that has not undergone slew rate control. The output signal of the second output unit is a signal whose slew rate is controlled by the capacitor delay unit. The output signal of the third output unit is a signal whose slew rate is controlled by both the capacitor delay unit and the delay unit.

Description

Technical Field

[0001] The present invention relates to a slew rate control circuit, and more particularly to a slew rate control circuit capable of providing stable performance and duty cycle. Background Art

[0002] With the rapid advancement of technology, various volatile and non-volatile memory types have been incorporated into computer systems. Dynamic Random Access Memory (DRAM) is a type of semiconductor memory that falls under the volatile category. Its primary function is to use the amount of charge stored in a capacitor to represent a binary bit as a 1 or 0. DRAM is a short-term data storage area in a computer system, storing information currently in use for quick access.

[0003] DRAM can provide high-speed transmission and high bandwidth utilization. However, high-speed transmission and high bandwidth utilization will cause electromagnetic interference (EMI). The interference of EMI will affect performance. The common way to solve the EMI problem is to control the slew rate. In the output buffer circuit of traditional DRAM, the slew rate can be adjusted. The larger the slew rate, the greater the maximum rate of change of the output voltage per unit time, and the faster the capacitor charges.

[0004] Conversely, the smaller the slew rate, the smaller the maximum rate of change of the output voltage per unit time, and the slower the capacitor charging speed. However, traditional slew rate control circuits can cause performance fluctuations (Performance Disturbance) when outputting data caches.

[0005] Therefore, developing a slew rate control circuit to control the slew rate and maintain the signal duty cycle with almost no performance fluctuation is an important design issue. Summary of the Invention

[0006] This embodiment provides a slew rate control circuit. The slew rate control circuit includes a slew rate control unit, a capacitor delay unit, a delay unit, a first output unit, a second output unit, and a third output unit. The slew rate control unit includes a first input terminal for receiving a first control signal, a second input terminal for receiving a second control signal, a third input terminal for receiving a third control signal, and an output terminal for outputting a plurality of control voltages. The capacitor delay unit includes an output terminal, a first input terminal coupled to the output terminal of the slew rate control unit, and a second input terminal for receiving an input signal. The delay unit includes an output terminal and an input terminal coupled to the output terminal of the capacitor delay unit. The first output unit includes an input terminal coupled to the second input terminal of the capacitor delay unit for receiving an input signal, a first output terminal for outputting a first output signal, and a second output terminal for outputting a second output signal. The second output unit includes a first input terminal coupled to the output terminal of the capacitor delay unit for receiving the output signal of the capacitor delay unit, a second input terminal for receiving the second control signal, and an output terminal for outputting a third output signal. The third output unit includes a first input terminal coupled to the output terminal of the delay unit for receiving the output signal of the delay unit, a second input terminal for receiving the third control signal, and an output terminal for outputting a fourth output signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram of an embodiment of a slew rate control circuit of the present invention.

[0008] Figure 2 yes Figure 1 The architecture diagram of the slew rate control unit in the slew rate control circuit.

[0009] Figure 3 yes Figure 1 Schematic diagram of the capacitor delay unit in the slew rate control circuit.

[0010] Figure 4 yes Figure 1 Architectural diagram of the delay unit in the slew rate control circuit.

[0011] Figure 5 yes Figure 1 Schematic diagram of the first output unit in the slew rate control circuit.

[0012] Figure 6 yes Figure 1 Schematic diagram of the second output unit in the slew rate control circuit.

[0013] Figure 7 yes Figure 1 Schematic diagram of the third output unit in the slew rate control circuit.

[0014] Figure 8 yes Figure 1 Schematic diagram of waveforms of the third output signal and the fourth output signal in the slew rate control circuit.

[0015] The description of the accompanying drawings is as follows:

[0016] 100 Slew rate control circuit

[0017] DOIN input signal

[0018] CAPONT First control signal

[0019] MRS_SR1 second control signal

[0020] MRS_SR2 third control signal

[0021] A1, B1, A2, B2 control voltage

[0022] DOUT1 first output signal

[0023] DOUT2 Second output signal

[0024] DOUT3 third output signal

[0025] DOUT4 fourth output signal

[0026] 10 Slew rate control unit

[0027] 11 Capacitor delay unit

[0028] 12 Delay Units

[0029] 13 First output unit

[0030] 14 Second output unit

[0031] 15 Third output unit

[0032] INV1 first inverter

[0033] INV2 Second inverter

[0034] INV3 third inverter

[0035] INV4 Fourth inverter

[0036] INV5 Fifth Inverter

[0037] INV6 Sixth inverter

[0038] INV7 Seventh Inverter

[0039] INV8 Eighth Inverter

[0040] INV9 Ninth Inverter

[0041] INV10 tenth inverter

[0042] INV11 Eleventh Inverter

[0043] NOR1 First NOR gate

[0044] NOR2 Second NOR gate

[0045] NOR3 third NOR gate

[0046] C1 first capacitor

[0047] C2 Second capacitor

[0048] C3 third capacitor

[0049] C4 fourth capacitor

[0050] 12b Inverter

[0051] NAND1 first NAND gate

[0052] NAND2 second NAND gate

[0053] NAND3 third NAND gate

[0054] 11a, 12a, 13a, 14a, 15a input terminals

[0055] 11b, 12c output terminals DETAILED DESCRIPTION

[0056] Figure 1This is a block diagram of an embodiment of a slew rate control circuit 100. The purpose of the slew rate control circuit 100 is to control the slew rate and maintain the signal duty cycle, thereby reducing performance disturbance. The slew rate control circuit 100 is described below. The slew rate control circuit 100 includes a slew rate control unit 10, a capacitor delay unit 11, a delay unit 12, a first output unit 13, a second output unit 14, and a third output unit 15. The slew rate control unit 10 includes a first input terminal, a second input terminal, a third input terminal, and an output terminal. The first input terminal of the slew rate control unit 10 is used to receive a first control signal CAPONT. The second input terminal of the slew rate control unit 10 is used to receive a second control signal MRS_SR1. The third input terminal of the slew rate control unit 10 is used to receive a third control signal MRS_SR2. The output terminal of the slew rate control unit 10 is used to output a plurality of control voltages A1, B1, A2, and B2. The capacitor delay unit 11 includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the capacitor delay unit 11 is coupled to the output terminal of the slew rate control unit 10 for receiving the multiple control voltages A1, B1, A2, and B2 output by the slew rate control unit 10. The second input terminal of the capacitor delay unit 11 is used to receive the input signal DOIN. The delay unit 12 includes an input terminal and an output terminal. The input terminal of the delay unit 12 is coupled to the output terminal of the capacitor delay unit 11. The first output unit 13 includes an input terminal, a first output terminal, and a second output terminal. The input terminal of the first output unit 13 is coupled to the second input terminal of the capacitor delay unit 11 for receiving the input signal DOIN. The first output terminal of the first output unit 13 is used to output a first output signal DOUT1. The second output terminal of the first output unit 13 is used to output a second output signal DOUT2. The second output unit 14 includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the second output unit 14 is coupled to the output terminal of the capacitor delay unit 11 for receiving the output signal of the capacitor delay unit 11. The second input terminal of the second output unit 14 is used to receive the second control signal MRS_SR1. The output terminal of the second output unit 14 is used to output the third output signal DOUT3. The third output unit 15 includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the third output unit 15 is coupled to the output terminal of the delay unit 12 and is used to receive the output signal of the delay unit 12. The second input terminal of the third output unit 15 is used to receive the third control signal MRS_SR2. The output terminal of the third output unit 15 is used to output the fourth output signal DOUT4. In the slew rate control circuit 100, the first output signal DOUT1 and the second output signal DOUT2 output by the first output unit 13 are two signals that are not slew rate controlled.The third output signal DOUT3 output by the second output unit 14 is a signal whose slew rate is controlled via the capacitor delay unit 11. The fourth output signal DOUT4 output by the third output unit 15 is a signal whose slew rate is controlled via the capacitor delay unit 11 and the delay unit 12. In other words, the slew rate control circuit 100 of the present invention can provide signals for controlling slew rates in various modes. Furthermore, the slew rate control circuit 100 can maintain the signal duty cycle while optimizing slew rate control. The circuit details of the slew rate control circuit 100 will be described in detail below.

[0057] Figure 21 is a block diagram of the slew rate control unit 10 in the slew rate control circuit 100. The slew rate control unit 10 includes a first inverter INV1, a first NOR gate NOR1, a second NOR gate NOR2, a second inverter INV2, a third inverter INV3, a first NAND gate NAND1, a third NOR gate NOR3, and a fourth inverter INV4. The first inverter INV1 includes an input and an output. The input of the first inverter INV1 is used to receive the first control signal CAPONT. The first NOR gate NOR1 includes a first input, a second input, and an output. The first input of the first NOR gate NOR1 is used to receive the second control signal MRS_SR1. The second input of the first NOR gate NOR1 is used to receive the third control signal MRS_SR2. The second NOR gate NOR2 includes a first input, a second input, and an output. The first input of the second NOR gate NOR2 is coupled to the output of the first inverter INV1. The second input terminal of the second NOR gate NOR2 is coupled to the output terminal of the first NOR gate NOR1. The second inverter INV2 includes an input terminal and an output terminal. The input terminal of the second inverter INV2 is coupled to the output terminal of the second NOR gate NOR2. Furthermore, the output terminal of the second NOR gate NOR2 can output a control voltage A1. The output terminal of the second inverter INV2 can output a control voltage B1. The phases of the control voltages A1 and B1 are opposite. The third inverter INV3 includes an input terminal and an output terminal. The input terminal of the third inverter INV3 is used to receive the first control signal CAPONT. The first NAND gate NAND1 includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the first NAND gate NAND1 is used to receive the second control signal MRS_SR1. The second input terminal of the first NAND gate NAND1 is used to receive the third control signal MRS_SR2. The third NOR gate NOR3 includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the third NOR gate NOR3 is coupled to the output terminal of the third inverter INV3. The second input terminal of the third NOR gate NOR3 is coupled to the output terminal of the first NAND gate NAND1. The fourth inverter INV4 includes an input terminal and an output terminal. The input terminal of the fourth inverter INV is coupled to the output terminal of the third NOR gate NOR3. In addition, the output terminal of the third NOR gate NOR3 can output the control voltage A2. The output terminal of the fourth inverter INV4 can output the control voltage B2. The phases of the control voltage A2 and the control voltage B2 are opposite. In the slew rate control unit 10, the inputs are the first control signal CAPONT, the second control signal MRS_SR1, and the third control signal MRS_SR2. The outputs are the control voltage A1, the control voltage B1, the control voltage A2, and the control voltage B1. The relationship between the input and output signals of the slew rate control unit 10 can be expressed as follows.

[0058] CAPONT MRS_SR1 MRS_SR2 A1 B1 L L L L H L L H L H L H L L H L H H L H H L L L H H L H H L H H L H L H H H H L

[0059] Table 1

[0060] CAPONT MRS_SR1 MRS_SR2 A2 B2 L L L L H L L H L H L H L L H L H H L H H L L L H H L H L H H H L L H H H H H L

[0061] Table 2

[0062] Where "L" represents a low voltage, and "H" represents a high voltage. According to the architecture of the slew rate control unit 10 and Tables 1 and 2, when the first control signal CAPONT, the second control signal MRS_SR1, and the third control signal MRS_SR2 change, the control voltages A1, A2, B1, and B2 of the slew rate control unit 10 also change.

[0063] Figure 3This is a diagram of the architecture of the capacitor delay unit 11 in the slew rate control circuit 100. Slew rate is defined as the amplitude of voltage increase per unit time. Intuitively, it is the time required for a square wave voltage to rise from a trough to a peak. Because capacitors have charging and discharging functions, the capacitor delay unit 11 can use the characteristics of capacitors to control the slew rate. The capacitor delay unit 11 includes a fifth inverter 1NV5, a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4. The fifth inverter 1NV5 includes an input terminal 11a and an output terminal 11b. The input terminal 11a is used to receive the input signal DOIN. The first capacitor C1 includes a first terminal and a second terminal. The first terminal of the first capacitor C1 is coupled to the output terminal of the second NOR gate NOR2 to receive the control voltage A1. The second terminal of the first capacitor C1 is coupled to the output terminal 11b of the fifth inverter INV5. The second capacitor C2 includes a first terminal and a second terminal. The first terminal of the second capacitor C2 is coupled to the output terminal of the second inverter INV2 to receive the control voltage B1. The second end of the second capacitor C2 is coupled to the output terminal 11b of the fifth inverter INV5. The third capacitor C3 includes a first end and a second end. The first end of the third capacitor C3 is coupled to the output terminal of the third NOR gate NOR3 for receiving the control voltage A2. The second end of the third capacitor C3 is coupled to the output terminal 11b of the fifth inverter INV5. The fourth capacitor C4 includes a first end and a second end. The first end of the fourth capacitor C4 is coupled to the output terminal of the fourth inverter INV4 for receiving the control voltage B2. The second end of the fourth capacitor C4 is coupled to the output terminal 11b of the fifth inverter INV5. It should be understood that because the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 can each generate a charging path or a discharging path for the voltage at the output terminal 11b of the fifth inverter INV5, the slew rate control circuit 100 can change the magnitude of the voltage step-up and step-down per unit time at the output terminal 11b of the fifth inverter INV5, i.e., the slew rate. The first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 can be polarized capacitors. As mentioned above, since in the slew rate control unit 10, when the first control signal CAPONT, the second control signal MRS_SR1, and the third control signal MRS_SR2 change, the control voltages A1, A2, B1, and B2 of the slew rate control unit 10 will also change. Therefore, the control voltages A1, A2, B1, and B2 of the slew rate control unit 10 can control the voltage of the output terminal 11b of the fifth inverter INV5 through the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4. For example, if the voltage of the output terminal 11b of the fifth inverter INV5 charges part of the capacitor, the voltage of the output terminal 11b of the fifth inverter INV5 will drop. Conversely, if part of the capacitor discharges the output terminal 11b of the fifth inverter INV5, the voltage of the output terminal 11b of the fifth inverter INV5 will rise.Furthermore, the first capacitor C1 , the second capacitor C2 , the third capacitor C3 , and the fourth capacitor C4 may be metal-oxide-semiconductor capacitors (MOS capacitors). Any reasonable technical or hardware changes fall within the scope of the present invention.

[0064] Figure 4 : is an architectural diagram of the delay unit 12 in the slew rate control circuit 100. The delay unit 12 may include multiple inverters 12b. The multiple inverters 12b are coupled in series. The delay unit 12 may include an input terminal 12a and an output terminal 12c. The input terminal 12a of the delay unit 12 is coupled to the output terminal of the capacitor delay unit 11. The output terminal 12c of the delay unit 12 is coupled to the first input terminal of the third output unit 15. It should be understood that each inverter 12b of the delay unit 12 will produce a delay effect, and there is no limit to the number of inverters 12b connected in series in the delay unit 12. In addition, since the delay unit 12 delays the voltage waveform, the time for the output terminal 11b of the fifth inverter INV5 to step up and down in unit time can be delayed. In other words, after the delay unit 12 is introduced, the slew rate control circuit 100 can further reduce the slew rate.

[0065] Figure 5 yes Figure 1 FIG1 is a block diagram of the first output unit 13 in the slew rate control circuit 100. The first output unit 13 includes a sixth inverter INV6, a seventh inverter INV7, and an eighth inverter INV8. The sixth inverter INV6 includes an input terminal 13a and an output terminal. The input terminal 13a is used to receive the input signal DOIN. The seventh inverter INV7 includes an input terminal and an output terminal. The input terminal of the seventh inverter INV7 is coupled to the output terminal of the sixth inverter INV6. The output terminal of the seventh inverter INV7 is used to output the first output signal DOUT1. The eighth inverter INV8 includes an input terminal and an output terminal. The input terminal of the eighth inverter INV8 is coupled to the output terminal of the sixth inverter INV6. The output terminal of the eighth inverter INV8 is used to output the second output signal DOUT2. In the first output unit 13, the first output signal DOUT1 and the second output signal DOUT2 are generated by receiving the input signal DOIN through two inverters. Therefore, the first output signal DOUT1 and the second output signal DOUT2 are in phase. Furthermore, the first output signal DOUT1 and the second output signal DOUT2 can be represented as the input signal DOIN after a very small delay through two inverters. Therefore, the waveforms of the first output signal DOUT1 and the second output signal DOUT2 are nearly identical to the input signal DOIN. The first output signal DOUT1 and the second output signal DOUT2 are not slew rate controlled.

[0066] Figure 6 : is an architectural diagram of the second output unit 14 in the slew rate control circuit 100. The second output unit 14 includes a ninth inverter INV9, a second NAND gate NAND2, and a tenth inverter INV10. The ninth inverter INV9 includes an input terminal 14a and an output terminal. The input terminal 14a is coupled to the output terminal of the capacitor delay unit 11. The second NAND gate NAND2 includes a first input terminal and a second input terminal. The first input terminal of the second NAND gate NAND2 is coupled to the output terminal of the ninth inverter INV9. The second input terminal of the second NAND gate NAND2 is used to receive the second control signal MRS_SR1. The tenth inverter INV10 includes an input terminal and an output terminal. The input terminal of the tenth inverter INV10 is coupled to the output terminal of the second NAND gate NAND2. The output terminal of the tenth inverter INV10 is used to output the third output signal DOUT3. The relationship between the voltage of the input terminal 14a, the second control signal MRS_SR1, and the third output signal DOUT3 is as follows:

[0067] The voltage at the input terminal 14a MRS_SR1 DOUT3 L L L L H H H L L H H L

[0068] Table 3

[0069] Where "L" represents a low voltage, and "H" represents a high voltage. As can be seen from Table 3, when the second control signal MRS_SR1 is in the off state "L", the third output signal DOUT3 is always at a low voltage "L". And when the second control signal MRS_SR1 is in the on state "H", the third output signal DOUT3 is in phase with the voltage at the input terminal 14a. However, since the voltage at the input terminal 14a is also in phase with the input signal DOIN (through the fifth inverter 11a), when the second control signal MRS_SR1 is in the on state "H", the third output signal DOUT3 is in phase with the input signal DOIN. In other words, the second control signal MRS_SR1 can be regarded as an activation signal for the second output unit 14. When the second output unit 14 is activated, the third output signal DOUT3 is a signal that controls the slew rate of the input signal DOIN through the capacitor delay unit 11.

[0070] Figure 71 is a schematic diagram of the architecture of the third output unit 15 in the slew rate control circuit 100. The third output unit 15 includes a third NAND gate NAND3 and an eleventh inverter INV11. The third NAND gate NAND3 includes a first input terminal, a second input terminal, and an output terminal. The first input terminal 15a of the third NAND gate NAND3 is coupled to the output terminal of the delay unit 12. The second input terminal of the third NAND gate NAND3 is used to receive the third control signal MRS_SR2. The eleventh inverter INV11 includes an input terminal and an output terminal. The input terminal of the eleventh inverter INV11 is coupled to the output terminal of the third NAND gate NAND3. The output terminal of the eleventh inverter INV11 is used to output the fourth output signal DOUT4. The circuit operation mode of the third output unit 15 is similar to that of the second output unit 14 and will not be further described here. In the third output unit 15, the third control signal MRS_SR2 can be regarded as an activation signal for the third output unit 15. When the third output unit 15 is activated, the fourth output signal DOUT4 is a signal whose slew rate is controlled through the capacitor delay unit 11 and the delay unit 12 .

[0071] Figure 8 : is a waveform diagram of the third output signal DOUT3 and the fourth output signal DOUT4 in the slew rate control circuit 100. As mentioned above, the third output signal DOUT3 is a signal for controlling the slew rate through the capacitor delay unit 11. The fourth output signal DOUT4 is a signal for controlling the slew rate through the capacitor delay unit 11 and the delay unit 12. Therefore, Figure 8 In FIG, when the capacitor delay unit 11 and the delay unit 12 are turned on by the first control signal CAPONT, the second control signal MRS_SR1 and the third control signal MRS_SR2, the rising waveform and the falling waveform of the fourth output signal DOUT4 will be delayed, so that the rising speed of the fourth output signal DOUT4 is lower than the rising speed of the third output signal DOUT3, and the falling speed of the fourth output signal DOUT4 is lower than the falling speed of the third output signal DOUT3. In other words, the slew rate of the fourth output signal DOUT4 will be lower than the slew rate of the third output signal DOUT3. For example, in Figure 8 The slew rate of the fourth output signal DOUT4 is 22% lower than that of the third output signal DOUT3. Figure 8 As for the waveforms of the third output signal DOUT3 and the fourth output signal DOUT4, the difference between the duty cycle of the third output signal DOUT3 and the duty cycle of the fourth output signal DOUT4 is less than 5%. Figure 8In the example, the duty cycle of the third output signal DOUT3 is 50.72%. The duty cycle of the fourth output signal DOUT4 is 50.82%. In other words, the duty cycle of the third output signal DOUT3 is substantially equal to the duty cycle of the fourth output signal DOUT4. Therefore, for the slew rate control circuit 100, although the slew rate can be adjusted (e.g., through down control), its duty cycle does not fluctuate significantly, thus maintaining performance stability.

[0072] In summary, the present invention describes a slew rate control circuit. The slew rate control circuit can provide multiple modes for dynamic random access memory applications. For example, the slew rate control circuit can provide a signal that is not slew rate controlled, a signal whose slew rate is controlled only by a capacitor delay unit, and a signal whose slew rate is controlled by both a capacitor delay unit and a delay unit. Furthermore, because the slew rate control circuit incorporates a delay unit, the slew rate can be further adjusted (e.g., down control). Furthermore, in the slew rate control circuit of the present invention, when the slew rate is adjusted, the duty cycle does not fluctuate significantly, thereby maintaining performance stability.

[0073] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A slew rate control circuit, characterized in that: include: Slew rate control unit, including: A first input terminal, for receiving a first control signal; A second input terminal, for receiving a second control signal; a third input terminal for receiving a third control signal; and An output terminal, used for outputting a plurality of control voltages; Capacitive delay unit, comprising: A first input terminal coupled to an output terminal of the slew rate control unit; A second input terminal for receiving an input signal; and Output terminal; Delay unit, including: an input terminal coupled to the output terminal of the capacitor delay unit; and Output terminal; The first output unit includes: an input terminal coupled to the second input terminal of the capacitor delay unit, for receiving the input signal; A first output terminal, configured to output a first output signal; and A second output terminal, used to output a second output signal; The second output unit includes: a first input terminal coupled to the output terminal of the capacitor delay unit, for receiving an output signal of the capacitor delay unit; a second input terminal, configured to receive the second control signal; and an output terminal, configured to output a third output signal; The third output unit includes: a first input terminal coupled to the output terminal of the delay unit, for receiving an output signal of the delay unit; a second input terminal for receiving the third control signal; and an output terminal, configured to output a fourth output signal; Wherein, the delay unit includes a plurality of inverters, and the plurality of inverters are coupled in series; The first output signal and the second output signal are two signals that are not slew rate controlled, the third output signal is a signal whose slew rate is controlled by the capacitor delay unit, and the fourth output signal is a signal whose slew rate is controlled by the capacitor delay unit and the delay unit.

2. The control circuit according to claim 1, wherein: The slew rate control unit further includes: a first inverter, including: an input terminal for receiving the first control signal; and Output terminal; The first NOR gate includes: a first input terminal, configured to receive the second control signal; a second input terminal for receiving the third control signal; and Output terminal; The second NOR gate includes: A first input terminal coupled to the output terminal of the first inverter; A second input terminal coupled to the output terminal of the first NOR gate; and Output terminal; The second inverter comprises: an input terminal coupled to the output terminal of the second NOR gate; and Output terminal; The third inverter includes: an input terminal for receiving the first control signal; and Output terminal; The first NAND gate includes: a first input terminal, configured to receive the second control signal; a second input terminal for receiving the third control signal; and Output terminal; The third NOR gate includes: A first input terminal coupled to the output terminal of the third inverter; A second input terminal coupled to the output terminal of the first NAND gate; and Output terminal; The fourth inverter includes: an input terminal coupled to the output terminal of the third NOR gate; and Output end.

3. The control circuit according to claim 2, wherein: The capacitor delay unit includes: a fifth inverter, including: an input terminal, for receiving the input signal; and Output terminal; The first capacitor includes: A first terminal coupled to the output terminal of the second NOR gate; and A second end coupled to the output end of the fifth inverter; The second capacitor includes: A first terminal coupled to the output terminal of the second inverter; and A second end coupled to the output end of the fifth inverter; The third capacitor includes: A first terminal coupled to the output terminal of the third NOR gate; and A second end coupled to the output end of the fifth inverter; The fourth capacitor includes: A first terminal coupled to the output terminal of the fourth inverter; and The second end is coupled to the output end of the fifth inverter.

4. The control circuit according to claim 3, wherein: The first capacitor, the second capacitor, the third capacitor, and the fourth capacitor are metal oxide semiconductor capacitors.

5. The control circuit according to claim 1, wherein: The first output unit further includes: The sixth inverter comprises: an input terminal, for receiving the input signal; and Output terminal; The seventh inverter comprises: an input terminal coupled to the output terminal of the sixth inverter; and an output terminal, configured to output the first output signal; The eighth inverter comprises: an input terminal coupled to the output terminal of the sixth inverter; and The output terminal is used to output the second output signal.

6. The control circuit according to claim 1, wherein: The second output unit further includes: a ninth inverter, including: an input terminal coupled to the output terminal of the capacitor delay unit; and Output terminal; The second NAND gate includes: A first input terminal coupled to the output terminal of the ninth inverter; a second input terminal, configured to receive the second control signal; and Output terminal; The tenth inverter comprises: an input terminal coupled to the output terminal of the second NAND gate; and The output terminal is used to output the third output signal.

7. The control circuit according to claim 1, wherein: The third output unit further includes: a third NAND gate, including: A first input terminal coupled to the output terminal of the delay unit; a second input terminal for receiving the third control signal; and Output terminal; The eleventh inverter comprises: an input terminal coupled to the output terminal of the third NAND gate; and The output terminal is used to output the fourth output signal.

8. The control circuit according to claim 1, wherein: When the capacitor delay unit and the delay unit are turned on by the first control signal, the second control signal, and the third control signal, a rising speed of the fourth output signal is lower than a rising speed of the third output signal, a falling speed of the fourth output signal is lower than a falling speed of the third output signal, and a difference between a duty cycle of the third output signal and a duty cycle of the fourth output signal is less than 5%.

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