Method for preparing vertical field effect transistor

Abstract

The present invention relates to a method for preparing a long-range ordered high aspect ratio structure and a vertical field effect transistor. The main steps of the method are: using acetone, isopropyl alcohol and deionized water to clean the long-range ordered porous alumina template, using the characteristic of atomic layer deposition technology that can deposit three-dimensional conformal deposition to deposit an insulating oxide film, and accurately controlling the film thickness by setting the number of cycles to obtain a long-range ordered ultra-high aspect ratio structure greater than 200:1. This method does not require the use of etching technology, and has a simple process and low cost. At the same time, based on the atomic layer deposition technology, an oxide semiconductor film is deposited on the ultra-high aspect ratio structure to fill the pores, and the oxide semiconductor film deposited on the surface is removed by etching, and then a metal layer is deposited using a physical vapor deposition system, and then a semiconductor device process is adopted, and finally it can be used to prepare a vertical field effect transistor.

Description

Technical Field

[0001] The invention relates to a method for preparing a vertical field effect transistor. Background Art

[0002] With the development of integrated circuits, device feature sizes continue to shrink. High-aspect-ratio structures can create more vertical space within the same planar surface area, meeting the requirements of high-density, high-integration, low-power consumption, and high-sensitivity integrated circuits. The fabrication of high-aspect-ratio structures typically utilizes techniques such as EBL (electron beam lithography), direct FIB (focused ion beam) patterning, DUV (deep ultraviolet lithography) double exposure, and EUV (extreme ultraviolet lithography). Most of these techniques require integration with other methods (e.g., etching), which increases both process complexity and fabrication costs.

[0003] In comparison, porous alumina membranes are cheaper and can be obtained by electrochemically forming an oxide layer on a high-purity aluminum sheet in an acidic solution. Porous alumina can then be used to prepare structures such as nanowires, nanopillars, and nanoparticles, which can be used in sensors, thermoelectrics, catalysis, photovoltaics, and microelectronics. A method for optimizing the porous alumina process was used to obtain porous alumina with an aspect ratio greater than 100:1, but the porous alumina membranes formed were mostly long-range disordered structures. The maximum aspect ratio of the long-range ordered porous alumina membrane currently available is approximately 30:1. Utilizing the characteristics of atomic layer deposition technology, which allows for precise control of film thickness and three-dimensional conformal film deposition, a thin film is uniformly grown on the inner wall and bottom of the pores on the basis of the long-range ordered porous alumina membrane to prepare a long-range ordered porous structure with an aspect ratio greater than 200:1. This high aspect ratio structure can then be used to prepare vertical transistors, with a precise and controllable process and lower cost. Summary of the Invention

[0004] The purpose of the present invention is to provide a method for preparing a vertical field-effect transistor while reducing costs without increasing process complexity. A thin film with controllable thickness is grown using atomic layer deposition technology to prepare an ultra-high aspect ratio structure greater than 200:1, which can be used to prepare a vertical field-effect transistor.

[0005] To achieve the above objectives, the technical solution of the present invention is: a method for preparing a vertical field-effect transistor, using an atomic layer deposition system to coat a porous aluminum oxide film with an insulating oxide film to prepare a high-aspect ratio structure, and then preparing a vertical field-effect transistor based on the high-aspect ratio structure, the specific steps are as follows:

[0006] Step 1: Cleaning the long-range ordered porous alumina membrane by sequentially using acetone, isopropyl alcohol, deionized water, and N2 purging to clean the porous alumina membrane;

[0007] Step 2: Place the cleaned porous aluminum oxide film into an atomic layer deposition system to deposit an insulating oxide film. Utilizing the three-dimensional conformal deposition characteristics of atomic layer deposition, the film thickness is precisely controlled to prepare a high aspect ratio structure.

[0008] Step 3: Place the prepared high aspect ratio structure into an atomic layer deposition system to deposit an oxide semiconductor film to fill the pores, and remove excess oxide semiconductor film on the surface by inductively coupled plasma dry etching;

[0009] Step 4: Using a physical vapor deposition system, a metal layer is deposited on the surface of the sample treated in step 3 as a source electrode;

[0010] Step 5: Place the sample treated in step 4 in a sodium hydroxide solution to remove the aluminum oxide on the back of the porous alumina, then place it in a copper chloride and hydrochloric acid solution to remove the aluminum substrate of the porous alumina, and finally place the sample in a sodium hydroxide solution to remove the porous alumina;

[0011] Step 6: Spin-coat photoresist and pattern the gate using electron beam exposure, partially fill the metal using physical vapor deposition, and then strip off the excess metal to form the gate;

[0012] Step 7: Using an atomic layer deposition system to deposit an insulating oxide film to fill the pores, and then using inductively coupled plasma dry etching to remove the surface insulating oxide film until the oxide semiconductor film is exposed, and then using chemical mechanical polishing to flatten it;

[0013] Step 8: Using physical vapor deposition to deposit a metal layer as a drain electrode.

[0014] In one embodiment of the present invention, in step 1, the porous alumina has a pore diameter of 150 nm and a pore depth of 4500 nm;

[0015] In one embodiment of the present invention, in step 2, the insulating oxide film is a high-k (dielectric constant) oxide material including aluminum oxide, hafnium oxide, zirconium oxide, hafnium lanthanum oxide, etc., and the thickness of the insulating oxide film is 65 nm to 72.5 nm.

[0016] In one embodiment of the present invention, in step 3, the oxide semiconductor film deposited by the atomic layer deposition system includes an oxide semiconductor such as indium oxide, indium tin oxide, or indium gallium zinc oxide, and the filling pore diameter is 5 nm to 20 nm.

[0017] In one embodiment of the present invention, in step 4, the metal layer is nickel-gold.

[0018] In one embodiment of the present invention, in step 5, the mass fraction of the sodium hydroxide solution is 5%, the mass fraction of the copper chloride is 20%, and the volume concentration of hydrochloric acid is 10%.

[0019] In one embodiment of the present invention, in step 6, the photoresist is methyl methacrylate (PMMA), and the metal material is nickel.

[0020] In one embodiment of the present invention, in step 7, the insulating oxide film is made of a high-k material such as aluminum oxide, hafnium oxide, or zirconium oxide.

[0021] In one embodiment of the present invention, in step 8, the metal layer is nickel-gold.

[0022] Compared with the prior art, the present invention has the following beneficial effects:

[0023] (1) Nanoscale thin films are prepared by ALD, with precise control of film thickness to achieve an aspect ratio greater than 200:1;

[0024] (2) The process is simple, and the preparation of high aspect ratio does not require etching and other methods, which is low cost;

[0025] (3) The film has strong coverage and good uniformity, and the vertical semiconductor device prepared has a simple process and low cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Schematic diagram of the cross-sectional structure of the porous aluminum oxide membrane according to an embodiment of the present invention, 1 is an aluminum substrate, 2 is aluminum oxide;

[0027] Figure 2 3 is a cross-sectional schematic diagram of an embodiment of the present invention in which an insulating oxide film is coated on the surface of the porous alumina membrane and on the inner wall and bottom of the pores using atomic layer deposition technology on the porous alumina membrane, where 3 is hafnium oxide;

[0028] Figure 3 This is a cross-sectional view obtained by SEM characterization of a thin film grown on a porous aluminum oxide membrane using atomic layer deposition technology in an embodiment of the present invention;

[0029] Figure 4 4 is a cross-sectional schematic diagram of an embodiment of the present invention using atomic layer deposition technology to grow oxide semiconductors to fill pores, where 4 is indium tin oxide;

[0030] Figure 5 Schematic cross-sectional view of a method for growing a metal layer on a sample surface using physical vapor deposition technology according to an embodiment of the present invention, where 5 represents nickel-gold;

[0031] Figure 6 This is a cross-sectional schematic diagram showing the metal layer as the bottom after porous alumina is removed using 5% by mass sodium hydroxide and 20% by mass copper chloride mixed with 10% by volume hydrochloric acid in an embodiment of the present invention;

[0032] Figure 7Schematic cross-sectional view of an embodiment of the present invention wherein physical vapor deposition technology is used to fill a portion of metal in the pores of a sample and an insulating oxide layer is grown by atomic layer deposition. 6 represents nickel and 7 represents hafnium oxide.

[0033] Figure 8 This is a cross-sectional schematic diagram of an embodiment of the present invention in which the surface insulating layer oxide is removed by etching to expose the channel;

[0034] Figure 9 Schematic cross-sectional view of growing a metal layer on a sample surface using physical vapor deposition technology according to an embodiment of the present invention, where 8 represents nickel-gold. DETAILED DESCRIPTION

[0035] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings.

[0036] The present invention provides a method for preparing a vertical field-effect transistor, which uses an atomic layer deposition system to coat a porous aluminum oxide film with an insulating oxide film to prepare a high-aspect ratio structure, and then prepares a vertical field-effect transistor based on the high-aspect ratio structure. The specific steps are as follows:

[0037] Step 1: Cleaning the long-range ordered porous alumina membrane by sequentially using acetone, isopropyl alcohol, deionized water, and N2 purging to clean the porous alumina membrane;

[0038] Step 2: Place the cleaned porous aluminum oxide film into an atomic layer deposition system to deposit an insulating oxide film. Utilizing the three-dimensional conformal deposition characteristics of atomic layer deposition, the film thickness is precisely controlled to prepare a high aspect ratio structure.

[0039] Step 3: Place the prepared high aspect ratio structure into an atomic layer deposition system to deposit an oxide semiconductor film to fill the pores, and remove excess oxide semiconductor film on the surface by inductively coupled plasma dry etching;

[0040] Step 4: Using a physical vapor deposition system, a metal layer is deposited on the surface of the sample treated in step 3 as a source electrode;

[0041] Step 5: Place the sample treated in step 4 in a sodium hydroxide solution to remove the aluminum oxide on the back of the porous alumina, then place it in a copper chloride and hydrochloric acid solution to remove the aluminum substrate of the porous alumina, and finally place the sample in a sodium hydroxide solution to remove the porous alumina;

[0042] Step 6: Spin-coat photoresist and pattern the gate using electron beam exposure, partially fill the metal using physical vapor deposition, and then strip off the excess metal to form the gate;

[0043] Step 7: Using an atomic layer deposition system to deposit an insulating oxide film to fill the pores, and then using inductively coupled plasma dry etching to remove the surface insulating oxide film until the oxide semiconductor film is exposed, and then using chemical mechanical polishing to flatten it;

[0044] Step 8: Using physical vapor deposition to deposit a metal layer as a drain electrode.

[0045] The following are specific implementation examples of the present invention.

[0046] like Figure 1 The figure shows a cross-sectional view of a porous alumina membrane with orderly arranged pores on its surface. 1 is the aluminum substrate, 2 is alumina, and the pore diameter of the porous alumina is 150 nm and the pore depth is 4500 nm.

[0047] Step 1: The porous alumina membrane was cleaned in 50°C acetone for 30 minutes and ultrasonically cleaned for 3 minutes at a power of 10 W. The sample was then placed in an isopropanol solution and cleaned at room temperature for 10 minutes. The sample was then rinsed with deionized water for 10 minutes and finally dried with nitrogen to remove impurities on the surface of the porous alumina.

[0048] Step 2: Place the cleaned porous alumina membrane in a water-free and oxygen-free glove box, place the porous alumina membrane into the atomic layer deposition system chamber through the sample introduction station, and deposit a layer of hafnium oxide film through the atomic layer deposition system to obtain a higher aspect ratio structure. The precursors of the hafnium oxide reaction are tetrakis(methylethylamino)hafnium (TEMAHf) and ozone, the reaction temperature is 300 ° C, and the deposition thickness is 65 nm. The cross-section of the obtained sample is shown in the figure below. Figure 2 As shown;

[0049] Step 3: Place the prepared high aspect ratio structure into an atomic layer deposition chamber, and fill the pores with indium tin oxide by atomic layer deposition. The precursors of indium tin oxide are trimethyl indium (TMIn), tetrakis(dimethylamino)tin (TDMASn) and 99.9% pure deionized water. The reaction temperature is 225 °C, the thickness is 10 nm, and the excess indium tin oxide on the surface is removed by inductively coupled plasma dry etching. The etching gases are hydrogen, carbon tetrafluoride and argon. The plasma power is 750 W and the radio frequency power is 50 W. The cross-section of the obtained sample is shown in the figure below. Figure 4 As shown;

[0050] Step 4: Use physical vapor deposition technology to deposit a layer of metal on the surface of the sample as the source of the vertical field effect transistor. The metal is nickel-gold, 20 nm nickel and 40 nm gold. The cross-section of the obtained sample is shown in the figure below. Figure 5 As shown;

[0051] Step 5: Place the sample in a 5% sodium hydroxide solution to remove the aluminum oxide on the back of the porous aluminum oxide, rinse with water, and then place it in a 20% copper chloride and 10% hydrochloric acid solution to remove the aluminum substrate of the porous aluminum oxide, rinse with water, and finally place the sample in a 5% sodium hydroxide solution to remove the porous aluminum oxide. The cross-section of the obtained sample is shown in the figure below. Figure 6 As shown;

[0052] Step 6: Spin-coat PMMA as a mask photoresist and pattern the gate using electron beam exposure. The gate is a portion of the removed porous alumina pores. After exposure, develop in a developer for 50 seconds and rinse in isopropyl alcohol for 30 seconds to expose the gate area. Then, partially fill it with metal nickel using physical vapor deposition. Then, heat it in acetone at 50°C for 30 minutes to dissolve the PMMA and peel off the metal nickel outside the gate area. Finally, rinse in isopropyl alcohol solution for 5 minutes to remove impurities.

[0053] Step 7: Use the atomic layer deposition system to deposit a hafnium oxide film to fill the pores. The deposition thickness is 50 nm. The conditions are the same as in step 2. The cross-section of the obtained sample is shown in the figure below. Figure 7 As shown. The surface hafnium oxide film was removed by inductively coupled plasma dry etching until the oxide semiconductor film stopped etching. The etching gas was boron trichloride and chlorine, the plasma power was 500 W, and the radio frequency power was 75 W. After that, chemical mechanical polishing was used for flattening. The cross-section of the obtained sample is shown in the figure below. Figure 8 As shown;

[0054] Step 8: Place the sample in a physical vapor deposition chamber and grow nickel-gold metal as source and drain electrodes with a thickness of 20 nm nickel and 40 nm gold. The cross-section of the obtained sample is shown in the figure below. Figure 9 shown.

[0055] The above-mentioned atomic layer deposition, physical vapor deposition, and inductively coupled plasma dry etching are all carried out in a vacuum.

[0056] In step 2, the ozone gas flow rate is 20 sccm.

[0057] In steps 4, 6, and 8, the physical vapor deposition technique is electron beam evaporation, a tungsten crucible is used for nickel, and a graphite crucible is used for gold, with a voltage of 10 kV.

[0058] like Figure 3 As shown, an aluminum oxide film was deposited using an atomic layer deposition system. The SEM characterization of the sample cross section showed that the film thickness was 4500 nm, the pore diameter was measured to be 20 nm, and a structure with an aspect ratio of 225:1 was obtained.

[0059] The above are preferred embodiments of the present invention. Any changes made according to the technical solution of the present invention, as long as the resulting functions and effects do not exceed the scope of the technical solution of the present invention, shall fall within the scope of protection of the present invention.

Claims

1. A method for preparing a vertical field effect transistor, characterized in that: An atomic layer deposition system is used to coat a porous aluminum oxide film with an insulating oxide film to prepare a high aspect ratio structure. A vertical field-effect transistor is then fabricated based on the high aspect ratio structure. The specific steps are as follows: Step 1: Cleaning the long-range ordered porous alumina membrane by sequentially using acetone, isopropyl alcohol, deionized water, and nitrogen purge to clean the porous alumina membrane; Step 2: Place the cleaned porous aluminum oxide film into an atomic layer deposition system to deposit an insulating oxide film. Utilizing the three-dimensional conformal deposition characteristics of atomic layer deposition, the film thickness is precisely controlled to prepare a high aspect ratio structure. Step 3: Place the prepared high aspect ratio structure into an atomic layer deposition system to deposit an oxide semiconductor film to fill the pores, and remove excess oxide semiconductor film on the surface by inductively coupled plasma dry etching; Step 4: Using a physical vapor deposition system, a metal layer is deposited on the surface of the sample treated in step 3 as a source electrode; Step 5: Place the sample treated in step 4 in a sodium hydroxide solution to remove the aluminum oxide on the back of the porous alumina, then place it in a copper chloride and hydrochloric acid solution to remove the aluminum substrate of the porous alumina, and finally place the sample in a sodium hydroxide solution to remove the porous alumina; Step 6: Spin-coat photoresist and pattern the gate using electron beam exposure, partially fill the metal using physical vapor deposition, and then strip off the excess metal to form the gate; Step 7: Using an atomic layer deposition system to deposit an insulating oxide film to fill the pores, and then using inductively coupled plasma dry etching to remove the surface insulating oxide film until the oxide semiconductor film is exposed, and then using chemical mechanical polishing to flatten it; Step 8: Using physical vapor deposition to deposit a metal layer as a drain electrode.

2. The method for preparing a vertical field effect transistor according to claim 1, wherein: The insulating oxide film is a high-k oxide material including aluminum oxide, hafnium oxide, zirconium oxide, and hafnium lanthanum oxide.

3. The method for preparing a vertical field effect transistor according to claim 1, wherein: The thickness of the insulating oxide film in step 2 is 65 nm to 72.5 nm.

4. The method for preparing a vertical field effect transistor according to claim 1, wherein: The oxide semiconductor film deposited by the atomic layer deposition system in step 3 is an oxide semiconductor including indium oxide, indium tin oxide, and indium gallium zinc oxide, and the filling pore diameter is 5 nm to 20 nm.

5. The method for preparing a vertical field effect transistor according to claim 1, wherein: The metal layer in step 4 is nickel-gold.

6. The method for preparing a vertical field effect transistor according to claim 1, wherein: The mass fraction of the sodium hydroxide solution described in step 5 is 5%, the mass fraction of cupric chloride is 20%, and the hydrochloric acid volume concentration is 10%.

7. The method for preparing a vertical field effect transistor according to claim 1, wherein: In step 6, the photoresist is methyl methacrylate, and the metal material is nickel.

8. The method for preparing a vertical field effect transistor according to claim 1, wherein: The insulating oxide film in step 7 is a high-k material including aluminum oxide, hafnium oxide, and zirconium oxide.

9. The method for preparing a vertical field effect transistor according to claim 1, wherein: The metal layer in step 8 is nickel-gold.

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