Adaptor plate for encapsulation and method for manufacturing same, semiconductor package structure
By employing a stacked structure and wet etching technology in the 2.5D/3D packaging structure, the problem of copper diffusion into the silicon substrate was solved, thereby improving the performance of the packaging structure.
Patent Information
- Application Number
- CN202110721421.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-06-28
- Publication Date
- 2026-01-20
- Estimated Expiration
- 2041-06-28
AI Technical Summary
In existing 2.5D/3D packaging structures, copper in the TSV holes can easily diffuse into the silicon substrate, leading to a decrease in packaging structure performance.
The structure employs a stacked structure, including a support substrate, a separation layer, and a silicon substrate. Copper conductive pillars are filled in the TSV holes to form a diffusion barrier layer. Etching grooves are formed by wet etching and filled with a protective layer. Combined with chemical mechanical polishing, copper diffusion to the silicon substrate is prevented.
This effectively prevents the diffusion of copper conductive pillars in the silicon substrate, thus improving the performance of the packaging structure.
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Figure CN115602605B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application belongs to the technical field of semiconductor packaging, and particularly relates to a re-distribution board for packaging, a preparation method thereof, and a semiconductor packaging structure. BACKGROUND
[0002] With the development of electronic products towards miniaturization, high performance, high reliability, and the like, the system integration degree is also increasing. In this case, the way of improving performance by further reducing the feature size and the line width of the interconnection line of integrated circuits is limited by the material physical properties and equipment processes, and the traditional Moore's law has been difficult to continue to develop. At present, advanced packaging methods include wafer level chip scale packaging (WLCSP), fan-out wafer level package (FOWLP), flip chip, package on package (POP), and the like. The 2.5D / 3D integration technology with TSV as the core has been widely recognized as the leading technology in the future high-density packaging field, and is an effective way to break through Moore's law.
[0003] The existing 2.5D / 3D packaging structure generally includes a silicon re-distribution board, and a through silicon via (TSV) hole is arranged in the silicon re-distribution board. A copper conductive pillar is formed in the TSV hole to interconnect a chip and a substrate. The process of exposing the copper conductive pillar in the back TSV hole is called BVR (backside via reveal), which generally includes the steps of silicon substrate grinding, silicon substrate surface chemical mechanical polishing (CMP), and silicon substrate etching. These steps can cause the copper in the TSV hole to diffuse into the silicon substrate, which eventually leads to a decrease in the performance of the entire packaging structure. SUMMARY
[0004] In view of the above-mentioned shortcomings of the prior art, the present application aims to provide a re-distribution board for packaging, a preparation method thereof, and a semiconductor packaging structure, which can solve the problem that the copper in the TSV hole easily diffuses into the silicon substrate during the preparation process of the silicon re-distribution board of the existing 2.5D / 3D packaging structure, which eventually leads to a decrease in the performance of the entire packaging structure.
[0005] To achieve the above-mentioned objects and other related objects, the present application provides a preparation method of a re-distribution board for packaging, which comprises the following steps:
[0006] A stack structure is provided, which comprises, from bottom to top, a support substrate, a separation layer and a silicon substrate, wherein a TSV hole extending from bottom to top is formed in the silicon substrate, and a copper conductive column is filled in the TSV hole, and a diffusion barrier layer is formed between the copper conductive column and the side wall of the TSV hole;
[0007] The upper surface of the silicon substrate is ground to expose the TSV hole completely;
[0008] The upper surface of the stack structure is polished by a chemical mechanical polishing process;
[0009] The copper conductive column is etched by a wet etching process to a preset depth to form an etching groove, and the copper ground into the surface of the silicon substrate is removed by the wet etching solution;
[0010] The etching groove is filled with a protective layer;
[0011] The upper surface of the silicon substrate is etched to expose the copper conductive column;
[0012] An insulating layer is formed on the upper surface of the silicon substrate by a chemical vapor deposition process.
[0013] Optionally, the wet etching solution is a copper etching solution, which comprises phosphoric acid and hydrogen peroxide.
[0014] Optionally, the step of forming the stack structure comprises:
[0015] The silicon substrate is provided, and the TSV hole is formed in the silicon substrate;
[0016] The diffusion barrier layer is formed on the side wall of the TSV hole;
[0017] The TSV hole is filled with copper material to form the copper conductive column;
[0018] The support substrate and the separation layer are provided, and the support substrate is bonded with the silicon substrate having the TSV hole based on the separation layer to form the stack structure.
[0019] Optionally, the step of forming the protective layer comprises:
[0020] A protective layer material is deposited on the upper surface of the stack structure by a chemical vapor deposition process to fill the etching groove;
[0021] The upper surface of the stack structure is polished by a chemical mechanical polishing process to the upper surface of the silicon substrate to form the protective layer covering the upper surface of the copper conductive column.
[0022] Optionally, the step of forming the insulating layer comprises:
[0023] depositing an insulating layer material on the upper surface of the stack structure by a chemical vapor deposition process;
[0024] polishing the insulating layer material and the protective layer by a chemical mechanical polishing process to expose the copper conductive pillars, forming an insulating layer covering the silicon substrate.
[0025] Optionally, the etched groove has a depth between 1% and 2% of the length of the copper conductive pillar, and the material of the protective layer is silicon oxide.
[0026] The application also provides a semiconductor package structure comprising any of the semiconductor package adapter as described above.
[0027] a support substrate and a silicon substrate adhered to the upper and lower sides of the separation layer;
[0028] a TSV hole penetrating through the silicon substrate;
[0029] a copper conductive pillar filling the TSV hole and protruding from the TSV hole, and the copper in the copper conductive pillar not diffusing into the surface of the silicon substrate;
[0030] a diffusion barrier layer formed between the copper conductive pillar and the sidewall of the TSV hole and extending to the same level as the copper conductive pillar;
[0031] an insulating layer formed on the surface of the silicon substrate and completely covering the circumferential side of the copper conductive pillar.
[0032] Optionally, the support substrate comprises one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate and a ceramic substrate; and the separation layer comprises a polymer layer or an adhesive layer.
[0033] Optionally, the diffusion barrier layer comprises one of a tantalum nitride layer, a titanium nitride layer, a silicon nitride layer and a silicon oxide layer, or a stack of at least two of them.
[0034] Optionally, the insulating layer comprises one of a silicon nitride layer and a silicon oxide layer, or a stack of both.
[0035] The application also provides a semiconductor package structure comprising any of the semiconductor package adapter as described above.
[0036] As described above, the package adapter plate of the present application and its preparation method, and the semiconductor package structure, by forming the etching groove through wet etching, the copper particles diffused into the surface of the silicon substrate in the previous process can be removed, and at the same time, the foundation for the subsequent deposition of the protective layer on the upper surface of the copper conductive column is laid. In addition, the etching groove in combination with the subsequent protective layer filled therein can effectively avoid the diffusion of copper particles into the silicon substrate during the etching process of the silicon substrate. Thus, the possibility of all copper conductive columns diffusing into the silicon substrate is avoided in the entire preparation process of the adapter plate, and the performance of the package structure is effectively improved. BRIEF DESCRIPTION OF DRAWINGS
[0037] Figures 1 to 6 The structure schematic diagram shown is the structure presented in each step in the preparation process of the package adapter plate in the prior art.
[0038] Figure 7 The flowchart shown is the preparation method of the package adapter plate of the embodiment one of the present application.
[0039] Figures 8 to 19 The structure schematic diagram shown is the structure presented in each step in the preparation method of the package adapter plate of the embodiment one of the present application. Figure 19 The structure schematic diagram shown is also the structure of the package adapter plate of the embodiment two of the present application.
[0040] ELEMENT NUMBER EXPLANATION
[0041] 100, 200, stack structure
[0042] 101, 201, support substrate
[0043] 102, 202, separation layer
[0044] 103, 203, silicon substrate
[0045] 104, 204, TSV hole
[0046] 105, 205, copper conductive column
[0047] 106, 206, diffusion barrier layer
[0048] 107, 210, insulating layer material
[0049] 108, 211, insulating layer
[0050] 207, etching groove
[0051] 208, protective layer material
[0052] 209, protective layer
[0053] A, copper particles
[0054] D depth of etched recess
[0055] S1-S7 steps DETAILED DESCRIPTION
[0056] Following specific embodiments of the present application are illustrated by way of specific examples, and other advantages and effects of the present application can be easily understood by those skilled in the art from the disclosure of this specification. The present application can also be implemented or applied by other different specific embodiments, and various modifications or changes can be made to the details in this specification based on different views and applications without departing from the spirit of the present application.
[0057] Reference will now be made to Figures 1 to 19 . It is noted that the drawings provided in this embodiment only schematically illustrate the basic concept of the present application, and thus the drawings only show the components related to the present application rather than being drawn according to the number, shape and size of the components in actual implementation, and the shape, number and proportion of each component in actual implementation can be changed according to actual needs, and the component layout pattern can also be more complex.
[0058] Embodiment one
[0059] As shown in Figures 1 to 6 , the preparation process of the adapter plate for packaging in the prior art includes the following steps:
[0060] As shown in Figure 1 , a laminated structure 100 is first provided, which includes a support substrate 101, a separation layer 102 and a silicon substrate 103 from bottom to top, the silicon substrate 103 has a TSV hole 104 extending from bottom to top formed therein, the TSV hole 104 is filled with a copper conductive column 105, and a diffusion barrier layer 106 is formed between the copper conductive column 105 and the sidewall of the TSV hole 104.
[0061] Generally, the silicon substrate 103 is relatively thick, and the TSV hole 104 cannot penetrate the silicon substrate 103, so the silicon substrate 103 needs to be thinned, as shown in Figure 2 , and then the silicon substrate 103 is thinned. During the process of thinning the silicon substrate 103 to completely expose the TSV hole 104, copper particles in the copper conductive column 105 will be ground into the silicon substrate 103 around the TSV hole 104, such as the copper particles A in Figure 2 .
[0062] As shown in Figure 3 , then a chemical mechanical polishing process (referred to as CMP) is used to polish the upper surface of the laminated structure 100. During the polishing process, copper particles in the copper conductive column 105 will be further ground into the silicon substrate 103 around the TSV hole 104, increasing the concentration of copper particles A in the silicon substrate.
[0063] As shown in Figure 4 , then etching the upper surface of the silicon substrate 103 to expose the copper conductive column 105. As described above, since the copper particles A in the copper conductive column 105 diffuse into the silicon substrate 103 around the TSV hole 104, the silicon substrate 103 around the TSV hole 104 is not easy to be etched during the etching of the silicon substrate 103, and the etching of the silicon substrate 103 will further cause the copper particles in the copper conductive column 105 to diffuse into the silicon substrate 103 around the TSV hole 104, making the etching of the silicon substrate 103 around the TSV hole 104 more difficult, thereby causing the silicon substrate etching defect.
[0064] As shown in Figure 5 , then depositing an insulating layer material 107 on the upper surface of the laminated structure 100 by chemical vapor deposition process.
[0065] As shown in Figure 6 , finally polishing the insulating layer material 107 by chemical mechanical polishing process to expose the copper conductive column 105, while forming an insulating layer 108 covering the silicon substrate. As can be seen from the above steps, since the silicon substrate 103 around the TSV hole 104 is not easy to be etched, the insulating layer material 107 around the TSV hole 104 will be ground off after polishing the insulating layer material 107, thereby failing to provide insulation protection effect for the copper conductive column 105, leading to the risk of electric leakage, and finally reducing the performance of the entire packaging structure.
[0066] Based on the research and analysis of the preparation process of the existing adapter plate for packaging, the inventor proposes a preparation method of an adapter plate for packaging from the perspective of preventing the diffusion of copper conductive column into the silicon substrate, which comprises the following steps:
[0067] As shown in Figure 7 and Figure 11 , first, step S1 is performed to provide a laminated structure 200, which comprises a support substrate 201, a separation layer 202 and a silicon substrate 203 from bottom to top, the silicon substrate 203 has a TSV hole 204 extending from bottom to top, the TSV hole 204 is filled with a copper conductive column 205, and a diffusion barrier layer 206 is formed between the copper conductive column 205 and the side wall of the TSV hole 204.
[0068] As an example, the support substrate 201 comprises one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate and a ceramic substrate. In this embodiment, the support substrate 201 is selected as a glass substrate, which has low cost, is easy to form a separation layer 202 on its surface, and can reduce the difficulty of subsequent peeling process.
[0069] The separation layer 202 is used as a separation layer between the silicon substrate 203 and the support substrate 201 in subsequent processes. The separation layer 202 is preferably made of an adhesive material with a smooth surface. The separation layer 202 must have a certain bonding force with the silicon substrate 203 to prevent the silicon substrate 203 from moving in subsequent processes. In addition, the separation layer 202 must also have a strong bonding force with the support substrate 201. In general, the bonding force between the separation layer 202 and the support substrate 201 is greater than the bonding force between the separation layer 202 and the silicon substrate 203. As an example, the separation layer 202 includes a polymer layer or an adhesive layer. The polymer layer or the adhesive layer is first coated on the surface of the support substrate 201 by a spin coating process, and then cured by a UV curing process or a thermal curing process.
[0070] In this embodiment, the polymer layer includes an LTHC light-to-heat conversion layer. When the support substrate 201 is peeled off, the LTHC light-to-heat conversion layer can be heated by a laser to separate the silicon substrate 203 and the support substrate 201 from each other at the LTHC light-to-heat conversion layer.
[0071] As an example, the diffusion barrier layer 206 includes one layer or a stack of at least two layers selected from a tantalum nitride layer, a titanium nitride layer, a silicon nitride layer, and a silicon oxide layer.
[0072] As shown in FIG. 2, the steps of forming the stack structure 200 include: Figures 8 to 11
[0073] As shown in FIG. 2, the steps of forming the stack structure 200 include: Figure 8
[0074] As shown in FIG. 2, the steps of forming the stack structure 200 include: Figure 9
[0075] As shown in FIG. 2, the steps of forming the stack structure 200 include: Figure 10
[0076] As shown in FIG. 2, the steps of forming the stack structure 200 include: Figure 11
[0077] As shown in FIG. 2, the steps of forming the stack structure 200 include: Figure 8 Figure 12 As shown in FIG. 6, then step S2 is performed to polish the upper surface of the silicon substrate 203 to expose the TSV hole 204 completely. As the silicon substrate 203 is thinned to expose the TSV hole 204 completely, the copper particles A in the copper conductive pillar 205 are polished into the silicon substrate 203 around the TSV hole 204, as shown in FIG. 7. Figure 12
[0078] As shown in FIG. 6, then step S2 is performed to polish the upper surface of the silicon substrate 203 to expose the TSV hole 204 completely. As the silicon substrate 203 is thinned to expose the TSV hole 204 completely, the copper particles A in the copper conductive pillar 205 are polished into the silicon substrate 203 around the TSV hole 204, as shown in FIG. 7. Figure 8 Figure 13 As shown in FIG. 6, then step S2 is performed to polish the upper surface of the silicon substrate 203 to expose the TSV hole 204 completely. As the silicon substrate 203 is thinned to expose the TSV hole 204 completely, the copper particles A in the copper conductive pillar 205 are polished into the silicon substrate 203 around the TSV hole 204, as shown in FIG. 7.
[0079] As shown in FIG. 6, then step S2 is performed to polish the upper surface of the silicon substrate 203 to expose the TSV hole 204 completely. As the silicon substrate 203 is thinned to expose the TSV hole 204 completely, the copper particles A in the copper conductive pillar 205 are polished into the silicon substrate 203 around the TSV hole 204, as shown in FIG. 7. Figure 8 Figure 14 As shown in FIG. 6, then step S2 is performed to polish the upper surface of the silicon substrate 203 to expose the TSV hole 204 completely. As the silicon substrate 203 is thinned to expose the TSV hole 204 completely, the copper particles A in the copper conductive pillar 205 are polished into the silicon substrate 203 around the TSV hole 204, as shown in FIG. 7.
[0080] The wet etching process for forming the etching groove 207 can remove the copper particles diffused into the surface of the silicon substrate 203 in the previous process, and can also lay a foundation for the subsequent deposition of the protective layer on the upper surface of the copper conductive pillar 205. As an example, the etching solution used in the wet etching process can be any existing copper etching solution suitable for etching copper particles. In the present embodiment, the wet etching solution preferably includes phosphoric acid and hydrogen peroxide. The hydrogen peroxide can oxidize the copper into copper oxide, and the phosphoric acid can etch away the copper oxide, thereby achieving etching of the copper conductive pillar 205. As an example, the depth D of the etching groove is between 1% and 2% of the length of the copper conductive pillar. For example, when the length of the copper conductive pillar is 100 μm, the depth D of the etching groove is generally between 1 μm and 2 μm.
[0081] As shown in FIG. 6, then step S2 is performed to polish the upper surface of the silicon substrate 203 to expose the TSV hole 204 completely. As the silicon substrate 203 is thinned to expose the TSV hole 204 completely, the copper particles A in the copper conductive pillar 205 are polished into the silicon substrate 203 around the TSV hole 204, as shown in FIG. 7. Figure 8 Figure 16 As shown in FIG. 6, then step S2 is performed to polish the upper surface of the silicon substrate 203 to expose the TSV hole 204 completely. As the silicon substrate 203 is thinned to expose the TSV hole 204 completely, the copper particles A in the copper conductive pillar 205 are polished into the silicon substrate 203 around the TSV hole 204, as shown in FIG. 7.
[0082] As shown in FIG. 6, then step S2 is performed to polish the upper surface of the silicon substrate 203 to expose the TSV hole 204 completely. As the silicon substrate 203 is thinned to expose the TSV hole 204 completely, the copper particles A in the copper conductive pillar 205 are polished into the silicon substrate 203 around the TSV hole 204, as shown in FIG. 7. Figure 15 Figure 16 As shown in FIG. 6, then step S2 is performed to polish the upper surface of the silicon substrate 203 to expose the TSV hole 204 completely. As the silicon substrate 203 is thinned to expose the TSV hole 204 completely, the copper particles A in the copper conductive pillar 205 are polished into the silicon substrate 203 around the TSV hole 204, as shown in FIG. 7.
[0083] As shown in FIG. 6, then step S2 is performed to polish the upper surface of the silicon substrate 203 to expose the TSV hole 204 completely. As the silicon substrate 203 is thinned to expose the TSV hole 204 completely, the copper particles A in the copper conductive pillar 205 are polished into the silicon substrate 203 around the TSV hole 204, as shown in FIG. 7. Figure 15 As shown, a chemical vapor deposition process is performed to deposit a protective layer material 208 on the upper surface of the stack structure 200 to fill the etching recess 207;
[0084] As shown, a chemical mechanical polishing process is performed to polish the upper surface of the stack structure 200 to the upper surface of the silicon substrate 203 to form the protective layer 209 covering the upper surface of the copper conductive pillar 205. Figure 16
[0085] As an example, the material of the protective layer 209 can be a conventional silicon etching protective material with a preferable etching selectivity ratio with silicon. In the present embodiment, the material of the protective layer is preferably silicon oxide.
[0086] As shown, step S6 is then performed to etch the upper surface of the silicon substrate 203 to expose the copper conductive pillar 205. During this step, the copper conductive pillar 205 is not affected by the etching process due to the diffusion barrier layer 206 on the sidewall and the protective layer 209 on the top surface of the copper conductive pillar 205, thereby avoiding the diffusion of copper particles into the silicon substrate. The effectiveness of the silicon substrate etching process is thus ensured. As an example, a dry etching process can be performed to etch the silicon substrate 203. Figure 8 Figure 17 As shown, step S7 is finally performed to form an insulating layer 211 on the upper surface of the silicon substrate 203 by a chemical vapor deposition process.
[0087] As an example, the insulating layer 211 can be a single layer or a stack structure. For example, the insulating layer 211 can be a single layer of silicon nitride or silicon oxide, or a stack structure of silicon oxide and silicon nitride. Figure 8 Figure 19 As shown, as an example, the step of forming the insulating layer 211 includes:
[0088] As shown, first, a chemical vapor deposition process is performed to deposit an insulating layer material 210 on the upper surface of the stack structure 200;
[0089] As shown, then, a chemical mechanical polishing process is performed to polish the insulating layer material 210 and the protective layer 209 to expose the copper conductive pillar 205 and form the insulating layer 211 covering the silicon substrate 203. Figure 18 Figure 19 As an example, the step of forming the insulating layer 211 includes:
[0090] As shown, first, a chemical vapor deposition process is performed to deposit an insulating layer material 210 on the upper surface of the stack structure 200; Figure 18 As shown, then, a chemical mechanical polishing process is performed to polish the insulating layer material 210 and the protective layer 209 to expose the copper conductive pillar 205 and form the insulating layer 211 covering the silicon substrate 203.
[0091] Figure 19 As an example, the step of forming the insulating layer 211 includes:
[0092] The etching groove 207 formed by wet etching in the embodiment can remove the copper particles diffused into the surface of the silicon substrate 203 in the previous process and lay a foundation for the subsequent deposition of the protective layer on the upper surface of the copper conductive column 205. In addition, the etching groove 207 in combination with the protective layer 209 filled therein can effectively prevent the diffusion of copper particles into the silicon substrate during the etching of the silicon substrate 203. Thus, the possibility of diffusion of all copper conductive columns into the silicon substrate is avoided in the whole preparation process of the adapter plate, and the performance of the packaging structure is effectively improved.
[0093] Embodiment Two
[0094] The embodiment provides a packaging adapter plate prepared by the preparation method of the above embodiment one, and the beneficial effects thereof can be seen in the embodiment one, which will not be described here.
[0095] As shown in Figure 19 The packaging adapter plate comprises:
[0096] a support substrate 201 and a silicon substrate 203 bonded to the upper and lower sides of the separation layer 202;
[0097] a TSV hole 204 penetrating through the silicon substrate 203;
[0098] a copper conductive column 205 filled in the TSV hole 204 and protruding out of the TSV hole 204, and the copper in the copper conductive column 205 is not diffused into the surface of the silicon substrate 203;
[0099] a diffusion barrier layer 206 formed between the copper conductive column 205 and the sidewall of the TSV hole 204 and extending to the same level as the copper conductive column 205;
[0100] an insulating layer 211 formed on the surface of the silicon substrate 203 and completely covering the circumferential side of the copper conductive column 205.
[0101] As an example, the support substrate 201 comprises one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate and a ceramic substrate; and the separation layer 202 comprises a polymer layer or an adhesive layer.
[0102] As an example, the diffusion barrier layer 206 comprises one layer or a stack of at least two layers of a tantalum nitride layer, a titanium nitride layer, a silicon nitride layer and a silicon oxide layer.
[0103] As an example, the insulating layer 211 comprises one layer or a stack of two layers of a silicon nitride layer and a silicon oxide layer.
[0104] The embodiment also provides a semiconductor packaging structure comprising the packaging adapter plate as described above.
[0105] In summary, the application provides a packaging adapter plate and its manufacturing method, and a semiconductor packaging structure. The copper particles diffused into the surface of the silicon substrate in the previous process are removed by forming the etching groove by wet etching, and a foundation is laid for the subsequent deposition of the protective layer on the upper surface of the copper conductive column. In addition, the etching groove, in combination with the subsequent protective layer filled therein, can effectively prevent the diffusion of copper particles into the silicon substrate during the etching process of the silicon substrate. Thus, the possibility of all copper conductive columns diffusing into the silicon substrate is avoided during the entire manufacturing process of the adapter plate, and the performance of the packaging structure is effectively improved. Therefore, the application effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.
[0106] The above embodiments only exemplarily illustrate the principles and effects of the application, and are not intended to limit the application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed by the application should be covered by the claims of the application.
Claims
1. A method for preparing a conversion plate for encapsulation, characterized in that The preparation method comprises: providing a stack structure comprising, from bottom to top, a support substrate, a separation layer and a silicon substrate, wherein a TSV hole extending from bottom to top is formed in the silicon substrate, and a copper conductive column is filled in the TSV hole, and a diffusion barrier layer is formed between the copper conductive column and the side wall of the TSV hole; grinding the upper surface of the silicon substrate until the TSV hole is completely exposed; polishing the upper surface of the stack structure by using a chemical mechanical polishing process; etching the copper conductive column by a wet etching process to a preset depth to form an etching groove, and the wet etching solution removes the copper ground into the surface of the silicon substrate; filling the etching groove with a protective layer; etching the upper surface of the silicon substrate to expose the copper conductive column; forming an insulating layer on the upper surface of the silicon substrate by using a chemical vapor deposition process; wherein the step of forming the stack structure comprises: providing the silicon substrate and forming the TSV hole in the silicon substrate, wherein the TSV hole is a blind hole which does not penetrate the silicon substrate; forming the diffusion barrier layer on the side wall of the TSV hole; filling the TSV hole with copper material to form the copper conductive column; providing the support substrate and the separation layer, and bonding the support substrate and the silicon substrate with the TSV hole on one side based on the separation layer to form the stack structure.
2. The method of claim 1, wherein: The wet etching solution is a copper etching solution comprising phosphoric acid and hydrogen peroxide.
3. The method of claim 1, wherein The step of forming the protective layer comprises: depositing a protective layer material on the upper surface of the stack structure by using a chemical vapor deposition process until the etching groove is filled; polishing the upper surface of the stack structure to the upper surface of the silicon substrate by using a chemical mechanical polishing process to form the protective layer covering the upper surface of the copper conductive column.
4. The method of claim 1, wherein The step of forming the insulating layer comprises: depositing an insulating layer material on the upper surface of the stack structure by using a chemical vapor deposition process; polishing the insulating layer material and the protective layer to expose the copper conductive column by using a chemical mechanical polishing process to form an insulating layer covering the silicon substrate.
5. The method of claim 1, wherein: The depth of the etching groove is between 1% and 2% of the length of the copper conductive column, and the material of the protective layer is silicon oxide.
6. An adapter plate for packaging, characterized by The adapter plate is prepared by using the preparation method for the adapter plate for packaging according to any one of claims 1-5, comprising: a silicon substrate bonded to the upper side of the separation layer and a support substrate bonded to the lower side of the separation layer; a TSV hole penetrating the silicon substrate; a copper conductive column filling the TSV hole and protruding from the TSV hole, and the copper in the copper conductive column does not diffuse into the surface of the silicon substrate; a diffusion barrier layer formed between the copper conductive column and the side wall of the TSV hole and extending to the same level as the copper conductive column; an insulating layer formed on the surface of the silicon substrate and completely covering the circumferential side of the copper conductive column.
7. The board for encapsulation according to claim 6, characterized in that: The support substrate comprises one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate and a ceramic substrate; and the separation layer comprises a polymer layer or an adhesive layer.
8. The board for encapsulation of claim 6, wherein: The diffusion barrier layer comprises one layer or a stack of at least two layers of a tantalum nitride layer, a titanium nitride layer, a silicon nitride layer and a silicon oxide layer.
9. The board for encapsulation of claim 6, wherein: The insulating layer includes one or both of a stack of a silicon nitride layer and a silicon oxide layer.
10. A semiconductor package structure, comprising: A conversion board for packaging as claimed in any one of claims 6 to 9.