Display substrate, preparation method thereof and display device

Abstract

A display substrate and its fabrication method, and a display device, the display substrate comprising: a substrate; a driving circuit layer disposed on the substrate, the driving circuit layer including at least one first signal line; a light-emitting structure layer disposed on the side of the driving circuit layer away from the substrate, the light-emitting structure layer including a pixel defining layer and an organic light-emitting layer, the pixel defining layer defining a plurality of sub-pixel regions and having a first opening that at least partially exposes the driving circuit layer, the organic light-emitting layer being located in the sub-pixel regions and overlapping with the first opening of the pixel defining layer; and a color filter structure layer disposed on the side of the light-emitting structure layer away from the substrate, the color filter structure layer including a color filter and a black matrix, the black matrix having a second opening that at least partially exposes the first opening, the color filter being disposed within the second opening, the black matrix including a first sub-side, the orthographic projection of the first signal line on the substrate, the orthographic projection of the first sub-side on the substrate, and the orthographic projection of the color filter on the substrate having a first overlap.

Description

[0001] This case is a divisional application of patent application 202110764582.0, which was filed on July 7, 2021, with application number 202110764582.0 and the invention title "Display substrate and its preparation method, display device". Technical Field

[0002] This disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate, a method for preparing the substrate, and a display device. Background Technology

[0003] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices, possessing advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0004] This disclosure provides a display substrate and its preparation method, as well as a display device, which can improve the display effect of the display panel.

[0005] This disclosure provides a display substrate, comprising: a substrate; a driving circuit layer disposed on the substrate; a light-emitting structure layer disposed on the side of the driving circuit layer away from the substrate, the light-emitting structure layer including a pixel defining layer and an organic light-emitting layer, the pixel defining layer defining a plurality of sub-pixel regions and having a first opening that at least partially exposes the driving circuit layer, the organic light-emitting layer being located in the sub-pixel regions and overlapping with the first opening of the pixel defining layer; and a color filter structure layer disposed on the side of the light-emitting structure layer away from the substrate, the color filter structure layer including a color filter and a black matrix, the black matrix having a second opening that at least partially exposes the first opening, the color filter being disposed within the second opening, the black matrix including a first sub-side, the driving circuit layer including at least one first signal line, the orthographic projection of the first signal line on the substrate, the orthographic projection of the first sub-side on the substrate, and the orthographic projection of the color filter on the substrate having a first overlap.

[0006] The orthogonal projection of the color filter onto the substrate at least partially covers the orthogonal projection of the first opening of the pixel defining layer onto the substrate.

[0007] In an exemplary embodiment, in the third direction, the maximum thickness of the color filter is greater than the maximum thickness of the first sub-side, and the color filter at least partially covers the first sub-side, wherein the third direction is the direction along the substrate toward the color filter structure layer.

[0008] In an exemplary embodiment, the first sub-side has a stepped structure, and the color filter is closely attached to the edge of the black matrix near the side of the color filter.

[0009] In an exemplary embodiment, the black matrix has a second thickness l4 in a third direction, the second thickness being between 0.9 micrometers and 1.2 micrometers, the third direction being the direction along the substrate toward the color filter structure layer.

[0010] In an exemplary embodiment, the first sub-side has a broken line structure.

[0011] In an exemplary embodiment, the black matrix further includes a second sub-side disposed opposite to the first sub-side, the first sub-side and the second sub-side being asymmetrically disposed with respect to the center line of the sub-pixel region, the black matrix further includes a third sub-side and a fourth sub-side disposed opposite to each other, the first sub-side, the third sub-side, the second sub-side and the fourth sub-side being connected end to end, the third sub-side and the fourth sub-side having a straight strip shape or having a generally straight strip shape.

[0012] In an exemplary embodiment, the first sub-side includes a third sub-segment that is neither parallel nor perpendicular to the first direction and the second direction, and the black matrix includes at least one of the third sub-segments.

[0013] In an exemplary embodiment, the first sub-side has multiple bends, and the number of bends on the first sub-side increases the further away from the center line of the sub-pixel region.

[0014] In an exemplary embodiment, the first signal line has a broken line structure, the black matrix has multiple sub-sides, and the number of bends of the first signal line in at least one sub-pixel region is less than the number of bends of at least one sub-side of the black matrix, but greater than the number of bends of at least one other sub-side of the black matrix.

[0015] In an exemplary embodiment, the sub-pixel region includes a first sub-pixel region, a second sub-pixel region, and a third sub-pixel region. The first sub-pixel region includes a first light-emitting unit and a first color filter. The second sub-pixel region includes a second light-emitting unit and a second color filter. The third sub-pixel region includes a third light-emitting unit and a third color filter. The orthographic projection of the first color filter on the substrate covers the orthographic projection of the first light-emitting unit on the substrate. The orthographic projection of the second color filter on the substrate covers the orthographic projection of the second light-emitting unit on the substrate. The orthographic projection of the third color filter on the substrate covers the orthographic projection of the third light-emitting unit on the substrate. The second light-emitting unit includes at least two separately disposed sub-light-emitting units.

[0016] In an exemplary embodiment, the display substrate further includes an encapsulation layer disposed on the side of the color filter structure layer away from the light-emitting structure layer, wherein the orthographic projection of the encapsulation layer on the substrate covers the orthographic projection of the color filter structure layer on the substrate.

[0017] In an exemplary embodiment, the sub-pixel region includes a first sub-pixel region, a second sub-pixel region, a third sub-pixel region, and a fourth sub-pixel region. The first sub-pixel region includes a first light-emitting unit and a first color filter. The second sub-pixel region includes a second light-emitting unit and a second color filter. The third sub-pixel region includes a third light-emitting unit and a third color filter. The fourth sub-pixel region includes a fourth light-emitting unit and a fourth color filter. The orthographic projection of the first color filter onto the substrate covers the orthographic projection of the first light-emitting unit onto the substrate. The orthographic projection of the second color filter onto the substrate covers the orthographic projection of the second light-emitting unit onto the substrate. The orthographic projection of the third color filter onto the substrate covers the orthographic projection of the third light-emitting unit onto the substrate. The orthographic projection of the fourth color filter onto the substrate covers the orthographic projection of the fourth light-emitting unit onto the substrate. The encapsulation layer covers the first color filter, the second color filter, and the third color filter. The fourth color filter is disposed in the same layer and with the same material as at least a portion of the encapsulation layer.

[0018] In an exemplary embodiment, the first sub-pixel region is a red sub-pixel region, the second sub-pixel region is a green sub-pixel region, and the third sub-pixel region is a blue sub-pixel region.

[0019] In an exemplary embodiment, the areas of sub-pixel regions of different colors are different.

[0020] In an exemplary embodiment, the display substrate further includes a blanking structure, the orthographic projection of the blanking structure on the substrate not overlapping the orthographic projection of the sub-pixel region on the substrate.

[0021] In an exemplary embodiment, the ratio of the area of ​​the blank structure to the area of ​​the sub-pixel region is greater than or equal to 45%.

[0022] In an exemplary embodiment, the first sub-side has a first width along a first direction; the first signal line has a second width along the first direction; the orthographic projection of the first signal line on the substrate and the orthographic projection of the first sub-side on the substrate have a first overlap; the first overlap has a third width along the first direction; the first width is l1, the second width is l2, and the third width is l3.

[0023] The sub-pixel region includes a center line and a first reference line along the first direction. The distance between the first reference line and the center line of the sub-pixel region is k. The length of the sub-pixel region along the first direction is L. Then: 6*l2<L<7*l2;20*l3<L<35*l3;3.5*l3<l2≤4*l3;

[0024] In an exemplary embodiment, the first width is l1, the second width is l2, the sub-pixel region includes a center line and a first reference line along the first direction, the distance between the first reference line and the center line of the sub-pixel region is k, and the length of the sub-pixel region along the first direction is L. Then: 10*l1≤L≤10*l2; 2*k<L≤3*k.

[0025] In an exemplary embodiment, the driving circuit layer further includes a repair structure, the orthographic projection of the repair structure on the substrate at least partially overlapping the orthographic projection of the blank structure on the substrate.

[0026] In an exemplary embodiment, the plurality of sub-pixel regions include red sub-pixel regions and blue sub-pixel regions, wherein the repair structures of the red sub-pixel regions and the blue sub-pixel regions are at least partially symmetrical and at least partially asymmetrical.

[0027] In an exemplary embodiment, the light-emitting structure layer further includes an anode, the first opening at least partially exposing the anode, and at least one sub-pixel region comprising a plurality of discretely arranged sub-anode blocks.

[0028] In an exemplary embodiment, the discretely arranged plurality of sub-anode blocks include two.

[0029] In an exemplary embodiment, the two sub-anode blocks have different morphologies.

[0030] In an exemplary embodiment, the drive circuit layer includes an anode hole, which is electrically connected to the two sub-anode blocks respectively.

[0031] In an exemplary embodiment, the drive circuit layer further includes a repair structure, wherein the two sub-anode blocks are electrically connected to each other and to the repair structure.

[0032] This disclosure also provides a display device, including: a display substrate as described above.

[0033] This disclosure also provides a method for preparing a display substrate, the method comprising:

[0034] A driving circuit layer is formed on a substrate, the driving circuit layer including at least one first signal line;

[0035] A light-emitting structure layer is formed on the side of the driving circuit layer away from the substrate. The light-emitting structure layer includes a pixel defining layer and an organic light-emitting layer. The pixel defining layer defines a plurality of sub-pixel regions and has a first opening that at least partially exposes the driving circuit layer. The organic light-emitting layer is located in the sub-pixel regions and overlaps with the first opening of the pixel defining layer.

[0036] A color filter structure layer is formed on the side of the light-emitting structure layer away from the substrate. The color filter structure layer includes a color filter and a black matrix. The black matrix has a second opening that at least partially exposes the first opening. The color filter is disposed within the second opening. The black matrix includes a first sub-side. The orthographic projection of the first signal line on the substrate, the orthographic projection of the first sub-side on the substrate, and the orthographic projection of the color filter on the substrate have a first overlap.

[0037] The display substrate and its fabrication method and display device provided in this disclosure, by setting a driving circuit layer, a light-emitting structure layer and a color filter structure layer, wherein the driving circuit layer includes at least one first signal line, the color filter structure layer includes a color filter and a black matrix, the black matrix includes a first sub-side, and the orthographic projection of the first signal line on the substrate, the orthographic projection of the first sub-side on the substrate and the orthographic projection of the color filter on the substrate have a first overlap, thereby reducing reflectivity and improving light purity. The display substrate of this disclosure does not require the use of a polarizer, thereby reducing the cost of the display substrate, reducing the thickness of the display substrate, improving the bendability of the display substrate, and reducing grating effects, such as diffraction effect, interference effect and scattering color separation, thereby improving the display effect.

[0038] Other features and advantages of this disclosure will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the disclosure. Other advantages of this disclosure may be realized and obtained by means of the methods described in the description and the accompanying drawings. Attached Figure Description

[0039] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0040] Figure 1 This is a schematic diagram of the structure of a display device according to an exemplary embodiment of the present disclosure;

[0041] Figures 2 to 5 This is a schematic diagram of pixel arrays of four display substrates according to exemplary embodiments of the present disclosure;

[0042] Figure 6 This is a schematic diagram of the structure of a sub-pixel, which is an exemplary embodiment of the present disclosure;

[0043] Figure 7 for Figure 6 A schematic diagram of the cross-sectional structure of the OO' region;

[0044] Figure 8 This is a schematic diagram of the structure of a pixel driving circuit for a display substrate, which is an exemplary embodiment of the present disclosure.

[0045] Figure 9 This is a schematic diagram of the structure of the first sub-side of the black matrix in a sub-pixel, as an exemplary embodiment of the present disclosure.

[0046] Figure 10 This is a schematic diagram of the structure of the first sub-side of the black matrix in another sub-pixel, as an exemplary embodiment of the present disclosure;

[0047] Figure 11 This is a schematic diagram illustrating the overlapping structure of a first signal line and a first sub-side in a sub-pixel, as an exemplary embodiment of this disclosure.

[0048] Figure 12 for Figure 11 Schematic diagram of the cross-sectional structure of region aa' in the middle;

[0049] Figure 13 This is a schematic diagram of the structure of a first opening and a second opening in a sub-pixel, which is an exemplary embodiment of the present disclosure.

[0050] Figure 14 This is a schematic diagram of the structure of a color filter in a sub-pixel, as an exemplary embodiment of the present disclosure;

[0051] Figure 15 This is a schematic diagram of the overlapping structure of the first signal line and the first sub-side in another sub-pixel in an exemplary embodiment of the present disclosure;

[0052] Figure 16 This is a schematic diagram of the structure of the first sub-side in another sub-pixel, as an exemplary embodiment of the present disclosure;

[0053] Figure 17This is a schematic diagram illustrating the structure of a first sub-side and a second sub-side in a sub-pixel, as an exemplary embodiment of the present disclosure.

[0054] Figure 18 This is a schematic diagram illustrating the structure of a second sub-side in a sub-pixel, as an exemplary embodiment of the present disclosure.

[0055] Figure 19 This is a schematic diagram illustrating the structure of a black matrix in adjacent pixels, as an exemplary embodiment of this disclosure.

[0056] Figure 20 This is a schematic diagram illustrating the structure of a black matrix in adjacent pixels as an exemplary embodiment of this disclosure;

[0057] Figure 21 This is a schematic diagram of a color filter structure in different color sub-pixels, as an exemplary embodiment of the present disclosure;

[0058] Figure 22 This is a schematic diagram of an encapsulation structure in a sub-pixel of a different color, as an exemplary embodiment of the present disclosure;

[0059] Figure 23 This is a schematic diagram of a blanking structure in a sub-pixel, as an exemplary embodiment of the present disclosure.

[0060] Figure 24 This is a schematic diagram of a repair structure in a sub-pixel, as an exemplary embodiment of the present disclosure;

[0061] Figure 25 This is a schematic diagram of a repair structure in another sub-pixel, as an exemplary embodiment of the present disclosure;

[0062] Figure 26 This is a schematic diagram of a repair structure in a sub-pixel, as an exemplary embodiment of the present disclosure;

[0063] Figure 27 This is a schematic diagram of the structure of an anode in a sub-pixel, as an exemplary embodiment of the present disclosure;

[0064] Figure 28 for Figure 27 A schematic diagram of the cross-sectional structure of the bb' region. Detailed Implementation

[0065] To make the objectives, technical solutions, and advantages of this disclosure clearer, embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0066] In the accompanying drawings, the size of the constituent elements, the thickness of the layers, or the area are sometimes exaggerated for clarity. Therefore, one aspect of this disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0067] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0068] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0069] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0070] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0071] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0072] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0073] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0074] In this specification, "two angles are approximately equal" means that the ratio between the two angles is greater than 0.9 and less than 1.1. Therefore, it also includes the range where the ratio between the two angles is greater than 0.95 and less than 1.05. Thus, the sum of two angles is approximately equal to 360°, which can include the range where the sum of the two angles is greater than 342° and less than 378°.

[0075] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0076] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors. Figure 1 This is a schematic diagram of the structure of a display device as an exemplary embodiment of the present disclosure. Figure 1As shown, the display device may include a timing controller, a data signal driver, a scan signal driver, and a pixel array. The pixel array may include multiple scan signal lines (S1 to Sm), multiple data signal lines (D1 to Dn), and multiple sub-pixels Pxij. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals of specifications suitable for the data signal driver to the data signal driver, and may provide clock signals, scan start signals, etc., of specifications suitable for the scan signal driver to the scan signal driver. The data signal driver may use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to the data signal lines D1, D2, D3, ..., Dn. For example, the data signal driver may use a clock signal to sample the grayscale values ​​and apply data voltages corresponding to the grayscale values ​​to the data signal lines D1 to Dn on a sub-pixel row basis, where n can be a natural number. The scan signal driver may generate scan signals to be provided to the scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc., from the timing controller. For example, a scan signal driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, the scan signal driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals provided in the form of on-level pulses to the next stage circuit under the control of a clock signal, where m can be a natural number. A sub-pixel array can include multiple pixel sub-Pxij. Each pixel sub-Pxij can be connected to a corresponding data signal line and a corresponding scan signal line, where i and j can be natural numbers. A sub-pixel Pxij can refer to a sub-pixel whose transistor is connected to the i-th scan signal line and connected to the j-th data signal line.

[0077] Figures 2 to 4 This is a schematic diagram of the planar structure of three display substrates according to embodiments of this disclosure. Figures 2 to 4As shown, the display substrate may include multiple pixel units P arranged in a matrix. At least one of the multiple pixel units P includes a first light-emitting unit (sub-pixel) P1 emitting a first color light, a second light-emitting unit P2 emitting a second color light, and a third light-emitting unit P3 emitting a third color light. Each of the first light-emitting unit P1, the second light-emitting unit P2, and the third light-emitting unit P3 includes a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first light-emitting unit P1, the second light-emitting unit P2, and the third light-emitting unit P3 are respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuits are configured to receive the data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting devices in the first light-emitting unit P1, the second light-emitting unit P2, and the third light-emitting unit P3 are respectively connected to the pixel driving circuit of their respective light-emitting unit. The light-emitting devices are configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of their respective light-emitting unit.

[0078] In an exemplary embodiment, the first light-emitting unit may be a red (R) light-emitting unit, the second light-emitting unit may be a green (G) light-emitting unit, and the third light-emitting unit may be a blue (B) light-emitting unit. This disclosure does not limit the scope of the invention.

[0079] In an exemplary implementation, such as Figure 5 As shown, at least one of the plurality of pixel units P further includes a fourth light-emitting unit P4 that emits a fourth color light. Exemplarily, the fourth light-emitting unit P4 can be a white (W) light-emitting unit, which is not limited herein. The fourth light-emitting unit P4 may include a pixel driving circuit and a light-emitting device. The pixel driving circuit in the fourth light-emitting unit P4 is connected to a scan signal line, a data signal line, and a light-emitting signal line, respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting device in the fourth light-emitting unit P4 is connected to the pixel driving circuit in the fourth light-emitting unit P4, and the light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the light-emitting unit.

[0080] In an exemplary embodiment, the shape of the light-emitting unit in the pixel unit can be rectangular, rhomboid, pentagonal, or hexagonal. When the pixel unit includes three light-emitting units, the three light-emitting units can be arranged horizontally side by side, vertically side by side, or in a triangular arrangement. When the pixel unit includes four light-emitting units, the four light-emitting units can be arranged horizontally side by side, vertically side by side, or in a square arrangement. This disclosure does not limit the arrangement.

[0081] With the continuous development of display technology, OLED technology is increasingly being applied to transparent displays. Transparent displays are an important area of ​​personalized display technology, referring to image display in a transparent state. Viewers can see not only the image on the display device but also the scene behind it, enabling virtual reality (VR), augmented reality (AR), and 3D display functions. Transparent display devices using AMOLED technology typically divide each pixel into a display area and a transparent area. The display area houses the pixel driving circuitry and light-emitting elements to display the image, while the transparent area allows light to pass through.

[0082] Monitors larger than 27 inches can be considered large-screen monitors. In large-size transparent display products, when external light passes through the gap between two adjacent pixel columns, it produces strong diffraction, interference, and scattering color separation effects, resulting in poor display quality of large-size transparent display panels.

[0083] An exemplary embodiment of this disclosure provides a display substrate, which may include a substrate, a driving circuit layer disposed on the substrate, the driving circuit layer including at least one first signal line; a light-emitting structure layer disposed on the side of the driving circuit layer away from the substrate, the light-emitting structure layer including a pixel defining layer and an organic light-emitting layer, the pixel defining layer defining a plurality of sub-pixel regions and having a first opening that at least partially exposes the driving circuit layer, the organic light-emitting layer being located in the sub-pixel regions and overlapping with the first opening of the pixel defining layer; and a color filter structure layer disposed on the side of the light-emitting structure layer away from the substrate, the color filter structure layer including a color filter and a black matrix, the black matrix having a second opening that at least partially exposes the first opening, the color filter being disposed within the second opening, the black matrix including a first sub-side, and the orthographic projection of the first signal line on the substrate, the orthographic projection of the first sub-side on the substrate, and the orthographic projection of the color filter on the substrate having a first overlap.

[0084] The display substrate of this embodiment comprises a driving circuit layer, a light-emitting structure layer, and a color filter structure layer. The driving circuit layer includes at least one first signal line, and the color filter structure layer includes a color filter and a black matrix. The black matrix includes a first sub-side. The orthographic projection of the first signal line on the substrate, the orthographic projection of the first sub-side on the substrate, and the orthographic projection of the color filter on the substrate have a first overlap, which reduces reflectivity and improves light purity. The display substrate of this embodiment does not require the use of a polarizer, which reduces the cost of the display substrate, reduces the thickness of the display substrate, improves the bendability of the display substrate, and reduces grating effects such as diffraction, interference, and scattering color separation, thereby improving the display effect.

[0085] Figure 6This is a schematic diagram of the structure of a display substrate provided in an embodiment of the present disclosure. Figure 7 for Figure 6 A cross-sectional view of the OO' region illustrates the structure of a sub-pixel, as shown below. Figure 6 and Figure 7 As shown, an exemplary embodiment of this disclosure provides a display substrate, including:

[0086] Substrate 101;

[0087] A driving circuit layer 102 disposed on a substrate 101;

[0088] A light-emitting structure layer 103 is disposed on the side of the driving circuit layer 102 away from the substrate 101. The light-emitting structure layer 103 includes a pixel defining layer 103b and an organic light-emitting layer 103c. The pixel defining layer 103b defines a plurality of sub-pixel regions and has a first opening K1 that at least partially exposes the driving circuit layer 102. The organic light-emitting layer 103c is located in the sub-pixel regions and overlaps with the first opening K1 of the pixel defining layer 103b.

[0089] And a color filter structure layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101. The color filter structure layer 104 includes a color filter 104b and a black matrix 104a. The black matrix 104a has a second opening K2 that at least partially exposes the first opening K1. The color filter 104b is disposed in the second opening K2. The black matrix 104a includes a first sub-side 1041 and the first sub-side 1041 has a zigzag structure.

[0090] In an exemplary embodiment, the display substrate further includes an encapsulation layer 105 disposed on the side of the color filter structure layer 104 away from the light-emitting structure layer 103. In some possible implementations, the display substrate may include other film layers, such as spacers, etc., which are not limited herein.

[0091] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The driving circuit layer 102 of each sub-pixel may include a plurality of transistors and storage capacitors constituting a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C or 7T1C structure. Figure 8 This is a schematic diagram of an equivalent circuit for a pixel driving circuit. (Example) Figure 8 As shown, the pixel driving circuit is a 3T1C structure, which may include three transistors (first transistor T1, second transistor T2, and third transistor T3) and one storage capacitor C. STIt has six signal lines (data signal line Dn, first scan signal line Gn, second scan signal line Sn, compensation line Se, first power line VDD, and second power line VSS). In an exemplary embodiment, the first transistor T1 is a switching transistor, the second transistor T2 is a driving transistor, and the third transistor T3 is a compensation transistor. The gate electrode of the first transistor T1 is coupled to the first scan signal line Gn, the first electrode of the first transistor T1 is coupled to the data signal line Dn, and the second electrode of the first transistor T1 is coupled to the gate electrode of the second transistor T2. The first transistor T1 is used to receive the data signal transmitted by the data signal line Dn under the control of the first scan signal line Gn, so that the gate electrode of the second transistor T2 receives the data signal. The gate electrode of the second transistor T2 is coupled to the second electrode of the first transistor T1, the first electrode of the second transistor T2 is coupled to the first power line VDD, and the second electrode of the second transistor T2 is coupled to the first electrode of the OLED. The second transistor T2 is used to generate a corresponding current at its second electrode under the control of the data signal received at its gate electrode. The gate electrode of the third transistor T3 is coupled to the second scan signal line Sn. The first electrode of the third transistor T3 is connected to the compensation line Se. The second electrode of the third transistor T3 is coupled to the second electrode of the second transistor T2. The third transistor T3 is used to extract the threshold voltage Vth and mobility of the second transistor T2 in response to the compensation timing, so as to compensate for the threshold voltage Vth. The first electrode of the OLED is coupled to the second electrode of the second transistor T2. The second electrode of the OLED is coupled to the second power line VSS. The OLED is used to emit light of corresponding brightness in response to the current at the second electrode of the second transistor T2. Storage capacitor C ST The first electrode is coupled to the gate electrode of the second transistor T2, and the storage capacitor C ST The second terminal is coupled to the second terminal of the second transistor T2, and the storage capacitor C ST Used to store the potential of the gate electrode of the second transistor T2.

[0092] In an exemplary embodiment, the first power line VDD continuously provides a high-level signal, and the second power line VSS continuously provides a low-level signal. The first transistor T1 to the third transistor T3 can be P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit simplifies the process flow, reduces the manufacturing difficulty of the display panel, and improves product yield. In some possible implementations, the first transistor T1 to the third transistor T3 may include both P-type and N-type transistors. In an exemplary embodiment, the light-emitting device can be an organic light-emitting diode (OLED), including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode).

[0093] In an exemplary embodiment, the light-emitting structure layer 103 may include an anode 103a, a pixel defining layer 103b, an organic light-emitting layer 103c, and a cathode 103d. The pixel defining layer 103b defines a plurality of sub-pixel regions and has a first opening K1 that at least partially exposes the driving circuit layer 102. The anode 103a is connected to the drain electrode of a transistor in the driving circuit layer 102 through a via. The organic light-emitting layer 103c is connected to the anode 103a, and the cathode 103d is connected to the organic light-emitting layer 103c. The organic light-emitting layer 103c emits light of a corresponding color under the drive of the anode 103a and the cathode 103d. The color filter structure layer 104 may include a black matrix 104a and a color filter 104b. The black matrix 104a has a second opening K2 that at least partially exposes the first opening K1, and the color filter 104b is disposed within the second opening K2. The encapsulation layer 105 may include a first encapsulation layer and a second encapsulation layer stacked together. The first encapsulation layer may be made of organic materials, and the second encapsulation layer may be made of inorganic materials, which can ensure that external moisture cannot enter the light-emitting structure layer and the color filter structure layer.

[0094] Figure 9 This is a schematic diagram illustrating the structure of the first sub-side of a black matrix in a sub-pixel region, as an exemplary embodiment of this disclosure. (See diagram below.) Figure 6 and Figure 9 As shown, in an exemplary embodiment, within a sub-pixel region, the black matrix includes a first sub-side 1041, which has a certain width along a first direction and has a polygonal structure with multiple bends. The number of bends increases in the region farther away from the center line A of the sub-pixel region.

[0095] The display substrate of this embodiment has a zigzag structure on the first sub-side 1041 of the black matrix. The number of zigzags increases as the distance from the center line A of the sub-pixel increases, which further reduces the diffraction and interference effects of the display panel and improves the display effect.

[0096] like Figure 6 As shown, the sub-pixel region has sub-sides I and III arranged along a first direction, and sub-sides II and IV arranged along a second direction, with sub-sides I, II, III, and IV connected end-to-end. In this embodiment, the sub-side is defined as the outer contour line of the sub-pixel region (the outer contour line is the boundary away from the center of the sub-pixel region). For example, if the outer contour line of the black matrix is ​​the outermost contour line of the sub-pixel region in a certain direction, then the sub-side of the sub-pixel in that direction is the outer contour line of the black matrix; and if the outer contour line of the pixel boundary layer is the outermost contour line of the sub-pixel region in a certain direction, then the sub-side of the sub-pixel in that direction is the outer contour line of the pixel boundary layer.

[0097] In an exemplary embodiment, the sub-pixel region has a center line A, which can be defined as the center line of two oppositely arranged sub-sides. In an exemplary embodiment, if one or both of the two oppositely arranged sub-sides have a polyline segment, the center line of the two polyline segments that are furthest apart from each other in the two oppositely arranged sub-sides is selected as the center line of the sub-pixel region. For example, as shown... Figure 6 As shown, the two oppositely positioned sub-sides can be sub-side I and sub-side III, or they can be sub-side II and sub-side IV. The following explanation will use sub-side II and sub-side IV as the two oppositely positioned sub-sides.

[0098] In an exemplary embodiment, the length of the sub-pixel region along the first direction is L, such as... Figure 6 As shown, the length L of the sub-pixel region along the first direction can be defined as the farthest distance between two opposite edges of the sub-pixel region along the first direction, that is, the distance between the leftmost edge and the rightmost edge of the sub-pixel region. A first reference line B can be set at a distance k from the center line A. The distance k between the center line A and the first reference line B is the length of the shortest line segment between the center line A and the first reference line B. In this embodiment, since the center line A and the first reference line B are parallel, the distance k between the center line A and the first reference line B is the length of the line segment perpendicular to the center line A and the first reference line B between them. The sub-pixel region may also include a second reference line C, a third reference line D, and a fourth reference line E. The sub-side IV has a sub-boundary m furthest from the center line A (if the sub-side IV is a straight line, then the sub-boundary m is the sub-side IV). The fourth reference line E overlaps with the sub-boundary m. In other words, the orthogonal projection of the fourth reference line E onto the substrate overlaps with the orthogonal projection of the sub-boundary m of sub-pixel 10, which is furthest from the center line on a certain sub-side, onto the substrate. The distances between each pair of the first reference line B and the second reference line C, the second reference line C and the third reference line D, and the third reference line D and the fourth reference line E are the same, as shown below. Figure 6 or Figure 9 As shown, the distance between the first reference line B and the second reference line C is n1, the distance between the second reference line C and the third reference line D is n2, and the distance between the third reference line D and the fourth reference line E is n3. In the exemplary embodiment, n1 = n2 = n3; k + n1 + n2 + n3 = L / 2. In this embodiment, the center line A, the first reference line B, the second reference line C, the third reference line D, and the fourth reference line E all extend along the second direction.

[0099] In an exemplary embodiment, within a sub-pixel region, the black matrix 104a has at least one first sub-side 1041, which has a certain width along a first direction. The first sub-side 1041 has multiple bends. The number of bends x between the center line A and the first reference line B, the number of bends y between the first reference line B and the second reference line C, and the number of bends z between the second reference line C and the third reference line D satisfy the following condition: x ≤ y ≤ z.

[0100] In this embodiment, within a range where the vertical distance from the center line A is less than or equal to k (i.e., between the center line A and the first reference line B), the number of bends included in the first sub-side 1041 is x; the bends described in this embodiment refer to angles less than 360° and not equal to 180° towards the center line A. Within a range where the vertical distance from the center line is between k and (k + (L / 2 - k) / 3) (i.e., between the first reference line B and the second reference line C), the number of bends included in the first sub-side 1041 is y; within a range where the vertical distance from the center line is between (k + (L / 2 - k) / 3) and (k + 2(L / 2 - k) / 3) (i.e., between the second reference line C and the third reference line D), the number of bends included in the first sub-side 1041 is z; wherein x, y, and z satisfy the following condition: x ≤ y ≤ z.

[0101] In another exemplary embodiment, the angle is not equal to 90°. That is, the angle refers to an angle less than 360° and not equal to 180° and 90° toward the center line A.

[0102] In another exemplary embodiment, the angle is an obtuse angle, that is, an angle less than 360° and greater than 90° and not equal to 180° toward the center line A.

[0103] In another exemplary embodiment, the number of bends x between the center line A and the first reference line B, the number of bends y between the first reference line B and the second reference line C, and the number of bends z between the second reference line C and the third reference line D of the first sub-side 1041 satisfy the following conditions: x≥3, y≥3, z≥3.

[0104] In an exemplary embodiment, within a range where the vertical distance from the center line A is less than or equal to k, the first sub-side 1041 includes at least three bends, and at least two of the at least three bends are approximately equal.

[0105] Within a range of k to (k+(L / 2-k) / 3) from the vertical distance of the centerline A, the first sub-side 1041 includes at least three bends, and at least two of the at least three bends are approximately equal.

[0106] Within a range of (k+(L / 2-k) / 3) to (k+2(L / 2-k) / 3) from the vertical distance of the centerline A, the first sub-side 1041 includes at least three bends, and at least two of the at least three bends are approximately equal.

[0107] For example, such as Figure 10 As shown, within a range where the vertical distance from center line A is less than or equal to k (i.e., between center line A and the first reference line B), the first sub-side 1041 includes at least three bends: x1, x2, and x3, with two of the bends having approximately equal angles; for example, x2 and x3 are approximately equal. Within a range where the vertical distance from center line A is between k and (k + (L / 2 - k) / 3) (i.e., between the first reference line B and the second reference line C), the first sub-side 1041 includes at least three bends: y1, y2, and y3, with two of the bends having approximately equal angles; for example, y2 and y3 are approximately equal. Within a range of (k+(L / 2-k) / 3) to (k+2(L / 2-k) / 3) from the vertical distance of the center line A (i.e., between the second reference line C and the third reference line D), the first sub-side 1041 includes at least three bends: z1, z2, and z3, and two of the bends are approximately equal in angle. For example, z1 and z4 are approximately equal.

[0108] In another exemplary embodiment, the first sub-side 1041 has at least one first bend angle within a vertical distance of k from the center line A; the first sub-side 1041 has at least one second bend angle within a vertical distance of k from the center line to (k+(L / 2-k) / 3); and the first sub-side 1041 has at least one third bend angle within a vertical distance of (k+(L / 2-k) / 3) from (k+2(L / 2-k) / 3), wherein the angles of the first bend angle, the second bend angle, and the third bend angle are approximately equal.

[0109] For example, such as Figure 10 As shown, within a range where the vertical distance from the center line A is less than or equal to k, the first sub-side 1041 has a first bend angle x1 = 135°; within a range where the vertical distance from the center line A is k to (k + (L / 2 - k) / 3), the first sub-side 1041 has a second bend angle y1 = 135°; and within a range where the vertical distance from the center line A is (k + (L / 2 - k) / 3) to (k + 2(L / 2 - k) / 3), the first sub-side 1041 has a third bend angle z1 = 135°. This embodiment of the present disclosure makes the angles of some bends in the black matrix approximately equal, which is more conducive to the realization of the process.

[0110] In another exemplary embodiment, the number of bends x between the center line A and the first reference line B, the number of bends y between the first reference line B and the second reference line C, and the number of bends z between the second reference line C and the third reference line D of the first sub-side 1041 satisfy the following conditions: x≥3, y≥4, z≥5.

[0111] For example, such as Figure 10 As shown, within a vertical distance of k from the center line A, the black matrix 104a has three bends x1, x2, and x3; within a vertical distance of k to (k + (L / 2 - k) / 3) from the center line A, the black matrix 104a has four bends y1, y2, y3, and y4; and within a vertical distance of (k + (L / 2 - k) / 3) to (k + 2(L / 2 - k) / 3) from the center line A, the black matrix 104a has six bends z1, z2, z3, z4, z5, and z6. This embodiment of the present disclosure increases the number of bends the further away from the sub-pixel center line, thus mitigating grating effects such as diffraction, interference, and scattering color separation.

[0112] In another exemplary embodiment, within a range where the vertical distance from center line A is less than or equal to k (i.e., between center line A and the first reference line B), the black matrix 104a includes at least three bends: x1, x2, and x3, wherein x2 and x3 are approximately equal, and x1 + x2 is approximately equal to 360°; within a range where the vertical distance from center line A is between k and (k + (L / 2 - k) / 3) (i.e., between the first reference line B and the second reference line C), the black matrix 104a includes at least four bends: y1, y2, y3, and y4, wherein y1 and y2 are approximately equal, and y3 + y4 is approximately equal to 360°; within a range where the vertical distance from center line A is between (k + (L / 2 - k) / 3) and (k + 2(L / 2 - k) / 3) (i.e., between the second reference line C and the third reference line D), the black matrix 104a includes at least four bends: z1 z2, z3, and z4, where z1 is approximately equal to z2, and z3 + z4 is approximately equal to 360°.

[0113] For example, x1 is approximately equal to 135°, and x2 is approximately equal to 225°. For example, y1 is approximately equal to 135°, and y3 is approximately equal to 225°.

[0114] In another exemplary embodiment, within a range where the vertical distance from the center line A is less than or equal to k (i.e., between the center line A and the first reference line B), the black matrix 104a includes at least three bends: x1, x2, and x3, wherein x1, x2, and x3 are approximately equal. In this embodiment, making some angles of the black matrix 104a approximately equal facilitates process implementation.

[0115] In another exemplary embodiment, such as Figure 10 As shown, within a range where the vertical distance from the center line A is less than or equal to k (i.e., between the center line A and the first reference line B), the black matrix 104a includes at least three bends: x1, x2, and x3, which are n times 45 degrees, where n = 3 or 5. In this embodiment, making some angles of the black matrix 104a integer multiples of 45 degrees is beneficial for process implementation.

[0116] In one exemplary embodiment, Figure 12 for Figure 11 A schematic diagram of the cross-sectional structure of region aa' in the middle. (See diagram below.) Figure 11 and Figure 12 As shown, the display substrate includes a substrate 101, a driving circuit layer 102 disposed on the substrate 101, a light-emitting structure layer 103 (including a pixel defining layer, an organic light-emitting layer, an anode, and a cathode, etc.) disposed on the driving circuit layer 102, and a color filter structure layer 104 disposed on the light-emitting structure layer 103. The color filter structure layer 104 includes a black matrix 104a, and the black matrix 104a includes at least one first sub-side 1041. The driving circuit layer 102 includes at least one first signal line 1021, the first signal line 1021 having a second width l2 along a first direction, and the first sub-side 1041 having a first width l1 along the first direction. The orthographic projection of the first signal line 1021 on the substrate and the orthographic projection of the first sub-side 1041 on the substrate have a first overlap, and the first overlap has a third width l3 along the first direction.

[0117] The widths mentioned above satisfy the following relationship:

[0118] 10*l1≤L≤10*l2.

[0119] 2*k<L≤3*k.

[0120] For example, L = 220 μm, l1 = 12-20 μm, k is approximately 74 μm, l3 is approximately 8 μm, and l2 is approximately 32 μm.

[0121] In another exemplary embodiment, 6*l2 < L < 7*l2.

[0122] In another exemplary embodiment, 20*l3 < L < 35*l3.

[0123] In another exemplary embodiment, 3.5*l3<l2≤4*l3.

[0124] In one exemplary embodiment, the first signal line 1021 has a broken line structure, the black matrix has multiple sub-sides, and the number of bends of the first signal line in any sub-pixel region is less than the number of bends of at least one sub-side of the black matrix, but greater than the number of bends of at least one other sub-side of the black matrix.

[0125] Combination Figure 6 and Figure 11 As shown, the first signal line 1021 has a broken line structure, and the black matrix has sub-side I, sub-side II, sub-side III and sub-side IV. The number of bends of the first signal line in any sub-pixel region is less than the number of bends of at least one sub-side (such as sub-side II and sub-side IV) of the black matrix, but greater than the number of bends of at least one other sub-side (such as sub-side I and sub-side III) of the black matrix.

[0126] In one exemplary embodiment, such as Figure 12 As shown, in the third direction (i.e., the direction perpendicular to and away from the substrate), the first sub-side 1041 has a first thickness l4. Wherein, 0.9 μm < l4 < 1.2 μm.

[0127] In one exemplary embodiment, such as Figure 13 As shown, the color filter structure layer 104 includes an annular black matrix 104a and a color filter 104b located within the opening of the black matrix 104a, i.e., the second opening. The orthographic projection of the color filter 104b onto the substrate at least partially covers the orthographic projection of the first opening K1 of the pixel defining layer 103b onto the substrate.

[0128] In one exemplary embodiment, such as Figure 13 As shown, the sub-pixel region has a pixel defining layer 103b and a color filter structure layer 104 disposed on the pixel defining layer 103b. The color filter structure layer 104 has a black matrix 104a and a separately disposed color filter 104b. The black matrix 104a includes at least one first sub-side 1041. In a third direction, the color filter 104b has a maximum thickness greater than the maximum thickness of the first sub-side 1041 of the black matrix, and the color filter 104b at least partially covers the first sub-side 1041 of the black matrix.

[0129] In one exemplary embodiment, such as Figure 13 As shown, the edge of the black matrix 104a near the color filter 104b has a stepped structure. For example, this stepped structure is a single-step structure, meaning it includes only one step surface. Because the edge of the black matrix 104a near the color filter 104b forms a stepped structure, the color filter 104b can be tightly attached to the edge of the black matrix 104a near the color filter 104b.

[0130] In one exemplary embodiment, such as Figure 14As shown, the color filter 104b may have a first sub-part 10421 and a second sub-part 10422. The first sub-part 10421 is connected to the first sub-side 1041 of the black matrix. The orthographic projection of the second sub-part 10422 onto the substrate covers the orthographic projection of the first sub-part 10421 onto the substrate. In other words, the second sub-part 10422 may have a protruding structure relative to the first sub-part 10421 on a plane parallel to the substrate. In this embodiment, by setting the orthographic projection of the second sub-part 10422 onto the substrate to cover the orthographic projection of the first sub-part 10421 onto the substrate, the light emission purity of the display substrate is improved.

[0131] In one exemplary embodiment, such as Figure 15 As shown, the first signal line 1021 also has a polygonal shape with bends. Within any sub-pixel region, the number of bends in the first signal line 1021 is less than the number of bends in the first sub-side of the black matrix. For example, the number of bends in the first signal line 1021 is less than the number of bends in the first sub-side (or second sub-side) of the black matrix, but greater than the number of bends in the third sub-side (or fourth sub-side), which is beneficial for process implementation.

[0132] In one exemplary embodiment, the color filter 104b covers the zigzag structure of the first signal line 1021.

[0133] In one exemplary embodiment, such as Figure 15 As shown, the orthographic projection of the first signal line 1021 on the substrate and the orthographic projection of the first sub-side 1041 of the black matrix 104a on the substrate have a first overlap 202, which is covered by the color filter 104b. Since the first signal line 1021 is metallic and has high reflectivity, it has a first overlap 202, and the width l3 of the first overlap is small. Figure 14 This ensures that the sub-color filter can cover the first signal line 1021, which helps reduce reflection and improve the purity of the emitted light.

[0134] In one exemplary embodiment, the first signal line 1021 has a broken line structure, the black matrix has multiple sub-sides (sub-side I, sub-side II, sub-side III, sub-side IV), and the number of bends of the first signal line 1021 in any sub-pixel region is less than the number of bends of at least one sub-side of the black matrix (exemplarily, sub-side II or sub-side IV), but greater than the number of bends of at least one other sub-side of the black matrix (exemplarily, sub-side I or sub-side III).

[0135] In one exemplary embodiment, such as Figure 16As shown, the first sub-side 1041 of the black matrix 104a has multiple third sub-segments. These multiple third sub-segments are neither parallel nor perpendicular to the first direction and the second direction. Furthermore, the multiple third sub-segments are arranged independently of each other, and are spaced apart by other sub-segments that are either parallel to the first direction or parallel to the second direction.

[0136] For example, such as Figure 16 As shown, the first sub-side 1041 of the black matrix 104a has four third sub-segments 10411 to 10414. These four third sub-segments 10411 to 10414 are neither parallel nor perpendicular to the first direction and the second direction. Furthermore, the four third sub-segments 10411 to 10414 are independently arranged and are spaced apart by other sub-segments parallel to the second direction.

[0137] In one exemplary embodiment, such as Figure 17 As shown, the black matrix 104a has a second sub-side 1042 disposed opposite to the first sub-side 1041. Figure 17 As shown, sub-pixel 10' has another side, namely the second side II, which is set opposite to the fourth side IV, and the black matrix has a second sub-side 1042.

[0138] Figure 17 In the diagram, at a distance k from the center line A, a first reference line B and a fifth reference line B' can be set. The sub-pixel region can also include a second reference line C, a third reference line D, a fourth reference line E, a sixth reference line C', a seventh reference line D', and an eighth reference line E'. The fifth reference line B', sixth reference line C', seventh reference line D', and eighth reference line E' are symmetrical structures of the first reference line B, second reference line C, third reference line D, and fourth reference line E about the center line A. That is, the center line A and the fifth reference line B' are also at a distance of k, and the distances between the fifth reference line B' and the sixth reference line C', the sixth reference line C' and the seventh reference line D', and the seventh reference line D' and the eighth reference line E' are also n. Furthermore, the second sub-side 1042 of the black matrix 104a also has a broken line structure with bends.

[0139] In an exemplary embodiment, the number of bends x' between the center line A and the fifth reference line B', the number of bends y' between the fifth reference line B' and the sixth reference line C', and the number of bends z' between the sixth reference line C' and the seventh reference line D' satisfy the following conditions: x = x', y ≠ y', z ≠ z'.

[0140] Because x is relatively small, x' is also relatively small, meaning that the number of bends in the polygonal structure near the center line A of the sub-pixel is relatively small. y≠y', z≠z', meaning that the first sub-side 1041 and the second sub-side 1042 are asymmetrically set, which achieves a better display effect, that is, fewer interference and diffraction structures.

[0141] In an exemplary embodiment, within a sub-pixel region, the number of bends x' between the center line A and the fifth reference line B', the number of bends y' between the fifth reference line B' and the sixth reference line C', and the number of bends z' between the sixth reference line C' and the seventh reference line D' of the second sub-side 1042 satisfy the following condition: x'≤y'≤z'.

[0142] In an exemplary embodiment, the second sub-side 1042 has ≥2 bends between the center line A and the fifth reference line B'; the second sub-side 1042 has ≥3 bends between the fifth reference line B' and the sixth reference line C'; and the second sub-side 1042 has ≥3 bends between the sixth reference line C' and the seventh reference line D'.

[0143] For example, such as Figure 18 As shown, within the range where the vertical distance from center line A is less than or equal to k (i.e., between center line A and the fifth reference line B'), the number of bends included in the second sub-side 1042 is x' = 2. Within the range where the vertical distance from center line A is between k and (k + (L / 2 - k) / 3) (i.e., between the fifth reference line B' and the sixth reference line C'), the number of bends included in the second sub-side 1042 is y' = 3; within the range where the vertical distance from center line A is between (k + (L / 2 - k) / 3) and (k + 2(L / 2 - k) / 3) (i.e., between the sixth reference line C' and the seventh reference line D'), the number of bends included in the second sub-side 1042 is z' = 6.

[0144] In an exemplary embodiment, the second sub-side 1042 has at least two approximately equal bends between the center line A and the fifth reference line B'; the second sub-side 1042 has at least two approximately equal bends between the fifth reference line B' and the sixth reference line C'; and the second sub-side 1042 has at least two approximately equal bends between the sixth reference line C' and the seventh reference line D'.

[0145] For example, the second sub-side 1042 has two bends x2' and x3' between the center line A and the fifth reference line B', and x2' and x3' are approximately equal. The second sub-side 1042 has three bends y1', y2' and y3' between the fifth reference line B' and the sixth reference line C', where y2' and y3' are approximately equal. The second sub-side 1042 has six bends z1', z2', z3', z4', z5' and z6' between the sixth reference line C' and the seventh reference line D', where z3' and z4' are approximately equal.

[0146] In an exemplary embodiment, the second sub-side 1042 has at least one fourth bend between the center line A and the fifth reference line B'; the second sub-side 1042 has at least one fifth bend between the fifth reference line B' and the sixth reference line C'; the second sub-side 1042 has at least one sixth bend between the sixth reference line C' and the seventh reference line D', and the angles of the fourth bend, the fifth bend, and the sixth bend are approximately equal.

[0147] For example, the angles x2' between the center line A and the fifth reference line B', y2' between the fifth reference line B' and the sixth reference line C', and z3' between the sixth reference line C' and the seventh reference line D' of the second sub-side 1042 satisfy the following: x2', y2' and z3' are approximately equal.

[0148] In one exemplary embodiment, such as Figure 19 As shown, the black matrix 104a includes a third sub-side and a fourth sub-side. The third sub-side connects to the first sub-side and the second sub-side, and the fourth sub-side connects to the first sub-side and the second sub-side. The first sub-side, the third sub-side, the fourth sub-side, and the second sub-side are connected end to end to form a second opening.

[0149] In one exemplary embodiment, such as Figure 19 As shown, the third sub-side is parallel to the first direction, and the fourth sub-side is parallel to the first direction.

[0150] In one exemplary embodiment, such as Figure 19 As shown, a pixel unit in the display substrate may include a first sub-pixel 301, a second sub-pixel 302, and a third sub-pixel 303. Any two adjacent sub-pixels have different black matrix sides. This achieves better display results, i.e., fewer interference and diffraction structures. For example, the first sub-pixel 301, the second sub-pixel 302, and the third sub-pixel 303 may be red (R) sub-pixels, green (G) sub-pixels, and blue (B) sub-pixels, but this disclosure is not limiting in this regard.

[0151] In another exemplary embodiment, such as Figure 20As shown, a pixel unit in the display substrate may include a first sub-pixel 301, a second sub-pixel 302, a third sub-pixel 303, and a fourth sub-pixel 304. In this case, the sub-sides of the black matrix in each sub-pixel can be different, thus achieving a better display effect, i.e., fewer interference and diffraction structures.

[0152] In an exemplary embodiment, the pixel arrangement can be according to Figure 20 In this layout, two subpixels are arranged along a first direction, and another two subpixels are arranged along a second direction. Of course, the subpixels can be arranged according to other pixel structures.

[0153] For example, the first sub-pixel 301, the second sub-pixel 302, the third sub-pixel 303 and the fourth sub-pixel 304 can be red (R) sub-pixels, green (G) sub-pixels, blue (B) sub-pixels and white (W) sub-pixels, and this disclosure does not limit them.

[0154] In one exemplary embodiment, the number of folded corners of the first sub-side of the black matrix in the green (G) sub-pixel is less than the number of folded corners of the first sub-side of the black matrix in the blue (B) sub-pixel.

[0155] In one exemplary embodiment, the area of ​​the second opening formed by the black matrices of different sub-pixels can be different, and the area of ​​the second opening formed by the black matrices of each sub-pixel can be set according to the brightness requirements. For example, the area of ​​the second opening formed by the green (G) sub-pixel is the smallest, and the area of ​​the second opening formed by the white (W) sub-pixel is the largest.

[0156] In one exemplary embodiment, when the sub-pixel includes a red (R) sub-pixel, a green (G) sub-pixel, a blue (B) sub-pixel, and a white (W) sub-pixel, the white (W) sub-pixel may not have a color filter.

[0157] For example, such as Figure 21 As shown, the green (G) subpixel, red (R) subpixel, and blue (B) subpixel all include a color filter, while the white (W) subpixel may not have a color filter.

[0158] In one exemplary embodiment, such as Figure 22 As shown, the display substrate may further include an encapsulation layer 105 disposed on the side of the color filter structure layer away from the light-emitting structure layer 103. The encapsulation layer 105 may include a first encapsulation layer and a second encapsulation layer stacked together. The first encapsulation layer may be made of organic materials, and the second encapsulation layer may be made of inorganic materials, which can ensure that external moisture cannot enter the light-emitting structure layer and the color filter structure layer.

[0159] Since the white (W) subpixel may not have a color filter, the first encapsulation layer can cover and fill the white (W) subpixel. In other words, the filling structure on the white (W) subpixel is made of the same material as the first encapsulation layer, forming a single integrated structure.

[0160] In one exemplary embodiment, such as Figure 23 As shown, the display substrate may also include a blank structure 305, the orthographic projection of the blank structure 305 on the substrate does not overlap with the orthographic projection of the driving circuit on the substrate, which helps to improve transmittance.

[0161] In one exemplary embodiment, the blank structure may occupy ≥45% of the display area; for example, the blank structure may occupy 46% of the display area.

[0162] In one exemplary embodiment, the blank structure has a width l5 in a first direction, where the width is defined as the distance between two sides that are approximately parallel along a second direction. Here, the width l5 can be equal to or approximately equal to the total length of each polygonal structure of the sub-side 1041 of the black matrix in the first direction. This allows the blank structures 305 to be arranged more uniformly on the display substrate, achieving a better display effect.

[0163] In one exemplary embodiment, the blank structure has a first sub-edge adjacent to a first sub-side of a white sub-pixel region and a first sub-side of a red sub-pixel region, the shape of which is conformal to the shape of the first sub-side of the white sub-pixel region and the first sub-side of the red sub-pixel region. In this embodiment, "conformal preservation" of A and B means that the shapes of the adjacent edges of A and B are completely identical, or that A and B share a certain edge as the edge between A and B.

[0164] In one exemplary embodiment, the blank structure 305 is not necessarily rectangular; it can also be the region between two sub-sides of the black matrix 104a along the first direction. That is, the sides of the blank structure 305 also have a polygonal structure with bends. This further eliminates regular lines, reduces diffraction and interference effects, and improves the display effect.

[0165] In one exemplary embodiment, such as Figure 24 As shown, a sub-pixel may include a first power line VDD, which continuously provides a high potential voltage. Combined with... Figure 15 The aforementioned first signal line 1021 can be the first power line VDD. In this embodiment, the color filter between the black matrices completely covers the first power line VDD, reducing reflectivity and improving light purity.

[0166] In one exemplary embodiment, such as Figure 24As shown, a sub-pixel may include a second power line VSS, which continuously provides a low potential voltage. Combined with... Figure 15 The aforementioned first signal line 1021 can be the second power line VSS. In this embodiment, the color filter between the black matrices completely covers the first power line VDD, reducing reflectivity and improving light purity.

[0167] In one exemplary embodiment, such as Figure 24 As shown, a sub-pixel may include a repair structure 401. The repair structure 401 may be electrically connected to multiple pixel electrodes.

[0168] In one exemplary embodiment, a repair structure 401 may be electrically connected to the first electrodes of two sub-pixels. Here, the light-emitting layer may be an electroluminescent layer comprising the first and second electrodes. Exemplarily, the first electrode is an anode and the second electrode is a cathode. The anodes of adjacent sub-pixels may be separate block structures, while the cathodes of adjacent sub-pixels may be solid-surface structures.

[0169] In one exemplary embodiment, the plurality of sub-pixel regions include red sub-pixel regions and blue sub-pixel regions, wherein the repair structures of the red sub-pixel regions and the repair structures of the blue sub-pixel regions are at least partially symmetrical and at least partially asymmetrical.

[0170] In one exemplary embodiment, the orthogonal projection of the color filter on the substrate can cover the orthogonal projection of the corresponding driving circuit layer on the substrate, which can further reduce reflection, improve light extraction efficiency, and enhance display effect.

[0171] In one exemplary embodiment, the light-emitting structure layer further includes an anode, a first opening at least partially exposing the anode, and at least one sub-pixel region comprising a plurality of discretely arranged sub-anode blocks.

[0172] In one exemplary embodiment, such as Figure 25 As shown, the anode of the display substrate includes at least two discretely arranged sub-anode blocks, meaning the anode has a discrete structure, and the edge of at least one sub-anode may include a zigzag structure. This reduces diffraction effects and improves display performance.

[0173] In one exemplary embodiment, such as Figure 25As shown, taking any two adjacent sub-pixels 301 and 302 as examples, each sub-pixel can include at least two separately arranged sub-anodes. For example, sub-pixel 301 includes a separate first sub-anode block 5011 and a second sub-anode block 5012, and both the first sub-anode block 5011 and the second sub-anode block 5012 have a polygonal structure to improve the display effect; sub-pixel 302 includes a separate third sub-anode block 5021 and a fourth sub-anode block 5022, and both the third sub-anode block 5011 and the fourth sub-anode block 5012 have a polygonal structure to improve the display effect.

[0174] In one exemplary embodiment, the morphologies of the multiple sub-anode blocks are different. In this embodiment, the different morphologies of the multiple sub-anode blocks refer to the different shapes of their orthographic projections on the substrate, or the same shape of their orthographic projections on the substrate, but with different stacking directions.

[0175] For example, such as Figure 25 As shown, the shape of the orthographic projection of the first sub-anode block 5011 onto the substrate can be different from the shape of the orthographic projection of the second sub-anode block 5012 onto the substrate.

[0176] In one exemplary embodiment, the shapes of the orthographic projections of sub-anode blocks in adjacent sub-pixels onto the substrate can be different, for example, such as... Figure 25 As shown, the orthographic projections of the multiple sub-anode blocks 5011, 5012, 5021, and 5022 on the substrate have different shapes. The different shapes of the orthographic projections described in this embodiment mean that the orthographic projection of one sub-anode block on the substrate, after translation, cannot overlap with the orthographic projection of another sub-anode block on the substrate.

[0177] In one exemplary embodiment, multiple sub-anodide blocks within the same sub-pixel are respectively connected to a connection structure. For example, such as... Figure 25 As shown, the first sub-anode block 5011 and the second sub-anode block 5012 are electrically connected to the first connecting structure 601, respectively. The third sub-anode block 5021 and the fourth sub-anode block 5022 are electrically connected to the second connecting structure 602, respectively.

[0178] like Figure 26 As shown, the first connection structure 601 may include: a first connection electrode CE1, which extends from a first end of the first sub-anode block 5011 in a first direction; a second connection electrode CE2, which extends from a first end of the second sub-anode block 5012 in a first direction; and a third connection electrode CE3, which is electrically connected to a driving transistor (exemplarily, it may be...). Figure 8The second transistor T2 extends in a first direction; and a fourth connection electrode CE4 has a first end in contact with the first connection electrode CE1 and a second end in contact with the second connection electrode CE2, the fourth connection electrode CE4 being in contact with the third connection electrode CE3 between the first end and the second end. In this case, the fourth connection electrode CE4 is disposed in a layer different from at least one of the first to third connection electrodes CE1 to CE3, and is in contact with the first to third connection electrodes CE1 to CE3.

[0179] The first connecting electrode CE1, the second connecting electrode CE2, and the third connecting electrode CE3 are spaced apart from each other and arranged in parallel. The first connecting electrode CE1 may be integrally formed with the first sub-anode block 5011, and the second connecting electrode CE2 may be integrally formed with the second sub-anode block 5012. The third connecting electrode CE3 is spaced apart from the first sub-anode block 5011 and the second sub-anode block 5012 and is arranged between the first sub-anode block 5011 and the second sub-anode block 5012.

[0180] The third connecting electrode CE3 may be made of the same material as at least one of the first sub-anode block 5011, the second sub-anode block 5012, the first connecting electrode CE1, and the second connecting electrode CE2, or the third connecting electrode CE3 may be disposed in the same layer as at least one of the first sub-anode block 5011, the second sub-anode block 5012, the first connecting electrode CE1, and the second connecting electrode CE2. The third connecting electrode CE3, connected to the driving transistor, may be electrically connected to the first connecting electrode CE1 and the second connecting electrode CE2 to drive the first sub-light-emitting unit corresponding to the first sub-anode block 5011 and the second sub-light-emitting unit corresponding to the second sub-anode block 5012 via a driving transistor.

[0181] The connecting electrode CE4 may be arranged along a second direction that is different from or perpendicular to a first direction in which the first to third connecting electrodes CE1 to CE3 are arranged, and the connecting electrode CE4 electrically connects the first connecting electrode CE1, the second connecting electrode CE2, and the third connecting electrode CE3 to each other. The fourth connecting electrode CE4 is arranged in a layer different from at least one of the first connecting electrodes CE1, the second connecting electrode CE2, and the third connecting electrode CE3. The fourth connecting electrode CE4 connects the first connecting electrode CE1 to the third connecting electrode CE3 via a bridge, or connects the second connecting electrode CE2 to the third connecting electrode CE3 via a bridge.

[0182] The fourth connection electrode CE4 can be disposed in the same layer as the active layer constituting the driving thin-film transistor. The first connection electrode CE1, the second connection electrode CE2, and the third connection electrode CE3 are in contact with the fourth connection electrode CE4 through vias disposed on the insulating layer of the fourth connection electrode CE4. The fourth connection electrode CE4 can be made of the same material as the active layer constituting the driving thin-film transistor.

[0183] Reference Figure 8 This may require a driving transistor and at least two switching transistors to drive the sub-pixels. One switching transistor ( Figure 8 The gate electrode of the first transistor T1 is connected to the first scan signal line Sn to provide the signal of the data signal line Dn connected to the source / drain electrode of the switching transistor to the driving transistor ( Figure 8 The gate electrode of the second transistor T2 in the process.

[0184] In response to a signal from the gate electrode, the driving transistor applies a voltage VDD, connected to the source / drain electrode on one side of the driving transistor, to the first sub-anode block 5011 and the second sub-anode block 5012. At this time, a first connection structure 601 is electrically connected between the source / drain electrode on the other side of the driving transistor and the first sub-anode block 5011 and the second sub-anode block 5012, so that the voltage or current of the source / drain electrode on the other side of the driving transistor is applied to the first sub-anode block 5011 and the second sub-anode block 5012 through the first connection structure 601. Another switching transistor ( Figure 8 The third transistor T3 is connected to the source / drain electrode on the other side of the driving transistor. The gate electrode of the switching transistor is connected to the second scan signal line Sn, and the reference voltage VRef is connected to one side of the source / drain electrode of the switching transistor.

[0185] If a dark spot or a bright spot appears in any sub-pixel of the display panel, a portion of the fourth connection electrode CE4 of the first connection structure 601 can be laser-cut, thereby allowing the first sub-anode block 5011 or the second sub-anode block 5012 from a sub-pixel to be electrically connected to the driving transistor.

[0186] For example, laser cutting can be performed on the fourth connecting electrode CE4 between the second connecting electrode CE2 and the third connecting electrode CE3, thereby electrically disconnecting the second sub-anode block 5012 connected to the second connecting electrode CE2 from the driving transistor, and the second light-emitting unit corresponding to the second sub-anode block 5012 becomes floating. At this time, the first sub-anode block 5011 can be electrically connected to the driving transistor through the third connecting electrode CE3, and thus the first sub-anode block 5011 can be driven, wherein the third connecting electrode CE3 is electrically connected to the driving transistor through the first connecting electrode CE1 and the fourth connecting electrode CE4.

[0187] In other words, even if a dark spot or a bright spot appears in a sub-pixel, laser cutting can be performed on the fourth connecting electrode CE4 to make a sub-light-emitting unit float, thereby driving the sub-pixel normally.

[0188] Although the laser cutting is shown to be performed on the fourth connecting electrode CE4 between the second connecting electrode CE2 and the third connecting electrode CE3, the laser cutting can also be performed on the fourth connecting electrode CE4 between the first connecting electrode CE1 and the third connecting electrode CE3.

[0189] If a dark spot or bright spot appears in the first sub-light-emitting unit region corresponding to the first sub-anode block 5011, laser cutting can be performed on the fourth connecting electrode CE4 between the first connecting electrode CE1 and the third connecting electrode CE3. This electrically disconnects the first sub-anode block 5011 connected to the first connecting electrode CE1 from the driving transistor, and the first sub-light-emitting unit corresponding to the first sub-anode block 5011 becomes floating. At this time, the second sub-anode block 5012 can be electrically connected to the driving transistor through the third connecting electrode CE3, and thus the second sub-anode block 5012 can be driven. The third connecting electrode CE3 is electrically connected to the driving transistor through the second connecting electrode CE2 and the fourth connecting electrode CE4.

[0190] Even if a dark spot or bright spot appears in a sub-pixel, laser cutting can be performed on the fourth connecting electrode CE4 to drive the second sub-light-emitting unit, thereby driving the sub-pixel normally.

[0191] If a dark spot or a bright spot appears in a sub-pixel, the first connecting electrode CE1 and the fourth connecting electrode CE4, which is disposed on a different layer than the third connecting electrode CE3, can be separated from each other between the first connecting electrode CE1 and the third connecting electrode CE3, and the second connecting electrode CE2 and the fourth connecting electrode CE4, which is disposed on a different layer than the third connecting electrode CE3, can be separated from each other between the second connecting electrode CE2 and the third connecting electrode CE3.

[0192] If no dark or bright spot appears in a sub-pixel, then as described above, the fourth connecting electrode CE4 electrically connects the first connecting electrode CE1, the second connecting electrode CE2, and the third connecting electrode CE3 to each other.

[0193] In one exemplary embodiment, when a fault such as an open circuit occurs in the sub-pixel driving circuit corresponding to a sub-pixel, the electrical connection repair structure and the connection structure can be ablated to electrically connect the sub-pixel with the adjacent sub-pixel driving circuit, thereby enabling illumination. For example, when a fault such as an open circuit occurs in the sub-pixel driving circuit corresponding to sub-pixel 301, the first electrical connection repair structure 4011 and the first connection structure 601 can be ablated to electrically connect the sub-pixel 301 with the adjacent sub-pixel driving circuit, thereby enabling illumination.

[0194] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0195] In an exemplary embodiment, a process for fabricating a display substrate may include the following operations.

[0196] (1) First, a driving circuit layer 102 pattern is fabricated on the substrate 101. The driving circuit layer 102 includes multiple gate lines and multiple data signal lines, which intersect to define multiple matrix-arranged pixel units. Each pixel unit includes at least three sub-pixels, and each sub-pixel includes a thin film transistor (TFT). In this embodiment, a pixel unit includes three sub-pixels, namely a red sub-pixel R, a green sub-pixel G, and a blue sub-pixel B. Of course, this embodiment is also applicable to the case where a pixel unit includes four sub-pixels (red sub-pixel R, green sub-pixel G, blue sub-pixel B, and white sub-pixel W).

[0197] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate.

[0198] In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The first and second flexible material layers may be made of materials such as polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer films. The first and second inorganic material layers may be made of materials such as silicon nitride (SiNx) or silicon oxide (SiOx) to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also referred to as barrier layers. The semiconductor layer may be made of amorphous silicon (a-Si). In an exemplary embodiment, taking a multilayer structure as an example, the preparation process may include: firstly, coating a layer of polyimide on a glass substrate, curing it into a film to form a first flexible (PI1) layer; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then depositing an amorphous silicon film on the first barrier layer to form an amorphous silicon (a-Si) layer covering the first barrier layer; then coating another layer of polyimide on the amorphous silicon layer, curing it into a film to form a second flexible (PI2) layer; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, thus completing the preparation of the substrate 101.

[0199] In an exemplary embodiment, the fabrication process of the driving circuit layer 102 may include:

[0200] A first insulating film and an active layer film are sequentially deposited on a substrate 101. The active layer film is patterned using a patterning process to form a first insulating layer covering the entire substrate 101, and an active layer pattern disposed on the first insulating layer. The active layer pattern includes at least the first active layer.

[0201] Subsequently, a second insulating film and a first metal film are deposited sequentially. The first metal film is patterned using a patterning process to form a second insulating layer covering the active layer pattern, and a first gate metal layer pattern disposed on the second insulating layer. The first gate metal layer pattern includes at least a first gate electrode, a first capacitor electrode, multiple gate lines, and multiple gate leads.

[0202] Subsequently, a third insulating film and a second metal film are deposited sequentially. The second metal film is patterned using a patterning process to form a third insulating layer covering the first gate metal layer, and a second gate metal layer pattern disposed on the third insulating layer. The second gate metal layer pattern includes at least a second capacitor electrode and a second gate lead, and the position of the second capacitor electrode corresponds to the position of the first capacitor electrode.

[0203] Subsequently, a fourth insulating film is deposited, and the fourth insulating film is patterned using a patterning process to form a fourth insulating layer pattern covering the second gate metal layer. Multiple first vias are formed on the fourth insulating layer, and the positions of the multiple first vias correspond to the positions of the two ends of the first active layer, respectively. The fourth insulating layer, the third insulating layer and the second insulating layer in the multiple first vias are etched away, exposing the surface of the first active layer.

[0204] Subsequently, a third metal thin film is deposited, and the third metal thin film is patterned using a patterning process to form a source / drain metal layer pattern on the fourth insulating layer. The source / drain metal layer is formed in the display area and includes at least a first source electrode, a first drain electrode, a low-voltage (VSS) line, multiple data signal lines, and multiple data lead patterns. The first source electrode and the first drain electrode are respectively connected to the first active layer through a first via. In an exemplary embodiment, depending on actual needs, the source / drain metal layer may further include any one or more of a power line (VDD), a compensation line, and an auxiliary cathode. The source / drain metal layer is also referred to as the first source / drain metal layer (SD1).

[0205] Subsequently, a fifth insulating film is deposited to form a fifth insulating layer pattern covering the source and drain metal layers.

[0206] A first planarization film is coated on the substrate 101 on which the aforementioned pattern is formed to form a first planarization (PLN) layer covering the entire substrate 101. A second via is formed on the first planarization layer by a patterning process. The second via is formed in the display area. The first planarization layer and the fifth insulating layer in the second via are etched away to expose the surface of the first drain electrode of the first transistor 102a.

[0207] At this point, the pattern of the driving structure layer 102 is completed on the substrate 101. The first active layer, the first gate electrode, the first source electrode, and the first drain electrode constitute the first transistor 102a, the first capacitor electrode and the second capacitor electrode constitute the first storage capacitor 102b, and multiple gate leads and data leads constitute the driving leads of the array substrate gate driver on array (GOA). In an exemplary embodiment, the first transistor 102a may be a driving transistor in a pixel driving circuit, and the driving transistor may be a thin film transistor (TFT).

[0208] (2) A pattern of a light-emitting structure layer 103 is fabricated on the substrate 101 on which the aforementioned pattern is formed. In an exemplary embodiment, the fabrication process of the light-emitting structure layer 103 may include:

[0209] A transparent conductive film is deposited on the substrate 101 on which the aforementioned pattern is formed. The transparent conductive film is patterned by a patterning process to form an anode 103a pattern. The anode 103a is formed in the display area and is connected to the first drain electrode of the first transistor 102a through a second via.

[0210] A pixel definition film is coated on the substrate 101 on which the aforementioned pattern is formed. A pixel definition (PDL) layer 103b pattern is formed by masking, exposure and development processes. The pixel definition layer 103b has pixel openings. The pixel definition film inside the pixel openings is developed away, exposing the surface of the anode 103a.

[0211] An organic material film is coated on the substrate on which the aforementioned pattern is formed, and multiple isolation pillar (PS) patterns are formed through masking, exposure, and development processes.

[0212] An organic light-emitting layer 103c and a cathode 103d are sequentially formed on the substrate on which the aforementioned pattern is formed. The organic light-emitting layer 103c may include a stacked hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer, formed in the display area, thereby connecting the organic light-emitting layer 103c to the anode 103a. Since the anode 103a is connected to the drain electrode of the first transistor 102a, the light emission control of the organic light-emitting layer 103c is achieved. The cathode 103d is connected to the organic light-emitting layer 103c.

[0213] (4) A second planarization film is coated on the substrate 101 on which the aforementioned pattern is formed, and a second planarization layer pattern is formed on the light-emitting structure layer 103 by masking, exposure and development processes.

[0214] (5) A color filter structure layer 104 pattern is fabricated on the substrate 101 on which the aforementioned pattern is formed. In an exemplary embodiment, the fabrication process of the color filter structure layer 104 may include:

[0215] First, a polymer photoresist layer mixed with black matrix material is coated on the second planarization layer. After exposure and development, the pattern of black matrix 104a is formed. Then, a polymer photoresist layer mixed with red pigment is coated on the second planarization layer. After exposure and development, the pattern of the red area is formed. The same method and steps are used to form the patterns of the green area and the blue area in sequence, and finally a color film pattern of the three primary colors of red, green and blue arranged according to certain rules is formed.

[0216] (4) An encapsulation layer 105 is formed on the substrate 101 on which the aforementioned pattern is formed. The encapsulation layer 105 is formed in the display area and adopts a stacked structure of organic / inorganic materials, such as... Figure 27 and Figure 28 As shown.

[0217] In an exemplary embodiment, the fabrication process of the flexible display substrate may include processes such as peeling off the glass substrate, attaching the back film, and cutting, which are not limited herein.

[0218] As can be seen from the structure and fabrication process of the display substrate in the exemplary embodiments of this disclosure, the exemplary embodiments of this disclosure, by setting the black matrix to have a zigzag structure, reduce grating effects, such as diffraction effects, interference effects, and scattering color separation, thereby improving the display effect; because the use of the black matrix and color filter reduces reflectivity and improves light purity; since a polarizer is not used, the cost is reduced, and the thickness of the display panel is thinned, improving the flexibility of the display panel. The fabrication method of the display substrate in the exemplary embodiments of this disclosure has good process compatibility, simple process implementation, easy implementation, high production efficiency, low production cost, and high yield.

[0219] The structures and fabrication processes shown in the exemplary embodiments of this disclosure are merely illustrative. In the exemplary embodiments, the corresponding structures and patterning processes can be modified and added or reduced according to actual needs. For example, the transistors in the driving circuit layer can be top-gate structures, bottom-gate structures, single-gate structures, or double-gate structures. Furthermore, other film structures, electrode structures, or lead structures can also be provided in the driving circuit layer and the light-emitting structure layer. Moreover, the substrate can be a glass substrate; this disclosure does not specifically limit its application.

[0220] This disclosure also provides a method for fabricating a display substrate. In an exemplary embodiment, the fabrication method may include:

[0221] A driving circuit layer is formed on the substrate;

[0222] A light-emitting structure layer is formed on the side of the driving circuit layer away from the substrate. The light-emitting structure layer includes a pixel defining layer and an organic light-emitting layer. The pixel defining layer defines a plurality of sub-pixel regions and has a first opening that at least partially exposes the driving circuit layer. The organic light-emitting layer is located in the sub-pixel regions and overlaps with the first opening of the pixel defining layer.

[0223] A color filter structure layer is formed on the side of the light-emitting structure layer away from the substrate. The color filter structure layer includes a color filter and a black matrix. The black matrix has a second opening that at least partially exposes the first opening. The color filter is disposed within the second opening. The black matrix includes a first sub-side and the first sub-side has a zigzag structure.

[0224] The following points need to be explained:

[0225] The accompanying drawings of the embodiments disclosed herein only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in a general design.

[0226] Where there is no conflict, the embodiments of this disclosure, i.e., the features in the embodiments, can be combined with each other to obtain new embodiments.

[0227] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this disclosure shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, characterized by, The application relates to an organic light emitting diode display panel, comprising: a substrate; a driving circuit layer arranged on the substrate, the driving circuit layer comprising at least one first signal line; a light emitting structure layer arranged on the driving circuit layer away from the substrate, the light emitting structure layer comprising a pixel defining layer and an organic light emitting layer, the pixel defining layer defining a plurality of sub-pixel regions and having a first opening at least partially exposing the driving circuit layer, and the organic light emitting layer being arranged in the sub-pixel regions and overlapping the first opening of the pixel defining layer; and a color film structure layer arranged on the light emitting structure layer away from the substrate, the color film structure layer comprising a color film and a black matrix, the black matrix having a second opening at least partially exposing the first opening, and the color film being arranged in the second opening; the black matrix comprising a first sub-side edge; a first projection of the first signal line on the substrate, a first projection of the first sub-side edge on the substrate, and a first projection of the color film on the substrate have a first overlap; the black matrix further comprises a second sub-side edge arranged opposite to the first sub-side edge, and the black matrix further comprises a third sub-side edge and a fourth sub-side edge arranged opposite to each other, the first sub-side edge, the third sub-side edge, the second sub-side edge and the fourth sub-side edge are connected in sequence, the first sub-side edge and the second sub-side edge have a fold line structure, and the third sub-side edge and the fourth sub-side edge have a straight strip shape; the first sub-side edge has a plurality of fold angles, and the farther the region is from a center line of the sub-pixel region, the more the number of fold angles of the first sub-side edge is; the second sub-side edge has a plurality of fold angles, and the farther the region is from a center line of the sub-pixel region, the more the number of fold angles of the second sub-side edge is; the first sub-side edge and the second sub-side edge are asymmetrically arranged relative to the center line of the sub-pixel region.

2. The display substrate of claim 1, wherein, a first projection of the color film on the substrate at least partially covers a first projection of the first opening of the pixel defining layer on the substrate. 3.The display substrate of claim 1, wherein, in a third direction, a maximum thickness of the color film is greater than a maximum thickness of the first sub-side edge, and the color film at least partially covers the first sub-side edge, the third direction being a direction along the substrate towards the color film structure layer.

4. The display substrate of claim 1, wherein, the first sub-side edge has a step structure, and the color film is closely attached to an edge of the black matrix close to the color film.

5. The display substrate of claim 1, wherein, the black matrix has a second thickness l4 in a third direction, the second thickness being between 0.9 microns and 1.2 microns, and the third direction being a direction along the substrate towards the color film structure layer. 6.The display substrate of claim 1, wherein, the first sub-side edge comprises a third sub-line segment which is neither parallel nor perpendicular to the first direction and the second direction, and the black matrix comprises at least one third sub-line segment.

7. The display substrate of claim 1, wherein, the first signal line has a fold line structure, the black matrix has a plurality of sub-side edges, and the number of fold angles of the first signal line in at least one sub-pixel region is less than the number of fold angles of at least one sub-side edge of the black matrix and greater than the number of fold angles of at least one other sub-side edge of the black matrix. 8.The display substrate of claim 1, wherein, The sub-pixel region comprises a first sub-pixel region, a second sub-pixel region and a third sub-pixel region, the first sub-pixel region comprises a first light emitting unit and a first color color film, the second sub-pixel region comprises a second light emitting unit and a second color color film, the third sub-pixel region comprises a third light emitting unit and a third color color film, the first color color film covers the orthographic projection of the first light emitting unit on the substrate, the orthographic projection of the second color color film covers the orthographic projection of the second light emitting unit on the substrate, and the orthographic projection of the third color color film covers the orthographic projection of the third light emitting unit on the substrate, and the second light emitting unit comprises at least two sub-light emitting units arranged separately. 9.The display substrate of claim 1, wherein, The display substrate further comprises an encapsulation layer arranged on the side of the color film structure layer away from the light emitting structure layer, and the orthographic projection of the encapsulation layer on the substrate covers the orthographic projection of the color film structure layer on the substrate. 10.The display substrate of claim 9, wherein, The sub-pixel region comprises a first sub-pixel region, a second sub-pixel region, a third sub-pixel region and a fourth sub-pixel region, the first sub-pixel region comprises a first light emitting unit and a first color color film, the second sub-pixel region comprises a second light emitting unit and a second color color film, the third sub-pixel region comprises a third light emitting unit and a third color color film, the fourth sub-pixel region comprises a fourth light emitting unit and a fourth color color film, the first color color film covers the orthographic projection of the first light emitting unit on the substrate, the orthographic projection of the second color color film covers the orthographic projection of the second light emitting unit on the substrate, the orthographic projection of the third color color film covers the orthographic projection of the third light emitting unit on the substrate, the orthographic projection of the fourth color color film covers the orthographic projection of the fourth light emitting unit on the substrate, the encapsulation layer covers the first color color film, the second color color film and the third color color film, and the fourth color color film is arranged in the same layer and of the same material as at least part of the encapsulation layer. 11.The display substrate of claim 8 or 10, wherein, The first sub-pixel region is a red sub-pixel region, the second sub-pixel region is a green sub-pixel region, and the third sub-pixel region is a blue sub-pixel region. 12.The display substrate of claim 11, wherein, The areas of the sub-pixel regions of different colors are different. 13.The display substrate of claim 1, wherein, The display substrate further comprises a blank structure, and the orthographic projection of the blank structure on the substrate does not overlap the orthographic projection of the sub-pixel region on the substrate. 14.The display substrate of claim 13, wherein, The ratio of the area of the blank structure to the area of the sub-pixel region is greater than or equal to 45%. 15.The display substrate of claim 1, wherein, The first sub-side edge has a first width along the first direction; the first signal line has a second width along the first direction, the orthographic projection of the first signal line on the substrate and the orthographic projection of the first sub-side on the substrate have a first overlap, the first overlap has a third width along the first direction, the first width is l1, the second width is l2, and the third width is l3. The sub-pixel region includes a center line and a first reference line along the first direction, the distance between the first reference line and the center line of the sub-pixel region is k, and the length of the sub-pixel region along the first direction is L, then: 6*l2 16.The display substrate of claim 15, wherein, The first width is l1, the second width is l2, the sub-pixel region includes a center line and a first reference line along the first direction, the distance between the first reference line and the center line of the sub-pixel region is k, and the length of the sub-pixel region along the first direction is L, then: 10*l1 17. A display substrate, comprising: Comprise: a substrate; a driving circuit layer disposed on the substrate, the driving circuit layer comprising at least one first signal line, the driving circuit layer further comprising a repair structure; a light-emitting structure layer disposed on the side of the driving circuit layer away from the substrate, the light-emitting structure layer comprising a pixel definition layer and an organic light-emitting layer, the pixel definition layer defining a plurality of sub-pixel regions and having a first opening at least partially exposing the driving circuit layer, and the organic light-emitting layer being located in the sub-pixel regions and overlapping the first opening of the pixel definition layer; and a color filter structure layer disposed on the side of the light-emitting structure layer away from the substrate, the color filter structure layer comprising a color filter and a black matrix, the black matrix having a second opening at least partially exposing the first opening, and the color filter being disposed in the second opening; the black matrix comprising a first sub-side, the first signal line, the first sub-side, and the color filter having a first overlap in the substrate; The display substrate further comprises a blank structure, the projection of the blank structure on the substrate does not overlap with the projection of the sub-pixel region on the substrate, and the projection of the repair structure on the substrate at least partially overlaps with the projection of the blank structure on the substrate; The black matrix further comprises a second sub-side disposed opposite to the first sub-side, and the black matrix further comprises a third sub-side and a fourth sub-side disposed opposite to each other, the first sub-side, the third sub-side, the second sub-side, and the fourth sub-side are connected end to end, the first sub-side and the second sub-side have a fold line structure, and the third sub-side and the fourth sub-side have a straight bar shape; The first sub-side has a plurality of fold angles, and the farther the area is from the center line of the sub-pixel region, the more the number of fold angles of the first sub-side is; The second sub-side has a plurality of fold angles, and the farther the area is from the center line of the sub-pixel region, the more the number of fold angles of the second sub-side is; The first sub-side and the second sub-side are asymmetrically disposed relative to the center line of the sub-pixel region. 18.The display substrate of claim 17, wherein, The plurality of sub-pixel regions comprise red sub-pixel regions and blue sub-pixel regions, the repair structure of the red sub-pixel region and the repair structure of the blue sub-pixel region are at least partially symmetrical and at least partially asymmetrical. 19.The display substrate of claim 17, wherein, The light-emitting structure layer further comprises an anode, the first opening at least partially exposes the anode, and the at least one sub-pixel region comprises a plurality of sub-anode blocks arranged discretely. 20.The display substrate of claim 19, wherein, The plurality of sub-anode blocks arranged discretely comprises two. 21.The display substrate of claim 20, wherein, The two sub-anode blocks have different topographies. 22.The display substrate of claim 20, wherein, The driving circuit layer comprises anode holes, and the anode holes are electrically connected to the two sub-anode blocks respectively. 23.The display substrate of claim 20, wherein, The two sub-anode blocks are electrically connected to each other and to the repair structure.

24. A display device comprising: The display substrate comprises the display substrate as claimed in any one of claims 1 to 23.

25. A method for manufacturing a display substrate, comprising: The display substrate comprises: forming a driving circuit layer on a substrate, the driving circuit layer comprising at least one first signal line; forming a light-emitting structure layer on a side of the driving circuit layer away from the substrate, the light-emitting structure layer comprising a pixel defining layer and an organic light-emitting layer, the pixel defining layer defining a plurality of sub-pixel regions and having a first opening at least partially exposing the driving circuit layer, and the organic light-emitting layer being located in the sub-pixel regions and overlapping the first opening of the pixel defining layer; forming a color film structure layer on a side of the light-emitting structure layer away from the substrate, the color film structure layer comprising a color film and a black matrix, the black matrix having a second opening at least partially exposing the first opening, the color film being arranged in the second opening, and the black matrix comprising a first sub-side, a projection of the first signal line on the substrate, a projection of the first sub-side on the substrate, and a projection of the color film on the substrate having a first overlap; the black matrix further comprising a second sub-side arranged opposite to the first sub-side, and the black matrix further comprising a third sub-side and a fourth sub-side arranged opposite to each other, the first sub-side, the third sub-side, the second sub-side, and the fourth sub-side being connected end to end, the first sub-side and the second sub-side having a zigzag structure, and the third sub-side and the fourth sub-side having a straight strip shape; the first sub-side has a plurality of angles, and the farther the region is from a center line of the sub-pixel region, the more the number of angles of the first sub-side is; the second sub-side has a plurality of angles, and the farther the region is from the center line of the sub-pixel region, the more the number of angles of the second sub-side is; the first sub-side and the second sub-side are asymmetrically arranged with respect to the center line of the sub-pixel region.

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