Semiconductor Structure and Method of Manufacturing the Same

Abstract

A semiconductor structure and a manufacturing method thereof, comprising providing an N-type semiconductor layer (11), a light-emitting layer (12), a P-type ion-doped layer (13), and a barrier material layer (14') that are distributed from bottom to top; patterning the barrier material layer (14') to form a barrier layer (14), the barrier layer (14) having at least one opening (14a) to expose a partial region of the P-type ion-doped layer (13); using the barrier layer (14) as a mask to activate P-type doping ions in the exposed P-type ion-doped layer (13) to form an activation region (131), and the P-type ion-doped layer (13) covered by the barrier layer (14) forms a non-activation region (132).

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] Group III nitride semiconductor materials have advantages such as a large bandgap (0.7 eV to 6.2 eV), a high carrier saturation migration rate, a high breakdown electric field, and good thermal conductivity, and are very suitable for preparing blue, green, and ultraviolet LED devices as well as high-frequency, high-power, and anti-electromagnetic radiation integrated electronic devices.

[0003] How to improve the light intensity, luminous efficiency of LEDs based on group III nitride semiconductor materials, and reduce production costs is the focus of attention in the LED industry. Providing a reliable structure to increase the optical power, thereby greatly improving the grade of LED products is the main goal of current research and development. Summary of the Invention

[0004] The object of the present invention is to provide a semiconductor structure and a manufacturing method thereof, which can improve the light intensity, luminous efficiency of LEDs, and reduce production costs.

[0005] To achieve the above object, on the one hand, the present invention provides a semiconductor structure, including:

[0006] An N-type semiconductor layer, a light-emitting layer, and a P-type ion-doped layer distributed from bottom to top. The P-type ion-doped layer includes an activation region and non-activation regions located on both sides of the activation region. The P-type doping ions in the activation region are activated, and the P-type doping ions in the non-activation regions are passivated.

[0007] Optionally, the P-type ion-doped layer includes at least two of the activation regions and at least three of the non-activation regions, and the activation regions and the non-activation regions are distributed at intervals.

[0008] Optionally, the semiconductor structure further includes: a blocking layer, which is located on the non-activation region and is used to expose the activation region.

[0009] Optionally, the material of the blocking layer includes: SiNx, N-type GaN, or a combination of SiNx and N-type GaN.

[0010] Optionally, the light-emitting layer and the P-type ion-doped layer expose a partial region of the N-type semiconductor layer. An N electrode is provided on the exposed N-type semiconductor layer, and an ohmic contact is formed between the N electrode and the N-type semiconductor layer; a P electrode is provided on the activation region, and an ohmic contact is formed between the P electrode and the activation region.

[0011] Optionally, the P electrodes on each of the activation regions are electrically connected together.

[0012] Optionally, the light-emitting layer includes a single quantum well structure or a multiple quantum well structure.

[0013] Optionally, the material of the N-type semiconductor layer includes group III nitride material, and / or the material of the light-emitting layer includes group III nitride material, and / or the material of the P-type ion-doped layer includes group III nitride material.

[0014] Optionally, an electron blocking layer is provided between the light-emitting layer and the P-type ion-doped layer.

[0015] On the other hand, the present invention provides a method for manufacturing a semiconductor structure, including:

[0016] Providing an N-type semiconductor layer, a light-emitting layer, a P-type ion-doped layer, and a blocking material layer distributed from bottom to top;

[0017] Patterning the blocking material layer to form a blocking layer, the blocking layer having at least one opening to expose a partial region of the P-type ion-doped layer; using the blocking layer as a mask to activate P-type doping ions in the exposed P-type ion-doped layer to form an activation region, and the P-type ion-doped layer covered by the blocking layer forms a non-activation region.

[0018] Optionally, the openings in the blocking layer are multiple to form at least two activation regions and at least three non-activation regions, and the activation regions and the non-activation regions are distributed at intervals.

[0019] Optionally, the method for manufacturing the semiconductor structure further includes: removing the blocking layer to expose the non-activation region.

[0020] Optionally, the material of the blocking material layer includes: SiNx, N-type GaN, or a combination of SiNx and N-type GaN.

[0021] Optionally, the P-type doping ions are activated by annealing at a temperature higher than 500 °C.

[0022] Optionally, the P-type doping ions are activated in an atmosphere of nitrogen, a mixed gas of nitrogen and oxygen, nitrous oxide, or argon.

[0023] Optionally, the growth temperature range of the P-type ion-doped layer is 700 °C to 1200 °C.

[0024] Optionally, the method for manufacturing the semiconductor structure further includes: removing partial regions of the P-type ion-doped layer and the light-emitting layer to expose the N-type semiconductor layer, forming an N electrode on the exposed N-type semiconductor layer, and forming an ohmic contact between the N electrode and the N-type semiconductor layer; forming a P electrode on the activation region, and forming an ohmic contact between the P electrode and the activation region.

[0025] Optionally, the light-emitting layer includes a single quantum well structure or a multiple quantum well structure.

[0026] Optionally, the material of the N-type semiconductor layer includes group III nitride material, and / or the material of the light-emitting layer includes group III nitride material, and / or the material of the P-type ion-doped layer includes group III nitride material.

[0027] Optionally, the manufacturing method of the semiconductor structure further includes: providing an electron blocking layer between the light-emitting layer and the P-type ion-doped layer.

[0028] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0029] 1) The semiconductor structure of the present invention includes: an N-type semiconductor layer, a light-emitting layer, and a P-type ion-doped layer distributed from bottom to top. Among them, the P-type ion-doped layer includes an activation region and non-activation regions located on both sides of the activation region. The P-type doping ions in the activation region are activated, and the P-type doping ions in the non-activation regions are passivated. The distribution of the activation region and the non-activation regions enables the LED to include: a high-efficiency light-emitting region and light-emitting barrier regions located on both sides of the high-efficiency light-emitting region. The high-efficiency light-emitting region includes: the activation region, the light-emitting layer in the region directly below the activation region, and the N-type semiconductor layer in the region directly below the activation region. The light-emitting barrier regions include: the non-activation regions, the light-emitting layer in the region directly below the non-activation regions, and the N-type semiconductor layer in the region directly below the non-activation regions. When the area of the LED is fixed, compared with the case where the entire P-type ion-doped layer is an activation region, the high-efficiency light-emitting region makes the electric field concentrate between the P electrode and the N electrode. The concentrated electric field means a large electric field strength and the LED emits light concentratedly, which can improve the light-emitting efficiency. In addition, by using a blocking layer to selectively activate the P-type ion-doped layer regionally, etching of the P-type ion-doped layer is avoided, damage to the light-emitting layer in the high-efficiency light-emitting region is reduced, and defects are decreased. At the same time, due to the presence of the mask, light-emitting barrier regions are formed on both sides of the LED device, thereby suppressing the non-uniform light emission caused by the non-radiative recombination effect and improving the light-emitting efficiency at the same time.

[0030] 2) In an alternative embodiment, the P-type ion-doped layer includes at least two activation regions and at least three non-activation regions, and the activation regions and the non-activation regions are spaced apart. The multiple activation regions and the multiple non-activation regions are spaced apart, and multiple alternately distributed high-efficiency light-emitting regions and light-emitting barrier regions can be formed. When the area of the LED is fixed, compared with a large-area light-emitting region, the multiple small-area high-efficiency light-emitting regions can further improve the carrier recombination efficiency per unit area of the LED and can further improve the light-emitting efficiency.

[0031] 3) In an alternative embodiment, a) the light-emitting layer and the P-type ion-doped layer expose a partial region of the N-type semiconductor layer, an N electrode is disposed on the exposed N-type semiconductor layer, and an ohmic contact is formed between the N electrode and the N-type semiconductor layer; a P electrode is disposed on the active region, and an ohmic contact is formed between the P electrode and the active region. Or b) an N electrode is disposed on a side of the N-type semiconductor layer away from the light-emitting layer, an ohmic contact is formed between the N electrode and the N-type semiconductor layer; a P electrode is disposed on the active region, and an ohmic contact is formed between the P electrode and the active region. The a) embodiment corresponds to a horizontally structured LED, and the conduction current flows in a horizontal direction (perpendicular to the thickness direction of the LED). The b) embodiment corresponds to a vertically structured LED, and the conduction current flows in a vertical direction (the thickness direction of the LED). BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a flowchart of a method for fabricating a semiconductor structure according to a first embodiment of the present invention;

[0033] Figures 2 to 3 is Figure 1 a schematic diagram of an intermediate structure corresponding to the process in

[0034] Figure 4 a schematic cross-sectional structure diagram of a semiconductor structure according to a first embodiment of the present invention;

[0035] Figure 5 a schematic cross-sectional structure diagram of a semiconductor structure according to a second embodiment of the present invention;

[0036] Figure 6 a schematic cross-sectional structure diagram of a semiconductor structure according to a third embodiment of the present invention;

[0037] Figure 7 a schematic cross-sectional structure diagram of a semiconductor structure according to a fourth embodiment of the present invention;

[0038] Figure 8 a schematic cross-sectional structure diagram of a semiconductor structure according to a fifth embodiment of the present invention;

[0039] Figure 9 a schematic cross-sectional structure diagram of a semiconductor structure according to a sixth embodiment of the present invention.

[0040] For ease of understanding of the present invention, all the reference numerals appearing in the present invention are listed below:

[0041] Semiconductor structures 1, 2, 3, 4, 5, 6 N-type semiconductor layer 11

[0042] Light-emitting layer 12 P-type ion-doped layer 13

[0043] Blocking material layer 14' Blocking layer 14

[0044] Opening 14a Active region 131

[0045] Non - active region 132, N - electrode 151

[0046] P - electrode 152, Passivation layer 16

[0047] Electron blocking layer 17, First region 171

[0048] Second region 172 Detailed implementation manners

[0049] To make the above - mentioned objects, features, and advantages of the present invention more obvious and understandable, the following will describe in detail the specific embodiments of the present invention with reference to the accompanying drawings.

[0050] Figure 1 is a flowchart of a method for manufacturing a semiconductor structure according to the first embodiment of the present invention; Figures 2 to 3 is Figure 1 the schematic diagram of the intermediate structure corresponding to the process in Figure 4 is a cross - sectional structure schematic diagram of a semiconductor structure according to the first embodiment of the present invention.

[0051] First, referring to Figure 1 the step S1 in Figure 2 as shown, provide an N - type semiconductor layer 11, a light - emitting layer 12, a P - type ion - doped layer 13, and a blocking material layer 14' distributed from bottom to top.

[0052] The material of the N - type semiconductor layer 11 can be a group - III nitride material, such as at least one of GaN, AlGaN, InGaN, and AlInGaN. The N - type doping element can include at least one of Si, Ge, Sn, Se, or Te.

[0053] The light - emitting layer 12 can include at least one of a single - quantum - well structure, a multi - quantum - well (MQW) structure, a quantum - wire structure, and a quantum - dot structure. The light - emitting layer 12 can include a well layer and a barrier layer formed of a group - III nitride material.

[0054] For example, the well layer can include Al x Ga 1-x N layer, where x is the mass percentage of Al element in the sum of the masses of Al element and Ga element, 1≥x≥0; and / or the barrier layer can include Al y Ga 1-y N layer, where y is the mass percentage of Al element in the sum of the masses of Al element and Ga element, 1≥y≥0. The bandgap of the well layer is less than that of the barrier layer. The well layer and / or the barrier layer can be doped with Al or not doped with Al.

[0055] The multi - layer alternation of the well layer and the barrier layer can form a multi - quantum - well structure.

[0056] The material of the P-type ion doping layer 13 can be a group III nitride material, such as at least one of GaN, AlGaN, InGaN, and AlInGaN, and the P-type doping ions therein can be at least one of Mg ions, Zn ions, Ca ions, Sr ions, or Ba ions.

[0057] In this embodiment, the barrier material layer 14' is formed on the P-type ion doping layer 13 without activation.

[0058] In some embodiments, the barrier material layer 14' can be a single-layer structure. The material of this single-layer structure can include: SiNx, N-type GaN, or a combination of SiNx and N-type GaN. SiNx means that the molar ratio of silicon element to nitrogen element is variable.

[0059] In other embodiments, the barrier material layer 14' can be a stacked structure. The material of any layer in this stacked structure can include: SiNx, N-type GaN, or a combination of SiNx and N-type GaN.

[0060] In some embodiments, step S1 can also include: sequentially forming an N-type semiconductor layer 11, a light-emitting layer 12, a P-type ion doping layer 13, and a barrier material layer 14' on the substrate.

[0061] The substrate can also include at least one of sapphire, silicon carbide, and silicon, or at least one of sapphire, silicon carbide, and silicon and the group III nitride material thereon, and this embodiment does not limit this.

[0062] The N-type semiconductor layer 11, and / or the light-emitting layer 12, and / or the P-type ion doping layer 13 can be a group III nitride material. The group III nitride material can be at least one of GaN, AlGaN, InGaN, and AlInGaN. The formation process of the group III nitride material can include: atomic layer deposition (ALD, Atomic layer deposition), or chemical vapor deposition (CVD, Chemical Vapor Deposition), or molecular beam epitaxy (MBE, Molecular Beam Epitaxy), or plasma-enhanced chemical vapor deposition (PECVD, Plasma Enhanced Chemical Vapor Deposition), or low-pressure chemical vapor deposition (LPCVD, Low Pressure Chemical Vapor Deposition), or metal-organic chemical vapor deposition (MOCVD, Metal-Organic Chemical Vapor Deposition), or a combination thereof.

[0063] In some embodiments, the growth temperature range of the P-type ion-doped layer 13 is 700°C to 1200°C, which can avoid the deterioration of the quality of the previously formed light-emitting layer 12 and / or N-type semiconductor layer 11 during high-temperature growth, and optimize the crystal quality of the light-emitting layer 12 and / or N-type semiconductor layer 11.

[0064] In this embodiment, the barrier material layer 14' is formed on the P-type ion-doped layer 13 without activation.

[0065] When the material of the barrier material layer 14' includes SiNx, it is formed by physical vapor deposition or chemical vapor deposition. When the material of the barrier material layer 14' includes N-type GaN, please refer to the formation process of the N-type semiconductor layer 11, and / or the light-emitting layer 12, and / or the P-type ion-doped layer 13.

[0066] After that, the substrate can be removed. The substrate can be removed by laser lift-off or chemical etching.

[0067] The substrate can also be removed after the end of step S2 or step S3.

[0068] In some embodiments, the substrate can also not be removed and be retained in the semiconductor structure 1.

[0069] Next, referring to Figure 1 the steps S2 in Figure 3 as shown, the barrier material layer 14' is patterned to form the barrier layer 14. The barrier layer 14 has at least one opening 14a to expose a partial region of the P-type ion-doped layer 13; using the barrier layer 14 as a mask, the P-type doping ions in the exposed P-type ion-doped layer 13 are activated to form the activation region 131, and the P-type ion-doped layer 13 covered by the barrier layer 14 forms the non-activation region 132.

[0070] The patterning of the barrier material layer 14' can be achieved by dry etching or wet etching. Specifically, a photoresist layer is first formed on the barrier material layer 14', and the photoresist layer is patterned by a process of first exposure and then development. The dry etching gas can be CF4, C3F8, etc., and the wet etching solution can be hot phosphoric acid.

[0071] In the process environment for growing the P-type ion-doped layer 13, for example, in the MOCVD growth environment, there are a large number of H atoms. If not removed, the P-type doping ions (acceptor dopants, such as Mg ions) in the group III nitride material will bond with the H atoms, that is, they will be passivated by a large number of H atoms and no holes will be generated. The exposure of the P-type ion-doped layer 13 can provide an escape path for the release of H atoms.

[0072] Thus, for the P-type ion-doped layer 13 covered by the barrier layer 14, due to the blocking effect of the barrier layer 14, the H atoms in the P-type ion-doped layer 13 cannot overflow. The H atoms will combine with P-type doping ions (such as Mg ions), which passivates the P-type doping ions and makes them unable to generate holes, correspondingly forming the non-activated region 132. For the P-type ion-doped layer 13 exposed by the opening 14a of the barrier layer 14, the H atoms therein can overflow, which activates the P-type doping ions and correspondingly forms the activated region 131.

[0073] It can be seen that by using the barrier layer 14 as the barrier layer when activating P-type doping ions, in the P-type ion-doped layer 13, the region not covered by the barrier layer 14 forms the activated region 131, and the region covered by the barrier layer 14 forms the non-activated region 132. The advantage is that it can avoid etching the P-type ion-doped layer 13, thereby avoiding the loss of the light-emitting layer 12 caused by etching.

[0074] In some embodiments, high-temperature annealing is performed in an inert gas, for example, annealing at a temperature greater than 500 °C to activate P-type doping ions to prevent the introduction of H atoms. In some embodiments, P-type doping ions can be activated in an atmosphere of nitrogen, a mixed gas of nitrogen and oxygen, nitrous oxide (NO), or argon, etc., which do not contain hydrogen atoms. During high-temperature annealing, nitrogen molecules and their decomposition products can effectively penetrate into the surface of the group-III nitride material, well compensating for the nitrogen vacancies caused during the etching process and improving the quality of the activated region 131.

[0075] After that, referring to Figure 1 the steps S3 in Figure 4 as shown, partial regions of the P-type ion-doped layer 13 and the light-emitting layer 12 are removed to expose the N-type semiconductor layer 11. An N electrode 151 is formed on the exposed N-type semiconductor layer 11, and an ohmic contact is formed between the N electrode 151 and the N-type semiconductor layer 11; a P electrode 152 is formed on the activated region 131, and an ohmic contact is formed between the P electrode 152 and the activated region 131.

[0076] Referring to Figure 4 as shown, removing partial regions of the P-type ion-doped layer 13 and the light-emitting layer 12 may include: first forming a photoresist mask layer on the barrier layer 14 and the activated region 131; then exposing the photoresist mask layer and developing a photoresist pattern; and then using the photoresist pattern to perform dry etching or wet etching on the barrier layer 14, the P-type ion-doped layer 13, and the light-emitting layer 12.

[0077] Specifically, before forming the photoresist mask layer, a stripping solution (dimethyl sulfoxide) can be used to perform ultrasonic treatment on Figure 3Clean the intermediate structure shown to remove surface organic particles; and use H2SO4:H2O2:H2O (5:1:1) to clean at 80°C to 90°C to remove surface metal particles and the surface oxide layer;

[0078] Next, apply a tackifier HMDS (hexamethyldisilazane) on the surfaces of the barrier layer 14 and the activation region 131 to modify the surfaces of the barrier layer 14 and the activation region 131 from hydrophilic to hydrophobic.

[0079] After etching, the remaining photoresist pattern can be removed by ashing.

[0080] Still referring to Figure 4 As shown, after removing partial regions of the P-type ion-doped layer 13 and the light-emitting layer 12, a passivation layer 16 can be formed on a) the upper surfaces of the barrier layer 14 and the activation region 131, b) the side surfaces of the barrier layer 14, the P-type ion-doped layer 13, and the light-emitting layer 12, and c) the upper surface of the exposed N-type semiconductor layer 11.

[0081] The passivation layer 16 can be an insulating material, such as silicon dioxide, silicon nitride, etc., and can be formed into one or more layers of equal thickness by physical vapor deposition or chemical vapor deposition.

[0082] Still referring to Figure 4 As shown, pattern the passivation layer 16 to remove at least the passivation layer 16 in the regions where the N electrode 151 and the P electrode 152 are to be formed.

[0083] Referring to Figure 4 As shown, the materials of the N electrode 151 and the P electrode 152 can be at least one of Ti, Al, Ni, and Au. For example, the N electrode 151 and the P electrode 152 are a stacked structure of a Ti layer / Al layer / Ni layer / Au layer, or a stacked structure of a Ti layer / Al layer, or a stacked structure of a Ni layer / Au layer, and can be formed by sputtering.

[0084] In some embodiments, the N electrode 151 and the P electrode 152 are formed by high-temperature annealing.

[0085] In some embodiments, before forming the N electrode 151 and the P electrode 152, an ion re-doped layer (not shown) can also be formed on the activation region 131 and the exposed N-type semiconductor layer 11. The ion re-doped layer can directly form an ohmic contact layer between the P electrode 152 and the activation region 131 and between the N electrode 151 and the N-type semiconductor layer 11 without high-temperature annealing.

[0086] The material of the ion heavily doped layer can be a group III nitride material, such as at least one of GaN, AlGaN, and AlInGaN. In some embodiments, the growth temperature of the ion heavily doped layer can be lower than 1000 °C, preferably lower than 800 °C, to avoid the secondary passivation of the activated P-type doped ions.

[0087] In the ion heavy doping layer growth process, the passivation layer 16 can serve as a barrier layer to prevent the formation of the ion heavy doping layer thereon.

[0088] In some embodiments, an ion heavy doping layer can also be formed on at least one of the activation region 131 and the exposed N-type semiconductor layer 11.

[0089] For the P electrode 152 without an ion heavy doping layer and the activation region 131, or the N electrode 151 without an ion heavy doping layer and the N-type semiconductor layer 11, an ohmic contact layer can be formed by high-temperature annealing.

[0090] Referring to Figure 4 as shown, the semiconductor structure 1 includes:

[0091] An N-type semiconductor layer 11, a light-emitting layer 12, a P-type ion-doped layer 13, and a barrier layer 14 distributed from bottom to top. The P-type ion-doped layer 13 includes an activation region 131 and non-activation regions 132 on both sides of the activation region 131. The P-type doped ions in the activation region 131 are activated, and the P-type doped ions in the non-activation regions 132 are passivated. The barrier layer 14 is located on the non-activation region 132 to expose the activation region 131. The light-emitting layer 12 and the P-type ion-doped layer 13 expose a partial region of the N-type semiconductor layer 11. An N electrode 151 is provided on the exposed N-type semiconductor layer 11, and an ohmic contact is formed between the N electrode 151 and the N-type semiconductor layer 11. A P electrode 152 is provided on the activation region 131, and an ohmic contact is formed between the P electrode 152 and the activation region 131.

[0092] According to the setting positions of the N electrode 151 and the P electrode 152, it can be seen that the semiconductor structure 1 corresponds to a horizontally structured LED, that is, the conduction current flows in the horizontal direction (perpendicular to the thickness direction of the semiconductor structure 1).

[0093] In some embodiments, the N electrode 151 can also be provided on the side of the N-type semiconductor layer 11 away from the light-emitting layer 12. Since the P electrode 152 is formed on the side of the activation region 131 away from the light-emitting layer 12, therefore, this semiconductor structure corresponds to a vertically structured LED, that is, the conduction current flows in the vertical direction (the thickness direction of the semiconductor structure).

[0094] The distribution of the activation region 131 and the non-activation region 132 enables the LED semiconductor structure to include: a high-efficiency light-emitting region and light-emitting barrier regions located on both sides of the high-efficiency light-emitting region. The high-efficiency light-emitting region includes: the activation region 131, the light-emitting layer 12 in the region directly below the activation 131 region, and the N-type semiconductor layer 11 in the region above and below the activation 131 region. The light-emitting barrier regions include: the non-activation region 132, the light-emitting layer 12 in the region directly below the non-activation region 132, and the N-type semiconductor layer 11 in the region directly below the non-activation region 132. When the area of the LED is fixed, compared with the case where the entire P-type ion-doped layer 13 is the activation region 131, the high-efficiency light-emitting region causes the electric field to concentrate between the P electrode 152 and the N electrode 151. The concentration of the electric field means a large electric field intensity and an increase in the carrier recombination efficiency per unit area of the LED, thereby improving the light-emitting efficiency.

[0095] In addition, the blocking layer 14 is used to selectively activate the P-type ion-doped layer 13 in a region, avoiding etching the P-type ion-doped layer 13 and damaging the light-emitting layer 12 in the high-efficiency light-emitting region, reducing defects, thereby reducing the possibility of non-radiative recombination and improving the light-emitting efficiency.

[0096] Figure 5 It is a schematic cross-sectional structure diagram of the semiconductor structure of the second embodiment of the present invention.

[0097] Referring to Figure 5 As shown, the semiconductor structure 2 of the second embodiment is substantially the same as the semiconductor structure 1 of the first embodiment, except that: the semiconductor structure 2 further includes: an electron blocking layer 17 located between the light-emitting layer 12 and the P-type ion-doped layer 13.

[0098] The electron blocking layer 17 can prevent electrons from entering the P-type ion-doped layer 13 from the light-emitting layer 12, thereby increasing the probability of recombination of electrons and holes in the light-emitting layer 12 and improving the light-emitting efficiency. The material of the electron blocking layer 17 can be a group III nitride material, such as at least one of GaN, AlGaN, and AlInGaN.

[0099] Correspondingly, for the manufacturing method, in step S1, an electron blocking layer 17 is provided between the provided light-emitting layer 12 and the P-type ion-doped layer 13; or an electron blocking layer 17 is formed after the light-emitting layer 12, and a P-type ion-doped layer 13 is formed on the electron blocking layer 17.

[0100] Figure 6 It is a schematic cross-sectional structure diagram of the semiconductor structure of the third embodiment of the present invention.

[0101] Referring to Figure 6 As shown, the semiconductor structure 3 of the third embodiment is substantially the same as the semiconductor structure 2 of the second embodiment, except that: the electron blocking layer 17 contains P-type doping ions; the electron blocking layer 17 includes a first region 171 and a second region 172.

[0102] The P-type doping ions in the first region 171 can be activated in the same process as the P-type ion doping layer 13, and a second region 172 is formed in the region where the P-type doping ions in the electron blocking layer 17 are not activated. In other words, the orthographic projection of the first region 171 of the electron blocking layer 17 on the plane where the N-type semiconductor layer 11 is located coincides with the orthographic projection of the activation region 131 of the P-type ion doping layer 13 on the plane where the N-type semiconductor layer 11 is located; the orthographic projection of the second region 172 of the electron blocking layer 17 on the plane where the N-type semiconductor layer 11 is located coincides with the orthographic projection of the non-activation region 132 of the P-type ion doping layer 13 on the plane where the N-type semiconductor layer 11 is located.

[0103] The type of P-type ions in the electron blocking layer 17 can refer to the P-type ions in the P-type ion doping layer 13.

[0104] Correspondingly, for the manufacturing method, in step S1, a P-type ion doping layer 13 is formed on the electron blocking layer 17 without activation; in step S2, the activation region is formed in the same process for the electron blocking layer 17 and the P-type ion doping layer 13. The electron blocking layer 17 and the P-type ion doping layer 13 are regarded as a whole, and the H atoms therein escape through the opening 14a.

[0105] Figure 7 It is a schematic cross-sectional structure diagram of the semiconductor structure of the fourth embodiment of the present invention.

[0106] Referring to Figure 7 As shown, the semiconductor structure 4 of the fourth embodiment is substantially the same as the semiconductor structures 1, 2, and 3 of the first, second, and third embodiments, except that the blocking layer 14 is omitted.

[0107] Omitting the blocking layer 14 can reduce the thickness of the semiconductor structure 4, which is beneficial to the miniaturization of the device.

[0108] Correspondingly, for the manufacturing method, in step S2, after the P-type ion doping layer 13 is activated, the blocking layer 14 is removed to expose the non-activation region 132. Since the P-type doping ions in the non-activation region 132 cannot generate holes, the non-activation region 132 has electrical insulation properties.

[0109] Figure 8 It is a schematic cross-sectional structure diagram of the semiconductor structure of the fifth embodiment of the present invention.

[0110] Referring to Figure 8 As shown, the semiconductor structure 5 of the fifth embodiment is substantially the same as the semiconductor structures 1, 2, 3, and 4 of the first, second, third, and fourth embodiments, except that the P-type ion doping layer 13 includes at least two activation regions 131 and at least three non-activation regions 132, and the activation regions 131 and the non-activation regions 132 are distributed at intervals; the P electrodes 152 on each activation region 131 are electrically connected together.

[0111] A plurality of activation regions 131 and a plurality of non-activation regions 132 are distributed at intervals, and a plurality of alternately distributed high-efficiency light-emitting regions and light-emitting obstacle regions can be formed. When the size of the LED area is fixed, a plurality of small-area high-efficiency light-emitting regions can further improve the electric field concentration degree of the LED compared with a large-area high-efficiency light-emitting region, the light emission is more concentrated, and the light intensity can be further improved.

[0112] Correspondingly, for the manufacturing method, in step S2, the blocking layer 14 has at least two openings 14a.

[0113] In some embodiments, the P electrodes 152 on each activation region 131 may not be electrically connected together either.

[0114] In some embodiments, the P-type ion doping layer 13 includes at least M activation regions 131 and at least M + 1 non-activation regions 132, and the activation regions 131 and the non-activation regions 132 are distributed at intervals. M is a positive integer, and M ≥ 3.

[0115] Figure 9 It is a schematic cross-sectional structure diagram of the semiconductor structure of the sixth embodiment of the present invention.

[0116] Referring to Figure 9 As shown, the semiconductor structure 6 of the sixth embodiment is substantially the same as the semiconductor structures 1, 2, 3, 4, and 5 of the first, second, third, fourth, and fifth embodiments, except that: the N electrode 151 and the P electrode 152 are not provided.

[0117] Correspondingly, for the manufacturing method, in one embodiment, all of step S3 is omitted.

[0118] In another embodiment, in step S3, the following are omitted: forming an N electrode 151 on the exposed N-type semiconductor layer 11, and forming an ohmic contact between the N electrode 151 and the N-type semiconductor layer 11; forming a P electrode 152 on the activation region 131, and forming an ohmic contact between the P electrode 152 and the activation region 131.

[0119] The semiconductor structure 6 can be produced and sold as a semi-finished product.

[0120] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that, Comprising: An N-type semiconductor layer (11), a light-emitting layer (12), and a P-type ion-doped layer (13) distributed from bottom to top. The P-type ion-doped layer (13) includes an activation region (131) and non-activation regions (132) located on both sides of the activation region (131). The P-type doping ions in the activation region (131) are activated, and the P-type doping ions in the non-activation regions (132) are passivated; Wherein, an electron blocking layer (17) is provided between the light-emitting layer (12) and the P-type ion-doped layer (13); The electron blocking layer (17) includes a first region (171) and a second region (172). The P-type doping ions in the first region (171) are activated. The projection of the first region (171) of the electron blocking layer (17) on the plane where the N-type semiconductor layer (11) is located coincides with the projection of the activation region (131) of the P-type ion-doped layer (13) on the plane where the N-type semiconductor layer (11) is located; The P-type doping ions in the second region (172) are not activated, and the projection of the second region (172) of the electron blocking layer (17) on the plane where the N-type semiconductor layer (11) is located coincides with the projection of the non-activation region (132) of the P-type ion-doped layer (13) on the plane where the N-type semiconductor layer (11) is located.

2. The semiconductor structure according to claim 1, wherein The P-type ion-doped layer (13) includes at least two activation regions (131) and at least three non-activation regions (132), and the activation regions (131) and the non-activation regions (132) are distributed at intervals.

3. The semiconductor structure according to claim 1, wherein Also comprising: A blocking layer (14), which is located on the non-activation region (132) and is used to expose the activation region (131).

4. The semiconductor structure according to claim 3, wherein The material of the blocking layer (14) includes: SiNx, N-type GaN, or a combination of SiNx and N-type GaN.

5. The semiconductor structure according to claim 1 or 2, characterized in that, The light-emitting layer (12) and the P-type ion-doped layer (13) expose a partial region of the N-type semiconductor layer (11). An N electrode (151) is provided on the exposed N-type semiconductor layer (11), and an ohmic contact is formed between the N electrode (151) and the N-type semiconductor layer (11); A P electrode (152) is provided on the activation region (131), and an ohmic contact is formed between the P electrode (152) and the activation region (131).

6. The semiconductor structure according to claim 5, wherein The P electrodes (152) on each activation region (131) are electrically connected together.

7. The semiconductor structure according to claim 1, wherein The light-emitting layer (12) includes a single quantum well structure or a multi-quantum well structure.

8. The semiconductor structure according to claim 1, characterized in that, The material of the N-type semiconductor layer (11) includes group III nitride materials, and / or the material of the light-emitting layer (12) includes group III nitride materials, and / or the material of the P-type ion-doped layer (13) includes group III nitride materials.

9. A method for fabricating a semiconductor structure, characterized in that, Comprising: Providing an N-type semiconductor layer (11), a light-emitting layer (12), a P-type ion-doped layer (13), and a blocking material layer (14') distributed from bottom to top; The barrier material layer (14') is patterned to form a barrier layer (14), and the barrier layer (14) has at least one opening (14a) to expose a partial area of the P-type ion-doped layer (13); using the barrier layer (14) as a mask, P-type doping ions in the exposed P-type ion-doped layer (13) are activated to form an activation region (131), and the P-type ion-doped layer (13) covered by the barrier layer (14) forms a non-activation region (132); Wherein, it further includes: an electron blocking layer (17) is disposed between the light-emitting layer (12) and the P-type ion-doped layer (13); The electron blocking layer (17) includes a first region (171) and a second region (172), P-type doping ions in the first region (171) are activated, and a positive projection of the first region (171) of the electron blocking layer (17) on the plane where the N-type semiconductor layer (11) is located coincides with a positive projection of the activation region (131) of the P-type ion-doped layer (13) on the plane where the N-type semiconductor layer (11) is located; P-type doping ions in the second region (172) are not activated, and a positive projection of the second region (172) of the electron blocking layer (17) on the plane where the N-type semiconductor layer (11) is located coincides with a positive projection of the non-activation region (132) of the P-type ion-doped layer (13) on the plane where the N-type semiconductor layer (11) is located.

10. The manufacturing method of the semiconductor structure according to claim 9, characterized in that, There are multiple openings (14a) in the barrier layer (14) to form at least two activation regions (131) and at least three non-activation regions (132), and the activation regions (131) and the non-activation regions (132) are distributed at intervals.

11. The manufacturing method of the semiconductor structure according to claim 9, wherein, It further includes: The barrier layer (14) is removed to expose the non-activation region (132).

12. The method for fabricating a semiconductor structure according to claim 9 or 10 or 11, wherein The material of the barrier material layer (14') includes: SiNx, N-type GaN, or a combination of SiNx and N-type GaN.

13. The manufacturing method of the semiconductor structure according to claim 9, characterized in that, The P-type doping ions are activated by annealing at a temperature higher than 500 °C.

14. The method for manufacturing a semiconductor structure according to claim 13, wherein, The P-type doping ions are activated in an atmosphere of nitrogen, a mixed gas of nitrogen and oxygen, nitrous oxide, or argon.

15. The manufacturing method of the semiconductor structure according to claim 9, characterized in that, The growth temperature range of the P-type ion-doped layer (13) is 700 °C to 1200 °C.

16. The manufacturing method of the semiconductor structure according to claim 9, characterized in that, It further includes: Partial areas of the P-type ion-doped layer (13) and the light-emitting layer (12) are removed to expose the N-type semiconductor layer (11), an N electrode (151) is formed on the exposed N-type semiconductor layer (11), and an ohmic contact is formed between the N electrode (151) and the N-type semiconductor layer (11); a P electrode (152) is formed on the activation region (131), and an ohmic contact is formed between the P electrode (152) and the activation region (131).

17. The method for fabricating a semiconductor structure according to claim 9, wherein The light-emitting layer (12) includes a single quantum well structure or a multi-quantum well structure.

18. The method for manufacturing a semiconductor structure according to claim 9, wherein, The material of the N-type semiconductor layer (11) includes group III nitride materials, and / or the material of the light-emitting layer (12) includes group III nitride materials, and / or the material of the P-type ion-doped layer (13) includes group III nitride materials.

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