Method for improving deviation between photolithography pattern and pattern on mask
By establishing a PW OPC model and OPC result inspection program, the deviation of lithographic graphics and mask pattern is improved, the problems of adhesion and disconnection in the process window are solved, the product yield is improved, and mass production requirements are met.
Patent Information
- Application Number
- CN202210889932.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-07-27
- Publication Date
- 2025-09-02
- Estimated Expiration
- 2042-07-27
AI Technical Summary
In the prior art, at nodes of 19nm and below, the deviation between the lithographic patterns and the patterns on the masking pattern leads to easy adhesion and disconnection in the process window, affecting product yield.
By establishing a PW OPC model, collecting the safe range of exposure-assisted graphics parameters, using the OPC result inspection program to evaluate the process fluctuation bandwidth value, selecting the test graph structure, analyzing the upper and lower layers of overlay relationships, re-target processing of the graph structure, re-forming the layout line width and period, and fine-tuning it in combination with the PV-band results to meet the process window that meets the mass production requirements.
The process window of the 19nm Nand Flash CG layer is effectively improved, avoiding the risk of weakness, improving product yield, and meeting design rules does not affect device performance.
Smart Images

Figure CN115616852B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductors, and in particular to a method for improving the deviation between a photolithography pattern and a pattern on a mask. Background Art
[0002] As technology nodes continue to decrease, the feature size of semiconductor devices continues to shrink. The optical proximity effect (OPE) causes the deviation between the lithography pattern on the silicon wafer and the pattern on the mask to become increasingly serious, especially at the 19nm node and below. Due to the limitations of machine capabilities, some existing resolution enhancement techniques (RET), such as OPC (Optical Proximity Correction), SRAF (Subresolution Assist Features), PSM (Phase-Shifting Mask), SMO (Source-Mask Optimization) and other related technologies, cannot support all layout types to meet the process window required for factory mass production.
[0003] For the 19nm CG (control gate) layer, the 76nm period is close to the tool lithography limit. To ensure the process window in the high-density (Dense) cell area, off-axis illumination (Off-axis Illumination) or SMO extreme illumination is usually used. However, under these lighting conditions, the process window of low-density (semi-dense) patterns, especially isolated (Iso) patterns, is often unable to meet the requirements using traditional technologies, which is known as a weak point, affecting product yield.
[0004] like Figure 1 The layout shown in the figure is processed in the traditional way. Here, SRAF (Sub Resolution Assist Features) and OPC (Optical Proximity Correction) are used together to perform optical correction. The result is shown in the figure. Figure 2 In order to study its effect, we first establish a PW model (process window model), and then analyze its process fluctuation bandwidth (PV-band) to determine its process window, as shown in the figure below. Figure 3 As shown. Figure 3 The blue dashed box indicates the area with a narrow process window predicted by the model. This area has a large PV-band value and is prone to sticking and breaking within the process window. This represents a weak point that traditional technologies cannot address. Summary of the Invention
[0005] The technical problem to be solved by the present invention is to solve the problem of easy adhesion and wire breakage within the process window in the traditional process.
[0006] In order to solve the above technical problems, the present invention provides a method for improving the deviation between a photolithography pattern and a pattern on a mask, comprising the following steps:
[0007] Step S1: Establish a PW OPC model, collect the safe ranges of the main parameters of the exposure auxiliary pattern, and use the model and OPC result inspection program to use the obtained process fluctuation bandwidth value as a criterion for judging the size of the process window;
[0008] Step S2, selecting a test graphic structure;
[0009] Step S3, analyzing the relationship between the results and the upper and lower overlay layers;
[0010] Step S4, performing re-target processing on the graphic structure;
[0011] Step S5: Modify the layout line width and cycle to achieve the process window required for mass production.
[0012] Preferably, the method further comprises the following steps:
[0013] In step S6, the modified layout is fine-tuned based on the PV-band results, continuously improving and finally reaching the process window required for mass production.
[0014] Preferably, the PW OPC model is an OPC model covering multiple energy and depth of focus conditions within the process window.
[0015] Preferably, the evaluation criterion is the range of variation of graphic dimensions obtained under simulated different process conditions.
[0016] Preferably, the evaluation criterion is a process fluctuation bandwidth value, which is used to evaluate the quality of the process window. The smaller the value, the larger the process window.
[0017] Preferably, the test pattern is a pattern structure whose process window still cannot meet the process requirements even after being processed by multiple resolution enhancement technologies.
[0018] Preferably, the modified layout uses a model-based process fluctuation bandwidth value to guide the re-target direction and the obtained result.
[0019] Preferably, the method is used for a 19nm Nand Flash CG layer.
[0020] When the cycle of key graphics approaches the limit of the machine's lithography, existing technologies cannot support a process window that meets the factory's mass production requirements for all layout types. This technical invention re-targets the 19Nand CG (control gate) layer, effectively improving the weak point process window. While the lithography layout still meets the design rules, it will not affect device performance, effectively avoiding the risks caused by weak points and improving product yield. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] Figure 1-Figure 3 It is a schematic diagram of the layout in the existing technology process.
[0022] Figure 4 The figure is a flow chart of the method for improving the deviation between the photolithography pattern and the pattern on the mask according to the present invention.
[0023] Figure 5-Figure 7 This is a schematic diagram of the layout after using the present invention. DETAILED DESCRIPTION
[0024] like Figure 4 As shown, the method of improving the deviation between the photolithography pattern and the pattern on the mask of the present invention includes the following steps:
[0025] A method for improving the deviation between a photolithography pattern and a pattern on a mask, characterized by comprising the following steps:
[0026] In step S1, a PW OPC model is established to collect the safe ranges of the main parameters of the exposure auxiliary pattern. The model and the OPC result inspection program are used to obtain the process fluctuation bandwidth value as the criterion for judging the size of the process window.
[0027] In the present invention, the PW OPC model covers multiple energy and depth of focus conditions within the process window. The evaluation criterion is the range of pattern size variation obtained under simulated different process conditions. In other words, the process fluctuation bandwidth is used to evaluate the quality of the process window; the smaller the value, the larger the process window.
[0028] Step S2, selecting a test graphic structure;
[0029] In this embodiment, the test pattern is a pattern structure in which the process window still cannot meet the process requirements even after being processed by multiple resolution enhancement technologies.
[0030] Step S3: Analyze the relationship between the results and the upper and lower layer overlays.
[0031] Step S4: performing re-target processing on the graphic structure, that is, target resetting processing.
[0032] Step S5: Modify the layout line width and cycle to achieve the process window required for mass production.
[0033] Preferably, the method may further include the following steps:
[0034] Step S6: Fine-tune the modified layout based on the PV-band results, continuously improving and ultimately achieving the process window required for mass production. The modified layout is the result of using the process fluctuation bandwidth value based on the model to guide the re-target direction.
[0035] The method of the present invention can be used for 19nm Nand Flash CG layer.
[0036] The layout after the revision using this technology is as follows Figure 5 As shown, compared with the original Figure 1 The line width and period of some areas are increased and OPC processing is performed on them, such as Figure 6 The PV-band results analyzed using the PW model are shown below. Figure 7 As shown, it can be seen that compared with the original PV-band ( Figure 3 ), Figure 7 The results given are much improved.
[0037] The present invention has been described in detail above by way of specific embodiments and examples, but these do not constitute limitations of the present invention. Without departing from the principles of the present invention, those skilled in the art may make many variations and improvements, which should also be considered within the scope of protection of the present invention.
Claims
1. A method for improving the deviation between a photolithography pattern and a pattern on a mask, characterized in that: The following steps are involved: Step S1: Establish a PW OPC model, collect the safe ranges of the main parameters of the exposure auxiliary pattern, and use the model and OPC result inspection program to use the obtained process fluctuation bandwidth value as a criterion for judging the size of the process window; Step S2, selecting a test pattern structure; the test pattern structure is a pattern structure whose process window still cannot meet the process requirements after being processed by multiple resolution enhancement technologies; Step S3, analyzing the relationship between the results and the upper and lower overlay layers; Step S4, performing re-target processing on the graphic structure; Step S5, revising the line width and period of the layout, increasing the line width and period of some areas, and performing OPC processing on them to achieve the process window required for mass production.
2. The method for improving the deviation between the photolithography pattern and the pattern on the mask according to claim 1, characterized in that: The following steps are also included: In step S6, the modified layout is fine-tuned based on the PV-band results, continuously improving and finally reaching the process window required for mass production.
3. The method for improving the deviation between the photolithography pattern and the pattern on the mask according to claim 1, wherein: The PW OPC model is an OPC model covering multiple energy and focus depth conditions within the process window.
4. The method for improving the deviation between the photolithography pattern and the pattern on the mask according to claim 1, characterized in that: The evaluation criteria are the range of graphic size variation obtained under simulated different process conditions.
5. The method for improving the deviation between the photolithography pattern and the pattern on the mask according to claim 4, characterized in that: The evaluation criterion is the process fluctuation bandwidth value, which is used to evaluate the quality of the process window. The smaller the value, the larger the process window.
6. The method for improving the deviation between the photolithography pattern and the pattern on the mask according to claim 1, characterized in that: The test pattern is a pattern structure in which the process window still cannot meet the process requirements even after being processed by multiple resolution enhancement technologies.
7. The method for improving the deviation between the photolithography pattern and the pattern on the mask according to claim 2, characterized in that: The modified layout is the result obtained by using the process fluctuation bandwidth value based on the model to guide the re-target direction.
8. The method for improving the deviation between a photolithographic pattern and a pattern on a mask according to any one of claims 1 to 7, wherein: The method is used for 19nm Nand Flash CG layer.
Citation Information
Patent Citations
Method for optimizing exposure auxiliary graph
CN104090468A