A data storage method, a data dump method, and a data storage device

Abstract

The application discloses a data storage method, a data dump method and a data storage device. The data storage method comprises the following steps: acquiring bus data via an avionics bus connector; and storing the acquired bus data into at least one second storage chip. The data storage method can record bus data at a high speed in real time, thereby providing support for post-analysis of bus network abnormalities.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, bus data storage technology, and more specifically, to a data storage method, a data dumping method, and a data storage device. Background Technology

[0002] When the bus network encounters special circumstances such as sudden transmission tasks or anomalies in individual communication links, the recorded data can accurately reproduce the original scenario to help find the cause of the network anomaly. For valuable post-event analysis, such as unresponsive control commands or loss of critical data, storing bus data can preserve more valuable information and meet the needs of typical bus application scenarios such as complex environments.

[0003] In related technologies, the data interfaces of bus data storage devices are mostly based on traditional buses, such as 1553, RapidIO, and CAN, which are incompatible with newer buses, such as the next-generation avionics bus (avionics refers to the sum of all electronic systems on an aircraft), and cannot be directly connected. Furthermore, bus storage devices in these technologies are difficult to customize and cannot perform secondary encapsulation of bus data, thus causing inconvenience for post-analysis. Summary of the Invention

[0004] In view of this, the present disclosure provides the following solutions.

[0005] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0006] One embodiment of this disclosure provides a data storage method, including:

[0007] Bus data is acquired via the avionics bus connector;

[0008] The acquired bus data is stored in at least one second memory chip.

[0009] In an exemplary embodiment of this disclosure, storing the acquired bus data into at least one second memory chip includes:

[0010] Determine if this is the first time data is written to the bus;

[0011] In the case of the first write of bus data, a file is created for the acquired bus data; the bus data is stored in at least one second memory chip according to the file information and flash memory information, wherein the file information and flash memory information are pre-stored in the first memory chip; the file information of the first memory chip is updated according to the written bus data;

[0012] If it is not the first time bus data is written, the bus data is stored in at least one second memory chip according to file information and flash memory information, wherein the file information and flash memory information are pre-stored in the first memory chip; the file information of the first memory chip is updated according to the written bus data.

[0013] The file information includes: file name, file size, and data address index; the flash memory information includes: bad block replacement table, address mapping table, and usage statistics.

[0014] In an exemplary embodiment of this disclosure, before storing the acquired bus data into at least one second memory chip, the method further includes:

[0015] The bus data is deredundant.

[0016] The deredundant bus data is encapsulated into a data packet;

[0017] The bus data, encapsulated as a data packet, is stored in memory via direct memory access;

[0018] Read the stored bus data from memory and generate a checksum for the bus data.

[0019] In an exemplary embodiment of this disclosure, storing the bus data to at least one second memory chip includes:

[0020] The bus data read from memory and the generated checksum are stored sequentially into at least one second memory chip.

[0021] An embodiment of this disclosure also provides a data dumping method, including:

[0022] Data dump messages are obtained from the Ethernet interface via the avionics bus connector, and the data dump messages originate from the dump device.

[0023] Read bus data corresponding to the data dump message from at least one second memory chip;

[0024] The read bus data is transmitted from the connector to the dump device via an Ethernet interface.

[0025] In an exemplary embodiment of this disclosure, reading bus data corresponding to the data dump message from at least one second memory chip includes:

[0026] Parse the data dump message to obtain the filename of the dumped bus data;

[0027] Obtain the file information corresponding to the parsed file name;

[0028] Bus data is read from at least one second storage chip based on the file information and flash memory information, wherein the file information and flash memory information are pre-stored in the first storage chip;

[0029] The file information includes: file name, file size, and data address index; the flash memory information includes: bad block replacement table, address mapping table, and usage statistics.

[0030] In an exemplary embodiment of this disclosure, before transmitting the read bus data from the connector to the dump device via an Ethernet interface, the method further includes:

[0031] The faulty bus data is recovered based on the check code, wherein the check code is the check code of the bus data stored in the second memory chip;

[0032] The recovered bus data is transferred to memory via direct memory access;

[0033] Read the stored bus data from memory.

[0034] This disclosure also provides a data storage device, including:

[0035] The system includes an avionics bus connector, a fully programmable system-on-a-chip (SoC), a memory, a first memory chip, and at least one second memory chip. The fully programmable SoC is connected to the avionics bus connector, the memory, the first memory chip, and the second memory chip, respectively.

[0036] The fully programmable system-on-a-chip is configured to perform the data storage method described in any embodiment of this disclosure.

[0037] This disclosure also provides a data storage device, including:

[0038] The system includes an avionics bus connector, a fully programmable system-on-a-chip (SoC), a memory, a first memory chip, at least one second memory chip, and an Ethernet interface. The fully programmable SoC is connected to the connector, the memory, the first memory chip, the second memory chip, and the Ethernet interface, respectively. The Ethernet interface is also connected to the avionics bus connector.

[0039] The fully programmable on-chip system is configured to perform the data dumping method described in any embodiment of this disclosure.

[0040] In an exemplary embodiment of this disclosure, the Ethernet interface includes an Ethernet PHY chip and an Ethernet transformer chip.

[0041] The data storage method of this disclosure includes: acquiring bus data via an avionics bus connector; and storing the acquired bus data in at least one second memory chip. The data dumping method of this disclosure includes: acquiring a data dumping message from an Ethernet interface via an avionics bus connector, the data dumping message originating from a dumping device; reading bus data corresponding to the data dumping message from at least one second memory chip; and transmitting the read bus data from the connector to the dumping device via the Ethernet interface. The data storage method and data dumping method described in any embodiment of this disclosure can record and dump bus data at high speed and in real time, thereby providing support for post-event analysis of bus network anomalies. The data storage device of this disclosure includes: an avionics bus connector, a fully programmable on-chip system, memory, a first memory chip, and at least one second memory chip. The fully programmable on-chip system is connected to the avionics bus connector, memory, first memory chip, and second memory chip respectively. The fully programmable on-chip system is configured to execute the data storage method described in any embodiment of this disclosure. The data storage device described in any embodiment of this disclosure provides a high-speed, high-capacity storage device for bus networks that can adapt to various bus rates and features a simple hardware structure, high reliability, and easy functional upgrades.

[0042] Other features and advantages of this disclosure will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the disclosure. The objects and other advantages of this disclosure may be realized and obtained by means of the structures particularly pointed out in the description, claims and drawings. Attached Figure Description

[0043] The accompanying drawings are provided to further understand the technical solutions of this disclosure and constitute a part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0044] Figure 1 This is a schematic diagram of a data storage device according to an embodiment of the present disclosure;

[0045] Figure 2 This is a schematic diagram of a data storage device according to yet another embodiment of the present disclosure;

[0046] Figure 3 This is a schematic diagram of the functional architecture of a fully programmable system-on-a-chip according to an embodiment of the present disclosure;

[0047] Figure 4 This is a schematic diagram of a data storage method according to an embodiment of the present disclosure;

[0048] Figure 5 This is a schematic diagram of a data storage method according to yet another embodiment of this disclosure;

[0049] Figure 6 This is a schematic diagram of a data dumping method according to an embodiment of the present disclosure;

[0050] Figure 7 This is a schematic diagram of a data dumping method according to yet another embodiment of this disclosure. Detailed Implementation

[0051] This disclosure describes several embodiments, but these descriptions are exemplary and not limiting, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0052] This disclosure includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this disclosure may also be combined with any conventional features or elements to form a unique inventive scheme as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive schemes to form another unique inventive scheme as defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in this disclosure may be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

[0053] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that the method or process does not depend on the specific order of steps described herein. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims relating to the method and / or process should not be limited to the steps performed in the order written, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments disclosed herein.

[0054] Figure 1An embodiment of the present disclosure is shown, which can be applied to a data storage device, as shown in the figure, including: an avionics bus connector, a fully programmable system-on-a-chip, a memory, a first memory chip, and at least one second memory chip, wherein the fully programmable system-on-a-chip is connected to the avionics bus connector, the memory, the first memory chip, and the second memory chip respectively.

[0055] Figure 2 An embodiment of the present disclosure is shown, which can be applied to a data storage device, as shown in the figure, including: an avionics bus connector, a fully programmable system-on-a-chip, a memory, a first memory chip, at least one second memory chip, and an Ethernet interface. The fully programmable system-on-a-chip is connected to the connector, the memory, the first memory chip, the second memory chip, and the Ethernet interface, respectively. The Ethernet interface is also connected to the avionics bus connector.

[0056] like Figure 3 As shown, an All Programmable System-on-Chip (APSOC) comprises two parts: Programmable Logic (PL) and Processing System (PS). The PL part implements functions including: a new type of bus monitoring node; and a flash memory interface. The PS part implements functions including: an operating system; a file system; a flash translation layer (FTL); Ethernet communication; and control of various functions.

[0057] The main functions implemented by the programmable logic (PL) section include: a new type of bus monitoring node, which realizes functions such as bus data reception, redundancy management, data encapsulation, and direct memory access (DMA); and a flash memory interface, which realizes the timing of the read and write interfaces of the first and second memory chips, as well as bus data error checking and correction (ECC).

[0058] The functions implemented by the processor's PS section include: operating system, implementing the Linux operating system and including a TCP / IP protocol stack; file system, forming bus data into files to achieve a high-speed, lightweight file system for easy management; flash translation layer (FTL), including wear leveling (WL), bad block management (BBM), and low-level driver (LLD); Ethernet communication, exporting stored bus data to data dumping devices such as computers via Ethernet; and control and scheduling of various functions.

[0059] In an exemplary embodiment of this disclosure, the fully programmable on-chip system is configured as follows:

[0060] Bus data is acquired via the avionics bus connector;

[0061] The acquired bus data is stored in at least one second memory chip.

[0062] In an exemplary embodiment of this disclosure, the fully programmable on-chip system is configured as follows:

[0063] Data dump messages are obtained from the Ethernet interface via the avionics bus connector, and the data dump messages originate from the dump device.

[0064] Read bus data corresponding to the data dump message from at least one second memory chip;

[0065] The read bus data is transmitted from the connector to the dump device via an Ethernet interface.

[0066] In an exemplary embodiment of this disclosure, the avionics bus connectors include, but are not limited to: VPX connectors (VPX, also known as VITA 46, is a new generation high-speed serial bus standard proposed by the VITA organization in 2007 based on its VME bus), LRM connectors (LRM, The Line Replaceable Module), and FMC connectors (MFC, FPGA Mezzanine Card).

[0067] In an exemplary embodiment of this disclosure, the VPX connector is a VPX-21T8aAA8-A connector. Bus data is transmitted to the fully programmable on-chip system via two redundant channels, A and B.

[0068] In an exemplary embodiment of this disclosure, the first memory chip is a NOR FLASH memory chip used to store the logic program and software program of the fully programmable on-chip system; the second memory chip is a NAND FLASH memory chip used to realize non-volatile read and write of bus data.

[0069] In an exemplary embodiment of this disclosure, the Ethernet interface includes an Ethernet PHY chip and an Ethernet transformer chip.

[0070] In an exemplary embodiment of this disclosure, the Ethernet PHY chip is an 88E1111 chip, and the Ethernet transformer chip is an HX5120 chip.

[0071] In an exemplary embodiment of this disclosure, the number of second memory chips is changed to upgrade the capacity of the data storage device.

[0072] The data storage device described in any embodiment of this disclosure provides a high-speed, high-capacity storage device for bus networks that can adapt to various bus rates and features simple hardware structure, high reliability, and easy functional upgrades.

[0073] This disclosure provides a data storage method, such as... Figure 4 As shown, it includes:

[0074] Step 101: Obtain bus data via the avionics bus connector;

[0075] Step 102: Store the acquired bus data into at least one second memory chip.

[0076] In an exemplary embodiment of this disclosure, step 102, storing the acquired bus data into at least one second memory chip, includes:

[0077] Determine if this is the first time data is written to the bus;

[0078] In the case of the first write of bus data, a file is created for the acquired bus data; the bus data is stored in at least one second memory chip according to the file information and flash memory information, wherein the file information and flash memory information are pre-stored in the first memory chip; the file information of the first memory chip is updated according to the written bus data;

[0079] If it is not the first time bus data is written, the bus data is stored in at least one second memory chip according to file information and flash memory information, wherein the file information and flash memory information are pre-stored in the first memory chip; the file information of the first memory chip is updated according to the written bus data.

[0080] The file information includes: file name, file size, and data address index; the flash memory information includes: bad block replacement table, address mapping table, and usage statistics.

[0081] In an exemplary embodiment of this disclosure, prior to step 102, the method further includes:

[0082] The bus data is deredundant.

[0083] The deredundant bus data is encapsulated into a data packet;

[0084] The bus data, encapsulated as a data packet, is stored in memory via direct memory access;

[0085] Read the stored bus data from memory and generate a checksum for the bus data.

[0086] This embodiment can realize redundant management and data encapsulation of bus data, providing support for high-speed real-time recording of bus data.

[0087] In an exemplary embodiment of this disclosure, storing the bus data to at least one second memory chip includes:

[0088] The bus data read from memory and the generated checksum are stored sequentially into at least one second memory chip.

[0089] The data storage method described in any embodiment of this disclosure can record bus data at high speed in real time, thereby providing support for post-event analysis of bus network anomalies.

[0090] Another embodiment of this disclosure provides a data storage method, such as... Figure 3 and Figure 5 As shown, it includes:

[0091] Step 301: Read and load the PL programmable logic program and PS software program from the first memory chip.

[0092] Step 302: Read file information and flash memory information from the first storage chip and transfer them to memory.

[0093] Step 303: Initialize each module.

[0094] In an exemplary embodiment of this disclosure, initializing each module includes initializing the registers and memory addresses of the bus monitoring node module and the flash interface module, and transferring data to a specified address via direct memory access.

[0095] Step 304: Determine whether the bus monitoring node has received bus data; if bus data has been received, transfer the bus data to memory; if no bus data has been received, determine whether to exit or continue looping to check bus data based on the running flag.

[0096] Step 305: Store the bus data into the second storage chip according to the file information and the flash memory information.

[0097] Step 306: Determine whether this is the first time bus data is written. If it is the first time bus data is written, execute step 307 to create a new file and update the file information; if it is not the first time bus data is written, execute step 308 to update the file information.

[0098] Step 307: Create a new file and update the file information.

[0099] Step 308: Update the file information.

[0100] Step 309: After completing the bus data storage, determine whether to exit the program based on the running flag. If the program continues to run, loop back to step 304 to check again whether bus data has been received; if the program exits, determine whether there is a file to close.

[0101] Step 310: If there are any files that are not closed, close them; otherwise, exit the program.

[0102] Step 311: Mark the file as closed and update the file information.

[0103] Step 312: Exit the program.

[0104] One embodiment of this disclosure also provides a data dumping method, such as... Figure 6 As shown, it includes:

[0105] Step 201: Obtain a data dump message from the Ethernet interface via the avionics bus connector, the data dump message originating from the dump device;

[0106] Step 202: Read bus data corresponding to the data dump message from at least one second memory chip;

[0107] Step 203: The read bus data is transmitted from the connector to the dump device via the Ethernet interface.

[0108] In an exemplary embodiment of this disclosure, step 202, reading bus data corresponding to the data dump message from at least one second memory chip, includes:

[0109] Parse the data dump message to obtain the filename of the dumped bus data;

[0110] Obtain the file information corresponding to the parsed file name;

[0111] Bus data is read from at least one second storage chip based on the file information and flash memory information, wherein the file information and flash memory information are pre-stored in the first storage chip;

[0112] The file information includes: file name, file size, and data address index; the flash memory information includes: bad block replacement table, address mapping table, and usage statistics.

[0113] In an exemplary embodiment of this disclosure, prior to step 203, the method further includes:

[0114] The faulty bus data is recovered based on the check code, wherein the check code is the check code of the bus data stored in the second memory chip;

[0115] The recovered bus data is transferred to memory via direct memory access;

[0116] Read the stored bus data from memory.

[0117] The data dumping method described in any embodiment of this disclosure can transmit bus data stored on a second memory chip at high speed to a dumping device, such as a computer, thereby providing support for post-event analysis of bus network anomalies.

[0118] Another embodiment of this disclosure provides a data dumping method, such as... Figure 7 As shown, it includes:

[0119] Step 401: Read and load the PL programmable logic program and PS software program from the first memory chip.

[0120] Step 402: Read file information and flash memory information from the first storage chip and transfer them to memory.

[0121] Step 403: Initialize each module.

[0122] In an exemplary embodiment of this disclosure, initializing each module includes initializing the registers and memory addresses of the bus monitoring node module and the flash interface module, and transferring data to a specified address via direct memory access.

[0123] Step 404: Determine whether a data dump message has been received via the Ethernet interface; if a data dump message has been received, parse the filename of the bus data to be dumped from the data dump message; if no bus data has been received, determine whether to exit or continue looping to check for data dump messages based on the running flag.

[0124] Step 405: Parse the filename of the bus data to be dumped from the data dump message.

[0125] Step 406: Based on the file information and the flash memory information, locate the bus data corresponding to the data dump message in the second storage chip.

[0126] Step 407: Read the bus data that has been found.

[0127] Step 408: The read bus data is transmitted from the connector to the dump device via the Ethernet interface.

[0128] Step 409: Determine whether the transfer of all file data is complete based on the file size information. If the transfer is complete, check the program running flag; otherwise, loop back to step 406 to continue searching for the bus data address.

[0129] Step 410: Determine whether to exit the program based on the running flag. If the program continues to run, loop back to step 404 to check again for a data dump message; if the program exits, then exit the program.

[0130] Step 411: Exit the program.

[0131] One embodiment of this disclosure also provides a data storage device, such as... Figure 1 As shown, it includes:

[0132] The system includes an avionics bus connector, a fully programmable system-on-a-chip (SoC), a memory, a first memory chip, and at least one second memory chip. The fully programmable SoC is connected to the avionics bus connector, the memory, the first memory chip, and the second memory chip, respectively.

[0133] The fully programmable system-on-a-chip is configured to perform the data storage method described in any embodiment of this disclosure.

[0134] One embodiment of this disclosure also provides a data storage device, such as... Figure 2 As shown, it includes:

[0135] The system includes an avionics bus connector, a fully programmable system-on-a-chip (SoC), a memory, a first memory chip, at least one second memory chip, and an Ethernet interface. The fully programmable SoC is connected to the connector, the memory, the first memory chip, the second memory chip, and the Ethernet interface, respectively. The Ethernet interface is also connected to the avionics bus connector.

[0136] The fully programmable on-chip system is configured to perform the data dumping method described in any embodiment of this disclosure.

[0137] The data storage device described in any embodiment of this disclosure provides a high-speed, high-capacity storage device for bus networks that can adapt to various bus rates and features simple hardware structure, high reliability, and easy functional upgrades.

[0138] The data storage method of this disclosure includes: acquiring bus data via an avionics bus connector; and storing the acquired bus data in at least one second memory chip. The data dumping method of this disclosure includes: acquiring a data dumping message from an Ethernet interface via an avionics bus connector, the data dumping message originating from a dumping device; reading bus data corresponding to the data dumping message from at least one second memory chip; and transmitting the read bus data from the connector to the dumping device via the Ethernet interface. The data storage method and data dumping method described in any embodiment of this disclosure can record and dump bus data at high speed and in real time, thereby providing support for post-event analysis of bus network anomalies. The data storage device of this disclosure includes: an avionics bus connector, a fully programmable on-chip system, memory, a first memory chip, and at least one second memory chip. The fully programmable on-chip system is connected to the avionics bus connector, memory, first memory chip, and second memory chip respectively. The fully programmable on-chip system is configured to execute the data storage method described in any embodiment of this disclosure. The data storage device described in any embodiment of this disclosure provides a high-speed, high-capacity storage device for bus networks that can adapt to various bus rates and features a simple hardware structure, high reliability, and easy functional upgrades.

[0139] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

Claims

1. A data storage method, comprising: Bus data is acquired via the avionics bus connector; The acquired bus data is stored in at least one second memory chip; The process of storing the acquired bus data into at least one second memory chip includes: Determine if this is the first time data is written to the bus; In the case of the first write of bus data, a file is created for the acquired bus data; the bus data is stored in at least one second memory chip according to the file information and flash memory information, wherein the file information and flash memory information are pre-stored in the first memory chip; the file information of the first memory chip is updated according to the written bus data; If it is not the first time bus data is written, the bus data is stored in at least one second memory chip according to file information and flash memory information, wherein the file information and flash memory information are pre-stored in the first memory chip; the file information of the first memory chip is updated according to the written bus data. The file information includes: file name, file size, and data address index; the flash memory information includes: bad block replacement table, address mapping table, and usage statistics.

2. The data storage method according to claim 1, characterized in that: Before storing the acquired bus data into at least one second memory chip, the method further includes: The bus data is deredundant. The deredundant bus data is encapsulated into a data packet; The bus data, encapsulated as a data packet, is stored in memory via direct memory access; Read the stored bus data from memory and generate a checksum for the bus data.

3. The data storage method according to claim 2, characterized in that: The step of storing the bus data into at least one second memory chip includes: The bus data read from memory and the generated checksum are stored sequentially into at least one second memory chip.

4. A data dumping method, comprising: Data dump messages are obtained from the Ethernet interface via the avionics bus connector, and the data dump messages originate from the dump device. Read bus data corresponding to the data dump message from at least one second memory chip; The read bus data is transmitted from the connector to the dump device via an Ethernet interface. The step of reading bus data corresponding to the data dump message from at least one second memory chip includes: Parse the data dump message to obtain the filename of the dumped bus data; Obtain the file information corresponding to the parsed file name; Bus data is read from at least one second storage chip based on the file information and flash memory information, wherein the file information and flash memory information are pre-stored in the first storage chip; The file information includes: file name, file size, and data address index; the flash memory information includes: bad block replacement table, address mapping table, and usage statistics.

5. The data dumping method according to claim 4, characterized in that: Before transmitting the read bus data from the connector to the dump device via the Ethernet interface, the method further includes: The faulty bus data is recovered based on the check code, wherein the check code is the check code of the bus data stored in the second memory chip; The recovered bus data is transferred to memory via direct memory access; Read the stored bus data from memory.

6. A data storage device, comprising: The system includes an avionics bus connector, a fully programmable system-on-a-chip (SoC), a memory, a first memory chip, and at least one second memory chip. The fully programmable SoC is connected to the avionics bus connector, the memory, the first memory chip, and the second memory chip, respectively. The fully programmable system-on-a-chip is configured to perform the data storage method as described in any one of claims 1 to 3.

7. A data storage device, comprising: The system includes an avionics bus connector, a fully programmable system-on-a-chip (SoC), a memory, a first memory chip, at least one second memory chip, and an Ethernet interface. The fully programmable SoC is connected to the connector, the memory, the first memory chip, the second memory chip, and the Ethernet interface, respectively. The Ethernet interface is also connected to the avionics bus connector. The fully programmable on-chip system is configured to perform the data dumping method as described in any one of claims 4 to 5.

8. The data storage device according to claim 7, characterized in that: The Ethernet interface includes an Ethernet PHY chip and an Ethernet transformer chip.

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