Display Substrate, Driving Method Thereof, Display Panel, and Display Device

Abstract

The present disclosure provides a display substrate, including: a substrate, a plurality of voltage transmission lines, one end of the voltage transmission line extending into a first driving area and connected to a corresponding voltage supply terminal; a plurality of pixel unit groups, the pixel unit group including a plurality of pixel units, the pixel unit including a driving transistor and a reset and data writing circuit; the reset and data writing circuit is configured to: control writing the reset voltage provided by the voltage transmission line to the gate of the driving transistor, and starting from stopping writing the reset voltage to the gate of the driving transistor, writing the data voltage to the gate of the driving transistor after a configured preset interval duration; for any two adjacent pixel unit groups, the preset interval duration configured for the pixel units in the pixel unit group closer to the first driving area among the two adjacent pixel unit groups is greater than the preset interval duration configured for the pixel units in the pixel unit group farther from the first driving area among the two adjacent pixel unit groups.

Description

Technical Field

[0001] The present invention relates to the field of displays, and particularly to a display substrate, a driving method thereof, a display panel, and a display device. Background Art

[0002] The application of Active Matrix Organic Light Emitting Diode (AMOLED) panels is becoming more and more widespread. The pixel display device of an AMOLED is an Organic Light-Emitting Diode (OLED). An AMOLED emits light by driving a thin film transistor to generate a driving current in a saturated state, and this driving current drives the OLED to emit light. Summary of the Invention

[0003] In a first aspect, an embodiment of the present disclosure provides a display substrate, including:

[0004] a substrate, including: a display area and a non-display area located around the display area, the non-display area including: a first driving area located on one side of the display area and arranged along a first direction with the display area;

[0005] a plurality of voltage supply terminals, located on one side of the substrate and within the first driving area;

[0006] a plurality of voltage transmission lines, located on one side of the substrate and within the display area, the voltage transmission lines extending along the first direction, and one end of the voltage transmission lines extending into the first driving area and connected to the corresponding voltage supply terminals;

[0007] a plurality of pixel unit groups, located on one side of the substrate and within the display area, the plurality of pixel unit groups arranged along the first direction, each pixel unit group including a plurality of pixel units arranged along a second direction, the second direction intersecting the first direction, and each pixel unit including a driving transistor and a reset and data writing circuit, the reset and data writing circuit being connected to the corresponding voltage transmission line;

[0008] The reset and data writing circuit is configured to: within one frame, in response to the control of a reset control signal, write the reset voltage provided by the voltage transmission line to the gate of the driving transistor, and starting from when writing the reset voltage to the gate of the driving transistor stops, after a configured preset interval duration, in response to the control of a data writing control signal, write a data voltage to the gate of the driving transistor;

[0009] For any two adjacent pixel unit groups, the preset interval duration configured for the pixel units in the pixel unit group closer to the first driving area among the two adjacent pixel unit groups is greater than the preset interval duration configured for the pixel units in the pixel unit group farther from the first driving area among the two adjacent pixel unit groups.

[0010] In some embodiments, the reset and data writing circuits included in the pixel units within all the pixel unit groups start writing the reset voltage to the gates of the corresponding driving transistors simultaneously, and stop writing the reset voltage to the gates of the driving transistors simultaneously.

[0011] In some embodiments, starting from the pixel unit group farthest from the first driving area to the pixel unit group closest to the first driving area;

[0012] The reset and data writing circuits included in the pixel units within each pixel unit group sequentially write the data voltage to the gates of the corresponding driving transistors.

[0013] In some embodiments, the display substrate further includes:

[0014] A first driving module, electrically connected to each of the voltage supply terminals, configured to provide the reset voltage and the data voltage to each of the voltage supply terminals, so that the voltage transmission lines connected to the voltage supply terminals transmit the reset voltage and the data voltage to the corresponding pixel units.

[0015] In some embodiments, the display substrate further includes:

[0016] A plurality of first control signal lines, located in the display area, the first control signal lines corresponding to the pixel unit groups one by one, and the reset and data writing circuits are connected to the corresponding first control signal lines;

[0017] A second driving module, electrically connected to each of the first control signal lines, configured to supply a reset control signal and a data writing control signal to each of the first control signal lines, so that each of the first control signal lines transmits the reset control signal and the data writing control signal to the corresponding pixel unit.

[0018] In some embodiments, the second driving module is specifically configured to: simultaneously provide the reset control signal to each of the first control signal lines, and starting from the first control signal line corresponding to the pixel unit group farthest from the first driving area to the first control signal line corresponding to the pixel unit group closest to the first driving area, sequentially provide the data writing control signal to each of the first control signal lines respectively.

[0019] In some embodiments, the pixel unit further includes:

[0020] The threshold compensation circuit is connected to a first power supply terminal, a second control signal line, a gate of the driving transistor, and a first pole of the driving transistor, and is configured to obtain a threshold voltage of the driving transistor in response to a signal provided by the second control signal line for threshold compensation of the driving transistor.

[0021] In some embodiments, the reset and data writing circuit includes a first transistor;

[0022] A gate of the first transistor is connected to a first control signal line, a first pole of the first transistor is connected to a voltage transmission line, and a second pole of the first transistor is connected to a gate of the driving transistor;

[0023] The threshold compensation circuit includes: a second transistor, a first capacitor, and a second capacitor;

[0024] A gate of the second transistor is connected to the second control signal line, a first pole of the second transistor is connected to the first power supply terminal, and a second pole of the second transistor is connected to a first pole of the driving transistor;

[0025] A first end of the first capacitor is connected to a gate of the driving transistor, and a second end of the first capacitor is connected to a first pole of the driving transistor;

[0026] A first end of the second capacitor is connected to the first power supply terminal, and a second end of the second capacitor is connected to a first pole of the driving transistor.

[0027] In some embodiments, the pixel unit further includes: a light emission control circuit and a light emitting element, wherein the light emission control circuit includes a third transistor;

[0028] A gate of the third transistor is connected to a third control signal line, a first pole of the third transistor is connected to a second pole of the driving transistor, and a second pole of the third transistor is connected to a second power supply terminal;

[0029] A first end of the light emitting element is connected to a second pole of the driving transistor, and a second end of the light emitting element is connected to the second power supply terminal.

[0030] In a second aspect, an embodiment of the present disclosure further provides a display panel, including: the display substrate provided in the first aspect.

[0031] In a third aspect, an embodiment of the present disclosure further provides a display device, including: the display panel provided in the second aspect.

[0032] In a fourth aspect, embodiments of the present disclosure further provide a driving method for a display substrate as described in the first aspect, including:

[0033] Pixels in each pixel unit group operate according to the received reset control signal and data writing control signal. The working phases of pixels in any one pixel unit group in one frame include a reset phase and a data writing phase that starts after a configured preset interval from the end of the reset phase. Wherein, in the reset phase, the reset and data writing circuit in the pixel unit writes the reset voltage provided by the voltage transmission line to the gate of the driving transistor in response to the control of the reset control signal; in the data writing phase, the reset and data writing circuit in the pixel unit writes the data voltage to the gate of the driving transistor in response to the control of the data writing control signal.

[0034] For any two adjacent pixel unit groups, the preset interval configured for pixels in the pixel unit group closer to the first driving area among the two adjacent pixel unit groups is greater than the preset interval configured for pixels in the pixel unit group farther from the first driving area among the two adjacent pixel unit groups.

[0035] In some embodiments, while pixels in each pixel unit group operate according to the received reset control signal and data writing control signal, it further includes:

[0036] The second driving module simultaneously provides the reset control signal to each first control signal line to control pixels in all pixel unit groups to simultaneously operate in the reset phase;

[0037] In the order from the first control signal line corresponding to the pixel unit group farthest from the first driving area to the first control signal line corresponding to the pixel unit group closest to the first driving area, the second driving module sequentially provides the data writing control signal to each first control signal line to control pixels in each pixel unit group to sequentially operate in the corresponding data writing phase. Description of the Drawings

[0038] Figure 1 It is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure;

[0039] Figure 2 It is a schematic circuit diagram of a pixel unit in an embodiment of the present disclosure;

[0040] Figure 3 For Figure 2A working timing diagram of the pixel unit shown therein;

[0041] Figure 4 A working timing schematic diagram of some of the first control signal lines in the embodiments of the present disclosure;

[0042] Figure 5 A flowchart of a driving method for a display substrate provided by the embodiments of the present disclosure. Detailed implementation manners

[0043] The following will describe in detail the specific implementation manners of the present disclosure with reference to the accompanying drawings. It should be understood that the specific implementation manners described herein are only for explaining and understanding the present disclosure, and are not used to limit the present disclosure.

[0044] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0045] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure shall have the ordinary meanings understood by those of ordinary skill in the art to which the present disclosure pertains. The "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components. Similarly, words such as "include" or "comprise" mean that the elements or items appearing before the word cover the elements or items listed after the word and their equivalents, without excluding other elements or items. "Connection" or "coupling" and similar terms are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Upper", "lower", "left", "right", etc. are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0046] It should be noted that the transistors in the present disclosure can be thin-film transistors, field-effect transistors, or other switching devices with the same characteristics. A transistor generally includes three poles: a gate, a source, and a drain. The source and drain in a transistor are symmetric in structure. Among them, the pole that sends carriers is used as the source, and the pole that receives carriers is used as the drain. In actual applications, for a transistor, according to the position and function of the transistor in the circuit and the channel type of the transistor, the source can be used as the first pole of the transistor, and correspondingly, the drain can be used as the second pole of the transistor; or, the drain can be used as the first pole of the transistor, and correspondingly, the source can be used as the second pole of the switching transistor.

[0047] In addition, according to the transistor characteristics, transistors can be divided into N-type transistors and P-type transistors; when the transistor is an N-type transistor, its conduction voltage is a high-level voltage, and its cut-off voltage is a low-level voltage; when the transistor is a P-type transistor, its conduction voltage is a low-level voltage, and its cut-off voltage is a high-level voltage.

[0048] In the present disclosure, the case where all the transistors in the pixel unit are simultaneously N-type transistors or simultaneously P-type transistors is only a preferred solution in the present disclosure. At this time, all the transistors in the pixel unit can be simultaneously fabricated based on the same process, which is beneficial to shortening the fabrication cycle. In the embodiments of the present disclosure, an example is described by taking all the transistors in the pixel unit as P-type transistors.

[0049] In the related art, a reset voltage needs to be used to reset the gate of the driving transistor in the pixel unit to ensure the normal operation of the subsequent working process of the pixel unit. However, it is found in actual applications that due to the impedance (IR Drop) on the voltage transmission line, the reset voltage attenuates during transmission, and the attenuation degree of the reset voltage at different positions on the voltage transmission line is different; specifically, the closer the position on the voltage transmission line is to the voltage supply terminal for providing the reset voltage, the lower the attenuation degree of the reset voltage, and the farther the position on the voltage transmission line is from the voltage supply terminal, the higher the attenuation degree of the reset voltage.

[0050] Since each voltage transmission line needs to provide a reset voltage for multiple pixel units, and multiple pixel units corresponding to the same voltage transmission line are connected to different positions on the voltage transmission line, this will cause the reset voltages actually provided by the voltage transmission line to different pixel units to be different. Among them, for the pixel unit whose connection position to the voltage transmission line is closer to the corresponding voltage supply terminal, the attenuation degree of the reset voltage received by this pixel unit relative to the reset voltage at the voltage supply terminal is lower; for the pixel unit whose connection position to the voltage transmission line is farther from the corresponding voltage supply terminal, the attenuation degree of the reset voltage received by this pixel unit relative to the reset voltage at the voltage supply terminal is higher.

[0051] Since the final emission brightness of the light-emitting unit in the pixel unit is not only related to the data voltage received by the pixel unit, but also related to the initial voltage at the gate of the driving transistor when the pixel unit starts to write the data voltage to the gate of the driving transistor, and the initial voltage at the gate of the driving transistor when the pixel unit starts to write the data voltage to the gate of the driving transistor is related to the reset voltage actually received by the pixel unit; that is to say, the final emission brightness of the light-emitting unit in the pixel unit is also related to the reset voltage actually received by the pixel unit.

[0052] For different pixel units connected to the same voltage transmission line, when the corresponding data voltages are the same, due to the different reset voltages received, the final emission brightnesses are different, which will affect the brightness uniformity of the display substrate.

[0053] In order to effectively solve the above technical problems existing in the related art, the present disclosure provides corresponding solutions.

[0054] Figure 1 It is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure. Figure 2 It is a schematic circuit diagram of a pixel unit in an embodiment of the present disclosure. Figure 3 For Figure 2 a working timing diagram of the pixel unit shown in Figure 4 It is a schematic working timing diagram of some first control signal lines in an embodiment of the present disclosure. As Figures 1 to 4 shown, the display substrate includes: a substrate 1, a plurality of voltage supply terminals (not shown), a plurality of voltage transmission lines TL, and a plurality of pixel unit groups.

[0055] The substrate 1 includes: a display area 101 and a non-display area surrounding the display area 101. The non-display area includes: a first driving area 102 located on one side of the display area 101 and arranged along the first direction Y with the display area 101. Among them, the substrate 1 can be a silicon-based substrate, and the silicon-based substrate can be a rigid silicon-based substrate (for example, a glass-silicon-based substrate or a PMMA-silicon-based substrate) or a flexible silicon-based substrate (for example, a PET-silicon-based substrate, a PEN-silicon-based substrate or a PI-silicon-based substrate).

[0056] The voltage supply terminals are located on one side of the substrate 1 and within the first driving area 102; the voltage transmission lines TL are located on one side of the substrate 1 and within the display area 101. The voltage transmission lines TL extend along the first direction Y, and one end of the voltage transmission lines TL extends into the first driving area 102 and is connected to the corresponding voltage supply terminals; among them, the voltage supply terminals can be used to provide a reset voltage, and the voltage transmission lines TL can be used to transmit the reset voltage provided by the voltage supply terminals to the corresponding pixel units P.

[0057] The pixel unit groups are located on one side of the substrate 1 and within the display area 101. A plurality of pixel unit groups are arranged along the first direction Y. Each pixel unit group includes a plurality of pixel units P arranged along the second direction X, where the second direction X intersects the first direction Y. The pixel unit P includes a driving transistor TD and a reset and data writing circuit 11, and the reset and data writing circuit 11 is connected to a corresponding voltage transmission line TL. That is, for the pixel units P within the pixel unit groups closer to the first driving area 102, the attenuation degree of the reset voltage received through the voltage transmission line TL (compared to the reset voltage at the corresponding voltage supply terminal) is lower; for the pixel units P within the pixel unit groups farther from the first driving area 102, the attenuation degree of the reset voltage received through the voltage transmission line TL (compared to the reset voltage at the corresponding voltage supply terminal) is higher.

[0058] As an example, the first direction Y is Figure 1 the column direction in Figure 1 and the second direction X is the row direction in, and one pixel unit group is a row of pixel units.

[0059] Within the pixel unit P, the reset and data writing circuit 11 is configured to: within one frame, in response to the control of the reset control signal, write the reset voltage provided by the voltage transmission line TL to the gate of the driving transistor TD, and starting from when writing the reset voltage to the gate of the driving transistor TD stops, after the configured preset interval duration, in response to the control of the data writing control signal, write the data voltage to the gate of the driving transistor TD.

[0060] For any two adjacent pixel unit groups, the preset interval duration configured for the pixel units P within the pixel unit group closer to the first driving area 102 among the two adjacent pixel unit groups is greater than the preset interval duration configured for the pixel units P within the pixel unit group farther from the first driving area 102 among the two adjacent pixel unit groups. That is, the closer the pixel unit group is to the first driving area 102, the longer the configured preset interval duration. That is to say, in the order from the pixel unit group farthest from the first driving area 102 to the pixel unit group closest to the first driving area 102, the preset interval durations configured for each pixel unit group gradually increase.

[0061] In the present disclosure, the working phases of any one pixel unit P within one frame at least include a reset phase, an intermediate phase (with a corresponding duration of "preset interval duration"), and a data writing phase that are sequentially performed; the working phases of all the pixel units P within the same pixel unit group always remain synchronized, that is, the reset phases are synchronized, the intermediate phases are synchronized, and the data writing phases are synchronized.

[0062] For any pixel unit P, in the intermediate stage, since the reset and data writing circuit 11 does not write a voltage to the gate of the driving transistor TD, the gate of the driving transistor TD is in a floating state. At this time, the voltage at the gate of the driving transistor TD will leak through the electrical devices connected thereto (for example, the transistors in the reset and data writing circuit 11), which will cause the reset voltage written to the gate of the driving transistor TD in the reset stage to decay. That is, the reset voltage written to the gate of the driving transistor TD in the reset stage will decay due to leakage in the intermediate stage; among them, the longer the duration of the intermediate stage, the higher the degree of voltage decay of the reset voltage at the gate of the driving transistor TD due to leakage.

[0063] Based on the above principle, in the present disclosure, the duration of the intermediate stage (i.e., the preset interval duration) configured for each pixel unit group can be designed accordingly to compensate for the problem that the degree of reset voltage decay of the pixel unit P in different pixel unit groups is different due to different IR Drops on the voltage transmission line TL.

[0064] Specifically, since the pixel unit P in the pixel unit group closer to the first driving region 102 has a lower degree of decay of the reset voltage received through the voltage transmission line TL, while the pixel unit P in the pixel unit group farther from the first driving region 102 has a higher degree of decay of the reset voltage received through the voltage transmission line TL; in order to compensate for the different degrees of reset voltage decay caused by different IR Drops on the voltage transmission line TL, the preset interval duration configured for the pixel unit P in the pixel unit group closer to the first driving region 102 can be set larger, so that the degree of voltage decay of the reset voltage at the gate of the driving transistor TD in the pixel unit P in the pixel unit group closer to the first driving region 102 due to leakage in the intermediate stage is higher; the preset interval duration configured for the pixel unit P in the pixel unit group farther from the first driving region 102 can be set smaller, so that the degree of voltage decay of the reset voltage at the gate of the driving transistor TD in the pixel unit P in the pixel unit group closer to the first driving region 102 due to leakage in the intermediate stage is lower.

[0065] In the embodiments of the present disclosure, the reset voltage attenuation is caused by the following two factors: (1) the reset voltage attenuation caused by the IR Drop on the voltage transmission line TL (abbreviated as "reset voltage IR Drop attenuation"); (2) the reset voltage attenuation caused by leakage in the intermediate stage (abbreviated as "reset voltage leakage attenuation"). The closer the pixel unit P in the pixel unit group is to the first driving region 102, the weaker the reset voltage IR Drop attenuation effect of the pixel unit P, but the stronger the reset voltage leakage attenuation effect; the farther the pixel unit P in the pixel unit group is from the first driving region 102, the stronger the reset voltage IR Drop attenuation effect of the pixel unit P, but the weaker the reset voltage leakage attenuation effect. By utilizing the complementary strengths of the reset voltage attenuation effects, the initial voltages at the gates of the driving transistors TD at the start of the data writing stage can be made the same or approximately the same for the pixel units P in each pixel unit group, effectively improving the brightness uniformity of the display substrate.

[0066] In some embodiments, the reset and data writing circuits 11 included in the pixel units P in all the pixel unit groups start writing the reset voltage to the gates of the corresponding driving transistors TD simultaneously, and stop writing the reset voltage to the gates of the driving transistors TD simultaneously.

[0067] Further, in some embodiments, starting from the pixel unit group farthest from the first driving region 102 to the pixel unit group closest to the first driving region 102, the reset and data writing circuits 11 included in the pixel units P in each pixel unit group sequentially write the data voltage to the gates of the corresponding driving transistors TD.

[0068] Through the above settings, it is possible to achieve that, in the order from the pixel unit group farthest from the first driving region 102 to the pixel unit group closest to the first driving region 102, the preset interval durations (the durations corresponding to the intermediate stage) configured for each pixel unit group gradually increase.

[0069] In some embodiments, the display substrate further includes: a first driving module 2; the first driving module 2 is electrically connected to each voltage supply terminal and is configured to provide a reset voltage and a data voltage to each voltage supply terminal for the voltage transmission line TL connected to each voltage supply terminal to transmit the reset voltage and the data voltage to the corresponding pixel unit P. That is to say, in the embodiments of the present disclosure, the voltage transmission line TL can be used not only to provide a reset voltage to the pixel unit P, but also to provide a data voltage to the pixel unit P.

[0070] In an embodiment of the present disclosure, the number of the first driving modules 2 may be one or more (only one first driving module 2 is schematically shown in the figure); the first driving module 2 may specifically be a display driver integrated circuit (DDIC for short), and the first driving module 2 can be bonded to the corresponding voltage supply terminal through a flexible circuit board 4.

[0071] In some embodiments, the display substrate further includes: a plurality of first control signal lines WS and a second driving module 3. The first control signal lines WS are located in the display area 101, and the first control signal lines WS correspond to the pixel unit groups one by one. The reset and data writing circuit 11 in the pixel unit P is connected to the corresponding first control signal line WS.

[0072] The second driving module 3 is electrically connected to each of the first control signal lines WS and is configured to supply a reset control signal and a data writing control signal to each of the first control signal lines WS, so that each of the first control signal lines WS can transmit the reset control signal and the data writing control signal to the corresponding pixel unit P.

[0073] In an embodiment of the present disclosure, the second driving module 3 can supply a reset control signal to each of the first control signal lines WS, and can also supply a data writing control signal to each of the first control signal lines WS.

[0074] As an alternative solution, the second driving module 3 is a gate driving circuit fabricated in the second driving area 103 in the non-display area by using the GOA process. The second driving area 103 is located on one side of the display area 101 and is along the second direction X with the display area 101. The gate driving circuit generally includes a plurality of cascaded shift register units (no corresponding figure is given in this case).

[0075] As another alternative solution, the second driving module 3 may specifically be a DDIC, and the number of the second driving modules 3 may be one or more. At this time, a plurality of driving connection terminals are provided in the non-display area (the driving connection terminals may be located in the first driving area 102 or the second driving area 103). The first control signal lines WS are electrically connected to the corresponding driving connection terminals, and the second driving module 3 can be bonded to the corresponding driving connection terminals through a flexible circuit board 4 ( Figure 1 The case where the second driving module 3 is located on the side close to the second driving area 103 is exemplarily shown).

[0076] The technical solution of the present disclosure does not limit the specific form and the setting position of the second driving module 3.

[0077] In some embodiments, the second driving module 3 is specifically configured to simultaneously provide a reset control signal to each first control signal line WS, so that the reset and data writing circuits 11 included in the pixel units P within all pixel unit groups start writing a reset voltage to the gates of the corresponding driving transistors TD simultaneously, and stop writing the reset voltage to the gates of the driving transistors TD simultaneously; meanwhile, the second driving module 3 is further configured to sequentially provide data writing control signals to each first control signal line WS starting from the first control signal line WS corresponding to the pixel unit group farthest from the first driving region 102 to the first control signal line WS corresponding to the pixel unit group closest to the first driving region 102, so that the reset and data writing circuits 11 included in the pixel units P within each pixel unit group sequentially write a data voltage to the gates of the corresponding driving transistors TD starting from the pixel unit group farthest from the first driving region 102 to the pixel unit group closest to the first driving region 102.

[0078] See Figures 2 to 4 As shown, in some embodiments, the pixel unit P includes not only a driving transistor TD, a reset and data writing circuit 11, but also a threshold compensation circuit 12. Among them, the threshold compensation circuit 12 is connected to the first power supply terminal, the second control signal line DS, the gate of the driving transistor TD, and the first pole of the driving transistor TD, and is configured to obtain the threshold voltage of the driving transistor TD in response to the control of the signal provided by the second control signal line DS for threshold compensation of the driving transistor TD.

[0079] In some embodiments, the reset and data writing circuit 11 includes a first transistor T1; the gate of the first transistor T1 is connected to the first control signal line WS, the first pole of the first transistor T1 is connected to the voltage transmission line TL, and the second pole of the first transistor T1 is connected to the gate of the driving transistor TD. That is, a first transistor T1 is used to write a reset voltage and a data voltage to the gate of the driving transistor TD at different stages.

[0080] In some embodiments, the threshold compensation circuit 12 includes: a second transistor T2, a first capacitor C1, and a second capacitor C2; the gate of the second transistor T2 is connected to the second control signal line DS, the first pole of the second transistor T2 is connected to the first power supply terminal, and the second pole of the second transistor T2 is connected to the first pole of the driving transistor TD; the first end of the first capacitor C1 is connected to the gate of the driving transistor TD, and the second end of the first capacitor C1 is connected to the first pole of the driving transistor TD; the first end of the second capacitor C2 is connected to the first power supply terminal, and the second end of the second capacitor C2 is connected to the first pole of the driving transistor TD.

[0081] In some embodiments, the pixel unit P further includes: a light-emitting control circuit 13 and a light-emitting element OLED; the light-emitting control circuit 13 includes a third transistor T3; the gate of the third transistor T3 is connected to a third control signal line AZ, the first pole of the third transistor T3 is connected to the second pole of the driving transistor TD, and the second pole of the third transistor T3 is connected to a second power supply terminal; the first end of the light-emitting element OLED is connected to the second pole of the driving transistor TD, and the second end of the light-emitting element OLED is connected to the second power supply terminal.

[0082] Taking each transistor in the pixel unit P as a P-type transistor, the first power supply terminal provides a first operating voltage Vdd, the second power supply terminal provides a second operating voltage Vss, the reset voltage Vofs received by the pixel unit P through the voltage transmission line TL, and the data voltage received by the pixel unit P through the voltage transmission line TL is Vdata as an example, Figure 2 A detailed description of an optional operating process of the pixel unit P shown is given.

[0083] See Figure 3 as shown, Figure 2 The pixel unit P shown includes the following several operating stages in one frame: a reset stage, an intermediate stage, a data writing stage, and a light-emitting stage; among them, the intermediate stage includes: a holding stage and a self-discharge threshold compensation stage.

[0084] In the reset stage t1, the first control signal line WS provides a low-level signal (the first control signal line WS provides a reset control signal), the second control signal line DS provides a low-level signal, and the third control signal line AZ provides a low-level signal; at this time, the first transistor T1, the second transistor T2, and the third transistor T3 are all turned on.

[0085] The first transistor T1 writes the reset voltage Vofs provided by the voltage transmission line TL to the gate of the driving transistor TD. The voltage at the gate of the driving transistor TD is Vofs. At this time, the voltage at the first node N1 is Vofs; at the same time, the second transistor T2 writes the first operating voltage Vdd provided by the first power supply terminal to the first pole of the driving transistor TD. At this time, the voltage at the second node N2 is Vdd.

[0086] In the holding stage t2_1, the first control signal line WS provides a high-level signal, the second control signal line DS provides a low-level signal, and the third control signal line AZ provides a low-level signal; at this time, the first transistor T1 is turned off, and the second transistor T2 and the third transistor T3 are both turned on.

[0087] Since the first transistor T1 is turned off, the gate of the driving transistor TD is in a floating state, that is, the point N1 is in a floating state. At this time, the first transistor T1 will generate leakage current through the electrical devices connected to it (for example, the first transistor T1, the driving transistor TD, the first capacitor C1, etc.), and the phenomenon of reset voltage attenuation appears at the first node N1.

[0088] At the end of the holding stage t2_1, the voltage at the first node N1 is Vofs_i, and the voltage at the second node N2 remains Vdd. Among them, the longer the duration of the holding stage t2_1, the higher the degree of reset voltage attenuation at the first node N1, that is, the smaller the voltage Vofs_i at the first node N1 at the end of the holding stage t2_1.

[0089] In the self-discharge threshold compensation stage t2_2, the first control signal line WS provides a high-level signal, the second control signal line DS provides a low-high level signal, and the third control signal line AZ provides a low-level signal; at this time, both the first transistor T1 and the second transistor T2 are turned off, and the third transistor T3 is turned on.

[0090] When entering the self-discharge threshold compensation stage t2_2, since the driving transistor TD is in the on state, the second node N2 can be discharged through the second power supply terminal based on the path formed by the driving transistor TD and the third transistor T3, causing the voltage at the second node N2 to drop. At the same time, due to the bootstrap effect of the first capacitor C1, the voltage at the first node N1 also drops to a certain extent, but the voltage drop rate at the second node N2 is faster than that at the first node N1. At this time, the gate-source voltage Vgs of the driving transistor TD (the voltage difference between the first node N1 and the second node N2, which is also the voltage difference across the first capacitor C1, and Vgs is a negative voltage) generally shows an increasing trend. When the gate-source voltage Vgs of the driving transistor TD is equal to the threshold voltage Vth of the driving transistor TD, the driving transistor TD is in the off state.

[0091] At the end of the self-discharge threshold compensation stage t2_2, the voltage at the first node N1 is VN1_t2, the voltage at the second node N2 is VN2_t2, and the gate-source voltage Vgs of the driving transistor TD = VN1_t2 - VN2_t2 = Vth.

[0092] It should be noted that the smaller the voltage Vofs_i at the first node N1 at the starting moment of entering the self-discharge threshold compensation stage t2_2, the smaller the voltage VN1_t2 at the first node N1 at the end of the self-discharge threshold compensation stage t2_2. Also, because the longer the duration of the holding stage t2_1, the smaller the voltage Vofs_i at the first node N1 at the starting moment of entering the self-discharge threshold compensation stage t2_2, it can be known that the longer the duration of the holding stage t2_1, the smaller the voltage VN1_t2 at the first node N1 at the end of the self-discharge threshold compensation stage t2_2.

[0093] In addition, in the self-discharge threshold compensation stage t2_2, the voltage drop at the first node N1 is partly due to the bootstrap effect of the first capacitor C1 and partly due to the leakage at the first node N1. However, the duration of the self-discharge threshold compensation stage t2_2 corresponding to the pixel unit P in different pixel unit groups in the display substrate is the same. It can also be understood that the degree of voltage drop due to leakage during the self-discharge threshold compensation stage t2_2 at the first node N1 (the gate of the driving transistor TD) in the pixel unit P in different pixel unit groups is the same. In other words, the difference in the "reset voltage leakage attenuation" at the gate of the driving transistor TD in the pixel unit P in different pixel unit groups in the middle stage is mainly caused by the difference in the duration of the holding stage t2_1. This will be described in detail later in combination with Figure 4 for a detailed description.

[0094] In the data writing stage, the first control signal line WS first provides a low-level signal (the first control signal line WS provides a data writing control signal) and then provides a high-level signal, the second control signal line DS first provides a high-level signal and then provides a low-level signal, and the switching moment when the second control signal line DS switches from providing a high-level signal to providing a low-level signal is after the switching moment when the first control signal line WS switches from providing a low-level signal to providing a high-level signal.

[0095] Among them, when the first control signal line WS provides a low-level signal, the first transistor T1 is turned on, and the data voltage Vdata is written to the gate of the driving transistor TD, that is, the first node N1. At this time, the voltage at the first node N1 changes from VN1_t2 to VN1_t3, where VN1_t3 = Vdata.

[0096] At this time, due to the bootstrap effect of the first capacitor C1 and the capacitive voltage division of the first capacitor C1 and the second capacitor C2, the voltage at the second node N2 becomes VN2_t3:

[0097] VN2_t3 = VN2_t2 + [C1 / (C1 + C2)] * (Vdata - VN1_t2) Equation (1)

[0098] Since VN2_t2 = VN1_t2 - Vth, substituting it into the above formula (1), we can obtain:

[0099] VN2_t3 = VN1_t2 - Vth + [C1 / (C1 + C2)]*(Vdata - VN1_t2) Equation (2)

[0100] At this time, the gate-source voltage Vgs of the driving transistor TD is:

[0101]

[0102] When the second control signal line DS provides a low-level signal, the second transistor T2 conducts, and the first operating voltage Vdd is written to the second node N2 through the second transistor T2. The voltage VN2_t3' at the second node N2 = Vdd. At the same time, the voltage at the first node will also be pulled up to VN1_t3' due to the bootstrap effect of the first capacitor C1. At this time, due to the effect of the first capacitor C1, the gate-source voltage Vgs of the driving transistor TD maintains the previous state, that is, Vgs = VN1_t3' - VN2_t3' satisfies:

[0103] VN1_t3' - VN2_t3' = [C2 / (C1 + C2)]*VN1_t2 + [C2 / (C1 + C2)]*Vdata + Vth

[0104] During the light-emitting stage, the first control signal line WS provides a high-level signal, the second control signal line DS provides a low-level signal, and the third control signal line AZ provides a high-level signal; at this time, the first transistor T1 and the third transistor T3 are turned off, and the second transistor T2 is turned on.

[0105] The gate-source voltage Vgs of the driving transistor TD maintains the state of the previous stage, that is, Vgs:

[0106] Vgs = [C2 / (C1 + C2)]*VN1_t2 + [C2 / (C1 + C2)]*Vdata + Vth

[0107] At this time, the driving current I output by the driving transistor TD is:

[0108] I = K*(Vgs - Vth) 2

[0109] = K*{[C2 / (C1 + C2)]*VN1_t2 + [C2 / (C1 + C2)]*Vdata + Vth - Vth} 2

[0110] = K*{[C2 / (C1 + C2)]*VN1_t2 + [C2 / (C1 + C2)]*Vdata} 2

[0111] Among them, K is a constant and is related to the channel characteristics of the driving transistor TD; the magnitude of the driving current I determines the luminance of the light-emitting element OLED; among them, the larger the driving current, the brighter the luminance of the light-emitting element OLED. Thus, it can be seen that the luminance of the light-emitting element OLED is not only related to the data voltage Vdata, but also related to the voltage VN1_t2 at the first node N1 at the end of the self-discharge threshold compensation stage t2_2; among them, when Vdata is constant, the larger VN1_t2 is, the larger the value of the driving current I is, and the brighter the luminance of the light-emitting element OLED is.

[0112] In addition, because the voltage VN1_t2 at the first node N1 at the end of the self-discharge threshold compensation stage t2_2 is positively correlated with the voltage Vofs_i at the first node N1 at the end of the holding stage t2_1, so when Vdata is constant, the larger the voltage Vofs_i at the first node N1 at the end of the holding stage t1’ is, the brighter the luminance of the light-emitting element OLED is.

[0113] See Figure 4 As shown, for the convenience of description, the pixel unit group closest to the source driver area in the display area 101 is called the first row of pixel units P, and the pixel unit group farthest from the source driver area in the display area 101 is called the last row of pixel units P; the first control signal line WS and the second control signal line DS configured for the first row of pixel units P are respectively called the first row WS and the first row DS, and the first control signal line WS and the second control signal line DS configured for the last row of pixel units P are respectively called the last row WS and the last row DS. The first control signal line WS and the second control signal line DS configured for a certain row of pixel units P between the first row of pixel units P and the last row of pixel units P are respectively called the middle row WS and the middle row DS.

[0114] Combined with the above analysis of Figure 3 As shown in the timing diagram, there are two low-level active pulse signals on each first control signal line WS. The first low-level active pulse signal is used to write the reset voltage Vofs provided by the voltage transmission line TL to the gate of the driving transistor TD during the reset stage, and the second low-level active pulse signal is used to write the data voltage Vdata provided by the voltage transmission line TL to the gate of the driving transistor TDTD during the data writing stage.

[0115] During the driving process of one frame time of the entire display substrate, first, the second driving module 3 simultaneously provides a reset control signal (a low-level effective pulse signal) to each first control signal line WS to control the pixel units P in all pixel unit groups to work in the reset stage simultaneously; then, when the second driving module 3 stops providing the reset control signal, all the pixel units P on the display substrate row start the holding stage; next, in the order from the last row DS to the first row DS, each second control signal line DS sequentially provides an ineffective level signal; and, in the order from the last row WS to the first row WS, the second driving module 3 sequentially provides a data writing control signal (a low-level effective pulse signal) to each first control signal line WS, that is, starting from the pixel units P in the last row (the last pixel unit group) to the pixel units P in the first row (the first pixel unit group), the pixel units P in each row sequentially perform the self-discharge threshold compensation stage and the data writing stage.

[0116] In the embodiment of the present disclosure, by designing the duration of the holding stage corresponding to each row of pixel units P, the leakage attenuation degree of the reset voltage of each row of pixel units P in the corresponding intermediate stage can be controlled. In the actual design process, ensuring that the reset voltages loaded at the inner gate of the driving transistor TD of each row of pixel units P are the same or approximately the same at the end of the holding stage can achieve that the initial voltages of each row of pixel units P are the same or approximately the same when entering the data writing stage.

[0117] Also, due to the IR Drop factor on the voltage transmission line TL, the IR Drop attenuation effect corresponding to each row of pixel units P gradually increases in the direction away from the first driving area 102, and the reset voltage received by each row of pixel units P in the reset stage gradually decreases in the direction away from the first driving area 102; to ensure that the reset voltage attenuation degrees of each row of pixel units P are the same or approximately the same, it is necessary to make the leakage attenuation effect of the reset voltage of each row of pixel units P in the corresponding intermediate stage gradually weaken in the direction away from the first driving area 102, that is, in the direction away from the first driving area 102, the duration of the intermediate stage configured for each row of pixel units P should gradually decrease; and because the durations of the self-discharge threshold compensation stages configured for each row of pixel units P are equal, in the direction away from the first driving area 102, the durations of the holding stages configured for each row of pixel units P gradually decrease, so as to achieve the complementary strength of the reset voltage attenuation effect.

[0118] Based on the same inventive concept, the embodiment of the present disclosure also provides a driving method for a display substrate, and the driving method for the display substrate includes:

[0119] Step S0: The pixel units in each pixel unit group operate according to the received reset control signal and data writing control signal. The working phases of the pixel units in any one pixel unit group in one frame include a reset phase and a data writing phase that starts after a configured preset interval from the end of the reset phase. Among them, in the reset phase, the reset and data writing circuit in the pixel unit writes the reset voltage provided by the voltage transmission line to the gate of the driving transistor in response to the control of the reset control signal. In the data writing phase, the reset and data writing circuit in the pixel unit writes the data voltage to the gate of the driving transistor in response to the control of the data writing control signal. Among them, for any two adjacent pixel unit groups, the preset interval configured for the pixel units in the pixel unit group closer to the first driving area among the two adjacent pixel unit groups is greater than the preset interval configured for the pixel units in the pixel unit group farther from the first driving area among the two adjacent pixel unit groups.

[0120] In the present disclosure, the duration of the intermediate phase (i.e., the preset interval) configured for each pixel unit group can be designed accordingly to compensate for the problem that the attenuation degree of the reset voltage is different for the pixel units in different pixel unit groups due to different IR Drops on the voltage transmission line. Among them, for the pixel units in the pixel unit group closer to the first driving area, the IR Drop attenuation effect of the reset voltage is weaker, but the leakage attenuation effect of the reset voltage is stronger. For the pixel units in the pixel unit group farther from the first driving area, the IR Drop attenuation effect of the reset voltage is stronger, but the leakage attenuation effect of the reset voltage is weaker. By utilizing the strong-weak complementarity of the reset voltage attenuation effect, the initial voltages at the gates of the driving transistors at the start of the data writing phase of the pixel units in each pixel unit group can be made the same or approximately the same, effectively improving the brightness uniformity of the display substrate.

[0121] Figure 5 It is a flowchart of a driving method for a display substrate provided by an embodiment of the present disclosure. As Figure 5 shown, the driving method includes:

[0122] Step S1: The second driving module simultaneously provides the reset control signal to each first control signal line, and the pixel units in all pixel unit groups operate in the reset phase simultaneously.

[0123] Step S2: In the order from the first control signal line corresponding to the pixel unit group farthest from the first driving area to the first control signal line corresponding to the pixel unit group closest to the first driving area, the second driving module sequentially provides the data writing control signal to each first control signal line, and the pixel units in each pixel unit group operate in the corresponding data writing phase in sequence.

[0124] For the descriptions of steps S1 and S2, reference may be made to the corresponding content in the previous embodiments, which will not be elaborated herein.

[0125] Based on the same inventive concept, an embodiment of the present disclosure further provides a display panel, which includes a display substrate, and the display substrate may adopt the display substrate in the above embodiment.

[0126] Based on the same inventive concept, an embodiment of the present disclosure further provides a display device, which includes a display panel, and the display panel may adopt the display panel in the above embodiment.

[0127] The above display device may be: any product or component with a display function such as an electronic paper, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc., and the present disclosure does not make any limitation thereto.

[0128] It can be understood that the above embodiments are merely exemplary embodiments adopted to illustrate the principle of the present disclosure, and however, the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present disclosure, and these modifications and improvements are also regarded as the protection scope of the present disclosure.

Claims

1. A display substrate, characterized in that, Comprising: A substrate, comprising: a display area and a non-display area located around the display area, the non-display area comprising: a first driving area located on one side of the display area and arranged with the display area in a first direction; A plurality of voltage supply terminals, located on one side of the substrate and within the first driving area; A plurality of voltage transmission lines, located on one side of the substrate and within the display area, the voltage transmission lines extending in the first direction, and one end of the voltage transmission lines extending into the first driving area and connected to the corresponding voltage supply terminals; A plurality of pixel unit groups, located on one side of the substrate and within the display area, the plurality of pixel unit groups arranged in the first direction, each pixel unit group comprising a plurality of pixel units arranged in a second direction, the second direction intersecting the first direction, each pixel unit comprising a driving transistor and a reset and data writing circuit, the reset and data writing circuit connected to the corresponding voltage transmission line; The reset and data writing circuit is configured to: within one frame, in response to the control of a reset control signal, write the reset voltage provided by the voltage transmission line to the gate of the driving transistor, and starting from when writing the reset voltage to the gate of the driving transistor stops, after a configured preset interval duration, in response to the control of a data writing control signal, write a data voltage to the gate of the driving transistor; For any two adjacent pixel unit groups, the preset interval duration configured for the pixel units in the pixel unit group closer to the first driving area among the two adjacent pixel unit groups is greater than the preset interval duration configured for the pixel units in the pixel unit group farther from the first driving area among the two adjacent pixel unit groups.

2. The display substrate according to claim 1, wherein All the reset and data writing circuits included in the pixel units within all the pixel unit groups start writing the reset voltage to the gates of the corresponding driving transistors simultaneously, and stop writing the reset voltage to the gates of the driving transistors simultaneously.

3. The display substrate according to claim 2, wherein Starting from the pixel unit group farthest from the first driving area to the pixel unit group closest to the first driving area; The reset and data writing circuits included in the pixel units within each pixel unit group sequentially write the data voltage to the gates of the corresponding driving transistors.

4. The display substrate according to claim 3, wherein Further comprising: A first driving module, electrically connected to each voltage supply terminal, configured to provide the reset voltage and the data voltage to each voltage supply terminal for the voltage transmission lines connected to each voltage supply terminal to transmit the reset voltage and the data voltage to the corresponding pixel units.

5. The display substrate according to claim 3, wherein Further comprising: A plurality of first control signal lines, located in the display area, the first control signal lines corresponding to the pixel unit groups one by one, the reset and data writing circuit connected to the corresponding first control signal line; A second driving module, electrically connected to each of the first control signal lines, is configured to provide a reset control signal and the data writing control signal to each of the first control signal lines, so that each of the first control signal lines transmits the reset control signal and the data writing control signal to the corresponding pixel unit.

6. The display substrate according to claim 5, wherein The second driving module is specifically configured to: simultaneously provide the reset control signal to each of the first control signal lines, and sequentially provide the data writing control signal to each of the first control signal lines starting from the first control signal line corresponding to the pixel unit group farthest from the first driving area to the first control signal line corresponding to the pixel unit group closest to the first driving area.

7. The display substrate according to any one of claims 1 to 6, characterized in that The pixel unit further includes: A threshold compensation circuit, connected to a first power supply terminal, a second control signal line, a gate of the driving transistor, and a first pole of the driving transistor, is configured to obtain a threshold voltage of the driving transistor in response to a signal provided by the second control signal line for threshold compensation of the driving transistor.

8. The display substrate according to claim 7, wherein The reset and data writing circuit includes a first transistor; A gate of the first transistor is connected to the first control signal line, a first pole of the first transistor is connected to a voltage transmission line, and a second pole of the first transistor is connected to the gate of the driving transistor; The threshold compensation circuit includes: a second transistor, a first capacitor, and a second capacitor; A gate of the second transistor is connected to the second control signal line, a first pole of the second transistor is connected to the first power supply terminal, and a second pole of the second transistor is connected to the first pole of the driving transistor; A first end of the first capacitor is connected to the gate of the driving transistor, and a second end of the first capacitor is connected to the first pole of the driving transistor; A first end of the second capacitor is connected to the first power supply terminal, and a second end of the second capacitor is connected to the first pole of the driving transistor.

9. The display substrate according to claim 8, characterized in that The pixel unit further includes: a light emission control circuit and a light emitting element, wherein the light emission control circuit includes a third transistor; A gate of the third transistor is connected to a third control signal line, a first pole of the third transistor is connected to a second pole of the driving transistor, and a second pole of the third transistor is connected to a second power supply terminal; A first end of the light emitting element is connected to the second pole of the driving transistor, and a second end of the light emitting element is connected to the second power supply terminal.

10. A display panel, characterized in that, Comprising: The display substrate according to any one of claims 1 to 9.

11. A display device, characterized in that, Comprising: The display panel according to claim 10.

12. A driving method for a display substrate according to any one of claims 1 to 9, the display substrate including a substrate, a plurality of voltage supply terminals, a plurality of voltage transmission lines, and a plurality of pixel unit groups; The substrate includes a display area and a non-display area, and the non-display area includes a first driving area located on one side of the display area and arranged along a first direction with the display area; The pixel unit group includes a plurality of pixel units arranged along a second direction, and the pixel unit includes a driving transistor and a reset and data writing circuit; It is characterized in that The driving method includes: The pixel units in each of the pixel unit groups operate according to the received reset control signal and data writing control signal. The operating phases of the pixel units in one frame of any of the pixel unit groups include a reset phase and a data writing phase that starts after a configured preset interval from the end of the reset phase. Among them, in the reset phase, the reset and data writing circuit in the pixel unit writes the reset voltage provided by the voltage transmission line to the gate of the driving transistor in response to the control of the reset control signal. In the data writing phase, the reset and data writing circuit in the pixel unit writes the data voltage to the gate of the driving transistor in response to the control of the data writing control signal. For any two adjacent pixel unit groups, the preset interval configured for the pixel units in the pixel unit group closer to the first driving area among the two adjacent pixel unit groups is greater than the preset interval configured for the pixel units in the pixel unit group farther from the first driving area among the two adjacent pixel unit groups.

13. The driving method according to claim 12, characterized in that, The display substrate further includes: a plurality of first control signal lines and a second driving module. The first control signal lines correspond to the pixel unit groups one by one, and the reset and data writing circuit is connected to the corresponding first control signal line; the second driving module is electrically connected to each of the first control signal lines. While the pixel units in each of the pixel unit groups operate according to the received reset control signal and data writing control signal, the driving method further includes: The second driving module simultaneously provides the reset control signal to each of the first control signal lines to control the pixel units in all the pixel unit groups to simultaneously operate in the reset phase. In the order from the first control signal line corresponding to the pixel unit group farthest from the first driving area to the first control signal line corresponding to the pixel unit group closest to the first driving area, the second driving module sequentially provides the data writing control signal to each of the first control signal lines to control the pixel units in each of the pixel unit groups to sequentially operate in the corresponding data writing phase.

Images