A read-write management circuit of a resource module in an FPGA

Abstract

The application discloses a read-write management circuit of a resource module in an FPGA, and relates to the technical field of FPGA, which utilizes a voltage management circuit to perform voltage management on the power supply voltage of a resource module to be managed, wherein during a working state process in which a read-write controller performs read-write operation on the resource module to be managed, the voltage management circuit provides the resource module to be managed with a normal required power supply voltage, and during a standby state process in which the read-write controller does not perform read-write operation on the resource module to be managed, the voltage management circuit reduces the power supply voltage of the resource module to be managed, so that the static power consumption of the resource module to be managed can be reduced without affecting the normal read-write function of the resource module to be managed, the static power consumption of the FPGA can be effectively reduced, and the performance is improved.

Description

Technical Field

[0001] The present application relates to the field of FPGA technology, and in particular to a read-write management circuit for a resource module in an FPGA. Background Art

[0002] SRAM-based FPGAs are programmed by downloading data streams. By configuring the SRAM to control routing switches and select different signal paths, programmable logic functions are implemented, enabling users to achieve different functions. Furthermore, SRAM-based FPGAs are highly integrated and can include multiple hard-core IPs such as DSP, BRAM, SERDES, and PCIE. Therefore, SRAM-based FPGAs are widely used in data processing, logic control, data transmission, and other fields.

[0003] However, with continuous technological advancements, device channels are becoming shorter (reaching 7nm), threshold voltages are becoming lower (reaching 0.2V), gate oxide thicknesses are becoming thinner (reaching 1.2nm), and integration is increasing. All of these factors have led to increasing power consumption in SRAM-based FPGAs. Currently, the power consumption of SRAM-based FPGAs is approximately 3 to 6A, and static power consumption accounts for an increasing proportion of the overall power consumption, reaching approximately 40%. This high power consumption not only leads to excessive power consumption but also causes FPGA device temperatures to rise, impacting reliability. Therefore, power consumption has become a pressing issue that needs to be addressed in the current development of FPGA devices. Summary of the Invention

[0004] In response to the above-mentioned problems and technical requirements, the applicant has proposed a read-write management circuit for a resource module in an FPGA. The technical solution of this application is as follows:

[0005] A read / write management circuit for a resource module in an FPGA includes a read / write controller and a voltage management circuit. The voltage management circuit includes a high-speed driver module, a linear voltage difference module, and a switching power transistor. A core power supply VCCINT is connected to a power supply voltage terminal of a resource module to be managed in the FPGA via the switching power transistor. The high-speed driver module connects to and controls the switching of the switching power transistor. The output terminal of the linear voltage difference module is connected to the power supply voltage terminal of the resource module to be managed.

[0006] When the resource module to be managed switches from standby state to working state, the high-speed driver module drives the switching power tube to turn on, and the core power supply VCCINT provides the operating voltage to the power supply voltage terminal of the resource module to be managed;

[0007] When the resource module to be managed switches from the working state to the standby state, the high-speed driving module drives the switching power tube to be disconnected, and the linear voltage difference module provides the standby voltage to the power supply voltage end of the resource module to be managed. The standby voltage is lower than the working voltage.

[0008] When the read / write controller performs read / write operations on the resource module to be managed, the resource module to be managed is in a working state; when the read / write controller does not perform read / write operations on the resource module to be managed, the resource module to be managed is in a standby state.

[0009] The beneficial technical effects of this application are:

[0010] The present application discloses a read / write management circuit for a resource module in an FPGA. The read / write management circuit utilizes a voltage management circuit to perform voltage management on the power supply voltage of the resource module to be managed. When the read / write controller is in an operating state in which it performs read / write operations on the resource module to be managed, the voltage management circuit provides the resource module to be managed with the normal power supply voltage required. When the read / write controller is in a standby state in which it does not perform read / write operations on the resource module to be managed, the voltage management circuit reduces the power supply voltage of the resource module to be managed, thereby reducing its static power consumption without affecting the function of the resource module to be managed. This can effectively reduce the static power consumption of the FPGA and improve its performance.

[0011] The voltage management circuit has the characteristics of low power consumption, high conversion efficiency, high stability and low latency. It can quickly complete the switching of the power supply voltage of the resource module to be managed between the working voltage and the standby voltage. In particular, it can quickly complete the recovery of the resource module to be managed from the standby voltage to the working voltage to enter the working state, thereby ensuring the correctness of the read and write operations, and preventing the omission of read and write data. In addition, the circuit power consumption of the voltage management circuit itself is also low, and no excessive additional power consumption will be generated.

[0012] The control logic implemented by the read / write controller has also been optimized. A preset delay is added after the managed resource module switches from standby state to working state to ensure that the power supply voltage has returned to the working voltage when performing read / write operations, ensuring the correctness of data reading and writing.

[0013] The voltage management circuit can also completely shut down the supply voltage of the resource modules to be managed that are not called by the user design, thereby completely shutting down the static power consumption generated by them and further reducing the static power consumption of the FPGA.

[0014] In scenarios where FPGAs, especially SRAM-type FPGAs, are highly integrated, use a large number of BRAM modules, and have high resource utilization, it is of great value to use BRAM modules as resource modules to be managed and perform read and write management using the read-write management circuit of this application. The maximum static current of a single BRAM module can be reduced from the original 0.5mA to 0.2mA. Taking a 69-million-gate SRAM-type FPGA containing 1,470 BRAM modules as an example, the cumulative reduction in static power consumption by a large number of BRAM modules is very considerable, which is of great significance to the performance optimization of FPGAs. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 This is a schematic diagram of the connection between the read-write management circuit and a single resource module to be managed in one embodiment of the present application.

[0016] Figure 2 Schematic diagram of the connection between a voltage management circuit and multiple BRAM modules in one embodiment of the present application.

[0017] Figure 3 This is a circuit diagram of a high-speed driving module in one embodiment of the present application.

[0018] Figure 4 This is a circuit diagram of a reference voltage module in one embodiment of the present application.

[0019] Figure 5 This is a circuit diagram of a linear voltage difference module in one embodiment of the present application.

[0020] Figure 6 This is a timing diagram of the power supply voltage VDD of the BRAM module and the read and write control of the BRAM module by the read and write controller in one embodiment of the present application.

[0021] Figure 7 This is a schematic diagram of the connection between a voltage management circuit and multiple BRAM modules in another embodiment of the present application. DETAILED DESCRIPTION

[0022] The specific implementation of this application will be further described below with reference to the accompanying drawings.

[0023] This application discloses a read-write management circuit for a resource module in an FPGA. The read-write management circuit includes a read-write controller and a voltage management circuit. The voltage management circuit is used to manage the voltage of the resource module to be managed in the FPGA. The resource module to be managed is a resource module in the FPGA. Figure 1 As shown in the circuit diagram, the voltage management circuit includes a high-speed driver module, a linear voltage difference module, and a switching power transistor Pc. The core power supply VCCINT is connected to the supply voltage VDD of the resource module to be managed in the FPGA through the switching power transistor Pc. The high-speed driver module connects to and controls the switching power transistor Pc, and the output of the linear voltage difference module is connected to the supply voltage VDD of the resource module to be managed.

[0024] The read-write controller connects to the resource module to be managed and performs read-write operations on it. The read-write controller can be an existing read-write controller of the FPGA. Its connection relationship with various resource modules in the FPGA and the read-write control method can be implemented according to the functional characteristics of the resource module. This application does not go into details about it.

[0025] During the operation of the FPGA, the read-write controller often does not continuously perform read-write operations on the resource module to be managed. When the read-write controller performs read-write operations on the resource module to be managed, the resource module to be managed is in a working state. When the read-write controller does not perform read-write operations on the resource module to be managed, the resource module to be managed is in a standby state.

[0026] The voltage management circuit performs voltage management on the resource module to be managed according to the status of the resource module to be managed, including:

[0027] When the managed resource module switches from the standby state to the active state, the high-speed driver module drives the switching power transistor Pc to conduct, and the core power supply VCCINT provides an operating voltage (hereinafter simply referred to as VCCINT) to the power supply voltage terminal of the managed resource module. While the managed resource module remains in the active state, the switching power transistor Pc remains on, and the core power supply VCCINT continues to supply power to the managed resource module. This allows the managed resource module to operate normally while powered by the core power supply VCCINT in the active state, performing the required read and write operations.

[0028] When the resource module to be managed switches from the working state to the standby state, the high-speed driving module drives the switching power tube Pc to be disconnected, and the linear voltage difference module provides the standby voltage Vs to the power supply voltage end of the resource module to be managed. When the resource module to be managed remains in the standby state, the switching power tube Pc is continuously disconnected, and the linear voltage difference module continues to provide the standby voltage Vs to the resource module to be managed. Among them, the standby voltage Vs is less than the working voltage VCCINT. For example, the standby voltage Vs can usually be configured to be 60%*VCCINT, but the specific value of the standby voltage Vs can be configured according to actual conditions, and this application does not limit this. The static power consumption of the resource module to be managed comes from the subthreshold leakage current I of the transistor. sub , the leakage current I from the gate tunneling through the oxide layer to the channel gtc , PN junction reverse bias current I between source, drain and substrate PN , and the gate-induced drain current I GIDL , where I sub and I gtc It is the main cause of static power consumption. The leakage current of each device is 10 -3 to 10 -2 The leakage current is on the order of μA, and the higher the temperature, the greater the leakage current. Both leakage currents are in a square relationship with the power supply voltage VDD obtained by the power supply voltage terminal of the resource module to be managed. Therefore, reducing the power supply voltage VDD of the resource module to be managed in the standby state from the operating voltage VCCINT to the standby voltage Vs can effectively reduce the static power consumption of the resource module to be managed. Moreover, since the resource module to be managed does not perform read and write operations in the standby state, reducing its operating voltage does not affect the operation of the device.

[0029] In actual implementation, an FPGA includes a large number of managed resource modules, each of which may switch between active and standby states at different times. The voltage management circuit of this application independently manages the voltage of each managed resource module according to the aforementioned structure and method, reducing the operating voltage of each managed resource module in its standby state and thus lowering static power consumption. Due to the high degree of integration of FPGAs, especially SRAM-based FPGAs, the cumulative reduction in static power consumption across the entire FPGA is substantial, as a result of the accumulation of a large number of managed resource modules.

[0030] Based on the working process of the voltage management circuit of the present application, since its operating voltage needs to be adjusted according to the state of the resource module to be managed, the resource module to be managed in the present application should be a resource module with a determinable state. Moreover, since the static power consumption reduction of a single resource module to be managed is relatively limited, the integration of the resource module to be managed in the FPGA should be as high as possible, so that a large static power consumption reduction can be generated. Based on the above two features, in one embodiment, the resource module to be managed is a BRAM module in the FPGA, and the BRAM module has a chip select signal port. The read-write controller provides a chip select signal CS to the chip select signal port of the BRAM module. The chip select signal CS can be well used to identify the state of the BRAM module: when the read-write controller provides a valid level chip select signal CS to the chip select signal port of the BRAM module, a read-write operation can be performed, and the BRAM module is in an operating state; when the read-write controller provides an invalid level chip select signal CS to the chip select signal port of the BRAM module, the BRAM module is in a standby state.

[0031] Therefore, if Figure 2 As shown, the high-speed driver module is connected to the chip select signal port of the BRAM module to obtain the chip select signal CS. When the high-speed driver module detects that the chip select signal CS received by the chip select signal port of the BRAM module switches from an inactive level to an active level, it drives the switching power transistor Pc to conduct. When the high-speed driver module detects that the chip select signal CS received by the chip select signal port of the BRAM module switches from an active level to an inactive level, it drives the switching power transistor Pc to disconnect. Generally, the chip select signal CS is active at a high level. Therefore, when the rising edge of the chip select signal CS arrives, it indicates that the BRAM module switches from a standby state to an active state, and when the falling edge of the chip select signal CS arrives, it indicates that the BRAM module switches from an active state to a standby state.

[0032] On the other hand, the number of BRAM modules in FPGAs, especially SRAM-type FPGAs, is very large. For example, an SRAM-type FPGA with a system equivalent gate count of 69 million gates contains a total of 1470 BRAM modules forming a 35*42 array structure. Each BRAM module is 36Kbit. Therefore, the approach of reducing the static power consumption of each BRAM module by voltage management of each BRAM module has a significant impact on reducing the static power consumption of the entire FPGA. For each BRAM module, such as Figure 2 As shown, there is a corresponding voltage management group connected to it and performs voltage management on it. Each voltage management group includes the high-speed drive module, linear voltage difference module and switching power tube as described above. The connection method between each voltage management group and the corresponding BRAM module is as follows Figure 1 As shown, the read-write controller is connected to all BRAM modules and performs read and write operations on each BRAM module as needed. The read-write controller is not shown in the figure.

[0033] In one embodiment, the high-speed driving module is implemented based on a comparison circuit, so Figure 2 As shown, the voltage management circuit also includes a reference voltage module, which is connected to the linear voltage difference module (LDO) in each voltage management group to provide a first reference voltage VREF1. The reference voltage module is also connected to the high-speed drive module (H_CMP) in each voltage management group to provide a second reference voltage VREF2. The high-speed drive module in each voltage management group outputs a corresponding drive signal Out to drive the connected switching power tube Pc based on the second reference voltage VREF2 and the chip select signal CS of the connected BRAM module. The linear voltage difference module in each voltage management group outputs a standby voltage Vs based on the obtained first reference voltage VREF1. For example Figure 2 In the example, the BRAM modules form an array of Y+1 rows and X+1 columns. The voltage management circuit also includes a reference voltage module and (Y+1)*(X+1) voltage management groups. The voltage management circuit connects all voltage management groups to provide VREF1 and VREF2. The voltage management group Group<0,0> connects to the BRAM module in the first row and first column, denoted as BRAM<0,0>, and performs voltage management on it. The high-speed driver module H_CMP in the voltage management group Group<0,0> obtains the chip select signal CS<0,0> of the BRAM<0,0> and controls the corresponding switching power transistor Pc. Voltage Management Group Group<Y,X> The BRAM module connected at row Y+1 and column X+1 is called BRAM.<Y,X> And perform voltage management on it, voltage management group Group<Y,X> The high-speed driver module H_CMP in the BRAM obtains the<Y,X> Chip select signal CS<Y,X> And control the corresponding switching power tube Pc, and so on.

[0034] During the operation of the read-write management circuit of the present application, how the voltage management circuit can quickly and flexibly realize the switching of the power supply voltage VDD of the resource module to be managed is a design difficulty, especially the timely conduction of the switching power tube Pc so that the voltage at the power supply voltage end of the resource module to be managed can be quickly switched from the standby voltage to the working voltage, so as to ensure that the resource module to be managed can be restored to the working state normally, thereby ensuring that the read-write controller can correctly read and write the resource module to be managed, especially the correct reading and writing of the first few data without omission. In order to optimize the control performance, the switching power tube Pc is implemented with a low-threshold, low-on-resistance PMOS tube to ensure high conversion efficiency. Each high-speed driver module compares the obtained VREF2 with the chip select signal CS of the corresponding BRAM module. Taking the high level of the chip select signal CS as an example, when the rising edge of the chip select signal CS arrives, the chip select signal CS rises to VREF2, the high-speed driver module H_CMP outputs a low-level drive signal Out to turn on the switching power tube Pc; when the falling edge of the chip select signal CS arrives, the chip select signal CS drops to less than VREF2, the high-speed driver module H_CMP outputs a high-level drive signal Out to turn off the switching power tube Pc.

[0035] In addition to the selection of the switching power tube Pc, in order to optimize the control performance, it is more important to design the circuit structure of the voltage management circuit, among which the structural design of the high-speed drive module H_CMP is the core. Figure 3 As shown, in one embodiment, the high-speed driving module includes a pre-amplifier unit, a high-speed comparison unit, and an output driver unit connected in sequence. The positive input terminal of the pre-amplifier unit is connected to the reference voltage module to obtain VREF2, and the negative input terminal of the pre-amplifier unit is connected to the chip select signal port of the corresponding BRAM module to obtain the chip select signal CS. The pre-amplifier unit pre-amplifies the second reference voltage VREF2 and the chip select signal of the BRAM module respectively and then inputs them into the high-speed comparison unit. The circuit structure of the pre-amplifier unit can be implemented using an existing circuit structure, such as Figure 3 The figure shows a pre-amplifier unit of a circuit structure composed of NMOS transistors N1, N2, N3 and PMOS transistors P2, P3, P4, P5.

[0036] The high-speed comparison unit compares the amplified second reference voltage VREF2 with the chip select signal CS and outputs a unilateral comparison signal to the output driver unit. The output driver unit generates a drive signal Out for the switching power transistor based on the unilateral comparison signal, controlling the on / off switching of the corresponding switching power transistor Pc. The output driver unit is implemented using an asymmetric buffer. An output driver unit implemented using an asymmetric buffer can minimize delay in one direction while increasing delay in the other direction. However, this application only requires a small delay for the unilateral comparison signal. Therefore, the output driver unit can further reduce the delay of the unilateral comparison signal, improve response speed, and ensure that the subsequent connected switching power transistor Pc is turned on promptly.

[0037] like Figure 3 As shown, in one embodiment, the high-speed comparison unit includes PMOS transistors P6 and P7 and NMOS transistors N4 and N5. The source of P6 and the source of P7 are both connected to the core power supply VCCINT, the drain of P6 is connected to the drain of N4, the gate of N4 and the gate of N5, the drain of P7 is connected to the drain of N5, and the source of N4 and the source of N5 are both grounded; the gate of P6 is connected to the pre-amplifier unit to obtain the voltage amplified by the second reference voltage VREF2, the gate of P7 is connected to the pre-amplifier unit to obtain the voltage amplified by the chip select signal, and the drain of P7 serves as the output end of the high-speed comparison unit to output a unilateral comparison signal.

[0038] The output driver unit includes PMOS transistors P8 and P9 and NMOS transistors N6 and N7. The sources of P8 and P9 are both connected to the core power supply VCCINT. The gates of P8 and N6 are connected and serve as the input of the output driver unit, connecting to the high-speed comparison unit to obtain a unilateral comparison signal. The drain of P8 is connected to the drain of N6, the gates of P9, and the gate of N7. The drain of P9 is connected to the drain of N7 and serves as the output of the output driver unit to output the drive signal for the switching power transistor. The sources of N6 and N7 are both grounded. P8 is larger than N6, and N7 is larger than P9, forming asymmetric buffers.

[0039] Based on this circuit structure, the high-speed driver module H_CMP has a delay of less than 300ps, which is very low. It can quickly turn on the switching power tube Pc, switching the BRAM module from the standby voltage Vs back to the operating voltage VCCINT, ensuring that the selected BRAM module can correctly read and write the first data.

[0040] In addition to the circuit structure of the high-speed drive module, the circuit structure design of the reference voltage module and the linear voltage difference module is equally important. The general bandgap reference voltage is 1.25V, so the power supply voltage needs to be above 1.25V. In one embodiment, Figure 4As shown in FIG, the reference voltage module is implemented based on the bandgap reference voltage of the Banba structure, which can adapt to the lower power supply voltage provided by the core power supply VCCINT in FPGA applications and can generate the required lower reference voltages VREF1 and VREF2. Figure 4 As shown, resistors R1 and R3 enable the reference voltage module to operate at a power supply voltage of approximately 1.0V, which is provided by the core power supply VCCINT. This generates a VREF1 of less than 1V for the linear voltage difference module. For example, if the standby voltage Vs generated by the linear voltage difference module is 60%*VCCINT, the reference voltage module can generate a VREF1 of 0.6V for the linear voltage difference module. A current mirror circuit then generates a smaller VREF2 for the high-speed driver module H_CMP. The VREF2 voltage is determined by the voltage of the BRAM module's chip select signal CS; for example, VREF2 = 0.25V is generally acceptable.

[0041] The linear voltage difference module uses a dynamic Miller frequency compensation structure to adapt to the load protection of the FPGA within the operating temperature range, ensuring a high degree of stability in the output voltage to ensure that the data in the BRAM module can be correctly stored. The output power of the linear voltage difference module is greater than the minimum power consumption of a single BRAM module to maintain data within the operating temperature range. The circuit structure of the linear voltage difference module in one embodiment is as follows: Figure 5 shown.

[0042] In order to ensure the correctness of data reading and writing when the BRAM module switches from the standby state to the working state, in addition to the circuit structure design of the voltage management circuit, in one embodiment, the read-write controller is also adaptively designed for the read-write control process of the BRAM module. Figure 6Taking the chip select signal CS as an example, the timing diagram shows that after the chip select signal CS provided by the read / write controller to the chip select signal port of the BRAM module switches from an inactive level to an active level, it begins to perform read / write operations on the BRAM module after a preset delay (delay) and a set delay (settime). After the rising edge of the chip select signal CS, after a preset delay (delay) and a set delay (settime), the clock signal CLK becomes active high to enable reading and writing. The voltage at the power supply terminal of the BRAM module recovers from the standby voltage Vs to the operating voltage VCCINT within the preset delay (delay). Conventional read / write controllers begin to perform read / write operations on the BRAM module after the chip select signal CS switches from an inactive level to an active level, after a set delay (settime). The set delay (settime) is used to complete the required settings. This embodiment builds on this by adding a preset delay after the state switch to ensure that the BRAM module's power supply voltage VDD returns to the operating voltage VCCINT, thereby ensuring data read and write accuracy. The length of the preset delay can be customized based on actual conditions.

[0043] On this basis, if Figure 6 As shown, when the chip select signal CS provided by the read-write controller to the chip select signal port of the BRAM module switches to a valid level, the read-write controller can only perform a read-write operation on the BRAM module and then end it. The chip select signal CS returns to an invalid level and the BRAM module returns to a standby state. Alternatively, while the chip select signal CS continues to maintain a valid level, the read-write controller can continuously perform multiple read-write operations on the BRAM module. After completing the current read-write operation, the read-write controller directly performs the next read-write operation after a set delay settime, and continuously performs multiple read-write operations on the BRAM module while the chip select signal maintains a valid level. For example Figure 6 In the process of performing the second read and write operation, the clock signal CLK is valid at a high level only after the set delay settime to continue reading and writing. That is, when performing read and write operations on the same BRAM module multiple times in succession, it is only necessary to wait for the preset delay delay after switching from the standby state to the working state for the first time. In subsequent read and write operations, since the power supply voltage VDD of the BRAM module has recovered to the working voltage VCCINT, the read and write operations can be performed directly and continuously multiple times in a conventional manner without waiting for the preset delay delay. After the BRAM module switches from the working state to the standby state, the power supply voltage VDD of the BRAM module drops to the standby voltage Vs again. Then, the next time the BRAM module resumes the working state from the standby state, the above process will continue to repeat, as shown in FIG. Figure 6 When the chip select signal CS rises next time, the above process is repeated.

[0044] By utilizing a linear voltage difference module with low power consumption, high conversion efficiency, and high stability, combined with a high-speed output drive module H_CMP with low power consumption, high speed, and output drive, the voltage management circuit can achieve rapid switching of the BRAM module's operating voltage, reducing the BRAM module's maximum static current and static power consumption while ensuring normal operation of the BRAM module. When the BRAM module is continuously supplied with operating voltage according to conventional practices, the size of a single BRAM module is 36Kbit, and the maximum static current of a single BRAM module is approximately 0.5mA. However, after voltage management of the BRAM module according to the methods of this application, the maximum static power consumption of a single BRAM module is reduced to approximately 0.2mA at 125°C.

[0045] In another embodiment, the voltage management circuit further includes a configuration module, which is connected to the enable terminal EN of the high-speed driving module and the enable terminal EN of the linear voltage difference module. Figure 2 When there are multiple voltage management groups, a configuration module can be used to connect the enable terminal EN of the high-speed drive module and the enable terminal EN of the linear voltage difference module in each voltage management group, or, as shown in the following example, Figure 7 As shown, each voltage management group includes a configuration module. The configuration module in each voltage management group is connected to the enable terminal EN of the high-speed drive module and the enable terminal EN of the linear voltage difference module in the voltage management group and provides an enable signal. FPGAs need to utilize internal resource modules to implement user designs. However, there are a large number of resource modules within the FPGA, and not all resource modules are used. Some resource modules may be idle. When the user design implemented by the FPGA calls a resource module to be managed, the configuration module outputs an enable signal EN of a valid level to the high-speed drive module and linear voltage difference module corresponding to the resource module to be managed. The high-speed drive module and the linear voltage difference module perform voltage management on the voltage of the power supply voltage terminal of the resource module to be managed in accordance with the contents described in the above embodiments, thereby reducing the static power consumption generated by the called resource module to be managed. When the user design implemented by FPGA does not call the resource module to be managed, the configuration module outputs an invalid level enable signal EN to the high-speed drive module and linear voltage difference module corresponding to the resource module to be managed. The high-speed drive module and the linear voltage difference module remain in the off state, and the switching power tube Pc connected to the high-speed drive module remains in the off state, the linear voltage difference module remains in the off state, and the power supply voltage terminal VDD of the resource module to be managed remains at 0V, that is, the power supply voltage of the resource module to be managed that has not been called is completely turned off, and the static power consumption generated by the resource module to be managed that has not been called is completely turned off, thereby further reducing the static power consumption of FPGA. For example, in Figure 7In the example shown, BRAM<0,X> is not called, so the configuration module in Group<0,X> outputs an invalid enable signal EN to the high-speed driver module and linear voltage difference module in the voltage management group to shut them down. The supply voltage of BRAM<0,X> remains at 0V, achieving complete shutdown, reducing the static power consumption of the FPGA without affecting the implementation of the user design.

[0046] The above description is only a preferred embodiment of the present application, and the present application is not limited to the above embodiments. It is understood that other improvements and variations directly derived or imagined by those skilled in the art without departing from the spirit and concept of the present application should be considered to be included in the scope of protection of the present application.

Claims

1. A read-write management circuit for a resource module in an FPGA, characterized in that: The read / write management circuit includes a read / write controller and a voltage management circuit. The voltage management circuit includes a high-speed drive module, a linear voltage difference module, and a switching power tube. The core power supply VCCINT is connected to the power supply voltage terminal of the resource module to be managed in the FPGA through the switching power tube; the high-speed drive module is connected to and controls the on / off of the switching power tube, and the output end of the linear voltage difference module is connected to the power supply voltage terminal of the resource module to be managed; When the resource module to be managed switches from a standby state to a working state, the high-speed driving module drives the switching power transistor to be turned on, and the core power supply VCCINT provides an operating voltage to the power supply voltage terminal of the resource module to be managed; When the resource module to be managed switches from the working state to the standby state, the high-speed driving module drives the switching power tube to be disconnected, and the linear voltage difference module provides a standby voltage to the power supply voltage terminal of the resource module to be managed, and the standby voltage is lower than the working voltage; When the read-write controller performs a read-write operation on the resource module to be managed, the resource module to be managed is in a working state; when the read-write controller does not perform a read-write operation on the resource module to be managed, the resource module to be managed is in a standby state; Wherein, the resource module to be managed is a BRAM module in the FPGA. When the read-write controller provides a chip select signal of a valid level to the chip select signal port of the BRAM module and performs a read-write operation, the BRAM module is in a working state; when the read-write controller provides a chip select signal of an invalid level to the chip select signal port of the BRAM module, the BRAM module is in a standby state; the high-speed drive module is connected to the chip select signal port of the BRAM module. When the high-speed drive module detects that the chip select signal received by the chip select signal port of the BRAM module switches from an invalid level to a valid level, it drives the switching power tube to turn on. When the high-speed drive module detects that the chip select signal received by the chip select signal port of the BRAM module switches from a valid level to an invalid level, it drives the switching power tube to turn off. The voltage management circuit includes a reference voltage module and multiple voltage management groups, each voltage management group includes a high-speed drive module, a linear voltage difference module and a switching power tube, each voltage management group is connected to a corresponding BRAM module and performs voltage management on the BRAM module connected to it; the reference voltage module is connected to the linear voltage difference module in each voltage management group to provide a first reference voltage VREF1, and the reference voltage module is also connected to the high-speed drive module in each voltage management group to provide a second reference voltage VREF2; the high-speed drive module in each voltage management group drives the connected switching power tube based on the second reference voltage VREF2 and the chip select signal of the connected BRAM module; the linear voltage difference module in each voltage management group outputs the standby voltage based on the obtained first reference voltage VREF1; Among them, the high-speed driving module includes a pre-amplifier unit, a high-speed comparison unit and an output driver unit connected in sequence. The pre-amplifier unit pre-amplifies the second reference voltage VREF2 and the chip select signal of the BRAM module respectively and inputs them into the high-speed comparison unit. The high-speed comparison unit compares the amplified second reference voltage VREF2 with the chip select signal and outputs a unilateral comparison signal to the output driver unit. The output driver unit generates a driving signal for the switching power tube according to the unilateral comparison signal to control the on and off of the switching power tube; the output driver unit is implemented based on an asymmetric buffer.

2. The read / write management circuit according to claim 1, characterized in that: The high-speed comparison unit includes PMOS transistors P6 and P7 and NMOS transistors N4 and N5. The source of P6 and the source of P7 are both connected to the core power supply VCCINT, the drain of P6 is connected to the drain of N4, the gate of N4 and the gate of N5, the drain of P7 is connected to the drain of N5, and the source of N4 and the source of N5 are both grounded; the gate of P6 is connected to the pre-amplifier unit to obtain the voltage after amplification of the second reference voltage VREF2, the gate of P7 is connected to the pre-amplifier unit to obtain the voltage after amplification of the chip select signal, and the drain of P7 serves as the output end of the high-speed comparison unit to output a unilateral comparison signal; The output drive unit includes PMOS tubes P8 and P9 and NMOS tubes N6 and N7. The source of P8 and the source of P9 are both connected to the core power supply VCCINT. The gate of P8 is connected to the gate of N6 and serves as the input end of the output drive unit to connect to the high-speed comparison unit to obtain a unilateral comparison signal; the drain of P8 is connected to the drain of N6, the gate of P9 and the gate of N7, the drain of P9 is connected to the drain of N7 and serves as the output end of the output drive unit to output the driving signal of the switching power tube, and the source of N6 and the source of N7 are both grounded; wherein the size of P8 is larger than that of N6, and the size of N7 is larger than that of P9, respectively forming an asymmetric buffer.

3. The read / write management circuit according to claim 2, characterized in that: The delay of the high-speed driving module is less than 300 ps.

4. The read / write management circuit according to claim 1, characterized in that: The reference voltage module is implemented based on a bandgap reference voltage of a Banba structure, the linear voltage difference module adopts a dynamic Miller frequency compensation structure, and the output power of the linear voltage difference module is greater than the minimum power consumption of a single BRAM module to maintain data within the operating temperature range.

5. The read / write management circuit according to claim 1, characterized in that: After the chip select signal provided by the read / write controller to the chip select signal port of the BRAM module is switched from an invalid level to a valid level, the read / write operation on the BRAM module begins after a preset delay and a set delay; the voltage at the power supply voltage end of the BRAM module recovers from the standby voltage to the working voltage within the preset delay.

6. The read / write management circuit according to claim 5, characterized in that: When the chip select signal provided by the read-write controller to the chip select signal port of the BRAM module is switched to a valid level and continuously maintained at a valid level, the read-write controller directly executes the next read-write operation after a set delay after completing the current read-write operation, and continuously performs multiple read-write operations on the BRAM module while the chip select signal maintains a valid level.

7. The read / write management circuit according to claim 1, characterized in that: The voltage management circuit further includes a configuration module, wherein the configuration module is connected to the enable terminal of the high-speed driving module and the enable terminal of the linear voltage difference module; When the user design implemented by the FPGA does not call the resource module to be managed, the configuration module outputs an enable signal of an invalid level to the high-speed drive module and the linear voltage difference module, the switching power tube continues to remain in the disconnected state, the linear voltage difference module continues to remain in the closed state, and the power supply voltage end of the resource module to be managed is 0V; When the user design implemented by the FPGA calls the resource module to be managed, the configuration module outputs an enable signal of a valid level to the high-speed drive module and the linear voltage difference module, and the high-speed drive module and the linear voltage difference module perform voltage management on the voltage of the power supply voltage end of the resource module to be managed.

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