Memory control circuit, chip and computing device

Abstract

Embodiments of the present disclosure disclose a memory control circuit, a chip, and a computing device. The circuit includes: a general controller, an address decoder, a data memory, and a storage block controller. The address decoder is configured to receive a target data operation instruction, extract a target storage unit address, a target block address, and an operation type code from the target data operation instruction, send the target block address to the storage block controller, and send the target storage unit address and the operation type code to the general controller. The storage block controller is configured to set a target state control switch group corresponding to a target storage block to an on state according to the target block address. The general controller is configured to operate on a target storage unit according to the target storage unit address in an operation mode indicated by the operation type code. Embodiments of the present disclosure reduce the energy consumed by storage blocks that are not used for reading and writing during the process of reading and writing the data memory, thereby improving the energy utilization efficiency of the memory.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technologies, and in particular, to a memory control circuit, a chip, and a computing device. Background Art

[0002] A memory is a memory device in a computer system for storing programs and data. The memory is the basis that can be frequently used by a computer system or an application-specific integrated circuit. Through reading from and writing to the memory, various circuits can implement the functions preset by the designer. For example, in an application-specific integrated circuit for a neural network, the memory undertakes the storage task of parameters such as weights. Being able to correctly and quickly read the parameters in the memory is a prerequisite for implementing various complex operations. It can be said that the intervention of the memory is required in the circuit usage in the vast majority of application scenarios.

[0003] The proportion of the static power consumption of traditional memories in the overall power consumption is increasing. A resistive random access memory (RRAM) is a type of emerging memory that stores data using a high resistance state and a low resistance state. Compared with traditional transistor memories, the RRAM has the characteristic of non-volatile data retention even when powered off. Therefore, its power consumption can be reduced by powering off when not in use, and thus it is called a non-volatile memory. Compared with traditional non-volatile memories such as flash memory, the RRAM can achieve a smaller size.

[0004] Based on the existing emerging memories such as the above-mentioned RRAM, how to further reduce power consumption and improve the energy efficiency of the memory is the current key improvement direction. Summary of the Invention

[0005] An embodiment of the present disclosure provides a memory control circuit, which includes: a general controller, an address decoder, a data memory, and a memory block controller. Among them, the data memory includes at least two memory blocks and at least two state control switch groups. The memory blocks in the at least two memory blocks and the state control switch groups in the at least two state control switch groups correspond one by one. Each memory block in the at least two memory blocks includes at least two memory cells; the address decoder is configured to receive a target data operation instruction, and extract a target memory cell address, a target block address, and an operation type code from the target data operation instruction, where the target block address represents the address of the target memory block where the target memory cell indicated by the target memory cell address is located; send the target block address to the memory block controller; send the target memory cell address and the operation type code to the general controller; the memory block controller is configured to set the target state control switch group corresponding to the target memory block to an on state according to the target block address; the general controller is configured to operate the target memory cell according to the operation mode indicated by the operation type code according to the target memory cell address.

[0006] In some embodiments, the master controller is further configured to: in response to receiving a status control instruction, send the status control instruction to an address decoder, where the types of the status control instruction include at least one of the following: a power switch instruction, a clock switch instruction; the address decoder is further configured to: decode the status control instruction to obtain the block address of the storage block corresponding to the status control instruction; send the block address to the master controller; the master controller is further configured to: based on the block address and the status control instruction, control a target status control switch in the status control switch group corresponding to the block address to perform a corresponding status adjustment operation.

[0007] In some embodiments, the circuit further includes an instruction buffer, and the instruction buffer is configured to: receive and cache a set of data operation instructions including a target data operation instruction, and send the set of data operation instructions to the address decoder.

[0008] In some embodiments, the storage block controller includes a power controller and a clock controller, and the status control switch group includes a power switch and a clock switch; the power controller is configured to turn on the target power switch corresponding to the target storage block according to the target block address; the clock controller is configured to turn on the target clock switch corresponding to the target storage block according to the target block address.

[0009] In some embodiments, the power controller is further configured to: after turning on the target power switch corresponding to the target storage block, in response to the time difference between the current moment and the turn-on moment of the target power switch being greater than or equal to a preset duration and no new target block address extracted from a new data operation instruction being received within the time difference, turn off the target power switch.

[0010] In some embodiments, the clock controller is further configured to: according to the target block address, turn on the target clock switch corresponding to the target storage block and turn off other clock switches except the target clock switch.

[0011] In some embodiments, the address decoder is configured to: obtain a set of data operation instructions; extract block addresses from each data operation instruction in the set of data operation instructions to obtain a set of block addresses, and send the set of block addresses to the power controller; send the target block address to the clock controller; the power controller is configured to turn on the target power switches corresponding to each block address in the set of block addresses in at least two storage blocks according to the set of block addresses; the clock controller is configured to turn on the target clock switch corresponding to the target storage block according to the target block address.

[0012] In some embodiments, the master controller is further configured to: when the master controller is in an idle state, in response to receiving a target storage unit address and an operation type code, or receiving a status control instruction, adjust the status of the master controller to a busy state; when the master controller is in a busy state, in response to receiving an operation end feedback signal sent by the data memory or a control end feedback signal sent by the storage block controller, adjust the current status of the master controller to an idle state.

[0013] According to another aspect of the embodiments of the present disclosure, a chip is provided, and the chip includes the above-mentioned memory control circuit.

[0014] According to another aspect of the embodiments of the present disclosure, a computing device is provided, and the computing device includes the above-mentioned chip.

[0015] The memory control circuit, chip, and computing device provided in the above embodiments of the present disclosure, by providing a master controller, an address decoder, a data memory, and a storage block controller, the address decoder receives a target data operation instruction, extracts a target storage unit address, a target block address, and an operation type code from the target data operation instruction, and sends the target block address to the storage block controller; sends the target storage unit address and the operation type code to the master controller, and then the storage block controller sets the target state control switch group corresponding to the target storage block to an on state according to the target block address, and the master controller operates on the target storage unit according to the target storage unit address, thereby realizing dynamic block control of the data memory, reducing the energy consumed by the storage blocks that are not used for reading and writing during the process of reading and writing the data memory, and further improving the energy utilization efficiency of the memory.

[0016] The technical solutions of the present disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Description of the Drawings

[0017] By describing the embodiments of the present disclosure in more detail in conjunction with the accompanying drawings, the above and other objects, features, and advantages of the present disclosure will become more obvious. The accompanying drawings are used to provide a further understanding of the embodiments of the present disclosure, and constitute a part of the specification, and are used to explain the present disclosure together with the embodiments of the present disclosure, and do not constitute a limitation to the present disclosure. In the accompanying drawings, the same reference numerals generally represent the same components or steps.

[0018] Figure 1 is a schematic structural diagram of a memory control circuit provided by an exemplary embodiment of the present disclosure.

[0019] Figure 2 is another schematic structural diagram of a memory control circuit provided by an exemplary embodiment of the present disclosure.

[0020] Figure 3It is the state machine flowchart of the master controller provided by an exemplary embodiment of the present disclosure. Detailed implementation manners

[0021] Next, exemplary embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments of the present disclosure. It should be understood that the present disclosure is not limited by the exemplary embodiments described herein.

[0022] It should be noted that: Unless otherwise specifically stated, the relative arrangements of components and steps, numerical expressions and values set forth in these embodiments do not limit the scope of the present disclosure.

[0023] Those skilled in the art can understand that terms such as "first", "second", etc. in the embodiments of the present disclosure are only used to distinguish different steps, devices or modules, etc., and do not represent any specific technical meaning, nor do they indicate an inevitable logical order between them.

[0024] It should also be understood that in the embodiments of the present disclosure, "a plurality of" may refer to two or more, and "at least one" may refer to one, two or more.

[0025] It should also be understood that for any component, data or structure mentioned in the embodiments of the present disclosure, without clear limitation or contrary indication in the context, it can generally be understood as one or more.

[0026] In addition, the term "and / or" in the present disclosure is only a description of the association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in the present disclosure generally represents an "or" relationship between the associated objects before and after.

[0027] It should also be understood that the present disclosure emphasizes the differences between the various embodiments. Their similarities or similarities can be referred to each other. For the sake of brevity, they will not be described in detail one by one.

[0028] At the same time, it should be understood that for the sake of description, the dimensions of the various parts shown in the drawings are not drawn according to the actual proportional relationship.

[0029] The following description of at least one exemplary embodiment is actually only illustrative and in no way restricts the present disclosure and its application or use.

[0030] Techniques, methods and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the techniques, methods and devices should be regarded as part of the specification.

[0031] It should be noted that like reference numerals and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.

[0032] Application Overview

[0033] Based on the solutions described in the above background art, the technical problem that the embodiments of the present disclosure focus on solving is: how to perform read / write control with finer granularity in a memory with a large data capacity to improve the energy efficiency of the entire memory.

[0034] For example, for a resistive random access memory (RRAM) that supports high concurrency, activating all memory arrays each time not only causes a huge waste of leakage power consumption, but also the consumption of its static power is immeasurable. Such a large waste of resources for the high-concurrency demand in a short time goes against the original intention of the RRAM for low power consumption and non-volatility.

[0035] When a memory such as an RRAM is used in a neural network computing scenario, the memory needs to store a large number of parameters. Since the number of parameters in each layer of the neural network is different, for a relatively large RRAM, the static power consumption in the idle state is inevitable. In addition, when performing high-concurrency read / write access to the RRAM, the low-resistance RRAM will bring a large amount of leakage current, resulting in power consumption waste.

[0036] Therefore, the embodiments of the present disclosure propose a memory control circuit, which dynamically controls the working states of each memory block in the memory by setting a memory block controller, reduces the power consumption and resource waste of the idle memory blocks during the read / write process, so as to achieve the purpose of reducing power consumption. If this circuit is applied to an RRAM, the power consumption of the RRAM can be further reduced on the basis of the high storage density and non-volatility of the RRAM.

[0037] Exemplary Structure

[0038] Figure 1 It is a schematic structural diagram of a memory control circuit provided by an exemplary embodiment of the present disclosure. Each component included in this circuit can be integrated into one chip, or can be provided in different chips or circuit boards, and a data communication link is established between these chips or circuit boards.

[0039] Such as Figure 1As shown in the figure, the circuit includes: a general controller 101, an address decoder 102, a data memory 103, and a storage block controller 104. Among them, the data memory 103 includes at least two storage blocks and at least two state control switch groups. The storage blocks in the at least two storage blocks and the state control switch groups in the at least two state control switch groups correspond one by one. Each storage block in the at least two storage blocks includes at least two storage units.

[0040] In this embodiment, the above data memory 103 can be used to store various data. For example, when the circuit provided in this embodiment is applied in the field of neural network computing, the above data memory 103 can store the parameters of the neural network (or called weight data).

[0041] The above data memory 103 can be various types of memories, such as RAM (random access memory), ROM (read-only memory), etc. Optionally, the above data memory 103 can be a resistive random access memory. The resistive random access memory has a non-volatile characteristic, which can ensure stable data storage without power supply. The resistive random access memory also has a high-density characteristic. The resistive random access memory has a higher storage density than traditional memories. Therefore, more data can be stored under the same area, and it can also support read and write operations with a larger bandwidth. Since the density of the resistive random access memory itself is larger than that of traditional memories, more space can be saved to set up the peripheral control circuit when using the resistive random access memory, greatly reducing the difficulty of designing the circuit. The characteristic of the resistive random access memory to save occupied area can be used to more finely configure the control granularity of the resistive random access memory array, which helps to obtain a resistive random access memory control circuit with a finer-grained storage block.

[0042] The above data memory 103 can be a storage array composed of multiple storage units. The storage array can be further divided into multiple storage blocks, and the size of each storage block can be set as needed. For example, the storage units included in each storage block can be arranged in a 4×4 manner. As Figure 1 shown, the data memory 103 includes N storage blocks (storage block 0 - storage block N - 1), and each storage block corresponds to a state control switch group (including state control switch group 0 - state control switch group N - 1). The storage block controller 104 is used to control the states of the respective state control switch groups (including two states: on and off), and thus control the states of each storage block.

[0043] In this embodiment, the above address decoder 102 is used to receive a target data operation instruction, and extract a target storage unit address, a target block address, and an operation type code from the target data operation instruction. Among them, the target block address represents the address of the target storage block where the target storage unit indicated by the target storage unit address is located.

[0044] The target block address can be represented by various forms of data. For example, it can be represented by a predefined binary block address encoding, that is, the corresponding relationship between each bit of the binary block address encoding and each storage block of the data memory is established in advance. If a certain storage block is selected as the target storage block, the corresponding bit of this storage block can be set to 1. As Figure 1 shown, when N is 4, if storage block 0 is the target storage block, the target block address is 1000. Similarly, if storage block 3 is the target storage block, the target block address is 0001. If storage blocks 2 and 3 are both target storage blocks, that is, storage blocks 2 and 3 are activated simultaneously, the target block address is 0011.

[0045] The target storage unit address can include a row address and a column address, and the row address and the column address can be represented by various forms of data, such as unsigned binary numbers. The operation type code is used to represent the type of operation performed on the target storage unit using the target data operation instruction. Usually, the operation type code can represent a read operation or a write operation.

[0046] The address decoder 102 can further send the target block address to the storage block controller 104, and send the target storage unit address and the operation type code to the general controller 101.

[0047] In this embodiment, the storage block controller 104 is used to set the target state control switch group corresponding to the target storage block to the on state according to the target block address. When the target state control switch group is set to the on state, the general controller 101 can perform a read or write operation on the target storage unit.

[0048] The target state control switch group can include at least one switch, and these switches can be respectively connected to interfaces such as a power supply terminal and a clock terminal. When the switch is turned on, resources such as power supply and clock can be supplied to the corresponding target storage block.

[0049] In this embodiment, the general controller 101 is used to operate on the target storage unit according to the target storage unit address in the operation mode indicated by the operation type code. Usually, the operation mode indicated by the operation type code can be a read operation or a write operation. The general controller 101 can write the externally input data into the target storage unit, or read the stored data from the target storage unit.

[0050] The circuit provided by the above embodiments of the present disclosure, by setting a general controller, an address decoder, a data memory, and a storage block controller, the address decoder receives a target data operation instruction, extracts a target storage unit address, a target block address, and an operation type code from the target data operation instruction, and sends the target block address to the storage block controller; sends the target storage unit address and the operation type code to the general controller, and then the storage block controller sets the target state control switch group corresponding to the target storage block to the on state according to the target block address, and the general controller operates on the target storage unit according to the target storage unit address, thereby realizing dynamic block control of the data memory, reducing the energy consumed by the storage blocks that are not used for reading and writing during the process of reading and writing the data memory, and further improving the energy utilization efficiency of the memory.

[0051] In some alternative implementation manners, the general controller 101 is further configured to: in response to receiving a state control instruction, send the state control instruction to the address decoder 102.

[0052] The above state control instruction may be sent by other circuits outside the memory control circuit of the embodiments of the present disclosure. The state control instruction may include a block address for adjusting the working state of the storage block corresponding to the block address. Optionally, the type of the state control instruction may include at least one of the following: a power switch instruction, a clock switch instruction, etc. Among them, the power switch instruction is used to control the power supply state of the corresponding storage block, and the clock switch instruction is used to control the clock state of the corresponding storage block.

[0053] For example, in a neural network computing scenario, the above data memory 103 is used to store network parameters. When designing the architecture level of the neural network, the network parameters of different layers are stored in different storage blocks. Therefore, when the user writes a neural network controller, the storage blocks corresponding to the network layer parameters that do not need to be accessed can be actively turned off. These storage blocks no longer need to provide resources such as power supply or clock, which can not only reduce power consumption, but also improve the flexibility of using the data memory 103 through the external opening of this instruction.

[0054] The address decoder 102 is further configured to: decode the state control instruction to obtain the block address of the storage block corresponding to the state control instruction, and send the block address to the general controller 101.

[0055] The state control instruction may include a block address and may also include an instruction type code. The instruction type code may indicate the type of the object controlled by the state control instruction. For example, the instruction type code may indicate that the instruction type is a power switch instruction or a clock switch instruction.

[0056] The master controller 101 is further configured to: based on the block address and the status control instruction, control the target status control switch in the status control switch group corresponding to the block address to perform a corresponding status adjustment operation.

[0057] The above-mentioned target status control switch corresponds to the type of the status control instruction. For example, when the status control instruction is a power switch instruction, the target status control switch is a power switch; when the status control instruction is a clock switch instruction, the target status control switch is a clock switch.

[0058] Optionally, the master controller 101 may send the block address included in the status control instruction to the storage block controller 104, and the storage block controller 104 controls the above-mentioned target status control switch corresponding to the block address to make an adjustment.

[0059] For example, if the status control instruction is a power switch instruction, the master controller 101 may send the block address to the power controller included in the storage block controller 104, and the switched-mode power supply controller controls the power switch corresponding to the block address to be turned on or off; if the status control instruction is a clock switch instruction, the master controller 101 may send the block address to the clock controller included in the storage block controller 104, and the clock controller controls the clock switch corresponding to the block address to be turned on or off.

[0060] In this embodiment, by receiving the externally input status control instruction, flexible control of resources such as power supply and clock of each storage block can be achieved, and the resource utilization status of any storage block can be adjusted at any time in a targeted manner, which helps to reduce the power consumption of the data memory in a targeted manner.

[0061] In some alternative implementation manners, as Figure 2 shown, the circuit further includes an instruction buffer 105, and the instruction buffer 105 is configured to:

[0062] Receive and cache a set of data operation instructions including a target data operation instruction, and send the set of data operation instructions to the address decoder 102. As Figure 2 shown, the instruction buffer 105 stores a set of data operation instructions composed of data operation instruction 0 - data operation instruction M. The address decoder 102 can further decode each data operation instruction in the set of data operation instructions.

[0063] Wherein, the target data operation instruction may be any specified data operation instruction in the set of data operation instructions. Generally, the target data operation instruction is the data operation instruction that is stored in the instruction buffer 105 earliest in the set of data operation instructions. For example, Figure 2The data operation instruction 0 shown is the target data operation instruction. Thus, each instruction in the data operation instruction set can, in chronological order, be used by the master controller 101 to perform read and write operations on the storage units indicated by each instruction. When the master controller performs read and write operations using the data operation instruction set in the instruction buffer 105, the data operation instruction set can be managed in a first-in, first-out manner. As Figure 2 shown, after the master controller finishes performing read and write operations on the data storage unit corresponding to data operation instruction 0, data operation instruction 0 is removed from the data operation instruction set, and data operation instruction 1 is used as the new target data operation instruction. If the instruction buffer 105 receives a new data operation instruction, the new data operation instruction is stored above the data operation instruction M shown in Figure 2 .

[0064] It should be noted that Figure 2 the instruction buffer shown is merely a schematic diagram, and the arrangement order of the data operation instructions it contains represents the order used for data read and write operations, rather than the arrangement order of the actual physical storage space.

[0065] In this embodiment, by setting up the instruction buffer 105, multiple data operation instructions can be received and cached simultaneously, so that the address decoder 102 can decode multiple data operation instructions. In the case of needing to perform read and write operations on a large amount of data, it can avoid the time consumed by receiving and decoding data operation instructions one by one, and during the period when the master controller 101 performs read and write operations on the data memory 103, the storage block controller 104 can control the state control switch groups corresponding to multiple storage blocks in advance to improve the power consumption utilization efficiency, and it helps to improve the efficiency of data read and write.

[0066] In some alternative implementation manners, as Figure 2 shown, the storage block controller 104 includes a power controller 1041 and a clock controller 1042, and the state control switch group includes a power switch and a clock switch. As an example, Figure 2 storage blocks 0 - storage block N - 1 respectively correspond to a power switch and a clock switch (such as power switch 0 - power switch N - 1, clock switch 0 - clock switch N - 1 shown in the figure). Under the control of the power controller 1041, the power switch can connect or disconnect each storage unit included in the corresponding storage block from the power port. Under the control of the clock controller 1042, the clock switch can connect or disconnect each storage unit included in the corresponding storage block from the clock port.

[0067] The power controller 1041 is used to connect the target power switch corresponding to the target storage block according to the above-mentioned target block address.

[0068] The clock controller 1042 is used to turn on the target clock switch corresponding to the target storage block according to the shown target block address.

[0069] In this embodiment, since the target block address is included in the target data operation instruction, the target storage block corresponding to the target block address is to be used for read and write operations. Therefore, the power controller 1041 and the clock controller 1042 turn on the target power switch and the target clock switch according to the target block address to support the read and write operations of the target storage block. If the power controller 1041 receives one or more block addresses, it can turn on the power switch corresponding to the received block address. If the clock controller 1042 receives one or more block addresses, it can turn on the clock switch corresponding to the received block address.

[0070] Optionally, the power controller 1041 and the clock controller 1042 can also separately receive a power switch instruction and a clock switch instruction. The power switch instruction can include a block address and a code indicating to turn on or off the power switch, so as to turn on or off the power switch corresponding to the block address according to the code. Similarly, the clock switch instruction can include a block address and a code indicating to turn on or off the clock switch, so as to turn on or off the clock switch corresponding to the block address according to the code.

[0071] In this embodiment, by setting the power controller 1041 and the clock controller 1042, and setting the power switch and the clock switch corresponding to each storage block, the power and clock resources of each storage block in the data memory 103 can be allocated and supplied specifically, thereby improving the utilization efficiency of the power and clock resources and reducing the power consumption.

[0072] In some alternative implementation manners, the power controller 1041 is further used for:

[0073] After turning on the target power switch corresponding to the target storage block, in response to the time difference between the current moment and the turn-on moment of the target power switch being greater than or equal to a preset duration, and no new target block address extracted from a new data operation instruction is received within the time difference, the target power switch is turned off.

[0074] As an example, the above preset duration can be set by setting the number of clock cycles L. If after turning on the target power switch, after L clock cycles, the above target block address is not received again, that is, after L clock cycles, the target storage block is still not read or written, the target power switch can be turned off.

[0075] In this embodiment, by setting the preset duration, after turning on the target power switch, if the target storage block is not read or written for a period of time, the connection between the power supply and the target storage block is automatically disconnected, so as to achieve the purpose of reducing power consumption.

[0076] Optionally, when receiving the above target block address, the power controller 1041 may also turn on the target power switch corresponding to the target storage block and turn off other power switches except the target power switch. Thus, when continuously and sequentially performing read and write operations on the data memory 103 according to multiple data operation instructions, the power supply of the storage blocks that do not perform data read and write is timely turned off, further reducing power consumption.

[0077] In some alternative implementation manners, the clock controller 1042 is further configured to:

[0078] According to the target block address, turn on the target clock switch corresponding to the target storage block and turn off other clock switches except the target clock switch.

[0079] In this embodiment, after receiving the target block address, the clock controller 1042 turns on the target clock switch and turns off other clock switches at the same time.

[0080] This embodiment realizes that when continuously and sequentially performing read and write operations on the data memory 103 according to multiple data operation instructions, the clock of the storage blocks that do not perform data read and write is timely turned off, further reducing power consumption.

[0081] Optionally, after turning on the target clock switch corresponding to the target storage block, in response to the time difference between the current moment and the turn-on moment of the target clock switch being greater than or equal to a preset duration, and no new target block address is received from the new data operation instruction within the time difference, the target clock switch is turned off. Thus, by setting the preset duration, it is realized that after turning on the target clock switch, if the target storage block is not read or written for a period of time, the connection between the clock and the target storage block is automatically disconnected, thereby achieving the purpose of reducing power consumption.

[0082] In some alternative implementation manners, the address decoder 102 is configured to:

[0083] Obtain a set of data operation instructions; extract the block addresses from each data operation instruction in the set of data operation instructions to obtain a set of block addresses, and send the set of block addresses to the power controller 1041; send the target block address to the clock controller 1042.

[0084] Optionally, the address decoder 102 may obtain the set of data operation instructions from the instruction buffer 105 as Figure 2 shown, or may receive the set of data operation instructions sent by an external circuit. It should be noted that the data operation instructions in the set of data operation instructions here may be sequentially sent to the address decoder 102, and the address decoder 102 sequentially decodes the data operation instructions to extract the above address set. Each address in the address set may also be sequentially sent to the power controller 1041.

[0085] The power supply controller 1041 is configured to turn on the target power switches corresponding to each block address in the block address set in at least two storage blocks according to the block address set.

[0086] The clock controller 1042 is configured to turn on the target clock switch corresponding to the target storage block according to the target block address.

[0087] Specifically, since the time consumed when the power switch performs the switching action is relatively long, while the clock switch performs the switching action relatively quickly, therefore, in this embodiment, the power switches of the storage blocks that have not yet performed read / write operations are turned on in advance, so as to achieve the purpose of saving the switching time. Since the action performed by the clock switch is fast, therefore, the clock switch can be directly controlled simultaneously while performing read / write operations based on each data operation instruction.

[0088] In this embodiment, by turning on the power switches of multiple storage blocks in batches and turning on the clock switch of the target storage block separately, the characteristics of the power switch and the clock switch are effectively utilized, and on the basis of reducing the power consumption of the data memory 103, the data read / write efficiency of the data memory 103 is further improved.

[0089] In some optional implementation manners, the general controller 101 is further configured to:

[0090] When the general controller 101 is in the idle state, in response to receiving the target storage unit address and the operation type code, or receiving the status control instruction, adjust the status of the general controller 101 to the busy state;

[0091] When the general controller 101 is in the busy state, in response to receiving the operation end feedback signal sent by the data memory 103, or receiving the control end feedback signal sent by the storage block controller 104, adjust the current status of the general controller 101 to the idle state.

[0092] As an example, the idle state can be represented by the number "1" and the busy state by the number "0". In the idle state, if the target storage unit address and operation type code included in the above target data operation instruction are received, the general controller 101 will adjust the current state to the busy state. The busy state can be divided into a read state, a write state, a clock switch state, a power switch state, and a wait state according to the type of the current operation. If the general controller 101 adjusts the current state to the busy state, it can send the number "0" representing the busy state to the above address decoder 102 and storage block controller 104 (including clock controller 1042 and power controller 1041). In the busy state, if an operation end feedback signal or a control end feedback signal is received, indicating that the read / write operation on the data buffer is ended or the control operation on the state control switch (including power switch instruction and clock switch instruction) is ended, at this time, the next data operation instruction or state control instruction can be processed.

[0093] As Figure 3 shown, it shows a state machine flowchart of a general controller 101 provided in this embodiment. Specifically, Figure 3 the state machine shown includes six states, which are respectively:

[0094] Idle state, at this time the general controller 101 can externally output an idle state signal (for example, represented by the number 1), indicating that it can receive instruction input.

[0095] Read state, if a read instruction is received in the idle state, it enters the read state. In the read state, the general controller 101 externally outputs a busy state signal (for example, represented by the number 0), and starts to read data from the data memory 103. Specifically, the storage unit corresponding to the corresponding row address, column address, and block address is activated, and the corresponding value is read out from the output end of the data memory 103. Since the read operation takes a certain amount of time, after the read operation starts, it enters the wait state.

[0096] Write state, if a write instruction is received in the idle state, it enters the write state. In the write state, the general controller 101 externally outputs a busy state signal, and starts to write data to the data memory 103. Specifically, the storage unit corresponding to the corresponding row address, column address, and block address is activated, and the value to be written is provided to the input end of the data memory 103. Since the write process takes a certain amount of time, after the write operation starts, it enters the wait state.

[0097] Clock switch state: In the idle state, if a clock switch instruction is received, it enters the clock switch state. In the clock switch state, the general controller 101 outputs a busy status signal externally, and sends the corresponding block address and the clock switch instruction to the clock controller 1042 to control the corresponding clock switch. For example, when the block address is represented by the above binary block address encoding, the clocks of the memory blocks corresponding to the bit positions with the value of "1" are turned off, and the clocks of the memory blocks corresponding to the bit positions with the value of "0" are turned on. Since the clock switch process takes a certain amount of time, after sending out the corresponding block address, it enters the waiting state.

[0098] Power switch state: In the idle state, if a power switch instruction is received, it enters the power switch state. In the power switch state, the general controller 101 outputs a busy status signal externally, and sends the corresponding block address and the power switch instruction to the power controller 1041 to control the corresponding power switch. For example, when the block address is represented by the above binary block address encoding, the powers of the memory blocks corresponding to the bit positions with the value of "1" are turned off, and the powers of the memory blocks corresponding to the bit positions with the value of "0" are turned on. Since the power switch process takes a certain amount of time, after sending out the corresponding block address, it enters the waiting state.

[0099] Waiting state: After the general controller 101 receives any instruction, it will enter the waiting state. Then it will wait for the instruction to complete. If a feedback signal indicating the completion of the instruction is received from the power controller 1041, the clock controller 1042, or the data memory 103, it means that the entire instruction is completed at this moment, and the state jumps to the idle state to wait for the next instruction.

[0100] In this embodiment, by setting the state of the controller to the busy state or the idle state, it can help to operate the data memory 103 and the memory block controller 104 orderly according to each instruction, and on this basis, the general controller 101 can control the data memory 103 by setting up a state machine, which helps to improve the operation efficiency of the data memory 103 and the memory block controller 104.

[0101] The embodiment of the present disclosure also provides a chip, on which a memory control circuit is integrated. The technical details of the memory control circuit are as Figures 1 - 3 shown in the relevant description and will not be elaborated here.

[0102] Embodiments of the present disclosure also provide a computing device, which includes the chip described in the above embodiments. In addition, the computing device may further include an input device, an output device, and a necessary memory (the memory may be the same as or different from the above-mentioned data memory 103), etc. Among them, the input device may include, for example, a mouse, a keyboard, a touch screen, a communication network connector, etc., for inputting data operation instructions, etc. The output device may include, for example, a display, a printer, a communication network, and remote output devices connected thereto, etc., for outputting data read from the data memory, etc. The memory is used to store the data input by the above input device and the data generated during the operation of the memory control circuit. The memory may include volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory, etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc.

[0103] The basic principles of the present disclosure have been described above in conjunction with specific embodiments. However, it should be noted that the advantages, benefits, effects, etc. mentioned in the present disclosure are only examples and not limitations. It cannot be considered that these advantages, benefits, effects, etc. are essential for each embodiment of the present disclosure. In addition, the above-mentioned specific details are only for the purpose of illustration and easy understanding, rather than limitations. The above details do not limit the present disclosure to necessarily adopt the above specific details for implementation.

[0104] Each embodiment in this specification is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. For the same or similar parts among the embodiments, reference can be made to each other.

[0105] The block diagrams of the devices, apparatuses, equipment, and systems involved in the present disclosure are only illustrative examples and do not intend to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including", "comprising", "having", etc. are open-ended words, meaning "including but not limited to", and can be used interchangeably with each other. The word "or" and "and" used herein refer to the word "and / or", and can be used interchangeably with each other, unless the context clearly indicates otherwise. The word "such as" used herein refers to the phrase "such as but not limited to", and can be used interchangeably with each other.

[0106] The circuits of the present disclosure can be implemented in many ways. For example, the circuits of the present disclosure can be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above order of the steps of the method in the circuit is only for illustration, and the steps of the method of the present disclosure are not limited to the order specifically described above, unless otherwise specifically stated. In addition, in some embodiments, the present disclosure can also be implemented as a program recorded in a recording medium, and these programs include machine-readable instructions for implementing the functions of the circuits according to the present disclosure. Therefore, the present disclosure also covers a recording medium storing a program for executing the functions of the circuits according to the present disclosure.

[0107] It should also be noted that in the circuits of the present disclosure, each component or each step can be decomposed and / or recombined. These decompositions and / or recombinations should be regarded as equivalent solutions of the present disclosure.

[0108] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects without departing from the scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the aspects shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0109] The above description has been given for purposes of illustration and description. In addition, this description is not intended to limit the embodiments of the present disclosure to the forms disclosed herein. Although several example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and subcombinations thereof.

Claims

1. A memory control circuit, comprising: a general controller, an address decoder, a data memory, and a memory block controller, wherein the data memory includes at least two memory blocks and at least two state control switch groups, the memory blocks in the at least two memory blocks and the state control switch groups in the at least two state control switch groups correspond one by one, and each memory block in the at least two memory blocks includes at least two memory cells; the address decoder is configured to receive a target data operation instruction, and extract a target memory cell address, a target block address, and an operation type code from the target data operation instruction, wherein the target block address represents the address of the target memory block where the target memory cell indicated by the target memory cell address is located; send the target block address to the memory block controller; send the target memory cell address and the operation type code to the general controller; the memory block controller is configured to set the target state control switch group corresponding to the target memory block to an on state according to the target block address; the general controller is configured to operate on the target memory cell according to the target memory cell address in the operation mode indicated by the operation type code; the circuit further includes an instruction buffer, and the instruction buffer is configured to: receive and cache a data operation instruction set including the target data operation instruction, and send the data operation instruction set to the address decoder.

2. The circuit according to claim 1, wherein, the general controller is further configured to: in response to receiving a state control instruction, send the state control instruction to the address decoder, wherein the types of the state control instructions include at least one of the following: a power switch instruction, a clock switch instruction; the address decoder is further configured to: decode the state control instruction to obtain the block address of the memory block corresponding to the state control instruction; send the block address to the general controller; the general controller is further configured to: control the target state control switch in the state control switch group corresponding to the block address to perform a corresponding state adjustment operation based on the block address and the state control instruction.

3. The circuit according to claim 1, wherein, the memory block controller includes a power controller and a clock controller, and the state control switch group includes a power switch and a clock switch; the power controller is configured to turn on the target power switch corresponding to the target memory block according to the target block address; the clock controller is configured to turn on the target clock switch corresponding to the target memory block according to the target block address.

4. The circuit according to claim 3, wherein, the power controller is further configured to: after turning on the target power switch corresponding to the target memory block, in response to the time difference between the current moment and the turn-on moment of the target power switch being greater than or equal to a preset duration, and no new target block address extracted from a new data operation instruction is received within the time difference, turn off the target power switch.

5. The circuit according to claim 3, wherein, the clock controller is further configured to: According to the target block address, turn on the target clock switch corresponding to the target storage block, and turn off other clock switches except the target clock switch.

6. The circuit according to claim 3, wherein, the address decoder is configured to: obtain a set of data operation instructions; extract block addresses from each data operation instruction in the set of data operation instructions to obtain a set of block addresses, and send the set of block addresses to the power controller; send the target block address to the clock controller; the power controller is configured to turn on the target power switches corresponding to each block address in the set of block addresses in the at least two storage blocks according to the set of block addresses; the clock controller is configured to turn on the target clock switch corresponding to the target storage block according to the target block address.

7. The circuit according to any one of claims 1-6, wherein, the general controller is further configured to: when the general controller is in an idle state, in response to receiving the target storage unit address and the operation type code, or receiving a status control instruction, adjust the status of the general controller to a busy state; when the general controller is in a busy state, in response to receiving an operation end feedback signal sent by the data memory or a control end feedback signal sent by the storage block controller, adjust the current status of the general controller to an idle state.

8. A chip, characterized in that, it includes the memory control circuit according to any one of claims 1-7.

9. A computing device, characterized in that, it includes the chip according to claim 8.

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