Non-volatile memory devices that can only be read a predetermined number of times

Abstract

Various embodiments of the present disclosure relate to a non-volatile memory device that can only be read a predetermined number of times. A non-volatile memory device includes a memory plane and a processor, the memory plane including at least one memory region, the at least one memory region including an array of memory cells having two rows and N columns, each memory cell including a state transistor having a control gate and a floating gate, the state transistor being selectable by a vertical select transistor buried in a substrate and including a buried select gate, each column of memory cells including a pair of twin memory cells, the two select transistors of the twin memory cells having a common select gate, and the processor being configured to store information including a series of N bits in the memory region, such that, except for the last bit in the series, the current bit in the series is stored in two memory cells located on the same row and on two adjacent columns, the current bit and the subsequent bit being stored in the two twin cells, respectively.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to French patent application No. 2107581, filed on July 13, 2021, which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to non-volatile memory, and more particularly to memory that can only be read once or a predefined number of times. Background Technology

[0004] There is a need to propose a non-volatile memory structure that can store multiple bits of information such that it is difficult or even impossible to recover the correct value of the stored information using conventional memory read methods.

[0005] It is also necessary to propose a memory structure that can be read only once, or at least only a predefined number of times, to prevent malicious third parties from repeatedly reading the memory in order to commit fraud by using the stored data multiple times. Summary of the Invention

[0006] An embodiment provides a non-volatile memory device including a memory plane, the memory plane including at least one memory region including an array of memory cells having two rows and N columns.

[0007] Each memory cell includes a state transistor having a control gate and a floating gate, the state transistor being selectable by a vertical select transistor that is buried in the substrate and includes a buried select gate.

[0008] Each column of memory cells includes a pair of twin memory cells.

[0009] When the two selection transistors of a pair of memory cells have a common selection gate, the two memory cells are called twins.

[0010] The memory device also includes a processing means configured to store information comprising a series of N bits in a memory region.

[0011] The N-bit information may include data useful for storing N bits, such as a key, or data useful for storing M bits, where M is less than N, and the NM virtual bits have, for example, predefined values.

[0012] Advantageously, the storage of the aforementioned information is performed such that, except for the last digit in the sequence,

[0013] - The current bit in the above series of bits is stored in two memory cells located in the same row and two adjacent columns, and

[0014] - The current bit and the subsequent bit are stored in two twin units respectively.

[0015] This twin-cell structure, combined with the lattice-type filling of the memory region and the redundant storage of the current bit in two memory cells, results in robust storage of information and makes it difficult to recover the correct value of the bit, especially when reading these memory cells using conventional methods.

[0016] In this respect, to ensure correct bit reading, the processing device is advantageously configured such that, in order to read the bits stored in the first twin cell, the bits stored in the second twin cell are pre-replaced with reference bits having a reference value, which is selected to enable the correct recovery of the values ​​of the bits stored in the first twin cell. This reference value is, for example, a logic value of 0 corresponding to the programming state of the twin memory cell.

[0017] In fact, since both twin units are selected simultaneously, the value of the bit stored in the second twin unit should not optionally "mask" (e.g., if the value is equal to 1) the value of the bit stored in the first twin unit.

[0018] Furthermore, the processing device is advantageously configured to read N bits of information sequentially, and for each other bit in the sequence except the last bit, to replace the currently read bit of the information with a reference bit before it is possible to read subsequent bits in the sequence.

[0019] Replacing each already read bit with a reference bit before the subsequent bits of information can be read is equivalent to "destroying" those bits while reading them, except for the last one, and thus makes the stored information unrecoverable.

[0020] The memory region and therefore the memory device can only be read once to transfer the stored information only once.

[0021] Of course, according to one embodiment, the memory device may include a plurality of memory regions intended to contain the same N bits of information, and the processing means is subsequently configured to read the respective memory regions sequentially.

[0022] Therefore, using this embodiment, as much of the stored information as the memory area can be read.

[0023] The number of memory regions depends, of course, on the applications envisioned for the use of the memory devices.

[0024] According to one embodiment, the memory region includes a unit line for each column of state transistors connected to the drains of the pair of twin cells in the corresponding column, and a gate control line for each row of memory cells connected to all control gates of the state transistors of the memory cells in the corresponding row.

[0025] According to one embodiment, the processing apparatus includes a column decoder configured to individually select two bit lines associated with two columns located at opposite ends of a memory region, and simultaneously select two adjacent bits for storage operations of the information and for read and pre-replace operations of the bits.

[0026] This non-restrictive example of a column decoder makes it possible to implement the specific storage and retrieval described above.

[0027] Each memory cell has a first state, such as an erase state, in which it stores a bit having a first logic value (e.g., logic 1); and a second state, such as a programmable state, in which it stores a bit having a second logic value (e.g., logic 0), and a reference bit (which replaces a bit that has been read so that subsequent bits can be read) advantageously has the second logic value.

[0028] Advantageously, the state transistor of the memory cell is configured to be normally turned on when the memory cell is in a first state and turned off when the memory cell is in a second state.

[0029] One simple way to obtain such a state transistor is to provide a depletion-type state transistor.

[0030] Furthermore, according to one embodiment, the state transistor has a negative threshold voltage in a first state of the memory cell and is lower than the threshold voltage of the state transistor of the memory cell in the original state, while in a second state of the memory cell, the threshold voltage of the state transistor is positive and is higher than the threshold voltage of the state transistor of the memory cell in the original state.

[0031] Although this is not necessary, it is particularly interesting that the channel of the state transistor of each memory cell includes a channel injected into the surface of the substrate and configured to cause the memory cell to operate in a depletion mode.

[0032] In practice, this would make it possible, for example, to apply zero voltage to the control gate during a read.

[0033] In fact, when the state transistor is of the deletion type, the normal conduction characteristics of the state transistor when the memory cell is in its original state and zero voltage is applied to the control gate are related to the value of the threshold voltage of the memory cell in its original state. For example, the threshold voltage can be selected to be negative or essentially zero.

[0034] Furthermore, the threshold voltage of the state transistor in both states of the memory cell (erase and program) is located on either side of the threshold voltage of the state transistor of the memory cell in the original state.

[0035] Therefore, processing devices can be configured to apply a zero read voltage to the control gate of the state transistor of the memory cell during the operation of reading the memory cell.

[0036] In fact, this zero read voltage can be used to distinguish the state of a memory cell, because the state transistor of a memory cell in its first state (e.g., an erased cell) will normally be turned on because its threshold voltage will be lower than the original cell voltage, while the state transistor will be turned off in the presence of a memory cell in its second state (e.g., a programmed cell) because the threshold voltage will be positive at this time.

[0037] The first state of the memory cell corresponds to the erase state of the cell and the first logic value is 1, and the second state of the memory cell corresponds to the programming state of the cell and the second logic value is 0, and the processing device is configured to program two memory cells containing the bit that has been read in order to replace the bit that has been read.

[0038] A particular advantage is that all memory cells in the memory region are erased before information is stored in the memory region.

[0039] In fact, in this case, it is sufficient to program the memory cell before storing logic 0.

[0040] Another embodiment provides a method that includes storing a sequence of N bits of information in a non-volatile memory device.

[0041] The device includes a memory plane comprising at least one memory region, the at least one memory region comprising an array of memory cells having two rows and N columns, each memory cell comprising a state transistor having a control gate and a floating gate, the state transistor being selectable by a vertical select transistor buried in a substrate and including a buried select gate, each column of memory cells comprising a pair of twin memory cells, the two select transistors of the pair of twin memory cells having a common select gate.

[0042] Perform N-bit storage such that, except for the last bit in the sequence, the current bit in the sequence is stored in two memory cells located in the same row and two adjacent columns, and the current bit and the subsequent bit are stored in two twin cells respectively.

[0043] According to one embodiment, the method includes: in order to be able to read bits stored in a first twin cell, replacing bits stored in a second twin cell with reference bits having a reference value selected such that the correct recovery of the value of the bits stored in the first twin cell is possible.

[0044] According to one embodiment, the method further includes reading N bits sequentially, and for each bit in the sequence except the last bit, replacing the currently read bit with a reference bit before it is possible to read subsequent bits in the sequence.

[0045] According to one embodiment, the method includes applying a zero read voltage to the control gate of the state transistor of the memory cell during an operation of reading the memory cell.

[0046] According to one embodiment, the method includes individually selecting two bit lines associated with two columns located at both ends of a memory region, and simultaneously selecting two adjacent bits for storage operations of the information and for reading and pre-replacement operations of the bits.

[0047] According to one embodiment, each memory cell has a first state in which logic 1 is stored corresponding to an erase state of the cell and a second state in which logic 0 is stored corresponding to a programmable state of the cell, the method comprising: programming two memory cells containing the read bit in order to replace a bit that has been read.

[0048] According to one embodiment, the method includes erasing all memory cells in the memory region before storing the information in the memory region.

[0049] According to one embodiment, the method includes storing the above information in multiple memory regions and sequentially reading each memory region. Attached Figure Description

[0050] Other advantages and features of the invention will become clear upon viewing the detailed description of the non-limiting implementations and embodiments, as well as the accompanying drawings, in which:

[0051] Figure 1 This illustrates a split-gate type non-volatile memory cell;

[0052] Figure 2 A planar memory structure with memory cells and one unit line per column is shown;

[0053] Figure 3 Two twin cells belonging to the same column and two rows are shown;

[0054] Figure 4Various threshold voltages corresponding to, for example, erased, raw, and programmed memory cells are schematically shown.

[0055] Figure 5 This illustrates how the column decoder individually selects two bit lines associated with two columns located at opposite ends of a memory region;

[0056] Figure 6 This shows that all memory cells in the memory area are in an erased state before information is stored in the memory area;

[0057] Figure 7 This illustrates how the column decoder selects two bit lines with the help of logic signals;

[0058] Figure 8 This illustrates how the column decoder selects two bit lines with the help of another logic signal;

[0059] Figure 9 This demonstrates how a write operation can be performed by selecting a bit line and by selecting a gate control line;

[0060] Figure 10 This illustrates the acquisition of the memory region's grid filling at the end of a write operation;

[0061] Figure 11 This demonstrates replacing the value stored in the twin cell with a reference bit before reading the memory cell;

[0062] Figure 12 This demonstrates reading two twin units;

[0063] Figure 13 This demonstrates the correct recovery of the logical values ​​of the data;

[0064] Figure 14 This shows the selection of two bit lines;

[0065] Figure 15 This demonstrates programming the cell before reading it;

[0066] Figure 16 The reading unit is shown;

[0067] Figure 17 The programming of the twin unit is shown;

[0068] Figure 18 The read twin unit is shown; and

[0069] Figure 19 The memory plane PM, comprising K regions, is shown. Detailed Implementation

[0070] exist Figure 1In this context, the numeral M indicates a split-gate type non-volatile memory cell, such as a selection transistor type non-volatile memory cell with a vertical gate buried in the substrate of the integrated circuit.

[0071] More specifically, the memory cell M includes a state transistor T, which includes a floating gate FG, the top of which is a control gate CG connected to the gate control line CGL.

[0072] The drain (D) of the state transistor T is connected to the bit line BL, while the source (S) of the state transistor T is connected to the drain of the select transistor ST.

[0073] The select transistor ST includes a gate CSG connected to the word line WL.

[0074] Select the source (S) of transistor ST and connect it to the source line SL.

[0075] As an example, Figure 2 A memory plane PM structure is shown, with each column having a unit line. The memory plane PM structure includes memory cells Mi,j, Mi,j+1, Mi-1,j, and Mi-1,j+1 of the type described in patent application US 2013 / 0228846.

[0076] The memory cells Mi,j and Mi,j+1 of group "i" belong to the row or line of group i in the memory plane and are connected to the word line WLi-1,i and the gate control line CGLi.

[0077] The memory cells Mi-1,j and Mi-1,j+1 of group "i-1" belong to the row or line of group "i-1" in the memory plane and are connected to the word line WLi-1,i and the gate control line CGLi-1.

[0078] The memory cells Mi,j and Mi-1,j belonging to group "j" of column j can be read and written through the unit line BLj, and the memory cells Mi,j+1 and Mi-1,j+1 of group "j-1" can be read and written through the unit line BLj+1.

[0079] Each memory cell includes floating-gate transistors FG, namely Ti,j, Ti,j+1, Ti-1,j, and Ti-1,j+1. The drain (D) regions of transistors Ti,j and Ti-1,j are connected to bit line BLj, and the drain terminals of transistors Ti,j+1 and Ti-1,j+1 are connected to bit line BLj+1. The control gates CG of transistors Ti,j and Ti,j+1 are connected to gate control line CGLi, and the control gates CG of floating-gate transistors Ti-1,j and Ti-1,j+1 are connected to gate control line CGLi-1.

[0080] The source (S) terminal of each floating gate transistor is connected to the source line SL via a select transistor ST. The select transistors ST of memory cells Mi,j and Mi-1,j have a common select gate CSG, and therefore the two memory cells are referred to as "twins". Similarly, memory cells Mi,j+1 and Mi-1,j+1 are twin memory cells, and their select transistors ST have a common select gate CSG.

[0081] Each select gate (CSG) is a vertical gate buried in the substrate in which the memory plane PM is generated, and the source line SL is also buried. These common select gates (CSGs) of the twin memory cells are connected to the word line WLi-1,i.

[0082] like Figure 3 As shown, and as stated above, Figure 2 Each state transistor of the memory device works in conjunction with a vertical selection transistor buried in the substrate SB.

[0083] The channel ZCH of a state transistor is called ZCH.

[0084] The select transistor ST connected to the two state transistors Ti,j and Ti+1,j each has a vertical channel ZCV and a buried vertical common select gate CSG. It should be noted that, for the sake of simplicity, the contact used to connect the buried common gate CSG to the corresponding word line WLi,i+1 is not shown.

[0085] Figure 3 More specifically, two twin units Mi,j and Mi+1,j belonging to the same column j and two rows i and i+1 are shown.

[0086] Their drains are connected to the same bit line BLj, which is the only bit line of column j.

[0087] Each memory cell has a first state, such as an erase state, in which it stores a bit with a first logical value (e.g., logical value 1); and a second state, such as a programmable state, in which it stores a bit with a second logical value (e.g., logical value 0).

[0088] Advantageously, the state transistor of the memory cell is configured to be normally turned on when the memory cell is in a first state and turned off when the memory cell is in a second state.

[0089] One simple way to obtain such a state transistor is to provide, for example, a depletion-type state transistor, as described in published French patent application No. 3049380.

[0090] As is well known to those skilled in the art, a depletion-type MOS transistor is normally turned on when no control voltage is applied to the control gate (the control gate connected to ground) of the state transistor, and therefore no control voltage is applied to the floating gate via capacitive coupling. Thus, the state transistor is referred to as "normally on". On the other hand, as the absolute value of the control voltage present on the control gate increases (becomes increasingly negative), the transistor becomes increasingly non-conductive, eventually turning off after exceeding the blocking voltage.

[0091] The channel ZCH of the state transistor is advantageously a surface channel, which allows it to be turned off by applying an acceptable control voltage to the control gate of the state transistor.

[0092] The dopant implantation energy defines the depth of the channel ZCH. For example, this energy can be between 5 keV and 100 keV, resulting in a channel depth of approximately 100 nm.

[0093] In the case of an N-type conductive channel, the implanted dopant can be, for example, arsenic (As), and the dopant concentration determines the threshold voltage Vth0 of the state transistor of the memory cell in its original state. Here, the state transistor is configured to have such a negative threshold voltage Vth0. At this point, 10... 12 atoms / cm 2 Up to 10 14 atoms / cm 3 The dosage of injected dopant between.

[0094] Using such a dopant dose, a negative voltage Vth0 can be obtained, for example, between -1 volt and -0.5 volt.

[0095] Figure 4 Various threshold voltages Vthe, Vth0, and Vthp are schematically shown, corresponding to, for example, erased, raw, and programmed memory cells, respectively.

[0096] In read mode, a zero read voltage can be applied to the control gate CG of the state transistor, and a positive voltage can be applied to the bit line BL.

[0097] Since the state transistor is in depletion mode with a negative voltage Vth0, it is normally turned on for the original memory cell, that is, when there is no charge in the floating gate.

[0098] therefore, Figure 4 It is emphasized that the state transistors of erased memory cells will normally be turned on, while the state transistors of programmed memory cells will be turned off. Furthermore, the fact that zero voltage is applied to the control gate, and therefore to the floating gate FG of the state transistors, does not cause read stress.

[0099] Furthermore, programming or erasing of floating-gate transistors is performed here by injecting or extracting charge into the gate of the transistor using hot electrons injected by (multiple) high voltages.

[0100] More specifically, the erasure of a memory cell is ensured by combining a positive voltage applied to the substrate with a negative voltage applied to the control gate of its floating gate state transistor.

[0101] For a twin cell, if you only want to erase it at the same time, apply a positive voltage to the control gate of its state transistor.

[0102] Programming of memory cells can be ensured, for example, by applying a positive voltage to the relevant bit line, by applying zero voltage to the substrate, and by applying a positive voltage to the control gate of the transistor in its floating gate state.

[0103] The selection of such a memory cell to be programmed is performed by applying a positive voltage above the threshold voltage of the state transistor on the relevant word line.

[0104] Regarding twin cells, if you only want to program them simultaneously, apply a fairly negative voltage, such as -0.5 volts, -1 volt, or zero, to the control gate of their state transistors.

[0105] Finally, as described above, reading from a memory cell is ensured by applying zero voltage to the control gate CG of its state transistor and a positive voltage to the corresponding bit line.

[0106] The selection of such a memory cell to be read is performed by applying a positive voltage above the threshold voltage of the state transistor on the relevant word line.

[0107] In practice, zero voltage will be applied to all cells in the memory plane during read mode.

[0108] Therefore, the two selected twin units will be read simultaneously.

[0109] Furthermore, if the column decoder is also configured to select two adjacent bit lines simultaneously, then two corresponding twin pairs will be read at the same time, as will be seen in more detail below.

[0110] Now for more specific reference Figure 5 The embodiments are described in more detail below.

[0111] exist Figure 5 In this context, DM refers to a memory device that includes a memory plane PM, which includes a memory region ZM.

[0112] Here, the memory region ZM contains an array of memory cells Mi,j with two rows or lines L0 and L1 and N columns (32 columns in this case).

[0113] Memory cells Mi,j are those memory cells as described with reference to the foregoing figures.

[0114] In this example, i specifies the row or line index, and i is equal to 0 or 1.

[0115] Index j specifies the column index, and in this example it varies between 0 and 31.

[0116] The memory region ZM is designed to store information including N binary data D0-D31.

[0117] The memory device DM also includes a processing unit MTR, which in particular includes a conventional line decoder DECR and is configured to deliver voltages on word lines WL0,1 and on gate control lines CGL0 and CGL1.

[0118] The processing unit also includes a column decoder (DECC).

[0119] The column decoder DECC here includes a set of switches SW0-SW31, each of which includes two MOS transistors connected in parallel.

[0120] The first terminal of switch SWj is connected to the corresponding bit line BLj.

[0121] The second terminal of switch SWJ is connected to the read amplifier AMP circuit via a MOS transistor controlled on its gate by a read signal, or to a programming device PRGL with a conventional structure controlled on its gate by another MOS transistor controlled on its gate by a programming PROG control signal.

[0122] These READ and PROG signals are transmitted by the processing unit MTR based on whether we are in the reading or programming phase.

[0123] like Figure 5As shown, the column decoder DECC is configured to individually select two bit lines BL0 and BL31 associated with two columns located at both ends of the memory region ZM via logic signals COL0 and COL31.

[0124] In addition, the column decoder is configured to simultaneously select two adjacent bit lines BLj and BLj+1 via the logic signal COLjj+1.

[0125] This individual selection of the two bit lines BL0 and BL31, and the simultaneous selection of the two adjacent bit lines, are for the operation of storing information D0-D31 in the memory cells of the memory region ZM, and are performed for the read operation, which will be seen in more detail below, including the pre-substitution of the bit with the reference bit, in this case, the bit with the logic value 0.

[0126] The logic signals COL0, COL31, and COLjj+1 are transmitted by the logic device MCC.

[0127] As described above, the memory region is designed to store 32 data bits D0-D31.

[0128] In addition, such as Figure 6 As shown, before storing the information in memory region ZM, all memory cells in memory region ZM are in an erased state, that is, they all contain the logic value 1.

[0129] Now for more specific reference Figures 7 to 10 This illustrates the sequential writing of N bits D0-D31 of the information in the memory region ZM.

[0130] Generally speaking, since the initial state of the memory cells in memory region ZM is the erased state, that is, containing logic "1", no operation will be performed in the memory cells to write data with the logic value "1".

[0131] On the other hand, if the data to be written to the cell is "0", the operation of programming the memory cell will be performed.

[0132] The voltages to be applied to the bit lines, substrate, control gate, and word lines for selecting and programming cells have been indicated above.

[0133] Similarly, the voltages to be applied to the bit lines, control gates, and word lines for selecting and reading cells have already been indicated above.

[0134] exist Figure 7 In the column decoder DECC, two bit lines BL0 and BL1 are selected with the help of the logic signal COL1.

[0135] In addition, select the gate control line CGL1.

[0136] Therefore, data D0 is written into both memory cell M1,0 and memory cell M1,1.

[0137] Then, as Figure 8 As shown, the column decoder selects two bit lines BL1 and BL2 with the help of the logic signal COL12.

[0138] In addition, the gate control line CGL0 was selected this time.

[0139] Therefore, the second data D1 of the information is simultaneously stored in two memory units M0,2 and M0,3 of the first row L0.

[0140] The writing operation continues sequentially until the last data D31 of the information has been written to memory cell M0,31.

[0141] This is achieved by selecting bit line BL31 using logic signal COL31 and by selecting gate control line CGL0. Figure 9 ) to execute.

[0142] When the write operation ends, such as Figure 10 As shown, the memory region is filled with squares so that all data except the last data D31 is stored in two adjacent memory cells in the same row, and two consecutive data are stored in two twin cells in the same column.

[0143] Furthermore, the twin unit M0,0 of the memory unit M1,0 storing data D0 stores the value 1, while the final data D31 is stored in the twin memory unit M0,31 of the memory unit M1,31 storing data D30.

[0144] Now for more specific reference Figures 11 to 18 This example illustrates reading information stored in the memory region ZM.

[0145] Because zero voltage (GND) is applied to the control gate of all memory cells in the memory region during the read, a read of the first twin memory cell in the column simultaneously results in a read of the second twin cell.

[0146] However, if the first twin unit contains a logic "1", then that logic "1" will mask the read value of the data located in the second twin unit.

[0147] In fact, reading from these two twin units will always return a logical "1", regardless of the value of the stored data.

[0148] This is why it is necessary to replace the value stored in its twin with a selected reference bit before reading the memory cell in order to correctly recover the stored data. In this case, the reference bit will have the value "0", which corresponds to the previous programming of the twin cell to store "0" therein.

[0149] This is Figure 11 This was explained in the text.

[0150] More specifically, with the help of the logic signal COL0, the bit line BL0 is selected, and with the help of the line control signal CGL0, the memory cell M0,0 is programmed to store logic "0" therein.

[0151] Then, two twin units M0,0 can be read to store logic "0" in them.

[0152] Then, as Figure 12 As shown, the reading of the two twin cells M0,0 and M1,0 can be always performed by selecting the bit line BL0 with the help of the logic signal COL0.

[0153] In addition, this time, data D0 was read correctly.

[0154] In fact, if the data D0 equals 0, then the value 0 will be effectively read by the read amplifier AMP circuit.

[0155] Additionally, if the logic value of data D0 is equal to 1, the read amplifier AMP circuit will read logic "1".

[0156] Subsequently, as Figure 13 and Figure 14 As shown, the data D1 will be read.

[0157] In addition, since the column decoder will select two bit lines BL0 and BL1 at the same time, and zero voltage GND is applied to the state transistor control gate of all memory cells, the two twin cells in column "0" and the two twin cells in column "1" will be read at the same time.

[0158] Furthermore, in order to obtain the correct recovery of the logical value of data D1, before reading data D1, it is necessary not only to program the twin cell of cell D1 to the value "0", but also to program the cells including the previously read data D0.

[0159] This is Figure 13 As shown in the image.

[0160] As can be seen, in this previous programming step, memory cells M1,0 and M1,1 are programmed with the logic value "0" due to the selection of bit lines BL0 and BL1 by the logic signal COL01 and due to the application of a programming voltage on the gate control line CGL1.

[0161] Therefore, as Figure 14 As shown, the selection of the two bit lines BL0 and BL1 and the application of a zero voltage GND on the control gate of the state transistor result in the simultaneous reading of the logic value of data D1 and the three logic values ​​"0" stored in memory cells M0,0, M1,0 and M1,1.

[0162] Therefore, the logic value of data D1 is correctly recovered. In fact, if the data is equal to 0, the read amplifier circuit will effectively read "0", and if the logic value is equal to 1, the read amplifier circuit will effectively read "1".

[0163] Therefore, it should be noted that not only does prior programming enable the correct recovery of the data to be read, but this prior programming also corrupts the data that has already been read.

[0164] Figure 15 and Figure 16 This explains how the subsequent data D2 was read.

[0165] Before this read, execution units M0,1 and M0,2 ( Figure 15 The program is then executed, and the data stored in memory cells M1,2 is processed. Figure 16 Reading data D2 from ).

[0166] Data D1 has therefore been corrupted.

[0167] Figure 17 and Figure 18 The last data D31 was read.

[0168] In this respect, such as Figure 17 As shown, the pre-programming of the twin units M1,31 is performed, and then as follows: Figure 18 As shown, the memory cell D31 stored in memory cell M0,31 is read.

[0169] At the end of this read, note that all memory cells except the last cell M0,31 store logic 0.

[0170] Reading N binary data of the stored information corrupts all bits of that information except for the last bit.

[0171] Furthermore, it is therefore no longer possible to read this information again.

[0172] Here, the memory device therefore includes memory that can only be read once.

[0173] If you wish to provide a memory device that can be read a predetermined number of times (e.g., K times), then as follows Figure 19 As schematically shown, it is possible to provide a memory plane PM comprising K regions ZM (ZM1-ZMK).

[0174] These regions will be read sequentially as indicated above for region ZM, thus allowing information to be read only K times.

[0175] Although the invention has been described with reference to illustrative embodiments, this specification is not intended to be limiting. Referring to this specification, those skilled in the art will clearly understand various modifications and combinations of the illustrative embodiments and other embodiments of the invention. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. A non-volatile memory device, comprising: A memory plane includes at least one memory region, said at least one memory region comprising an array of memory cells having two rows and N columns. Each memory cell includes a state transistor with a control gate and a floating gate, the state transistor being selectable by a vertical select transistor buried in the substrate and including a buried select gate. Each column of memory cells includes a pair of twin memory cells, wherein the two selection transistors of the pair of twin memory cells have a common selection gate; and The processor is configured to store a sequence of N bits of information in the memory region such that, except for the last bit in the sequence, the current bit in the sequence is stored in two memory cells located in two adjacent columns on the same row, and the current bit and the subsequent bit are stored in two twin memory cells of the pair of twin memory cells, respectively.

2. The device of claim 1, wherein the processor is configured to: in order to read bits stored in a first twin memory cell of the pair of twin memory cells, pre-replace bits stored in a second twin memory cell of the pair of twin memory cells with reference bits having reference values ​​selected to enable correct recovery of the values ​​of the bits stored in the first twin memory cell.

3. The device of claim 2, wherein the processor is further configured to sequentially read the N bits of the information, and to replace the currently read bit of the information with the reference bit before being able to read subsequent bits in the sequence.

4. The device of claim 1, wherein the memory region comprises a unit line per column of the drains of the state transistors of the pair of twin memory cells in corresponding columns, and a gate control line per row of memory cells of all the control gates of the state transistors of the memory cells in corresponding rows.

5. The device of claim 1, wherein the processor includes a column decoder configured to individually select two bit lines associated with two columns located at opposite ends of the memory region, and simultaneously select two adjacent bits for storing the information and for reading and pre-replacing the bits.

6. The device of claim 1, wherein each memory cell has a first state storing a bit having a first logic value and a second state storing a bit having a second logic value, and wherein a reference bit has the second logic value.

7. The device of claim 6, wherein the state transistor of the memory cell is configured to be normally turned on when the memory cell is in the first state and turned off when the memory cell is in the second state.

8. The device of claim 7, wherein the state transistor is depletion-type, wherein the state transistor has a negative threshold voltage and a lower voltage than the threshold voltage of the state transistor of the memory cell in the first state of the memory cell, and wherein the state transistor has a positive threshold voltage and a higher voltage than the threshold voltage of the state transistor of the memory cell in the second state of the memory cell.

9. The device of claim 8, wherein the processor is configured to apply a zero read voltage to the control gate of the state transistor of the memory cell during a read operation of the memory cell.

10. The device of claim 8, wherein the first state of the memory cell corresponds to an erase state of the memory cell and the first logic value is 1, and the second state of the memory cell corresponds to a programmable state of the memory cell and the second logic value is 0.

11. The device of claim 10, wherein all memory cells in the memory region are in an erased state before the information is stored in the memory region.

12. The device of claim 1, further comprising a plurality of memory regions configured to contain the same N bits of information, wherein the processor is configured to read the respective memory regions sequentially.

13. A method for storing information comprising a sequence of N bits in a non-volatile memory device, wherein the device includes a memory plane, the memory plane including at least one memory region, the at least one memory region including an array of memory cells having two rows and N columns, each memory cell including a state transistor having a control gate and a floating gate, the state transistor being selectable by a vertical select transistor buried in a substrate and including a buried select gate, each column of memory cells including a pair of twin memory cells, the two select transistors of the pair of twin memory cells having a common select gate, the method comprising: Store N bits such that, except for the last bit in the chain, the current bit in the chain is stored in two memory cells located in two adjacent columns on the same row, and the current bit and subsequent bits are stored in two twin memory cells of the pair of twin memory cells respectively.

14. The method of claim 13, further comprising: Before reading the bits stored in the first twin memory cell of the pair of twin memory cells, the bits stored in the second twin memory cell of the pair of twin memory cells are replaced with reference bits having reference values ​​selected such that the values ​​of the bits stored in the first twin memory cell can be correctly recovered.

15. The method of claim 14, further comprising: The N bits are read sequentially, and before subsequent bits in the sequence can be read, the currently read bit in the sequence is replaced with the reference bit.

16. The method of claim 14, further comprising: A zero read voltage is applied to the control gate of the state transistor of the memory cell while the memory cell is being read.

17. The method of claim 13, further comprising: Two bit lines are individually selected and associated with two columns located at both ends of the memory region, and two adjacent bits are selected simultaneously for storing the information and for reading and pre-replacing the bits.

18. The method of claim 13, wherein each memory cell has a first state corresponding to an erase state of storage logic 1 and a second state corresponding to a programming state of storage logic 0, and wherein the method further comprises: To replace the bit that has already been read, the two memory cells containing the bit that has already been read are programmed.

19. The method of claim 18, further comprising: Before storing the information in the memory region, all memory cells in the memory region are erased.

20. The method of claim 13, further comprising: The information is stored in multiple memory areas; as well as Read each memory region sequentially.

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