A semiconductor structure manufacturing method, a semiconductor structure and a memory

Abstract

The application provides a semiconductor structure manufacturing method, a semiconductor structure and a memory. The semiconductor structure manufacturing method comprises the following steps: providing a substrate, forming a stable layer on the substrate; forming a stable structure composed of a plurality of linear structures and grooves between the linear structures on the stable layer; forming a hard mask layer covering the stable structure; forming a mask pattern connected with the top of the linear structure and the inner wall of the groove on the hard mask layer; and transferring the mask pattern to the substrate. In the embodiment of the application, the stable structure composed of a plurality of linear structures and grooves between the linear structures is formed on the stable layer, and the mask pattern connected with the top of the linear structure and the inner wall of the groove of the stable structure is formed, so that the mask pattern and the stable structure have a large contact area. The increase of the contact area can significantly enhance the adhesion of the mask pattern, thereby effectively avoiding the phenomenon of distortion and peeling of the mask pattern in the process, and ensuring the yield of the semiconductor after the process.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and in particular to a method for fabricating a semiconductor structure, a semiconductor structure, and a memory. Background Technology

[0002] In the chip manufacturing process, hard masks are used for pattern transfer, and the hard mask directly affects the size and yield of the final transferred pattern.

[0003] Etching is used to etch a hard mask to form a mask pattern. After etching, the mask pattern needs to be wet-cleaned to remove any remaining hard mask. For some small mask patterns, due to the physical rinsing of the wet cleaning solution and the centrifugal force of the rapidly rotating wafer during the cleaning process, or the micro-etching effect that may exist in some of the solution, the adhesion of the mask pattern to the bottom may be insufficient. This can cause the shape of the mask pattern to become distorted or peel off from the substrate, ultimately leading to mask pattern transfer failure.

[0004] Therefore, how to solve the above problems has become an urgent issue for those skilled in the art.

[0005] Application content

[0006] (a) Purpose of application

[0007] The purpose of this application is to provide a method for fabricating a semiconductor structure that can solve the above-mentioned problems.

[0008] (II) Technical Solution

[0009] To address the aforementioned problems, according to one aspect of this application, a method for fabricating a semiconductor structure is provided, comprising:

[0010] Provide a substrate, on which a stable layer is formed;

[0011] A stable structure consisting of multiple linear structures and grooves between the linear structures is formed on the stable layer;

[0012] Form a hard mask layer covering the robust structure;

[0013] A mask pattern is formed on the hard mask layer, which is connected to the top of the linear structure and the inner wall of the groove;

[0014] The mask pattern is transferred to the substrate.

[0015] In this embodiment, a stabilizing structure consisting of multiple linear structures and grooves between the linear structures is formed on the stabilizing layer. A mask pattern is formed that connects to the top of the linear structures of the stabilizing structure and the inner wall of the grooves. This means the mask pattern and the stabilizing structure have both horizontal and vertical contact, resulting in a large contact area. This increased contact area significantly enhances the adhesion of the mask pattern, effectively preventing distortion and peeling of the mask pattern during the manufacturing process and ensuring the yield of the semiconductor after processing. Further, forming the stabilizing structure on the stabilizing layer includes:

[0016] A photoresist layer is formed on the stabilizing layer, and the photoresist layer has a target pattern formed on it.

[0017] The stabilizing layer is etched according to the target pattern;

[0018] The etched photoresist is removed to form the stable structure.

[0019] Furthermore, along the length direction of the linear structure, the cross-section of the linear structure is rectangular.

[0020] Furthermore, along the length of the linear structure, the cross-section of the groove is rectangular.

[0021] Furthermore, along the length direction of the linear structure, the width of the linear structure is greater than the width of the groove.

[0022] Further, forming a mask pattern on the hard mask layer that connects to the top of the linear structure and the inner wall of the groove includes:

[0023] The hard mask layer is etched to form multiple hard mask layer strips, and the multiple hard mask layer strips are arranged at intervals to form the mask pattern; wherein, the length direction of the hard mask layer strips forms a preset angle with the length direction of the linear structure.

[0024] Preferably, before etching the hard mask layer, the method further includes:

[0025] A photoresist layer is formed on the hard mask layer, and the photoresist layer constitutes the mask pattern.

[0026] Furthermore, a photoresist layer is formed on the hard mask layer using a spin coating process.

[0027] Furthermore, the etching process is used to ensure that the angle between the formed hard mask layer and the linear structure is within the range of 30°-60°.

[0028] Furthermore, along the length direction of the hard mask layer strips, each hard mask layer strip is formed to connect with the top of at least one of the linear structures and the inner wall of at least one of the grooves.

[0029] Preferably, after forming the mask pattern on the hard mask layer, the method further includes:

[0030] The mask pattern is cleaned.

[0031] Further, the transfer of the mask pattern to the substrate includes:

[0032] The mask pattern is transferred to the substrate using a dry etching process.

[0033] Preferably, after transferring the mask pattern to the substrate, the method further includes:

[0034] Remove the mask pattern and the solid structure.

[0035] According to a second aspect of this application, this application provides a semiconductor structure formed using the semiconductor structure fabrication method described above.

[0036] According to a third aspect of this application, this application provides a memory including the semiconductor structure described above.

[0037] (III) Beneficial Effects

[0038] The above-mentioned technical solution of this application has the following beneficial technical effects:

[0039] In the method of forming the technical solution of this application, a stable structure consisting of multiple linear structures and grooves between the linear structures is formed on the stable layer, and a mask pattern is formed that is connected to the top of the linear structure of the stable structure and the inner wall of the groove. That is, there is horizontal contact and vertical contact between the mask pattern and the stable structure, so that there is a large contact area between the mask pattern and the stable structure. The increase in contact area can significantly enhance the adhesion of the mask pattern, thereby effectively avoiding the phenomenon of mask pattern distortion and peeling during the process, and ensuring the yield of semiconductors after the process. Attached Figure Description

[0040] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment;

[0041] Figure 2 This is a flowchart illustrating a method for fabricating a semiconductor structure according to another exemplary embodiment;

[0042] Figures 3-8 The schematic flowchart illustrates the structural diagrams of each step in the semiconductor structure fabrication method of related technologies.

[0043] Figures 9-21 This is a schematic diagram illustrating the structure presented in the flowchart of a semiconductor structure fabrication method according to an exemplary embodiment.

[0044] Figure label:

[0045] 10. Substrate; 20. Stabilizing layer; 30. Hard mask layer; 40. Photoresist layer; 21. Linear structure; 22. Groove; 31. Hard mask layer strip. Detailed Implementation

[0046] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0048] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0049] In the chip manufacturing process, hard masks are used for pattern transfer, and the hard mask directly affects the size and yield of the final transferred pattern.

[0050] Etching is used to etch a hard mask to form a mask pattern. After etching, the mask pattern needs to be wet-cleaned to remove any remaining hard mask. For some small mask patterns, due to the physical rinsing of the wet cleaning solution and the centrifugal force of the rapidly rotating wafer during the cleaning process, or the micro-etching effect that may exist in some of the solution, the adhesion of the mask pattern to the bottom may be insufficient. This can cause the shape of the mask pattern to become distorted or peel off from the substrate, ultimately leading to mask pattern transfer failure.

[0051] Related technologies provide a method for fabricating a semiconductor structure, referencing Figures 3-8This diagram illustrates the structural process of semiconductor manufacturing. (Reference) Figure 3 , Figure 3 This is a top view of a semiconductor structure, showing a substrate 10a and a mask pattern 20a formed on the substrate 10a. (Reference) Figure 4 , Figure 4 for Figure 3 The cross-sectional view along section AA shows that mask pattern 20a is formed on the top end face of substrate 10a. It can be understood that the mask pattern 20a is formed by etching a hard mask located on substrate 10a.

[0052] We know that wet cleaning is required in semiconductor fabrication processes to remove residual hard masks after etching. Due to the physical rinsing of the cleaning solution, the centrifugal force from the rapid rotation of the wafer during cleaning, and the potential micro-etching effect of some cleaning solutions, insufficient adhesion to the bottom of the mask pattern 20a sometimes occurs. (Continue to refer to...) Figure 5 , Figure 5 This is a top view of a semiconductor structure, showing a substrate 10a and a mask pattern 20a formed on the substrate 10a. As can be seen from the figure, the relative position of the mask pattern 20a and the substrate 10a has changed; that is, the mask pattern 20a has been twisted or shifted. (Reference) Figure 6 , Figure 6 for Figure 5 The cross-sectional view formed along section AA shows that the mask pattern 20a is formed on the top end face of the substrate 10a, and the shape of the mask pattern 20a is distorted or creeped, which changes the spacing between some structures of the mask pattern 20a.

[0053] Continue to refer to Figure 7 , Figure 7 This is a top view of a semiconductor structure, showing a substrate 10a and a mask pattern 20a formed on the substrate 10a. As can be seen from the figure, part of the structure of the mask pattern 20a is missing, meaning that the structure of the mask pattern 20a has detached. (Reference) Figure 8 , Figure 8 for Figure 7 The cross-sectional view formed along section AA shows that the mask pattern 20a is formed on the top end face of the substrate 10a, and part of the structure of the mask pattern 20a is missing. The missing part of the structure of the mask pattern 20a will cause the failure of pattern transfer in the process, resulting in the failure of semiconductor structure fabrication.

[0054] like Figure 1 As shown, this application provides a method for fabricating a semiconductor structure, including: S110, providing a substrate 10, and forming a stabilizing layer 20 on the substrate 10;

[0055] Specifically, such as Figure 9 As shown, Figure 9 This is a top view of the semiconductor structure during the manufacturing process, illustrating the substrate 10 and the stabilizing layer 20 formed on the substrate 10. (Reference) Figure 10 , Figure 10 for Figure 9 A cross-sectional view along section AA shows that a stabilizing layer 20 is formed on the top end face of substrate 10. Substrate 10 can be any substrate 10 available in the prior art, and its structure and material can be adapted as needed. For example, the material of substrate 10 can be one or any combination of silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, indium gallium dihydrogen arsenide, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). Semiconductor devices, such as NMOS devices, PMOS devices, CMOS devices, resistors, capacitors, or inductors, can also be formed on substrate 10.

[0056] A stabilizing layer 20 is formed on the substrate 10. The stabilizing layer 20 can be formed on the substrate using a deposition process. The material of the stabilizing layer 20 can be at least one of SiN (silicon nitride), SiO2 (silicon oxide), SiON (silicon oxynitride), and BARC (bottom anti-reflective layer).

[0057] S120, A stable structure consisting of multiple linear structures 21 and grooves 22 between the linear structures 21 is formed on the stable layer 20;

[0058] Specifically, such as Figure 13 As shown, Figure 13 This is a top view of the semiconductor structure during the manufacturing process. The figure illustrates a substrate 10 and a stable structure formed on the substrate 10, including a linear structure 21 and a recess 22. (Reference) Figure 14 , Figure 14 for Figure 13 The cross-sectional view along section AA shows that the stabilizing structure is formed on the top end face of the substrate 10. The linear structure 21 of the stabilizing structure is formed on the top of the stabilizing layer 20. The top of the stabilizing layer 20 can also be understood as the side of the stabilizing layer 20 facing away from the substrate 10. A groove 22 is formed between each two adjacent linear structures 21.

[0059] There are multiple linear structures 21, which are arranged at intervals along a direction perpendicular to the length of the linear structures 21. There are also multiple grooves 22, which are arranged at intervals along a direction perpendicular to the length of the linear structures 21.

[0060] S130, forming a hard mask layer 30 that covers a stable structure;

[0061] refer to Figure 15 , Figure 15 This is a top view of the semiconductor structure during the manufacturing process. The figure illustrates the substrate 10, the stabilizing structure, and the hard mask layer 30 formed on the stabilizing structure. (Reference) Figure 16 , Figure 16 for Figure 15 A cross-sectional view along section AA shows that a robust structure is formed on the top end face of substrate 10, and a hard mask layer 30 covers the exposed surface of the robust structure. Further, as... Figure 16 It is known that the hard mask layer 30 is connected to the top of the linear structure 21 and the inner wall of the groove 22, respectively. The formed hard mask layer 30 completely fills the groove 22. In the direction perpendicular to the substrate 10, the formed hard mask layer 30 has a certain thickness above the top of the linear structure 21, and the hard mask layer 30 at the top of the linear structure 21 extends horizontally to the edge of the stable structure. The material of the hard mask layer 30 can be polycrystalline silicon, silicon nitride, or amorphous carbon.

[0062] S140, A mask pattern is formed on the hard mask layer 30 that connects to the top of the linear structure 21 and the inner wall of the groove 22;

[0063] refer to Figure 17 , Figure 17 This is a top view of the semiconductor structure during the manufacturing process, illustrating the stabilizing structure and the mask pattern formed on the stabilizing structure. (Reference) Figure 18 , Figure 18 for Figure 17 The cross-sectional view along section AA shows that a stable structure is formed on the top end face of substrate 10, and the mask pattern formed on hard mask layer 30 is connected to the top of linear structure 21 and the inner wall of groove 22, respectively. (Continue referring to...) Figure 18 The mask pattern is connected to the top of the linear structure 21, and also to the inner wall of the groove 22, which includes a bottom wall and two opposing side walls. (See reference) Figure 19 , Figure 19 for Figure 17 The cross-sectional view formed along BB shows that the mask pattern is connected to the top of the linear structure 21, and the mask pattern is also connected to the inner wall of the groove 22.

[0064] S150, Transfer the mask pattern to substrate 10.

[0065] refer to Figure 20 , Figure 20 This is a top view of substrate 10 during the manufacturing process. (Reference) Figure 21 , Figure 21 for Figure 20 The cross-sectional view formed along section AA shows that the mask pattern has been transferred to substrate 10. Figure 21 An example illustration shows the effect of mask pattern transfer after the process.

[0066] In this embodiment, a stabilizing structure consisting of multiple linear structures 21 and grooves 22 between the linear structures 21 is formed on the stabilizing layer 20. A mask pattern is formed that is connected to the top of the linear structure 21 and the inner wall of the groove 22 of the stabilizing structure. That is, there is horizontal and vertical contact between the mask pattern and the stabilizing structure, so that there is a large contact area between the mask pattern and the stabilizing structure. The increase in contact area can significantly enhance the adhesion of the mask pattern, thereby effectively avoiding the phenomenon of mask pattern distortion and peeling during the process and ensuring the yield of semiconductors after the process.

[0067] like Figure 2 As shown, in some embodiments, step S120, forming a stable structure on the stabilizing layer 20 consisting of a plurality of linear structures 21 and grooves 22 between the linear structures 21, includes:

[0068] S121. A photoresist layer 40 is formed on the stabilizing layer 20, and the photoresist layer 40 forms the target pattern.

[0069] refer to Figure 11 , Figure 11 This is a top view of the semiconductor structure during the manufacturing process, illustrating the stabilizing layer 20 and the photoresist layer 40 formed on the stabilizing layer 20. (Reference) Figure 12 , Figure 12 for Figure 11 The cross-sectional view along section AA shows that a stabilizing layer 20 and a photoresist layer 40 are sequentially stacked on the substrate 10. The photoresist layer 40 is located on the side of the stabilizing layer 20 facing away from the substrate 10. The photoresist layer 40 is patterned using an exposure process to form the target pattern. The photoresist layer 40 is formed on the stabilizing layer 20 using a spin-coating process.

[0070] S122. Etch the stabilizing layer 20 according to the target pattern;

[0071] Specifically, the stabilizing layer 20 containing the target pattern is etched back. (Reference) Figure 13-14 After etching, the target pattern is transferred to the stabilizing layer 20, forming a linear structure 21 of the stabilizing structure. The etched portion of the stabilizing layer 20 forms a groove 22 of the stabilizing structure. The stabilizing layer 20 after etching does not expose the surface of the substrate 10.

[0072] S123. Remove the etched photoresist to form a stable structure.

[0073] In other embodiments, the cross-section of the linear structure 21 along its length direction is, but is not limited to, rectangular. It should be noted that the cross-section of the linear structure 21 can be regular or irregular in shape; this application does not impose specific limitations on this.

[0074] Similarly, along the length of the linear structure 21, the cross-section of the groove 22 is, but is not limited to, rectangular. It should be noted that the cross-section of the groove 22 can be regular or irregular in shape; this application does not impose a specific limitation, and the specific shape is set according to the process requirements of the semiconductor structure.

[0075] In this embodiment, on the one hand, the rectangular cross-section of the linear structure 21 and the groove 22 provides sufficient adhesion area for the formation of the mask pattern, and the increase in the adhesion area of ​​the mask pattern is equivalent to the enhancement of its bottom adhesion force. On the other hand, the mask pattern connected to the sidewall of the groove 22 can, during the wet cleaning process, allow the physical scouring force of the cleaning solution and the centrifugal force of the rapidly rotating wafer to act directly on the linear structure 21 through the sidewall of the groove 22. This can also be understood as transferring the scouring force and centrifugal force to the stable structure, thereby effectively avoiding the distortion and peeling of the mask pattern during the process and ensuring the yield of the semiconductor structure after the process.

[0076] Similarly, the cross-sectional dimensions of each linear structure 21 may be the same or different. The cross-sectional dimensions of each groove 22 may be the same or different. The specific dimensions of the linear structure 21 and the groove 22 are set according to the semiconductor manufacturing process requirements.

[0077] In some embodiments, the width of the linear structure 21 is greater than the width of the groove 22 in the length direction of the vertical linear structure 21.

[0078] In this embodiment, the width of the linear structure 21 is greater than the width of the groove 22, so that the stable structure provides sufficient attachment area on the top of the linear structure 21 for the formation of the mask pattern, ensuring the stability of the mask pattern structure.

[0079] In some embodiments, step S140, forming a mask pattern on the hard mask layer 30 that connects to the top of the linear structure 21 and the inner wall of the groove 22, includes:

[0080] S141. The hard mask layer 30 is etched to form multiple hard mask layer strips 31, and the multiple hard mask layer strips 31 are arranged at intervals to form a mask pattern. The length direction of the hard mask layer strips 31 forms a preset angle with the length direction of the linear structure 21.

[0081] Continue to refer to Figure 17Multiple hard mask strips 31 cover the surface of the stable structure. The length direction of the hard mask strips 31 forms a predetermined angle with the length direction of the linear structure 21. Each hard mask strip 31 is formed to connect with the top of the linear structure 21 and the inner wall of the groove 22 of the stable structure. Furthermore, the length directions of each hard mask strip 31 are parallel to each other. Along a direction perpendicular to the length direction of the hard mask strips 31, each hard mask strip 31 is arranged on the surface of the stable structure at equal or unequal intervals. It can be understood that the surface of the stable structure is composed of the top surface of the stable structure and the inner wall of the groove 22.

[0082] In this embodiment, the length direction of the hard mask layer strip 31 forms a preset angle with the length direction of the linear structure 21, which allows each hard mask layer 30 to contact the top of the linear structure 21 and the inner wall of the groove 22 of the stable structure. This results in a large contact area between each hard mask layer strip 31 and the stable structure. The increased contact area significantly enhances the adhesion of the hard mask layer strip 31, thereby effectively preventing the hard mask layer strip 31 from twisting and peeling off during the process and ensuring the yield of the semiconductor structure after the process.

[0083] In other embodiments, before etching the hard mask layer 30 in step S141, the method further includes:

[0084] S142. A photoresist layer is formed on the hard mask layer 30, and the photoresist layer constitutes a mask pattern.

[0085] In this process, a photoresist layer is formed on the hard mask layer 30 using a spin coating process.

[0086] Specifically, a photoresist layer is spin-coated on the hard mask layer 30. The photoresist layer is located on the side of the hard mask layer 30 away from the substrate 10. The photoresist layer is patterned using an exposure process to form a photolithographic pattern. In the etching process, the photolithographic pattern is transferred to the hard mask layer 30 to form a mask pattern.

[0087] In some embodiments, an etching process is used to make the angle between the length direction of the formed hard mask layer 31 and the length direction of the linear structure 21 within the range of 30°-60°.

[0088] In this embodiment, the angle between the length direction of the formed hard mask layer strip 31 and the length direction of the linear structure 21 is within the range of 30°-60°, so that each hard mask layer 30 is staggered with the linear structure 21 and the groove 22 of the stable structure. This arrangement allows each hard mask layer 30 to have an effective contact area with the linear structure 21 and the groove 22 of the stable structure. The effective contact area formed by the angle between the length direction of the hard mask layer strip 31 and the length direction of the linear structure 21 within the range of 30°-60° can significantly enhance the adhesion of the hard mask layer strip 31, thereby effectively avoiding the phenomenon of mask pattern distortion and peeling during the process and ensuring the yield of semiconductors after the process.

[0089] In some other embodiments, along the length of the hard mask layer strip 31, each hard mask layer strip 31 is formed to connect to the top of at least one linear structure 21 and the inner wall of at least one groove 22.

[0090] In this embodiment, each hard mask layer strip 31 is formed to connect with the top of at least one linear structure 21 and the inner wall of at least one groove 22, which can ensure that each hard mask layer strip 31 has horizontal and vertical contact with the stable structure, so that the hard mask layer strip 31 has a large contact area with the stable structure. The increase in contact area can significantly enhance the adhesion of each hard mask layer strip 31, thereby effectively avoiding the phenomenon of each hard mask layer strip 31 twisting and peeling during the process, and ensuring the yield of semiconductors after the process.

[0091] In some embodiments, after forming a mask pattern on the hard mask layer 30 in step S140, the method further includes:

[0092] S143, Clean the mask pattern.

[0093] Specifically, a wet cleaning process is used to clean the mask pattern. The wet cleaning process includes, but is not limited to, using a chemical solution for physical rinsing and the centrifugal force generated by the rapid rotation of the wafer during the cleaning process to accelerate the cleaning process.

[0094] In some embodiments, step S150 of transferring the mask pattern to the substrate 10 includes:

[0095] The mask pattern is transferred to the substrate 10 using a dry etching process.

[0096] Preferably, after transferring the mask pattern to the substrate 10 in step S150, the method further includes:

[0097] S160, Remove mask pattern and stabilize structure.

[0098] Specifically, the mask pattern and the stabilizing layer 20 are removed by dry etching or wet etching.

[0099] According to a second aspect of this application, this application provides a semiconductor structure formed using the semiconductor structure fabrication method described above.

[0100] The semiconductor structure manufactured according to the embodiments described above can be applied to the fabrication of various integrated circuits (ICs). The ICs according to this application are, for example, memory circuits, such as random access memory (RAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), static RAM (SRAM), or read-only memory (ROM), etc. The ICs according to this application can also be logic devices, such as programmable logic arrays (PLAs), application-specific integrated circuits (ASICs), integrated DRAM logic integrated circuits (buried DRAM), radio frequency circuits, or any other circuit devices. The IC chips according to this application can be used in, for example, user electronic products, such as personal computers, portable computers, game consoles, cellular phones, personal digital assistants, cameras, digital cameras, mobile phones, and other electronic products.

[0101] According to a third aspect of this application, this application provides a memory including the semiconductor structure described above.

[0102] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0103] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0104] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method of fabricating a semiconductor structure, comprising: The method comprises: providing a substrate, and forming a stable layer on the substrate; forming a stable structure composed of a plurality of linear structures and grooves between the linear structures on the stable layer; forming a hard mask layer covering the stable structure; forming a mask pattern on the hard mask layer, the mask pattern being connected to the top of the linear structure and the inner wall of the groove; transferring the mask pattern to the substrate; the step of forming the mask pattern on the hard mask layer comprises: etching the hard mask layer to form a plurality of hard mask layer strips, the plurality of hard mask layer strips being arranged at intervals to form the mask pattern; using an etching process to make the angle between the length direction of the formed hard mask layer strip and the length direction of the linear structure within the range of 30°-60°.

2. The method of claim 1, wherein the step of forming the stable structure on the stable layer comprises: forming a photoresist layer on the stable layer, the photoresist layer being formed with a target pattern; etching the stable layer according to the target pattern; removing the etched photoresist to form the stable structure.

3. The method according to claim 1, wherein: in the length direction of the linear structure, the cross section of the linear structure is rectangular.

4. The method according to claim 1, wherein: in the length direction of the linear structure, the cross section of the groove is rectangular.

5. The method according to claim 1, wherein: in the direction perpendicular to the length direction of the linear structure, the width of the linear structure is greater than the width of the groove.

6. The method of claim 1, wherein Before the step of etching the hard mask layer, the method further comprises: forming a photoresist layer on the hard mask layer, the photoresist layer forming the mask pattern.

7. The method according to claim 6, wherein: a spin coating process is used to form the photoresist layer on the hard mask layer.

8. The method according to claim 1, wherein: in the length direction of the hard mask layer strip, each hard mask layer strip is formed to be connected to the top of at least one linear structure and the inner wall of at least one groove.

9. The method of claim 1, wherein After the step of forming the mask pattern on the hard mask layer, the method further comprises: cleaning the mask pattern.

10. The method of claim 1, wherein The step of transferring the mask pattern to the substrate comprises: using a dry etching process to transfer the mask pattern to the substrate.

11. The method of claim 1, wherein After the step of transferring the mask pattern to the substrate, the method further comprises: removing the mask pattern and the stable structure.

12. A semiconductor structure, characterized by The semiconductor structure is formed by using the method according to any one of claims 1-11.

13. A memory, comprising: The semiconductor structure comprises the semiconductor structure according to claim 12.

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