Methods for resetting metal gates, semiconductor devices and circuits
By forming a discrete gate structure through etching and deposition processes, the problem of the difficulty in realizing a discrete gate structure in CFET devices is solved, thereby improving device performance and integration, and reducing R&D costs.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- FUDAN UNIVERSITY
- Filing Date
- 2022-10-20
- Publication Date
- 2026-07-03
AI Technical Summary
In existing technologies, as transistor size approaches physical limits, quantum effects and parasitic effects lead to increased power density, resulting in high research and development difficulty and cost for proportionally miniaturizing transistor size. The speed of integration improvement lags behind Moore's Law, and the discrete gate structure in CFET devices is difficult to realize.
By forming a metal gate structure to be reset, etching the channel and peripheral structure of the second MOS transistor structure, depositing silicon dioxide and metal, and forming a via structure connecting the first MOS transistor structure, a separate gate structure is achieved.
This invention realizes a discrete gate structure in CFET devices, improving device performance and integration while reducing R&D costs.
Smart Images
Figure CN115621204B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for resetting a metal gate, a semiconductor device, and a circuit. Background Technology
[0002] The development of integrated circuit technology has encountered some bottlenecks at present. As transistor size gradually approaches its physical limits, quantum effects and parasitic effects cause an increase in power consumption density, making it increasingly difficult and costly to scale down transistor size proportionally. Therefore, the rate of increase in integration density in recent years has gradually fallen behind the predictions of Moore's Law, and the industry has entered the "post-Moore's Law era".
[0003] Currently, complementary field-effect transistors (CFETs) have emerged at the 2 / 3nm node. The "MOS" has been removed from the name to distinguish them from NMOS and PMOS transistors, which are manufactured separately in CMOS. CFETs fold the original planar CMOS cells in half, turning them into stacked P-devices and N-devices, while forming a common-gate structure.
[0004] Because CFETs transform the original planar semiconductor device into a vertical three-dimensional device, P and N devices can be configured into common-gate or split-gate structures according to the specific circuit logic requirements. In general circuits, split-gate structures will inevitably exist.
[0005] Therefore, it is necessary to provide a novel method, semiconductor device, and circuit for resetting a metal gate to solve the aforementioned problems existing in the prior art. Summary of the Invention
[0006] The purpose of this invention is to provide a method for resetting a metal gate, a semiconductor device, and a circuit that realizes a discrete gate structure.
[0007] To achieve the above objective, the method for resetting the metal gate according to the present invention includes:
[0008] A metal gate structure to be reset is formed, the metal gate structure to be reset includes a first MOS transistor structure and a second MOS transistor structure stacked from bottom to top;
[0009] The second channel and the peripheral structure of the second MOS transistor structure are etched to form a first via structure that connects the peripheral structure of the first channel of the first MOS transistor structure. The peripheral structure of the first channel and the peripheral structure of the second channel both include a gate and a dielectric layer, and the dielectric layer is disposed around the gate.
[0010] Silicon dioxide is deposited, and then a second via structure is formed on the silicon dioxide to connect the outer structure of the first channel of the first MOS transistor structure.
[0011] Deposit metal to form a metal contact structure that connects to the outer structure of the first channel.
[0012] The beneficial effect of the method for resetting the metal gate is that: etching the second channel and the peripheral structure of the second MOS transistor structure to form a first via structure connecting the peripheral structure of the first channel of the first MOS transistor structure, depositing silicon dioxide, then forming a second via structure connecting the peripheral structure of the first channel of the first MOS transistor structure on the silicon dioxide, depositing metal to form a metal contact structure connecting the peripheral structure of the first channel, thereby realizing the separation gate structure.
[0013] Optionally, the etching of the second channel of the second MOS transistor structure and the peripheral structure of the second channel includes:
[0014] A first photoresist is coated onto the metal gate structure to be reset;
[0015] The first photoresist is exposed to obtain a first photoresist pattern;
[0016] Using the first photoresist pattern as a mask, the second channel of the second MOS transistor structure and the peripheral structure of the second channel are etched to form a first via structure that connects to the peripheral structure of the first channel.
[0017] Optionally, the deposited silicon dioxide comprises:
[0018] Silica is deposited to fill the first through-hole structure.
[0019] Optionally, the step of forming a second via structure on the silicon dioxide that connects to the peripheral structure of the first channel of the first MOS transistor structure includes:
[0020] A second photoresist is coated onto the silicon dioxide;
[0021] The second photoresist is exposed to obtain a second photoresist pattern;
[0022] Using the second photoresist pattern as a mask, the silicon dioxide is etched until the peripheral structure of the first channel is exposed, so as to form a second via structure that connects to the peripheral structure of the first channel.
[0023] Optionally, the width of the second through-hole structure in the extension direction of the second channel is smaller than the length of the second channel in the extension direction.
[0024] Optionally, after performing the metal deposition, the method further includes:
[0025] Remove the metal outside the second through-hole structure.
[0026] Optionally, after performing the metal deposition to form a metal contact structure connecting the peripheral structure of the first channel, the process further includes a step of manufacturing a metal wire.
[0027] Optionally, the first MOS transistor structure is a structure with PMOS transistor function, and the second MOS transistor structure is a structure with NMOS transistor function.
[0028] The present invention also provides a semiconductor device, including a first MOS transistor structure and a MOS-like structure, wherein the MOS-like structure is stacked on the first MOS transistor structure. The MOS-like structure includes a metal contact structure, a first partial channel, and a second partial channel. The metal contact structure is connected to the peripheral structure of the first channel of the first MOS transistor structure. The first partial channel and the second partial channel are disposed on both sides of the metal contact structure, and the extension direction of the first partial channel coincides with the extension direction of the second partial channel. The peripheral structure of the first channel includes a gate and a dielectric layer, wherein the dielectric layer is disposed around the gate.
[0029] The beneficial effects of the semiconductor device are as follows: it includes a first MOS transistor structure and a MOS transistor-like structure, wherein the MOS transistor-like structure is stacked on the first MOS transistor structure, and the MOS transistor-like structure includes a metal contact structure, a first partial channel and a second partial channel. The metal contact structure is connected to the peripheral structure of the first channel of the first MOS transistor structure. The first partial channel and the second partial channel are disposed on both sides of the metal contact structure, and the extension direction of the first partial channel and the extension direction of the second partial channel coincide, thereby realizing a split gate structure.
[0030] Optionally, the first MOS transistor structure is a structure that has the function of a PMOS transistor.
[0031] The present invention also provides a circuit comprising at least one of the semiconductor devices. Attached Figure Description
[0032] Figure 1 This is a flowchart of the method for resetting the metal grid according to the present invention;
[0033] Figure 2 This is a schematic diagram of the structure of the metal grid structure to be reset in some embodiments of the present invention;
[0034] Figure 3 This is a schematic diagram of the structure forming the first through hole in some embodiments of the present invention;
[0035] Figure 4This is a schematic diagram of the structure after silicon dioxide deposition in some embodiments of the present invention;
[0036] Figure 5 This is a schematic diagram of the structure for forming the second photoresist pattern in some embodiments of the present invention;
[0037] Figure 6 This is a schematic diagram of the structure forming the second through hole in some embodiments of the present invention;
[0038] Figure 7 This is a schematic diagram of the structure after metal deposition in some embodiments of the present invention;
[0039] Figure 8 This is a schematic diagram of the structure after removing the metal and the second photoresist pattern outside the second through-hole structure in some embodiments of the present invention. Detailed Implementation
[0040] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without inventive effort are within the scope of protection of this invention. Unless otherwise defined, the technical or scientific terms used herein should have the ordinary meaning understood by those skilled in the art. The terms "comprising" and similar expressions used herein mean that the element or object preceding the word covers the element or object listed following the word and its equivalents, but do not exclude other elements or objects.
[0041] To address the problems existing in the prior art, embodiments of the present invention provide a method for resetting a metal gate. (Refer to...) Figure 1 The method for resetting the metal gate includes the following steps:
[0042] S1: Form a metal gate structure to be reset, the metal gate structure to be reset includes a first MOS transistor structure and a second MOS transistor structure stacked from bottom to top;
[0043] S2: Etch the second channel and the peripheral structure of the second MOS transistor structure to form a first via structure that connects the peripheral structure of the first channel of the first MOS transistor structure. The peripheral structure of the first channel and the peripheral structure of the second channel both include a gate and a dielectric layer, and the dielectric layer is disposed around the gate.
[0044] S3: Deposit silicon dioxide, and then form a second via structure on the silicon dioxide that connects to the peripheral structure of the first channel of the first MOS transistor structure;
[0045] S4: Deposit metal to form a metal contact structure that connects to the outer structure of the first channel.
[0046] Figure 2 This is a schematic diagram of the structure of the metal grid to be reset in some embodiments of the present invention. (Refer to...) Figure 2 The metal gate structure to be reset includes a first MOS transistor structure and a second MOS transistor structure stacked from bottom to top. The first MOS transistor structure includes a first channel 101 and a peripheral structure of the first channel 101. The second MOS transistor structure includes a second channel 102 and a peripheral structure of the second channel 102. Both the peripheral structures of the first channel and the peripheral structures of the second channel include a gate 103 and a dielectric layer 104, with the dielectric layer 104 surrounding the gate 103. The method for forming the metal gate structure to be reset is a technique in the art and will not be described in detail here.
[0047] Figure 3 This is a schematic diagram illustrating the structure of the first through-hole in some embodiments of the present invention. (Refer to...) Figure 2 and Figure 3 The etching of the second channel 102 and the peripheral structure of the second MOS transistor structure includes: coating a first photoresist on the metal gate structure to be reset; exposing the first photoresist to obtain a first photoresist pattern; using the first photoresist pattern as a mask, etching the second channel 102 and the peripheral structure of the second MOS transistor structure to form a first via structure 105 that connects the peripheral structure of the first channel 101.
[0048] Figure 4 This is a schematic diagram of the structure after silicon dioxide deposition in some embodiments of the present invention. (Refer to...) Figure 4 The deposition of silicon dioxide includes: depositing silicon dioxide 106 to fill the first through-hole structure 105.
[0049] Figure 5 This is a schematic diagram of the structure for forming a second photoresist pattern in some embodiments of the present invention. Figure 6 This is a schematic diagram illustrating the structure of the second through-hole in some embodiments of the present invention. (Refer to...) Figure 5 and Figure 6 The step of forming a second via structure on the silicon dioxide that connects to the peripheral structure of the first channel of the first MOS transistor structure includes: coating the silicon dioxide with a second photoresist; exposing the second photoresist to obtain a second photoresist pattern 107; using the second photoresist pattern 107 as a mask, etching the silicon dioxide 106 until the peripheral structure of the first channel is exposed to form a second via structure 108 that connects to the peripheral structure of the first channel 101.
[0050] In some embodiments, the width of the second through-hole structure in the extension direction of the second channel is smaller than the length of the second channel in the extension direction.
[0051] Figure 7 This is a schematic diagram of the structure after metal deposition in some embodiments of the present invention. (Refer to...) Figure 7 The metal 109 fills the second through-hole structure 108 and covers the surface of the second photoresist 107.
[0052] Figure 8 This is a schematic diagram of the structure after removing the metal and second photoresist pattern outside the second through-hole structure in some embodiments of the present invention. (Refer to...) Figure 7 and Figure 8 After depositing the metal, the process further includes: removing the metal 109 outside the second via structure 108, and then removing the second photoresist pattern 107.
[0053] In some embodiments, after performing the metal deposition to form a metal contact structure connecting the peripheral structure of the first channel, a step of manufacturing a metal wire is further included.
[0054] In some embodiments, the first MOS transistor structure is a structure with PMOS transistor function, and the second MOS transistor structure is a structure with NMOS transistor function.
[0055] The present invention also provides a semiconductor device manufactured by the method of resetting the metal gate, comprising a first MOS transistor structure and a MOS-like structure, wherein the MOS-like structure is stacked on the first MOS transistor structure, and the MOS-like structure includes a metal contact structure, a first partial channel and a second partial channel. The metal contact structure is connected to the peripheral structure of the first channel of the first MOS transistor structure. The first partial channel and the second partial channel are disposed on both sides of the metal contact structure, and the extension direction of the first partial channel coincides with the extension direction of the second partial channel.
[0056] In some embodiments, the first MOS transistor structure is a structure that has the function of a PMOS transistor.
[0057] In some embodiments, the peripheral structure of the first channel includes a gate and a dielectric layer disposed around the gate.
[0058] The present invention also provides a circuit comprising at least one of the semiconductor devices.
[0059] In some embodiments, the semiconductor device can be applied to various circuits requiring discrete gate structures, such as XNOR gates, without specifically limiting the circuits to which it is applied.
[0060] While embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations fall within the scope and spirit of the invention as set forth in the claims. Furthermore, the invention described herein may have other embodiments and can be implemented or carried out in various ways.
Claims
1. A method of resetting a metal gate, the method comprising: include: A metal gate structure to be reset is formed, the metal gate structure to be reset includes a first MOS transistor structure and a second MOS transistor structure stacked from bottom to top; The second channel and the peripheral structure of the second MOS transistor structure are etched to form a first via structure that connects the peripheral structure of the first channel of the first MOS transistor structure. The peripheral structure of the first channel and the peripheral structure of the second channel both include a gate and a dielectric layer, and the dielectric layer is disposed around the gate. Silicon dioxide is deposited, and then a second via structure is formed on the silicon dioxide to connect the outer structure of the first channel of the first MOS transistor structure. Deposit metal to form a metal contact structure that connects to the outer structure of the first channel.
2. The method of resetting a metal gate as claimed in claim 1, wherein, The etching of the second channel of the second MOS transistor structure and the peripheral structure of the second channel includes: A first photoresist is coated onto the metal gate structure to be reset; The first photoresist is exposed to obtain a first photoresist pattern; Using the first photoresist pattern as a mask, the second channel of the second MOS transistor structure and the peripheral structure of the second channel are etched to form a first via structure that connects to the peripheral structure of the first channel.
3. The method of resetting a metal gate of claim 1, wherein, The deposited silicon dioxide includes: Silica is deposited to fill the first through-hole structure.
4. The method for resetting a metal grid according to claim 1, characterized in that, The step of forming a second via structure on the silicon dioxide to connect the outer structure of the first channel of the first MOS transistor structure includes: A second photoresist is coated onto the silicon dioxide; The second photoresist is exposed to obtain a second photoresist pattern; Using the second photoresist pattern as a mask, the silicon dioxide is etched until the peripheral structure of the first channel is exposed, so as to form a second via structure that connects to the peripheral structure of the first channel.
5. The method of resetting a metal gate of any one of claims 1, 2, or 4, wherein, The width of the second through-hole structure in the extension direction of the second channel is less than the length of the second channel in the extension direction.
6. The method of resetting a metal gate as claimed in claim 1, wherein, After performing the metal deposition, the method further includes: Remove the metal outside the second through-hole structure.
7. The method of resetting a metal gate of claim 1, wherein, After performing the metal deposition to form a metal contact structure connecting the peripheral structure of the first channel, the process further includes a step of manufacturing a metal wire.
8. The method of resetting a metal gate of claim 1, wherein, The first MOS transistor structure is a structure with the function of a PMOS transistor, and the second MOS transistor structure is a structure with the function of an NMOS transistor.
9. A semiconductor device, characterized by The device includes a first MOS transistor structure and a MOS-like structure. The MOS-like structure is stacked on the first MOS transistor structure. The MOS-like structure includes a metal contact structure, a first partial channel, and a second partial channel. The metal contact structure is connected to the peripheral structure of the first channel of the first MOS transistor structure. The first partial channel and the second partial channel are disposed on both sides of the metal contact structure, and the extension direction of the first partial channel coincides with the extension direction of the second partial channel. The peripheral structure of the first channel includes a gate and a dielectric layer, and the dielectric layer is disposed around the gate.
10. The semiconductor device of claim 9, wherein, The first MOS transistor structure is a structure that has the function of a PMOS transistor.
11. A circuit, characterized by It includes at least one semiconductor device as described in claim 9 or 10.