Semiconductor structure and method of forming the same

Abstract

The application provides a semiconductor structure and a forming method thereof. The semiconductor structure comprises a substrate, a plurality of first wiring layers and a plurality of lower layer contact windows. The substrate has a first region and a second region. The surface of the substrate is sequentially provided with an electrode layer and a first insulating layer. The plurality of first wiring layers are arranged in the first insulating layer and comprise a first wiring structure and a second wiring structure. The first wiring structure is across the first region, and the two ends of the first wiring structure are respectively located at the edge positions of the first region adjacent to the two side edges of the second region. The second wiring structure is located at the edge position of the first region. The plurality of lower layer contact windows are arranged in the first insulating layer and comprise a first contact window and a second contact window. The first contact window is located at the edge region of the first region adjacent to the two side edges of the second region. The second contact window is located at the middle region of the first region. The first wiring structure is connected with the electrode layer of the first region through the first contact window and the second contact window, and the second wiring structure is connected with the electrode layer of the first region through the first contact window.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology

[0002] In existing semiconductor structures, metal wiring is connected to electrodes at the edge of the effective region via contact windows. Specifically, metal wiring is positioned at the two adjacent edges of the first region and the second region, and each metal wiring is connected to the electrode layer via a contact window. However, this design has the following drawbacks: the contact windows connecting the metal wiring and the electrode layer are concentrated at the edge of the first region, resulting in high contact resistance when the lower metal wiring connects to the electrode layer through these contact windows, leading to poor voltage transmission stability. Furthermore, the existing design, with wiring layers on both sides of the effective region, is highly susceptible to patterning effects during CMP (Chemical Mechanical Polishing), causing warping. Summary of the Invention

[0003] A primary objective of this invention is to overcome at least one of the deficiencies of the prior art and to provide a semiconductor structure with better voltage transmission stability and less susceptibility to warping during CMP.

[0004] To achieve the above objectives, the present invention adopts the following technical solution:

[0005] According to one aspect of the present invention, a semiconductor structure is provided, comprising a substrate, a plurality of first wiring layers, and a plurality of lower contact windows; the substrate has a first region and a second region, and an electrode layer and a first insulating layer are sequentially disposed on the surface of the substrate; the plurality of first wiring layers are disposed in the first insulating layer, and the plurality of first wiring layers include a first wiring structure and a second wiring structure; the first wiring structure spans the first region, and its two ends are respectively located at the two side edges of the first region adjacent to the second region; the second wiring structure is located at the edge position of the first region; the plurality of lower contact windows are disposed in the first insulating layer, and the plurality of lower contact windows include a first contact window and a second contact window; the first contact window is located in the two side edge regions of the first region adjacent to the second region; the second contact window is located in the middle region of the first region; wherein the first wiring structure is connected to the electrode layer of the first region through the first contact window and the second contact window, and the second wiring structure is connected to the electrode layer of the first region through the first contact window.

[0006] According to one embodiment of the present invention, the second wiring structures are arranged in pairs, with the two second wiring structures in the same pair spaced apart along a first direction and respectively located at the two side edges of the first region adjacent to the second region.

[0007] According to one embodiment of the present invention, the plurality of first wiring layers are arranged at intervals along a second direction perpendicular to the first direction; wherein, along the second direction, at least one pair of second wiring structures is provided between two adjacent first wiring structures.

[0008] According to one embodiment of the present invention, the plurality of first wiring layers includes at least three first wiring structures; wherein, along the second direction, the number of pairs of second wiring structures disposed between any two adjacent first wiring structures is equal.

[0009] According to one embodiment of the present invention, the plurality of first wiring layers are arranged at intervals along a second direction perpendicular to the first direction; wherein, along the second direction, at least one first wiring structure is provided between two adjacent pairs of second wiring structures.

[0010] According to one embodiment of the present invention, the plurality of first wiring layers includes at least three pairs of second wiring structures; wherein, along the second direction, the number of first wiring structures disposed between any two adjacent pairs of second wiring structures is equal.

[0011] According to one embodiment of the present invention, the plurality of first wiring layers are arranged at intervals along a second direction perpendicular to the first direction; wherein each of the first wiring structures and each pair of second wiring structures are arranged alternately along the second direction.

[0012] According to one embodiment of the present invention, along the second direction, each odd-numbered column of the plurality of first wiring layers is a first wiring structure, and each even-numbered column is a pair of second wiring structures; or, along the second direction, each even-numbered column of the plurality of first wiring layers is a first wiring structure, and each odd-numbered column is a pair of second wiring structures.

[0013] According to one embodiment of the present invention, the plurality of first wiring layers includes at least two first wiring structures; wherein: the number of first contact windows connected to the at least two first wiring structures is equal; and / or, the number of second contact windows connected to the at least two first wiring structures is equal.

[0014] According to one embodiment of the present invention, the plurality of first wiring layers includes at least two second wiring structures; wherein the number of first contact windows connected to each second wiring structure is equal.

[0015] According to one embodiment of the present invention, the first wiring layer extends along a first direction, and at least one first wiring structure is connected to at least two second contact windows; wherein, along the first direction, the at least two second contact windows connected to the same first wiring structure are evenly spaced.

[0016] According to one embodiment of the present invention, the diameter of the first contact window is equal to the diameter of the second contact window.

[0017] According to one embodiment of the present invention, the semiconductor structure further includes a first protective layer, a second insulating layer, a second wiring layer, a second protective layer, and a third insulating layer; the first protective layer is disposed on the surfaces of the first insulating layer and the first wiring layer; the second insulating layer is disposed on the surface of the first protective layer; the second wiring layer is disposed on the surface of the second insulating layer and is connected to the first wiring layer at the edge of the first region through a second contact window; the second protective layer is disposed on the surfaces of the second insulating layer and the second wiring layer; and the third insulating layer is disposed on the surface of the second protective layer.

[0018] As can be seen from the above technical solution, the advantages and positive effects of the semiconductor structure proposed in this invention are as follows:

[0019] The semiconductor structure proposed in this invention features a first wiring layer that spans the central region of a first region, and this first wiring layer is connected to the electrode layer through contact windows in the central region and at both ends. Through this design, the invention increases the number of contact windows between the first wiring layer and the electrode layer in the central region of the first region, thereby reducing contact resistance and optimizing voltage transfer stability. Furthermore, the invention provides wiring layers in the central region and on both sides of the first region, making the semiconductor structure less prone to warping during CMP (Continuous Metal Processing).

[0020] Another major objective of this invention is to overcome at least one of the defects of the prior art and to provide a method for forming a semiconductor structure that can optimize the stability of voltage transfer in the semiconductor structure and is less prone to warping during the CMP process.

[0021] To achieve the above objectives, the present invention adopts the following technical solution:

[0022] According to one aspect of the present invention, a method for forming a semiconductor structure is provided, comprising: forming a substrate having a first region and a second region, wherein an electrode layer and a first insulating layer are sequentially formed on the surface of the substrate; forming a plurality of contact windows in the first insulating layer; forming a plurality of first wiring layers in the first insulating layer, wherein the plurality of first wiring layers are respectively connected to the electrode layer of the first region through the plurality of contact windows, the plurality of first wiring layers including a first wiring structure and a second wiring structure, wherein the first wiring structure spans the first region and its two ends are respectively located at the two side edges of the first region adjacent to the second region, and the second wiring structure is located at the edge position of the first region.

[0023] As can be seen from the above technical solution, the advantages and positive effects of the semiconductor structure formation method proposed in this invention are as follows:

[0024] The semiconductor structure formation method proposed in this invention increases the number of contact windows between the first wiring layer and the electrode layer in the central region of the first region by designing a portion of the first wiring layer to span a first region and by adding contact windows connecting the first wiring layer and the electrode layer in the first region. This reduces contact resistance and optimizes voltage transmission stability. Furthermore, this invention provides wiring layers in the central and both sides of the first region, making the semiconductor structure less prone to warping during CMP (Continuous Metallurgy Processing). Attached Figure Description

[0025] Various objects, features, and advantages of the invention will become more apparent from the following detailed description of preferred embodiments of the invention, taken in conjunction with the accompanying drawings. The drawings are merely illustrative of the invention and are not necessarily drawn to scale. In the drawings, the same reference numerals always denote the same or similar parts. Wherein:

[0026] Figure 1 This is a planar schematic diagram of a semiconductor structure according to an exemplary embodiment;

[0027] Figure 2 It is along Figure 1 A sectional view of the central line EE;

[0028] Figure 3 It is along Figure 1 A sectional view of the line FF in the middle.

[0029] Figure 4 This is a planar schematic diagram of a semiconductor structure according to another exemplary embodiment;

[0030] Figure 5 This is a planar schematic diagram of a semiconductor structure according to another exemplary embodiment;

[0031] Figure 6 This is a planar schematic diagram of a semiconductor structure according to another exemplary embodiment;

[0032] Figure 7 This is a planar schematic diagram of a semiconductor structure according to another exemplary embodiment;

[0033] Figure 8 This is a process flow diagram illustrating a semiconductor structure and a method for forming the same, according to an exemplary embodiment.

[0034] The annotations in the attached figures are explained as follows:

[0035] 100. Substrate;

[0036] 200. Electrode layer;

[0037] 300. First insulating layer;

[0038] 400. First protective layer;

[0039] 500. Second insulating layer;

[0040] 600. Second protective layer;

[0041] 700. Third insulating layer;

[0042] A. First area;

[0043] B. Second Zone;

[0044] M1. First wiring layer;

[0045] M11. First wiring structure;

[0046] M12. Second wiring structure;

[0047] M2. Second wiring layer;

[0048] V1. Lower contact window;

[0049] V11. First contact window;

[0050] V12. Second contact window;

[0051] V2. Upper contact window;

[0052] S1~S3. Steps;

[0053] X. First direction;

[0054] Y. Second direction. Detailed Implementation

[0055] Typical embodiments embodying the features and advantages of the present invention will be described in detail in the following description. It should be understood that the present invention can have various variations in different embodiments without departing from the scope of the present invention, and the description and drawings therein are for illustrative purposes only and not intended to limit the present invention.

[0056] In the following description of different exemplary embodiments of the invention, reference is made to the accompanying drawings, which form part of the invention, and in which different exemplary structures, systems, and steps that can implement various aspects of the invention are shown by way of example. It should be understood that other specific embodiments of the components, structures, exemplary devices, systems, and steps may be used, and structural and functional modifications may be made without departing from the scope of the invention. Furthermore, although the terms “above,” “between,” “within,” etc., may be used in this specification to describe different exemplary features and elements of the invention, these terms are used herein only for convenience, such as the orientation according to the examples shown in the drawings. Nothing in this specification should be construed as requiring a specific three-dimensional orientation of the structure to fall within the scope of the invention.

[0057] Semiconductor structure implementation method 1

[0058] See Figure 1 The illustration represents a planar schematic diagram of the semiconductor structure proposed in this invention, and schematically shows the planar top view of the first wiring layer M1, the second wiring layer M2, and the lower contact window V1 in a perspective manner. In this exemplary embodiment, the semiconductor structure proposed in this invention is described using a dynamic random access memory as an example. It will be readily understood by those skilled in the art that various modifications, additions, substitutions, deletions, or other changes can be made to the specific embodiments described below in order to apply the relevant designs of this invention to other types of semiconductor memories or other semiconductor structures, and these changes are still within the scope of the principles of the semiconductor structure proposed in this invention.

[0059] like Figure 1 As shown, in this embodiment, the semiconductor structure proposed in this invention includes a substrate 100, a plurality of first wiring layers M1, and a plurality of lower contact windows V1. (See also...) Figure 2 and Figure 3 , Figure 2 The middle section represents the way along Figure 1 A sectional view of the central line EE; Figure 3 The middle section represents the way along Figure 1 A cross-sectional view along the straight line FF. The structure, stacking arrangement, and functional relationships of the main components of the semiconductor structure proposed in this invention will be described in detail below with reference to the above figures.

[0060] like Figures 1 to 3As shown, in this embodiment, the substrate 100 has a first region A and a second region B. The first region A can be understood as the effective region, i.e., the capacitor array region, and the second region B can be understood as the ineffective region, i.e., the sensing amplification short circuit and word line driving region. An electrode layer 200 and a first insulating layer 300 are sequentially disposed on the surface of the substrate 100. A plurality of first wiring layers M1 are disposed in the first insulating layer 300, and the plurality of first wiring layers M1 include a first wiring structure M11 and a second wiring structure M12. The first wiring structure M11 spans across the first region A, and the two ends of the first wiring structure M11 are respectively located at the two side edges of the first region A adjacent to the second region B. The second wiring structure M12 is located at the edge of the first region A. A plurality of lower contact windows V1 are disposed in the first insulating layer 300, and the plurality of lower contact windows V1 include a first contact window V11 and a second contact window V12. The first contact window V11 is located at the two side edge regions of the first region A adjacent to the second region B. The second contact window V12 is located in the central region of the first region A (i.e., the region of the first region A excluding the edges, not limited to its center). The first wiring structure M11 is connected to the electrode layer 200 of the first region A through the first contact window V11 and the second contact window V12, and the second wiring structure M12 is connected to the electrode layer 200 of the first region A through the first contact window V11. Through the above design, the present invention can increase the number of contact windows between the first wiring layer M1 and the electrode layer 200 in the central region of the first region A, thereby reducing contact resistance and optimizing the stability of voltage transmission. Furthermore, the present invention provides wiring layers in the central region and on both sides of the first region A, making the semiconductor structure less prone to warping during CMP.

[0061] Optionally, such as Figure 1 As shown, in this embodiment, the second wiring structures M12 can be arranged in pairs, with multiple second wiring structures M12 forming multiple pairs. The two second wiring structures M12 in the same pair are spaced apart along a first direction X, which can be the extension direction of the first wiring layer M1. The two second wiring structures M12 in the same pair can be located at the two adjacent edges of the second region B in the first region A. In other embodiments, based on the design of the second wiring structures M12 being arranged in pairs, multiple first wiring layers M1 can include at least one pair of first wiring structures M11, and are not limited to this embodiment.

[0062] Furthermore, such as Figure 1 As shown, based on the design of the second wiring structure M12 arranged in pairs, in this embodiment, along the second direction Y, the odd-numbered columns of the plurality of first wiring layers M1 (with...) Figure 1The sequence shown can be a first wiring structure M11, and each even-numbered column of the plurality of first wiring layers M1 can be a pair of second wiring structures M12. In other embodiments, along the second direction Y, each even-numbered column of the plurality of first wiring layers M1 can also be a first wiring structure M11, and each odd-numbered column of the plurality of first wiring layers M1 can also be a pair of second wiring structures M12. Furthermore, when the number of first wiring layers M1 is an odd number greater than or equal to three (in which case a pair of second wiring structures M12 is considered as a first wiring layer M1), the two first wiring layers M1 at both ends along the second direction Y can both be first wiring structures M11, and each first wiring structure M11 and each pair of second wiring structures M12 are arranged alternately along the second direction Y, which is equivalent to a pair of second wiring structures M12 being provided between two adjacent first wiring structures M11. Furthermore, when the number of first wiring layers M1 is an odd number (three or more), both first wiring layers M1 at both ends of the second direction Y can also be second wiring structures M12, and each first wiring structure M11 and each pair of second wiring structures M12 are arranged alternately along the second direction Y, which is equivalent to setting one first wiring structure M11 between two adjacent pairs of second wiring structures M12. Of course, when the number of first wiring layers M1 is an even number, each first wiring structure M11 and each pair of second wiring structures M12 can also be arranged alternately, and are not limited to this embodiment.

[0063] Optionally, such as Figure 1 As shown, in this embodiment, when multiple first wiring layers M1 include at least two first wiring structures M11, the number of first contact windows V11 connected to each of these first wiring structures M11 can be equal. For example, the number of first contact windows V11 connected to each first wiring structure M11 can be, but is not limited to, two, and these two first contact windows V11 are respectively connected to the two ends of the first wiring structure M11 along the first direction X.

[0064] Optionally, such as Figure 1 As shown, in this embodiment, when multiple first wiring layers M1 include at least two first wiring structures M11, the number of second contact windows V12 connected to each of these first wiring structures M11 can be equal. For example, the number of second contact windows V12 connected to each first wiring structure M11 can be, but is not limited to, three, and these three second contact windows V12 are arranged at intervals along the first direction X and connected to the middle part of the first wiring structure M11 (i.e., the part other than the two ends of the first wiring structure M11).

[0065] Optionally, such as Figure 1As shown, in this embodiment, when multiple first wiring layers M1 include at least two second wiring structures M12, the number of first contact windows V11 connected to each of these second wiring structures M12 can be equal. For example, the number of first contact windows V11 connected to each second wiring structure M12 can be, but is not limited to, one.

[0066] Based on the above description of the number of first contact windows V11 and second contact windows V12 corresponding to the first wiring structure M11 and the second wiring structure M12, the semiconductor structure proposed in this invention can also be understood as follows: based on the existing capacitor structure, after the capacitor structure is completed, the electrode layer is led out through the first wiring layers located on both sides of the first region. Furthermore, this invention can also be understood as changing at least one pair of first wiring layers into a connected wiring structure (i.e., the first wiring structure M11). The improved wiring structure then penetrates the central region of the first region, and a contact window (i.e., the second contact window V12) is added to the central region of the first region, thereby achieving the connection between the added portion of the wiring structure and the electrode layer.

[0067] Optionally, such as Figure 1 As shown, in this embodiment, each first wiring structure M11 can be connected to three second contact windows V12. Based on this, along the first direction X, the three second contact windows V12 connected to the same first wiring structure M11 can be arranged at even intervals.

[0068] Optionally, such as Figure 1 As shown, in this embodiment, the diameter of the first contact window V11 can be equal to the diameter of the second contact window V12.

[0069] Optionally, such as Figure 2 and Figure 3 As shown, in this embodiment, the semiconductor structure proposed in this invention may further include a first protective layer 400, a second insulating layer 500, a second wiring layer M2, a second protective layer 600, and a third insulating layer 700. Specifically, the first protective layer 400 is disposed on the surface of the first insulating layer 300 and the first wiring structure M11. The second insulating layer 500 is disposed on the surface of the first protective layer 400. The second wiring layer M2 is disposed on the surface of the second insulating layer 500, and the second wiring layer M2 extends generally along the second direction Y and is connected to the first wiring layer M1 at the edge of the first region A through the upper contact window V2. The second protective layer 600 is disposed on the surface of the second insulating layer 500 and the second wiring layer M2. The third insulating layer 700 is disposed on the surface of the second protective layer 600.

[0070] In other embodiments, regardless of the number of first wiring layers M1, each first wiring layer M1 may contain only one first wiring structure M11 or only one second wiring structure M12. In other words, in various possible embodiments consistent with the design concept of the present invention, there are at least two first wiring layers M1, and each first wiring layer M1 contains at least one first wiring structure M11 and at least one second wiring structure M12.

[0071] Semiconductor Structure Implementation Method Two

[0072] Based on the detailed description of the first embodiment of the semiconductor structure proposed in this invention above, the following will be combined with... Figure 4 A second embodiment of the semiconductor structure proposed in this invention will be described. Figure 4 A schematic planar view of the semiconductor structure in this second embodiment is shown. The design of the semiconductor structure in this second embodiment, which differs from other embodiments, will be described below.

[0073] like Figure 4 As shown, unlike the first embodiment where a pair of second wiring structures M12 is provided between two adjacent first wiring structures M11 (i.e., a first wiring structure M11 is provided between two adjacent pairs of second wiring structures M12), in this embodiment, two pairs of second wiring structures M12 are provided between two adjacent first wiring structures M11. In other words, in various possible embodiments conforming to the design concept of this invention, when the second wiring structures M12 are arranged in pairs, along the second direction Y, at least one pair of second wiring structures M12 can be provided between two adjacent first wiring structures M11, and the number of pairs of second wiring structures M12 provided between two adjacent first wiring structures M11 can be equal. It is easy to understand that, similarly, along the second direction Y, at least one first wiring structure M11 can be provided between two adjacent pairs of second wiring structures M12, and the number of first wiring structures M11 provided between two adjacent pairs of second wiring structures M12 can be equal.

[0074] Semiconductor Structure Implementation Method 3

[0075] Based on the detailed description of the second embodiment of the semiconductor structure proposed in this invention above, the following will be combined with... Figure 5 A third embodiment of the semiconductor structure proposed in this invention will be described. Figure 5 A schematic planar view of the semiconductor structure in this third embodiment is shown. The design of the semiconductor structure in this third embodiment, which differs from other embodiments, will be described below.

[0076] like Figure 5As shown, unlike the second embodiment where the number of second wiring structures M12 between two adjacent first wiring structures M11 is equal, in this embodiment, some pairs of second wiring structures M12 between two adjacent first wiring structures M11 are one pair, while others are two pairs. In other words, in various possible embodiments conforming to the design concept of this invention, when the second wiring structures M12 are arranged in pairs, the number of pairs of second wiring structures M12 between two adjacent first wiring structures M11 may not be completely equal (including completely unequal). It is readily understood that, similarly, along the second direction Y, the number of first wiring structures M11 between two adjacent pairs of second wiring structures M12 may not be completely equal.

[0077] Semiconductor Structure Implementation Method Four

[0078] Based on the detailed description of the second embodiment of the semiconductor structure proposed in this invention above, the following will be combined with... Figure 6 The fourth embodiment of the semiconductor structure proposed in this invention will be described. Figure 6 A schematic planar view of the semiconductor structure in this fourth embodiment is shown as a representative example. The design of the semiconductor structure in this fourth embodiment, which differs from other embodiments, will be described below.

[0079] like Figure 6 As shown, unlike the second and third embodiments where both first wiring layers M1 at both ends of the second direction Y are designed as first wiring structures M11, in this embodiment, both first wiring layers M1 at both ends of the second direction Y are paired second wiring structures M12. Based on this, two first wiring structures M11 are provided between two adjacent pairs of second wiring structures M12. In other words, in various possible embodiments conforming to the design concept of this invention, for the two first wiring layers M1 at both ends of the second direction Y (where a pair of second wiring structures M12 is considered as one first wiring layer M1), they can be two first wiring structures M11, a pair of second wiring structures M12, or one first wiring structure M11 and a pair of second wiring structures M12, and are not limited to the above embodiments.

[0080] Semiconductor Structure Implementation Method Five

[0081] Based on the detailed description of the first embodiment of the semiconductor structure proposed in this invention above, the following will be combined with... Figure 7 The fifth embodiment of the semiconductor structure proposed in this invention will be described. Figure 7A schematic planar view of the semiconductor structure in this fifth embodiment is shown as a representative example. The design of the semiconductor structure in this fifth embodiment, which differs from other embodiments, will be described below.

[0082] like Figure 7 As shown, unlike the first to fourth embodiments where each first wiring structure M11 is connected to an equal number of second contact windows V12, in this embodiment, one first wiring structure M11 can connect to one second contact window V12, two other second wiring structures M12 can each connect to two second contact windows V12, and the remaining two second wiring structures M12 can each connect to three second contact windows V12. That is, when multiple first wiring layers M1 include at least two first wiring structures M11, the number of second contact windows V12 connected to each first wiring structure M11 may not be completely equal (including completely unequal). In other words, in various possible embodiments that conform to the design concept of the present invention, when multiple first wiring layers M1 include at least two first wiring structures M11, the number of second contact windows V12 connected to each first wiring structure M11 may be equal or not completely equal, and is not limited to the above embodiments.

[0083] The two first wiring layers M1 located at both ends of the second direction Y are both pairs of second wiring structures M12. Based on this, two first wiring structures M11 are provided between two adjacent pairs of second wiring structures M12. In other words, in various possible embodiments conforming to the design concept of this invention, for the two first wiring layers M1 located at both ends of the second direction Y (where a pair of second wiring structures M12 is considered as one first wiring layer M1), they can be two first wiring structures M11, a pair of second wiring structures M12, or one first wiring structure M11 and a pair of second wiring structures M12, and are not limited to the above embodiments.

[0084] It should be noted that the semiconductor structures shown in the accompanying drawings and described in this specification are merely a few examples among many semiconductor structures capable of employing the principles of the present invention. It should be clearly understood that the principles of the present invention are by no means limited to any detail or component of the semiconductor structures shown in the accompanying drawings or described in this specification.

[0085] In summary, the semiconductor structure proposed in this invention features a first wiring layer that spans the central region of a first region, and this first wiring layer is connected to the electrode layer through contact windows in the central region and at both ends. Through this design, this invention increases the number of contact windows between the first wiring layer and the electrode layer in the central region of the first region, thereby reducing contact resistance and optimizing voltage transfer stability. Furthermore, the invention provides wiring layers in the central region and on both sides of the first region, making the semiconductor structure less prone to warping during CMP (Continuous Metal Processing).

[0086] Implementation of methods for forming semiconductor structures

[0087] Based on the detailed description of several embodiments of the semiconductor structure proposed in this invention above, the following is combined with... Figure 8 An exemplary embodiment of the method for forming a semiconductor structure proposed in this invention will be described.

[0088] See Figure 8 The diagram illustrates a process flow chart of the semiconductor structure formation method proposed in this invention. In this exemplary embodiment, the semiconductor structure formation method proposed in this invention is described using a method for forming a dynamic random access memory as an example. It will be readily understood by those skilled in the art that various modifications, additions, substitutions, deletions, or other changes may be made to the specific embodiments described below to apply the relevant designs of this invention to the processes of other types of semiconductor memories or other semiconductor structures; these changes remain within the scope of the principles of the semiconductor structure formation method proposed in this invention.

[0089] like Figure 8 As shown, in this embodiment, the method for forming a semiconductor structure proposed in this invention includes:

[0090] Step S1: Form a substrate, the substrate having a first region and a second region, and an electrode layer and a first insulating layer are sequentially formed on the surface of the substrate;

[0091] Step S2: Form multiple contact windows in the first insulating layer;

[0092] Step S3: A plurality of first wiring layers are formed on the surface of the first insulating layer. The plurality of first wiring layers are connected to the electrode layer of the first region through a plurality of contact windows. The plurality of first wiring layers include a first wiring structure and a second wiring structure. The first wiring structure spans the first region, and the two ends of the first wiring structure are located at the two sides of the first region adjacent to the second region. The second wiring structure is located at the edge of the first region.

[0093] It should be noted that the methods for forming the capacitor structure shown in the accompanying drawings and described in this specification are merely a few examples of many methods capable of employing the principles of the present invention. It should be clearly understood that the principles of the present invention are by no means limited to any detail or step of the methods for forming the capacitor structure shown in the accompanying drawings or described in this specification.

[0094] In summary, the semiconductor structure formation method proposed in this invention increases the number of contact windows between the first wiring layer and the electrode layer in the central region of the first region by designing a portion of the first wiring layer to span a first region and by adding contact windows connecting the first wiring layer and the electrode layer in the first region. This reduces contact resistance and optimizes voltage transfer stability. Furthermore, the invention provides wiring layers in the central and both sides of the first region, making the semiconductor structure less prone to warping during CMP (Continuous Metal Processing).

[0095] The foregoing has described and / or illustrated exemplary embodiments of the semiconductor structure and its formation method proposed in this invention. However, the embodiments of this invention are not limited to the specific embodiments described herein; rather, components and / or steps of each embodiment may be used independently and separately from other components and / or steps described herein. Each component and / or step of one embodiment may also be used in combination with other components and / or steps of other embodiments. In describing the elements / components / etc. described and / or illustrated herein, the terms “a,” “an,” and “the above” are used to indicate the presence of one or more elements / components / etc. The terms “comprising,” “including,” and “having” are used to indicate an open-ended inclusion and mean that additional elements / components / etc. may exist in addition to those listed. Furthermore, the terms “first” and “second,” etc., in the claims and specification are used only as illustrative marks and are not intended to limit the numerical scope of the subject matter.

[0096] Although the semiconductor structure and its formation method proposed in this invention have been described according to different specific embodiments, those skilled in the art will recognize that modifications can be made to the implementation of this invention within the spirit and scope of the claims.

Claims

1. A semiconductor structure, characterized in that, Include: A substrate having a first region and a second region, wherein an electrode layer and a first insulating layer are sequentially disposed on the surface of the substrate; A plurality of first wiring layers are disposed within the first insulating layer, the plurality of first wiring layers comprising: A first wiring structure spans the first region, with both ends of the first wiring structure located at the two adjacent edges of the second region of the first region. The second wiring structure is located at the edge of the first region; Multiple lower contact windows are disposed in the first insulating layer, the multiple lower contact windows comprising: The first contact window is located in the two side edge regions adjacent to the second region of the first region; The second contact window is located in the central region of the first region; Wherein, the first wiring structure is connected to the electrode layer of the first region through the first contact window and the second contact window, and the second wiring structure is connected to the electrode layer of the first region through the first contact window; In the first contact window and the second contact window connected by the first wiring structure, and in the first direction, the first contact window is located on both sides of the second contact window.

2. The semiconductor structure according to claim 1, characterized in that, The second wiring structures are arranged in pairs, with the two second wiring structures in the same pair spaced apart along the first direction and located at the two sides of the first region adjacent to the second region.

3. The semiconductor structure according to claim 2, characterized in that, The plurality of first wiring layers are arranged at intervals along a second direction perpendicular to the first direction; wherein, along the second direction, at least one pair of second wiring structures is provided between two adjacent first wiring structures.

4. The semiconductor structure according to claim 3, characterized in that, The plurality of first wiring layers include at least three first wiring structures; wherein, along the second direction, the number of pairs of second wiring structures disposed between any two adjacent first wiring structures is equal.

5. The semiconductor structure according to claim 2, characterized in that, The plurality of first wiring layers are arranged at intervals along a second direction perpendicular to the first direction; wherein, along the second direction, at least one first wiring structure is provided between two adjacent pairs of second wiring structures.

6. The semiconductor structure according to claim 5, characterized in that, The plurality of first wiring layers include at least three pairs of second wiring structures; wherein, along the second direction, the number of first wiring structures disposed between any two adjacent pairs of second wiring structures is equal.

7. The semiconductor structure according to claim 2, characterized in that, The plurality of first wiring layers are arranged at intervals along a second direction perpendicular to the first direction; wherein each of the first wiring structures and each pair of second wiring structures are arranged alternately along the second direction.

8. The semiconductor structure according to claim 7, characterized in that, Along the second direction, each odd-numbered column of the plurality of first wiring layers is a first wiring structure, and each even-numbered column is a pair of second wiring structures; or, along the second direction, each even-numbered column of the plurality of first wiring layers is a first wiring structure, and each odd-numbered column is a pair of second wiring structures.

9. The semiconductor structure according to any one of claims 1 to 8, characterized in that, The plurality of first wiring layers includes at least two first wiring structures; wherein: The number of first contact windows connected to the at least two first wiring structures is equal; and / or The number of second contact windows connected to the at least two first wiring structures is equal.

10. The semiconductor structure according to any one of claims 1 to 8, characterized in that, The plurality of first wiring layers include at least two second wiring structures; wherein the number of first contact windows connected to each second wiring structure is equal.

11. The semiconductor structure according to any one of claims 1 to 8, characterized in that, The first wiring layer extends along a first direction, and at least one of the first wiring structures is connected to at least two second contact windows; wherein, along the first direction, the at least two second contact windows connected to the same first wiring structure are evenly spaced.

12. The semiconductor structure according to any one of claims 1 to 8, characterized in that, The diameter of the first contact window is equal to the diameter of the second contact window.

13. The semiconductor structure according to any one of claims 1 to 8, characterized in that, The semiconductor structure further includes: A first protective layer is disposed on the surfaces of the first insulating layer and the first wiring layer; A second insulating layer is disposed on the surface of the first protective layer; The second wiring layer is disposed on the surface of the second insulating layer and is connected to the first wiring layer at the edge of the first region through the second contact window; A second protective layer is disposed on the surfaces of the second insulating layer and the second wiring layer; A third insulating layer is disposed on the surface of the second protective layer.

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