Semiconductor structure and method of forming the same

Abstract

The application provides a semiconductor structure and a forming method thereof. The semiconductor structure comprises a substrate and a plurality of first wirings. The substrate has a first region and a second region. An electrode layer and a first insulating layer are sequentially arranged on the surface of the substrate. The plurality of first wirings are arranged in the first insulating layer and located at the edge position of the first region adjacent to the second region. At least one first wiring is connected with the electrode layer of the first region through at least two first contact windows. The diameters of the at least two first contact windows connected with one first wiring are not completely equal.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular, to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] In the prior art semiconductor structure, the metal wiring and the electrode of the active region edge are connected through the contact window. However, the reliability and stability of the current structure are poor, and there is still much room for improvement. SUMMARY

[0003] One of the main purposes of the present application is to overcome at least one of the defects of the prior art, and to provide a semiconductor structure with better stress resistance of the contact window and avoiding delamination.

[0004] To achieve the above purpose, the present application adopts the following technical solutions:

[0005] According to one aspect of the present application, a semiconductor structure is provided, comprising a substrate and a plurality of first wirings; the substrate has a first region and a second region, and the surface of the substrate is sequentially provided with an electrode layer and a first insulating layer; the plurality of first wirings are arranged in the first insulating layer and located at the edge of the first region adjacent to the second region, and at least one of the first wirings is connected to the electrode layer of the first region through at least two first contact windows; wherein the diameters of the at least two first contact windows connected to one of the first wirings are not completely equal.

[0006] According to one of the embodiments of the present application, each of the first wirings is connected to the electrode layer of the first region through at least two first contact windows.

[0007] According to one of the embodiments of the present application, the number of the first contact windows connected to each of the first wirings is equal.

[0008] According to one of the embodiments of the present application, the first wiring is connected to the electrode layer of the first region through two first contact windows.

[0009] According to one of the embodiments of the present application, the first wiring extends in a first direction, and the at least two first contact windows connected to one of the first wirings are arranged at intervals in the first direction.

[0010] According to one of the embodiments of the present application, at least one of the first wirings is connected to the electrode layer of the first region through at least three first contact windows, and the at least three first contact windows connected to one of the first wirings are arranged at uniform intervals.

[0011] According to one of the embodiments of the present application, each of the first wirings is connected to the electrode layer through at least two first contact windows; wherein in the two adjacent first wirings, the diameter of the first contact window closest to the second region of one of the first wirings is greater than that of the rest of the first contact windows, and the diameter of the first contact window farthest from the second region of the other of the first wirings is greater than that of the rest of the first contact windows.

[0012] According to one of the embodiments of the present application, the substrate has two second regions located on both sides of the first region; wherein the semiconductor structure comprises two columns of the first wirings, which are respectively located at two edge positions of the first region adjacent to the two second regions, and the first wirings belonging to one column are arranged at intervals along the edge of the first region adjacent to the second region.

[0013] According to one of the embodiments of the present application, the two columns of the first wirings comprise the same number of the first wirings, and the first wirings belonging to different columns correspond one by one.

[0014] According to one of the embodiments of the present application, the semiconductor structure further comprises a first protective layer, a second insulating layer, a second wiring, a second protective layer and a third insulating layer; the first protective layer is arranged on the surface of the first insulating layer and the first wiring; the second insulating layer is arranged on the surface of the first protective layer; the second wiring is arranged on the surface of the second insulating layer and connected to the first wiring at the edge of the first region through a second contact window; the second protective layer is arranged on the surface of the second insulating layer and the second wiring; and the third insulating layer is arranged on the surface of the second protective layer.

[0015] According to one of the embodiments of the present application, in the at least two first contact windows connected to one of the first wirings, the ratio of the diameter of the first contact window closest to the second region to that of the rest of the first contact windows is greater than 1:1 and less than or equal to 5:1.

[0016] According to one of the embodiments of the present application, the first contact window has an inverted truncated cone structure; wherein in the at least two first contact windows connected to one of the first wirings: the diameter of the top of the first contact window closest to the second region is 60nm-100nm, and the diameter of the bottom is 20nm-50nm; and / or the diameter of the top of the rest of the first contact windows is 30nm-60nm, and the diameter of the bottom is 10nm-30nm.

[0017] According to one of the embodiments of the present application, the diameters of the first contact windows connected to one first wiring, except for the first contact window closest to the second region, are equal.

[0018] According to one of the embodiments of the present application, the first contact window has an inverted frustum structure; wherein the corresponding tapers of the at least two first contact windows connected to one first wiring are equal.

[0019] From the above technical solution, the semiconductor structure provided by the present application has the following advantages and positive effects:

[0020] The semiconductor structure provided by the present application has the following advantages and positive effects:

[0021] Another main purpose of the present application is to overcome at least one of the defects of the prior art, and to provide a semiconductor structure forming method capable of improving the stress resistance of the contact window and avoiding delamination.

[0022] To achieve the above-mentioned purpose, the present application adopts the following technical solution:

[0023] According to one aspect of the present application, a semiconductor structure forming method is provided, comprising: forming a substrate having a first region and a second region, and sequentially forming an electrode layer and a first insulating layer on the surface of the substrate; forming a plurality of first contact windows in the first insulating layer, wherein the diameters of the plurality of first contact windows are not completely equal; forming a plurality of first wirings on the surface of the first insulating layer, wherein the first wirings are connected to the electrode layer of the first region through the first contact windows, at least one of the first wirings is connected to the electrode layer of the first region through at least two first contact windows, and the diameters of the at least two first contact windows connected to one first wiring are not completely equal.

[0024] From the above technical solution, the semiconductor structure forming method provided by the present application has the following advantages and positive effects:

[0025] The method for forming a semiconductor structure is provided by forming at least two contact windows between the lower wiring and the electrode layer at the edge of the first region, and the contact window closest to the second region has a larger diameter than the rest of the contact windows. Through the above process design, the application can provide a better stress-resistant structure by using the contact window with a larger diameter at the edge, and alleviate the resistance increase or voltage instability caused by the delamination of the contact window. Moreover, the contact window with a larger diameter has a lower resistance, so that the voltage of the other upper structure can be more effectively dropped to the electrode layer. BRIEF DESCRIPTION OF DRAWINGS

[0026] Various objects, features and advantages of the present application will become more apparent to those skilled in the art from the following detailed description of preferred embodiments of the present application, when taken in conjunction with the accompanying drawings. The drawings are merely schematic and are not drawn to scale. In the drawings, like reference numerals refer to like parts throughout the various views. Wherever possible, the same or like reference numerals have been used throughout the drawings to refer to same or like parts. Among the other things, the present application comprises:

[0027] Figure 1 is a plan view of a semiconductor structure according to an exemplary embodiment;

[0028] Figure 2 is a cross-sectional view taken along the straight line X-X in Figure 1

[0029] Figure 3 is a plan view of a semiconductor structure according to another exemplary embodiment;

[0030] Figure 4 is a plan view of a semiconductor structure according to another exemplary embodiment;

[0031] Figure 5 is a plan view of a semiconductor structure according to another exemplary embodiment;

[0032] Figure 6 is a plan view of a semiconductor structure according to another exemplary embodiment;

[0033] Figure 7 is a process flow diagram of a semiconductor structure and a method for forming the same according to an exemplary embodiment.

[0034] The reference signs are explained as follows:

[0035] 100. substrate;

[0036] 200. electrode layer;

[0037] 300. first insulating layer;

[0038] 400. first protective layer;

[0039] ​500. second insulating layer;

[0040] 600. second protective layer;

[0041] 700. third insulating layer;

[0042] A. first region;

[0043] B. second region;

[0044] M1. first wiring;

[0045] M2. second wiring;

[0046] V1. first contact hole;

[0047] V2. second contact hole;

[0048] S1-S3. steps;

[0049] Y. first direction;

[0050] Z. second direction. DETAILED DESCRIPTION

[0051] The exemplary embodiments embodying the features and advantages of the present application will be described in detail hereinafter. It should be understood that the present application can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the application to those skilled in the art. In the drawings, the same reference numerals are used to represent similar components in the various views.

[0052] In the following description of various example embodiments of the present application, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustration various example structures, systems, and steps in which aspects of the application can be practiced. It is to be understood that other specific arrangements of parts, structures, example devices, systems, and steps can be utilized and structural and functional modifications can be made without departing from the scope of the present application. Also, while the terms "top," "bottom," "front," "back," and the like can be used in this specification to describe various example features and elements of the application, these terms are used herein as a shorthand notation, and in no way limit or restrict the scope of the application, which is defined solely by the claims and equivalents thereof. Nothing in this specification should be construed as requiring a specific three dimensional orientation of structures in order to fall within the scope of the present application.

[0053] Semiconductor structure embodiment one

[0054] Reference is made to Figure 1This illustration represents a planar schematic diagram of the semiconductor structure proposed in this application, and schematically shows the planar top view of the first wiring M1, the second wiring M2, and the first contact window V1 in a perspective manner. In this exemplary embodiment, the semiconductor structure proposed in this application is described using a dynamic random access memory as an example. It will be readily understood by those skilled in the art that various modifications, additions, substitutions, deletions, or other changes may be made to the specific embodiments described below in order to apply the relevant designs of this application to other types of semiconductor memories or other semiconductor structures, and these changes are still within the scope of the principles of the semiconductor structure proposed in this application.

[0055] like Figure 1 As shown, in this embodiment, the semiconductor structure proposed in this application includes a substrate 100 and a plurality of first wirings M1. (See also...) Figure 2 , Figure 2 The middle section represents the direction along Figure 1 A cross-sectional view along line XX. The following will, in conjunction with the above figures, provide a detailed description of the structure, stacking arrangement, and functional relationships of the main components of the semiconductor structure proposed in this application.

[0056] like Figure 1 and Figure 2 As shown, in this embodiment, the substrate 100 has a first region A and a second region B. The first region A can be understood as the effective region, i.e., the capacitor array region, and the second region B can be understood as the ineffective region, i.e., the sensing amplification short circuit and word line driving region. An electrode layer 200 and a first insulating layer 300 are sequentially disposed on the surface of the substrate 100. A plurality of first wirings M1 are disposed in the first insulating layer 300, and the first wirings M1 are located at the edge of the first region A adjacent to the second region B. The first wirings M1 are connected to the electrode layer 200 of the first region A through two first contact windows V1. The two first contact windows V1 connecting a first wiring M1 are at different distances from the second region B, and the diameter of the first contact window V1 closer to the second region B is larger than the diameter of the other first contact window V1.

[0057] The existing semiconductor structure is to connect the electrodes by a metal wiring through two contact windows with the same size. However, the above design has the following defects: the contact window located at the edge is prone to delamination from the electrode due to stress, resulting in high resistance or unstable voltage and other defects. Moreover, based on the above semiconductor structure, when the upper metal wiring is connected with the part of the lower metal wiring located in the invalid area through the upper contact window, due to the small size of the existing lower contact window, the resistance of the contact window is large, and the stability of voltage transmission is poor. Compared with the existing scheme, the application can provide a better stress-resistant structure through the above design of the contact window between the first wiring M1 and the electrode layer 200, and alleviate the resistance increase or voltage instability caused by the delamination of the contact window. Moreover, the contact window with a larger diameter has a lower resistance, so that the voltage of other upper structures can be more effectively applied to the electrode layer 200.

[0058] Optionally, as shown in the embodiment, each first wiring M1 is connected with the electrode layer 200 of the first area A through two first contact windows V1. Through the above design, the application can provide a better stress-resistant structure for each first wiring M1. In other embodiments, a part of the plurality of first wirings M1 can also have only one first contact window V1, and is not limited to the embodiment. Figure 1 Optionally, as shown in the embodiment, the first wiring M1 extends along the first direction Y, and on this basis, the two first contact windows V1 connected with one first wiring M1 can be arranged along the first direction Y, that is, the two first contact windows V1 connected with one first wiring M1 are arranged along the extension direction of the first wiring M1. In other embodiments, the first contact windows V1 connected with one first wiring M1 can also be arranged in other directions or in an irregular arrangement, but it is required that the first contact windows V1 connected with one first wiring M1 at least include one closest to the second area B, and the diameter of the at least one first contact window V1 is greater than that of the remaining first contact windows V1. Through the above design, the application can flexibly arrange the positions of the first contact windows V1 with different diameters according to the arrangement form of the first wiring M1.

[0059] Figure 1 Optionally, as shown in the embodiment, the substrate 100 can have two second areas B located on both sides of the first area A. On this basis, the semiconductor structure proposed by the application can include two columns of first wirings M1, and the two columns of first wirings M1 are located at the edge positions of the first area A adjacent to the two second areas B, and the plurality of first wirings M1 belonging to one column are arranged along the edge of the first area A adjacent to the second area B.

[0060] Optionally, as shown in the embodiment, the substrate 100 can have two second areas B located on both sides of the first area A. On this basis, the semiconductor structure proposed by the application can include two columns of first wirings M1, and the two columns of first wirings M1 are located at the edge positions of the first area A adjacent to the two second areas B, and the plurality of first wirings M1 belonging to one column are arranged along the edge of the first area A adjacent to the second area B. Figure 1

[0061] ​​Further, as shown in Figure 1 Based on the design that the semiconductor structure contains two rows of first wirings M1, in the present embodiment, the two rows of first wirings M1 can contain the same number of first wirings M1, and the first wirings M1 belonging to different rows correspond one by one.

[0062] Optionally, as shown in Figure 2 In the present embodiment, the semiconductor structure proposed by the present application can further contain a first protective layer 400, a second insulating layer 500, a second wiring M2, a second protective layer 600, and a third insulating layer 700. Specifically, the first protective layer 400 is arranged on the surface of the first insulating layer 300 and the first wiring M1. The second insulating layer 500 is arranged on the surface of the first protective layer 400. The second wiring M2 is arranged on the surface of the second insulating layer 500, and the second wiring M2 extends substantially along the second direction Z and is connected to the first wiring M1 at the edge of the first region A through the second contact window V2. The second protective layer 600 is arranged on the surface of the second insulating layer 500 and the second wiring M2. The third insulating layer 700 is arranged on the surface of the second protective layer 600.

[0063] Further, as shown in Figure 2 Based on the design that the semiconductor structure contains the second wiring M2, in the present embodiment, the position where the second wiring M2 is connected to the first wiring M1 through the second contact window V2 can be located on the side of the first contact window V1 closest to the second region B.

[0064] Optionally, as shown in Figure 1 In the present embodiment, the diameters of the first contact window V1 closest to the second region B of each of the plurality of first wirings M1 are equal.

[0065] Optionally, as shown in Figure 1 In the present embodiment, based on the design that each of the plurality of first wirings M1 is connected to the electrode layer 200 through two first contact windows V1, the diameters of the first contact windows V1 other than the first contact window V1 closest to the second region B of each of the first wirings M1 are equal.

[0066] Optionally, in the present embodiment, among the plurality of first contact windows V1 connected to one first wiring M1, the ratio of the diameter of the first contact window V1 closest to the second region B to the diameters of the remaining first contact windows V1 can be greater than 1:1 and less than or equal to 5:1, such as 1.1:1, 1.5:1, 3:1, 5:1, etc. In other embodiments, the ratio of the diameter of the first contact window V1 closest to the second region B to the diameters of the remaining first contact windows V1 connected to one first wiring M1 can also be greater than 5:1, such as 5.5:1, 6:1, etc., and is not limited to the present embodiment.

[0067] Optionally, such as Figure 2 As shown, in this embodiment, the first contact window V1 can be approximately shaped like an inverted frustum. Based on this, among the multiple first contact windows V1 connecting a first wiring M1, the diameter of the top of the first contact window V1 closest to the second region B can be 60nm to 100nm, for example, 60nm, 75nm, 90nm, 100nm, etc., and the diameter of the bottom of the first contact window V1 can be 20nm to 50nm, for example, 20nm, 25nm, 40nm, 50nm, etc. In other embodiments, the diameter of the top of the first contact window V1 closest to the second region B can also be less than 60nm or greater than 100nm, for example, 55nm, 110nm, etc., and the diameter of the bottom of the first contact window V1 can also be less than 20nm or greater than 50nm, for example, 18nm, 55nm, etc., but the bottom diameter must be smaller than the top diameter, and these are not limited to this embodiment.

[0068] Optionally, such as Figure 2 As shown, in this embodiment, the first contact window V1 can be approximately shaped like an inverted frustum. Based on this, among the multiple first contact windows V1 connecting a first wiring M1, the diameter of the top of the remaining first contact windows V1 can be 30nm to 60nm, for example, 30nm, 35nm, 40nm, 60nm, etc., and the diameter of the bottom of the first contact window V1 can be 10nm to 30nm, for example, 10nm, 20nm, 25nm, 30nm, etc. In other embodiments, the diameter of the top of the remaining first contact windows V1 can also be less than 30nm or greater than 60nm, for example, 25nm, 65nm, etc., and the diameter of the bottom of the first contact window V1 can also be less than 10nm or greater than 30nm, for example, 9nm, 35nm, etc., but the bottom diameter must be smaller than the top diameter, and this is not limited to this embodiment.

[0069] Optionally, such as Figure 2 As shown, the first contact window V1 can be approximately shaped like an inverted frustum. Based on this, the corresponding tapers of the plurality of first contact windows V1 connected to a first wiring M1 can be equal. In other words, among the plurality of first contact windows V1 connected to a first wiring M1, the corresponding tapers of first contact windows V1 with different diameters are equal. In other embodiments, the corresponding tapers of the plurality of first contact windows V1 connected to a first wiring M1 may not be equal, and this is not limited to this embodiment.

[0070] It should be noted that, in the description of the first embodiment and the following other embodiments, the description of the "diameter" of the first contact hole V1 is based on the assumption that the side wall of the contact hole is a straight wall surface, and specifically refers to the diameter of the middle part (the middle position in the height direction) of the first contact hole V1, that is, the average diameter of the contact hole of this structure. In other embodiments, when the first contact hole V1 has other structures, the average diameter can also be calculated in other ways. In addition, in the description of some preferred schemes, when the diameter of the "top" or "bottom" of the first contact hole V1 is specifically limited, it can be clearly understood as the diameter of the specific position, which is distinguished from the "diameter of the middle part" or "average diameter" described above.

[0071] Optionally, in the present embodiment, for one first wiring M1, the over-etching depth of the two first contact holes V1 in the electrode layer can gradually become shallower in the direction from the second region B to the first region A, that is, the over-etching depth of the first contact hole V1 closest to the second region B is the deepest, so as to prevent the first contact hole from delaminating and maximize the stability of the electrical signal.

[0072] Semiconductor structure embodiment two

[0073] Based on the above detailed description of the first embodiment of the semiconductor structure proposed in the present application, the following will be combined with Figure 3 The second embodiment of the semiconductor structure proposed in the present application will be described. Among them, Figure 3 The planar schematic diagram of the semiconductor structure in the second embodiment is typically shown. The following will describe the design of the semiconductor structure in the second embodiment which is different from other embodiments.

[0074] As Figure 3 shown, in the design that the first wiring M1 in the first embodiment is connected with the electrode layer 200 of the first region A through two first contact holes V1, in the present embodiment, each first wiring M1 is connected with the electrode layer 200 of the first region A through three first contact holes V1 respectively. On this basis, for the three first contact holes V1 connected with one first wiring M1, one of the first contact holes V1 is closer to the second region B than the other first contact holes V1, and the diameter of the first contact hole V1 closest to the second region B is greater than that of the other first contact holes V1.

[0075] Optionally, as Figure 3As shown, for a first wiring M1, the three first contact windows V1 connecting the first wiring M1 are evenly spaced, for example, evenly spaced in the first direction Y, or they can be arranged in other directions. In other embodiments, when a first wiring M1 is connected to the electrode layer 200 through three or more first contact windows V1, these first contact windows V1 can also be evenly spaced. Alternatively, when a first wiring M1 is connected to the electrode layer 200 through three or more first contact windows V1, these first contact windows V1 can also adopt other arrangement forms, but it must be ensured that at least one first contact window V1 is closer to the second region B than the other first contact windows V1, and the diameter of the at least one first contact window V1 is larger than the diameter of the other first contact windows V1.

[0076] Optionally, in this embodiment, for a first wiring M1, the spacing between each pair of the three first contact windows V1 can increase progressively from the second region B to the first region A. Through the above design, this application can enhance structural stability, making the transmission of electrical signals more stable and reliable. Optionally, as... Figure 3 As shown, for a first wiring M1, except for the first contact window V1 closest to the second region B, the diameters of the other two first contact windows V1 can be equal. In other words, in various possible embodiments conforming to the design concept of this application, among the at least two first contact windows V1 connecting a first wiring M1, except for the first contact window V1 closest to the second region B, the diameters of the other first contact windows V1 are all equal.

[0077] Semiconductor Structure Implementation Method 3

[0078] Based on the above detailed description of the first embodiment of the semiconductor structure proposed in this application, the following will be combined with Figure 4 The third embodiment of the semiconductor structure proposed in this application will be described. Figure 4 A schematic planar view of the semiconductor structure in this third embodiment is shown. The design of the semiconductor structure in this third embodiment, which differs from other embodiments, will be described below.

[0079] like Figure 4 As shown, in this embodiment, among the plurality of first wirings M1, a portion of the first wirings M1 are connected to the electrode layer 200 through a plurality of first contact windows V1 with a diameter relationship as described in the above embodiment, and another portion of the first wirings M1 can be connected to the electrode layer 200 through a plurality of first contact windows V1 with equal diameters.

[0080] Optionally, such as Figure 4As shown, in the present embodiment, for the plurality of first wirings M1 in the same column, the first wirings M1 with unequal diameters of the first contact windows V1 and the first wirings M1 with equal diameters of the first contact windows V1 can be arranged in an alternating manner.

[0081] Semiconductor structure embodiment four

[0082] Based on the above detailed description of the first embodiment of the semiconductor structure proposed in the present application, the following will be combined with the Figure 5 The fourth embodiment of the semiconductor structure proposed in the present application will be described. Among them, Figure 5 The planar schematic diagram of the semiconductor structure in the fourth embodiment is shown representatively. The following will describe the design of the semiconductor structure in the fourth embodiment which is different from other embodiments.

[0083] As Figure 5 shown, different from the design that the number of the first contact windows V1 of each first wiring M1 is equal in the first to third embodiments described above, in the present embodiment, the plurality of first wirings M1 can be connected with the electrode layer 200 through the first contact windows V1 with unequal numbers. For example, a part of the first wirings M1 are connected with the electrode layer 200 through two first contact windows V1, and another part of the first wirings M1 are connected with the electrode layer 200 through three first contact windows V1.

[0084] Alternatively, as Figure 5 shown, in the present embodiment, for the plurality of first wirings M1 in the same column, the first wirings M1 with unequal numbers of the first contact windows V1 can be arranged in an alternating manner. For example, the first wirings M1 containing three first contact windows V1 and the first wirings M1 containing two first contact windows V1 can be arranged in an alternating manner.

[0085] Semiconductor structure embodiment five

[0086] Based on the above detailed description of the first embodiment of the semiconductor structure proposed in the present application, the following will be combined with the Figure 6 The fifth embodiment of the semiconductor structure proposed in the present application will be described. Among them, Figure 6 The planar schematic diagram of the semiconductor structure in the fifth embodiment is shown representatively. The following will describe the design of the semiconductor structure in the fifth embodiment which is different from other embodiments.

[0087] As Figure 6As shown, in contrast to the design of the first contact window V1 of the first wiring M1 closest to the second region B in the first to fourth embodiments described above, in the present embodiment, for at least a portion of the first wiring M1, among the at least two first contact windows V1 connected to one first wiring M1, the first contact window V1 far from the second region B can also have a larger diameter than the remaining first contact windows V1.

[0088] Optionally, as shown, in the present embodiment, the plurality of first wirings M1 can include two portions, one portion of the first wirings M1 adopts the design of the first contact window V1 closest to the second region B having a larger diameter, and the other portion of the first wirings M1 adopts the design of the first contact window V1 far from the second region B having a larger diameter. On this basis, the two types of first wirings M1 in the two connection forms can be arranged alternately along the second direction Y. Figure 6 Further, as shown, in the present embodiment, for at least two first contact windows V1 belonging to one first wiring, the first contact window V1 with a smaller diameter has a smaller over-etching depth in the electrode layer, and the first contact window V1 with a larger diameter has a larger over-etching depth in the electrode layer, thereby better releasing stress. In combination with the above arrangement of the first wirings in different connection forms in the present embodiment, it is equivalent to that, along the second direction Y, one first contact window V1 with a smaller diameter is arranged between two adjacent first contact windows V1 with a larger diameter, and one first contact window V1 with a smaller over-etching depth is arranged between two adjacent first contact windows V1 with a larger over-etching depth.

[0089] Figure 6 In other words, in various possible embodiments consistent with the design concept of the present application, for one first wiring, when the first wiring is connected to the electrode layer via at least two first contact windows, if the distances of the at least two first contact windows from the second region are not completely the same, the diameter of the first contact window closest to the second region can be larger than that of the remaining first contact windows, or the diameter of the first contact window far from the second region can be larger than that of the remaining first contact windows. Of course, regardless of the arrangement of the at least two first contact windows connected to one first wiring, and regardless of the distance relationship of the at least two first contact windows from the second region, among the at least two first contact windows connected to one first wiring, the diameter of at least one first contact window is the largest, and the diameters of the remaining first contact windows can be completely equal or not completely equal, and are not limited to the above embodiments.

[0090] On this basis, in addition, for at least two first contact windows belonging to one first wiring, the first contact window with a smaller diameter has a smaller over-etching depth in the electrode layer, and the first contact window with a larger diameter has a larger over-etching depth in the electrode layer, thereby better releasing stress.

[0091] On this basis, in addition, for at least two first contact windows belonging to one first wiring, the first contact window with a smaller diameter has a smaller over-etching depth in the electrode layer, and the first contact window with a larger diameter has a larger over-etching depth in the electrode layer, thereby better releasing stress. ​

[0092] It should be noted that based on the above description of the first to fifth embodiments, in various possible embodiments consistent with the design concept of the present application, regardless of the number or arrangement of the first contact holes V1 included in each first wiring M1, preferably, the distance between the first contact holes V1 with larger diameters in each first wiring M1 can be equal, and the distance between the remaining first contact holes V1 can be equal.

[0093] It should be noted that the semiconductor structure shown in the drawings and described in the specification is only a few examples of many semiconductor structures that can employ the principles of the present application. It should be clearly understood that the principles of the present application are by no means limited to any details or any components of the semiconductor structure shown in the drawings or described in the specification.

[0094] In summary, the semiconductor structure proposed in the present application provides that the lower wiring is connected to the electrode layer at the edge of the first region through at least two contact holes, and the diameter of the contact hole closest to the second region is larger than that of the remaining contact holes, thereby providing a better stress-resistant structure and alleviating the resistance increase or voltage instability caused by contact hole delamination. Moreover, the contact hole with a larger diameter has a lower resistance, so that the voltage of the other upper structure can be more effectively dropped to the electrode layer.

[0095] Embodiment of the method for forming the semiconductor structure

[0096] Based on the above detailed description of the various embodiments of the semiconductor structure proposed in the present application, the following will describe an exemplary embodiment of the method for forming the semiconductor structure proposed in the present application. Figure 7 An exemplary embodiment of the method for forming the semiconductor structure proposed in the present application will be described.

[0097] Referring to Figure 7 which represents a process flow diagram of the method for forming the semiconductor structure proposed in the present application. In this exemplary embodiment, the method for forming the semiconductor structure proposed in the present application is described by taking the method for forming a dynamic random access memory as an example. It is easy for those skilled in the art to understand that various modifications, additions, substitutions, deletions or other changes can be made to the following specific embodiments in order to apply the relevant design of the present application to the process of other types of semiconductor memories or other semiconductor structures, and these changes are still within the scope of the principles of the method for forming the semiconductor structure proposed in the present application.

[0098] As Figure 7 shown in the present embodiment, the method for forming the semiconductor structure proposed in the present application comprises:

[0099] Step S1: forming a substrate having a first region and a second region, and sequentially forming an electrode layer and a first insulating layer on the surface of the substrate;

[0100] Step S2: forming a plurality of first contact windows in the first insulating layer, the diameters of the plurality of first contact windows are not completely same;

[0101] Step S3: forming a plurality of first wirings on the surface of the first insulating layer, the first wirings are connected with the electrode layer of the first region through the first contact windows, at least one first wiring is connected with the electrode layer of the first region through at least two first contact windows, the diameters of the at least two first contact windows connected with one first wiring are not completely same.

[0102] It should be noted that the forming methods of the memory capacitor structure shown in the drawings and described in the specification are only a few examples of the many forming methods that can employ the principles of the present application. It should be clearly understood that the principles of the present application are by no means limited to any details or any steps of the forming methods of the memory capacitor structure shown in the drawings or described in the specification.

[0103] In summary, the forming method of the semiconductor structure proposed in the present application forms at least two contact windows between the lower wiring and the electrode layer of the edge of the first region, and the diameter of the contact window closest to the second region is larger than that of the remaining contact windows. Through the above process design, the present application can provide a better stress-resistant structure by using the contact window with a larger diameter at the edge, and alleviate the resistance increase or voltage instability caused by the delamination of the contact window. Moreover, the contact window with a larger diameter has a lower resistance, so that the voltage of the other upper structure can be more effectively dropped to the electrode layer.

[0104] The exemplary embodiments of the semiconductor structure and the forming method thereof proposed in the present application are described and / or illustrated in detail above. However, the embodiments of the present application are not limited to the specific embodiments described herein, but rather, each of the individual components and / or steps of each embodiment can be used independently and separately from the other components and / or steps described herein. Each component and / or step of one embodiment can also be used in combination with other components and / or steps of other embodiments. The language used in the description herein has been principally selected for readability and instructional purposes and can not have been selected to delineate or circumscribe the inventive subject matter, resorting as needed to conjunctive language where indelicate or unclear. It is therefore intended that the scope of the application be determined by the following claims and their equivalents.

[0105] While the semiconductor structure and the forming method thereof proposed in the present application have been described in accordance with various specific embodiments, it is evident that modifications and alterations can be made to the embodiments of the present application by those skilled in the art without departing from the spirit and scope of the application.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a substrate having a first region and a second region, the substrate being provided with an electrode layer and a first insulating layer in sequence on a surface thereof; a plurality of first wirings provided in the first insulating layer and located at edge positions of the first region adjacent to the second region, at least one of the first wirings being connected to the electrode layer of the first region through at least two first contact windows; wherein, in the at least two first contact windows connected to one of the first wirings, the first contact window closest to the second region has a diameter greater than that of the remaining first contact windows.

2. The semiconductor structure of claim 1, wherein, Each of the first wirings is connected to the electrode layer of the first region through at least two first contact windows.

3. The semiconductor structure of claim 2, wherein, The number of the first contact windows connected to each of the first wirings is equal.

4. The semiconductor structure of claim 3, wherein, The first wiring is connected to the electrode layer of the first region through two first contact windows.

5. The semiconductor structure of claim 1, wherein, The first wirings extend in a first direction, and the at least two first contact windows connected to one of the first wirings are arranged in the first direction at intervals.

6. The semiconductor structure of claim 5, wherein, At least one of the first wirings is connected to the electrode layer of the first region through at least three first contact windows, and the at least three first contact windows connected to one of the first wirings are arranged at intervals.

7. The semiconductor structure of claim 5, wherein, Each of the first wirings is connected to the electrode layer through at least two first contact windows; wherein, in the two adjacent first wirings, the first contact window closest to the second region of one of the first wirings has a diameter greater than that of the remaining first contact windows, and the first contact window farthest from the second region of the other of the first wirings has a diameter greater than that of the remaining first contact windows.

8. The semiconductor structure of claim 1, wherein, The substrate has two second regions located on both sides of the first region; wherein, the semiconductor structure comprises two columns of first wirings, the two columns of first wirings being located at two edge positions of the first region adjacent to the two second regions respectively, and the first wirings belonging to one column are arranged at intervals along the edge of the first region adjacent to the second region.

9. The semiconductor structure of claim 8, wherein, The two columns of first wirings comprise the same number of first wirings, and the first wirings belonging to different columns correspond to each other one by one.

10. The semiconductor structure of any of claims 1-9, wherein, The semiconductor structure further comprises: a first protective layer provided on surfaces of the first insulating layer and the first wirings; a second insulating layer provided on a surface of the first protective layer; a second wiring provided on a surface of the second insulating layer and connected to the first wirings at the edge of the first region through second contact windows; a second protective layer provided on surfaces of the second insulating layer and the second wiring; a third insulating layer provided on a surface of the second protective layer.

11. The semiconductor structure of any of claims 1-9, wherein the semiconductor structure is a vertical semiconductor structure. In the at least two first contact windows connected to one of the first wirings, the diameter of the first contact window with the largest diameter is greater than 1:1 and less than or equal to 5:1 compared with the diameters of the remaining first contact windows.

12. The semiconductor structure of claim 11, wherein, The first contact window has an inverted truncated cone structure; wherein, in the at least two first contact windows connected to one of the first wirings, The diameter of the top of the first contact window with the largest diameter is 60-100 nm, and the diameter of the bottom is 20-50 nm; and / or The diameter of the top of the rest of the first contact windows is 30-60 nm, and the diameter of the bottom is 10-30 nm.

13. The semiconductor structure of any of claims 1-9, wherein: Among the at least two first contact windows connected to one first wiring, the diameter of one first contact window is the largest, and the diameters of the rest of the first contact windows are equal.

14. The semiconductor structure of any of claims 1-9, wherein, The first contact window has an inverted frustum structure; wherein the corresponding taper of the at least two first contact windows connected to one first wiring is equal.

15. A method of forming a semiconductor structure, comprising: Comprise: forming a substrate having a first region and a second region, and sequentially forming an electrode layer and a first insulating layer on the surface of the substrate; forming a plurality of first contact windows in the first insulating layer, the diameters of the plurality of first contact windows being not completely the same; forming a plurality of first wirings in the first insulating layer, the first wirings being connected to the electrode layer of the first region through the first contact windows, at least one first wiring being connected to the electrode layer of the first region through at least two first contact windows, and among the at least two first contact windows connected to one first wiring, the diameter of the first contact window closest to the second region is larger than that of the rest of the first contact windows.

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