Quasi-vertical power device and manufacturing method thereof, and chip

Abstract

The application provides a quasi-vertical power device and a manufacturing method and a chip thereof. The quasi-vertical power device comprises a substrate, a buffer layer, a gallium nitride high-doped N+ layer, a gallium nitride low-doped N- layer, a gallium nitride P-type substrate and a gallium nitride N-type active region which are sequentially arranged on the substrate along a first direction. The quasi-vertical power device is provided with two grooves, and ohmic contact metal and Schottky contact metal are arranged in the grooves respectively, so that ohmic contact and Schottky contact are realized, quasi-vertical MOSFET and Schottky barrier diode are formed respectively, the quasi-vertical MOSFET and the Schottky barrier diode are integrated in parallel, the reverse recovery loss is reduced, the reverse recovery speed is improved, the switching characteristic is faster, and the quasi-vertical power device can be used in high-frequency occasions, such as a step-down / step-up converter, a voltage source inverter and a resonant converter.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor technology, and in particular relates to a quasi-vertical power device, a manufacturing method thereof, and a chip. Background Art

[0002] Semiconductor power devices are the core elements for efficient conversion, control, and regulation of electrical energy. Today, they are widely used in a wide range of applications, from traditional industrial control to personal computers, consumer electronics, smart cars, new energy systems, rail transit, smart grids, and more.

[0003] Among them, power devices based on wide-bandgap GaN (gallium nitride) materials have the characteristics of high reverse blocking voltage, low forward on-resistance, high operating frequency, and high efficiency. They can meet the power electronics system's requirements for semiconductor devices with higher power, higher frequency, smaller size, lower power consumption, and harsher working environment.

[0004] GaN power field-effect transistor (MOSFET) products are now available. To use quasi-vertical MOSFETs in several devices, such as buck / boost converters, voltage source inverters, and resonant converters, an additional freewheeling diode is required to allow reverse current flow during the off state. The intrinsic body PiN diode embedded in the GaN quasi-vertical MOSFET can be used as a freewheeling diode, but its large turn-on voltage increases reverse recovery losses. Summary of the Invention

[0005] The purpose of the present application is to provide a quasi-vertical power device, aiming to solve the problem of reverse recovery loss in traditional quasi-vertical MOSFETs due to the provision of an intrinsic body diode.

[0006] A first aspect of an embodiment of the present application provides a quasi-vertical power device, comprising:

[0007] substrate;

[0008] A buffer layer, a gallium nitride highly doped N+ layer, a gallium nitride low doped N- layer, a gallium nitride P-type substrate and a gallium nitride N-type active region are sequentially stacked on the substrate along a first direction;

[0009] A first mesa region and a second mesa region are further provided on a side of the GaN high-doped N+ layer facing the GaN low-doped N- layer, formed by etching. The first mesa region and the second mesa region are provided at two ends of the GaN N-type active region along a second direction, and the first direction intersects the second direction.

[0010] a first recess and a second recess arranged side by side along the second direction, the first recess and the second recess penetrating the gallium nitride N-type active region and the gallium nitride P-type substrate and extending to the gallium nitride low-doped N-layer;

[0011] an insulating layer arranged on surfaces of the first recess and the second recess;

[0012] an ohmic contact metal and a Schottky contact metal arranged on a surface of the insulating layer, the ohmic contact metal being arranged in the first recess, and the Schottky contact metal being arranged in the second recess, wherein a portion of the Schottky contact metal at a bottom of the recess is in direct contact with the gallium nitride low-doped N-layer;

[0013] two drain electrodes arranged on the first mesa region and the second mesa region respectively;

[0014] two source electrodes arranged on a surface of the gallium nitride N-type active region respectively, the two source electrodes being arranged at two ends of the gallium nitride N-type active region along the second direction.

[0015] Optionally, the gallium nitride low-doped N-layer, the gallium nitride P-type substrate and the gallium nitride N-type active region are aligned at two ends along the second direction, and along the second direction, a size of the first mesa region is equal to a size of the second mesa region.

[0016] Optionally, the insulating layer is a SiO2 insulating layer formed by deposition.

[0017] Optionally, the ohmic contact metal is a Cr / Au double-layer metal film, and the Schottky contact metal is a Ni / Au double-layer metal film.

[0018] Optionally, the first recess and the second recess are V-shaped recesses.

[0019] Optionally, the gallium nitride N-type active region is provided with a third mesa region between the first recess and the second recess, and the third mesa region is provided with the insulating layer.

[0020] A second aspect of the embodiment of the application provides a manufacturing method of a quasi-vertical power device, comprising:

[0021] forming, on a substrate, a buffer layer, a gallium nitride high-doped N+ layer, a gallium nitride low-doped N-layer, a gallium nitride P-type substrate and a gallium nitride N-type active region in sequence along a first direction;

[0022] Etching a first mesa region and a second mesa region on a side of the GaN high-doped N+ layer facing the GaN low-doped N- layer, wherein the first mesa region and the second mesa region are arranged at two ends of the GaN N-type active region along a second direction, and the first direction intersects the second direction;

[0023] Etching a first groove and a second groove side by side along the second direction, wherein the first groove and the second groove penetrate the gallium nitride N-type active area and the gallium nitride P-type substrate and extend to the gallium nitride low-doped N-layer;

[0024] Depositing an insulating layer on the surfaces of the first groove and the second groove;

[0025] forming an ohmic contact metal and a Schottky contact metal on the surface of the insulating layer, wherein the ohmic contact metal is located in the first groove, and the Schottky contact metal is located in the second groove, wherein a portion of the Schottky contact metal located at the bottom of the groove is in direct contact with the gallium nitride low-doped N-layer;

[0026] Two drain electrodes are deposited on the first mesa region and the second mesa region respectively, and two source electrodes are deposited on the surface of the gallium nitride N-type active region respectively. The two source electrodes are arranged at both ends of the gallium nitride N-type active region along the second direction.

[0027] Optionally, the gallium nitride low-doped N-layer, the gallium nitride P-type substrate and the gallium nitride N-type active area are aligned at both ends along the second direction, and along the second direction, a size of the first mesa region is equal to a size of the second mesa region.

[0028] Optionally, the gallium nitride N-type active region is provided with a third mesa region between the first groove and the second groove, and the method for manufacturing the quasi-vertical power device further includes:

[0029] The insulating layer is deposited and formed in the third mesa region.

[0030] A third aspect of the embodiments of the present application provides a chip comprising at least one quasi-vertical power device as described above.

[0031] The beneficial effects of the embodiments of the present application compared with the prior art are as follows: the above-mentioned quasi-vertical power device is provided with two grooves and ohmic contact metal and Schottky contact metal are provided respectively to perform ohmic contact and Schottky contact, thereby equivalently forming a quasi-vertical MOSFET and a Schottky barrier diode respectively. The quasi-vertical MOSFET and the Schottky barrier diode are integrated in parallel, which reduces the reverse recovery loss, improves the reverse recovery speed, has faster switching characteristics, and can be used in high-frequency occasions, such as buck / boost converters, voltage source inverters, and resonant converters. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A schematic cross-sectional view of a quasi-vertical power device according to an embodiment of the present application;

[0033] Figure 2 Schematic diagram of an equivalent circuit of a quasi-vertical power device provided in an embodiment of the present application;

[0034] Figure 3 A schematic flow chart of a method for manufacturing a quasi-vertical power device provided in an embodiment of the present application;

[0035] Figure 4 for Figure 3 A schematic cross-sectional structure diagram of a quasi-vertical power device corresponding to step S11 in the method for manufacturing a quasi-vertical power device is shown;

[0036] Figure 5 for Figure 3 A schematic cross-sectional structure diagram of a quasi-vertical power device corresponding to step S12 in the method for manufacturing a quasi-vertical power device is shown;

[0037] Figure 6 for Figure 3 A schematic cross-sectional structure diagram of a quasi-vertical power device corresponding to step S13 in the method for manufacturing a quasi-vertical power device is shown;

[0038] Figure 7 for Figure 3 A schematic cross-sectional structure diagram of a quasi-vertical power device corresponding to step S14 in the method for manufacturing a quasi-vertical power device is shown;

[0039] Figure 8 for Figure 3 FIG. 1 is a schematic diagram of the cross-sectional structure of a quasi-vertical power device corresponding to step S15 in the method for manufacturing the quasi-vertical power device. DETAILED DESCRIPTION

[0040] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clearly understood, this application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0041] It should be understood that the terms "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0042] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. Throughout the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0043] The first aspect of the embodiment of the present application provides a quasi-vertical power device, such as Figure 1 As shown, Figure 1 This is a schematic diagram of the cross-sectional structure of a quasi-vertical power device provided in an embodiment of the present application. In this embodiment, the quasi-vertical power device includes a substrate 11, a buffer layer 12, a highly doped gallium nitride N+ layer 13, a low-doped gallium nitride N- layer 14, a gallium nitride P-type substrate 15, and a gallium nitride N-type active region 16 stacked in sequence along a first direction X on the substrate 11, wherein the highly doped gallium nitride N+ layer 13 constitutes a drain region, the low-doped gallium nitride N- layer 14 constitutes a drift region, the highly doped gallium nitride N+ layer 13 is grown on the buffer layer 12, and the low-doped gallium nitride N- layer 14, the gallium nitride P-type substrate 15, and the gallium nitride N-type active region 16 are formed by epitaxial growth on the highly doped gallium nitride N+ layer 13.

[0044] The substrate 11 may be a crystalline silicon substrate 11. Alternatively, the substrate 11 may be formed of other semiconductor materials, such as silicon germanium. In addition, the substrate 11 may be a bulk substrate 11. The substrate 11 may be lightly doped with p-type impurities, such as boron or indium.

[0045] Among them, by etching the two ends of the gallium nitride low-doped N-layer 14, the gallium nitride P-type substrate 15 and the gallium nitride N-type active area 16, a first mesa region 21 and a second mesa region 22 formed by etching are further provided on the side of the gallium nitride high-doped N+ layer 13 facing the gallium nitride low-doped N-layer 14. The first mesa region 21 and the second mesa region 22 are arranged at the two ends of the gallium nitride N-type active area 16 along the second direction Y, and the first direction X and the second direction Y intersect. The quasi-vertical power device also includes two drain electrodes 61 and 62 respectively arranged on the first mesa region 21 and the second mesa region 22. The two drain electrodes 61 and 62 are arranged opposite to each other and are connected to an external module through wiring to transmit power signals.

[0046] At the same time, after etching the first mesa region 21 and the second mesa region 22, the gallium nitride low-doped N-layer 14, the gallium nitride P-type substrate 15 and the gallium nitride N-type active region 16 are further etched by etching to form a first groove 31 and a second groove 32 arranged side by side along the second direction Y, wherein the first groove 31 and the second groove 32 penetrate the gallium nitride N-type active region 16 and the gallium nitride P-type substrate 15 and extend to the gallium nitride low-doped N-layer 14. The first groove 31 and the second groove 32 can be set as vertical grooves, V-shaped grooves or grooves of other shapes. The specific shape is not limited. Optionally, in order to simplify the manufacturing process, the first groove 31 and the second groove 32 are V-shaped grooves, and the MOSFET channel is formed within the V-shaped groove. The current flows in the plane of the V-shaped groove along the path in the V shape.

[0047] At the same time, an insulating layer 40 is deposited on the surface of the first groove 31 and the second groove 32, wherein the insulating layer 40 is deposited on the bottom and sidewalls of the first groove 31, the insulating layer 40 is deposited on the sidewalls of the second groove 32, and the insulating layer 40 is not deposited on the bottom of the second groove 32. The insulating layer 40 can be an insulating material of corresponding material. Optionally, the insulating layer 40 is a SiO2 insulating layer 40 formed by deposition. The silicon oxide (SiO2) insulating layer 40 is often used as the insulating layer 40 and forms an insulator.

[0048] In order to form a quasi-vertical MOSFET and a Schottky barrier diode, an ohmic contact metal 51 and a Schottky contact metal 52 are further provided on the surface of the insulating layer 40 of the quasi-vertical power device. The ohmic contact metal 51 is used for ohmic contact, and the Schottky contact metal 52 is used for Schottky contact. The ohmic contact metal 51 is located in the first groove 31, and the Schottky contact metal 52 is located in the second groove 32. The portion of the Schottky contact metal 52 located at the bottom of the groove is in direct contact with the gallium nitride low-doped N-layer 14. The gallium nitride N-type active region 16, the gallium nitride P-type substrate 15, the gallium nitride low-doped N-layer 14 and the nitride are directly connected. The gallium-doped N+ layer 13 constitutes a quasi-vertical MOSFET, the gallium nitride low-doped N- layer 14 and the gallium nitride high-doped N+ layer 13 constitute a Schottky barrier diode. At the same time, the quasi-vertical power device also includes two source electrodes 71 and 72 respectively arranged on the surface of the gallium nitride N-type active region 16. The two source electrodes 71 and 72 are arranged at both ends of the gallium nitride N-type active region 16 along the second direction Y. The ohmic contact metal 51, the drain electrodes 61 and 62, and the source electrodes 71 and 72 respectively constitute the gate terminal, drain terminal, and source terminal of the quasi-vertical MOSFET, and input and output corresponding power supply signals and control signals, thereby forming Figure 2 The equivalent circuit shown in FIG1 , where Q1 represents a quasi-vertical MOSFET and D1 represents a Schottky barrier diode.

[0049] By monolithically integrating a quasi-vertical MOSFET and a Schottky barrier diode, reverse recovery losses are reduced, reverse recovery speed is improved, and faster switching characteristics are achieved. This allows for use in high-frequency applications such as buck / boost converters, voltage source inverters, and resonant converters. Furthermore, it reduces chip footprint, effectively minimizing parasitic effects and simplifying chip packaging.

[0050] Among them, in order to ensure that the two ends of the quasi-vertical MOSFET have the same electrical effect and achieve current balance, optionally, the gallium nitride low-doped N-layer 14, the gallium nitride P-type substrate 15 and the gallium nitride N-type active area 16 are aligned at both ends along the second direction Y. Along the second direction Y, the size of the first mesa area 21 is equal to the size of the second mesa area 22, that is, the center line of the gallium nitride low-doped N-layer 14, the gallium nitride P-type substrate 15 and the gallium nitride N-type active area 16 is on the same line as the center line of the gallium nitride high-doped N+ layer 13, and the two ends are symmetrical. The two ends of the quasi-vertical MOSFET have the same electrical effect and achieve current balance.

[0051] The ohmic contact metal 51 and the Schottky contact metal 52 can be optionally implemented using corresponding single-layer or multi-layer metal films. For example, a four-layer metal film of Cr / Au / Ni / Au is used to prepare the gallium nitride contact. Optionally, in order to simplify the process, the ohmic contact metal 51 is a double-layer metal film of Cr / Au, and the Schottky contact metal 52 is a double-layer metal film of Ni / Au.

[0052] To further simplify the process, when setting the insulating layer 40, deposition is performed directly on the two grooves. That is, the gallium nitride N-type active area 16 is provided with a third mesa region 23 between the first groove 31 and the second groove 32. The third mesa region 23 is provided with an insulating layer 40. There is no need to deposit each groove separately, which simplifies the manufacturing process. Before setting the Schottky contact metal 52, the insulating layer 40 at the bottom of the second groove 32 is removed by etching, thereby achieving direct contact between the Schottky contact metal 52 and the gallium nitride low-doped N-layer 14.

[0053] The beneficial effects of the embodiments of the present application compared with the prior art are as follows: the above-mentioned quasi-vertical power device is provided with two grooves and respectively provided with an ohmic contact metal 51 and a Schottky contact metal 52 to perform ohmic contact and Schottky contact, respectively forming a quasi-vertical MOSFET and a Schottky barrier diode. The quasi-vertical MOSFET and the Schottky barrier diode are integrated in parallel, which reduces the reverse recovery loss, improves the reverse recovery speed, has faster switching characteristics, and can be used in high-frequency occasions, such as buck / boost converters, voltage source inverters and resonant converters.

[0054] The second aspect of the embodiment of the present application proposes a method for manufacturing a quasi-vertical power device, such as Figure 3As shown, the production method includes the following steps:

[0055] S11, a buffer layer 12, a gallium nitride high-doped N+ layer 13, a gallium nitride low-doped N- layer 14, a gallium nitride P-type substrate 15 and a gallium nitride N-type active region 16 are sequentially grown on the substrate 11 along a first direction X, wherein Figure 4 As shown, the GaN highly doped N+ layer 13 constitutes a drain region, the GaN low doped N- layer 14 constitutes a drift region, the GaN highly doped N+ layer 13 is grown on the buffer layer 12, and the GaN low doped N- layer 14, the GaN P-type substrate 15 and the GaN N-type active region 16 are epitaxially grown on the GaN highly doped N+ layer 13.

[0056] The substrate 11 may be a crystalline silicon substrate 11. Alternatively, the substrate 11 may be formed of other semiconductor materials, such as silicon germanium. In addition, the substrate 11 may be a bulk substrate 11. The substrate 11 may be lightly doped with p-type impurities, such as boron or indium.

[0057] S12, etching the two ends of the gallium nitride low-doped N-layer 14, the gallium nitride P-type substrate 15 and the gallium nitride N-type active region 16, as shown in FIG. Figure 5 As shown, a first mesa region 21 and a second mesa region 22 are etched on the side of the gallium nitride high-doped N+ layer 13 facing the gallium nitride low-doped N- layer 14. The first mesa region 21 and the second mesa region 22 are arranged at both ends of the gallium nitride N-type active region 16 along the second direction Y. The first direction X and the second direction Y intersect. The first mesa region 21 and the second mesa region 22 are used to set two drain electrodes 61 and 62. The two drain electrodes 61 and 62 are arranged opposite to each other and are connected to an external module through wiring to transmit power signals.

[0058] S13, after etching the first mesa region 21 and the second mesa region 22, further etching the gallium nitride low-doped N-layer 14, the gallium nitride P-type substrate 15 and the gallium nitride N-type active region 16 by etching, as shown in FIG. Figure 6 As shown, a first groove 31 and a second groove 32 are etched side by side along the second direction Y, wherein the first groove 31 and the second groove 32 penetrate the gallium nitride N-type active area 16 and the gallium nitride P-type substrate 15 and extend to the gallium nitride low-doped N-layer 14. The first groove 31 and the second groove 32 can be set as vertical grooves, V-shaped grooves or grooves of other shapes. The specific shape is not limited. Optionally, in order to simplify the manufacturing process, the first groove 31 and the second groove 32 are V-shaped grooves. The MOSFET channel is formed within the V-shaped groove, and the current flows within the plane of the V-shaped groove along the path in the V shape.

[0059] S14, forming an insulating layer 40 by deposition on the surface of the first groove 31 and the second groove 32, wherein Figure 7As shown, an insulating layer 40 is deposited on the bottom and sidewalls of the first groove 31, an insulating layer 40 is deposited on the sidewalls of the second groove 32, and no insulating layer 40 is deposited on the bottom of the second groove 32. The insulating layer 40 can be an insulating material of corresponding material. Optionally, the insulating layer 40 is a SiO2 insulating layer 40 formed by deposition. The silicon oxide (SiO2) insulating layer 40 is often used as an insulating layer 40 and forms an insulator.

[0060] S15, in order to form a quasi-vertical MOSFET and a Schottky barrier diode, such as Figure 8 As shown, an ohmic contact metal 51 and a Schottky contact metal 52 are formed on the surface of the insulating layer 40. The ohmic contact metal 51 is used for ohmic contact, and the Schottky contact metal 52 is used for Schottky contact. The ohmic contact metal 51 is located in the first groove 31, and the Schottky contact metal 52 is located in the second groove 32. Part of the Schottky contact metal 52 located at the bottom of the groove is in direct contact with the gallium nitride low-doped N-layer 14. The gallium nitride N-type active region 16, the gallium nitride P-type substrate 15, the gallium nitride low-doped N-layer 14 and the gallium nitride highly-doped N+ layer 13 constitute a quasi-vertical MOSFET, and the gallium nitride low-doped N-layer 14 and the gallium nitride highly-doped N+ layer 13 constitute a Schottky barrier diode.

[0061] S16, such as Figure 1 As shown, two drain electrodes 61 and 62 are deposited on the first mesa region 21 and the second mesa region 22, respectively, and two source electrodes 71 and 72 are deposited on the surface of the gallium nitride N-type active region 16, respectively. The two source electrodes 71 and 72 are arranged at both ends of the gallium nitride N-type active region 16 along the second direction Y. The ohmic contact metal 51, the drain electrodes 61 and 62, and the source electrodes 71 and 72 respectively constitute the gate terminal, drain terminal, and source terminal of the quasi-vertical MOSFET, and input and output corresponding power supply signals and control signals, thereby forming Figure 2 The equivalent circuit shown in FIG1 , where Q1 represents a quasi-vertical MOSFET and D1 represents a Schottky barrier diode.

[0062] By monolithically integrating a quasi-vertical MOSFET and a Schottky barrier diode, reverse recovery losses are reduced, reverse recovery speed is improved, and faster switching characteristics are achieved. This allows for use in high-frequency applications such as buck / boost converters, voltage source inverters, and resonant converters. Furthermore, it reduces chip footprint, effectively minimizing parasitic effects and simplifying chip packaging.

[0063] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0064] Among them, in order to ensure that the two ends of the quasi-vertical MOSFET have the same electrical effect and achieve current balance, optionally, the gallium nitride low-doped N-layer 14, the gallium nitride P-type substrate 15 and the gallium nitride N-type active area 16 are aligned at both ends along the second direction Y. Along the second direction Y, the size of the first mesa area 21 is equal to the size of the second mesa area 22, that is, the center line of the gallium nitride low-doped N-layer 14, the gallium nitride P-type substrate 15 and the gallium nitride N-type active area 16 is on the same line as the center line of the gallium nitride high-doped N+ layer 13, and the two ends are symmetrical. The two ends of the quasi-vertical MOSFET have the same electrical effect and achieve current balance.

[0065] The ohmic contact metal 51 and the Schottky contact metal 52 can be optionally implemented using corresponding single-layer or multi-layer metal films. For example, a four-layer metal film of Cr / Au / Ni / Au is used to prepare the gallium nitride contact. Optionally, in order to simplify the process, the ohmic contact metal 51 is a double-layer metal film of Cr / Au, and the Schottky contact metal 52 is a double-layer metal film of Ni / Au.

[0066] To further simplify the process, optionally, the gallium nitride N-type active region 16 is provided with a third mesa region 23 between the first groove 31 and the second groove 32 . The method for manufacturing the quasi-vertical power device further includes:

[0067] An insulating layer 40 is deposited and formed in the third mesa region 23 .

[0068] In this embodiment, when providing the insulating layer 40, deposition is performed directly on the two grooves, that is, the gallium nitride N-type active area 16 is provided with a third mesa region 23 between the first groove 31 and the second groove 32, and the third mesa region 23 is provided with an insulating layer 40. There is no need to deposit each groove separately, which simplifies the manufacturing process. Before providing the Schottky contact metal 52, the insulating layer 40 at the bottom of the second groove 32 is removed by etching, thereby achieving direct contact between the Schottky contact metal 52 and the gallium nitride low-doped N-layer 14.

[0069] The present application also proposes a chip, which includes a quasi-vertical power device. The specific structure of the quasi-vertical power device refers to the above-mentioned embodiment. Since this chip adopts all the technical solutions of all the above-mentioned embodiments, it has at least all the beneficial effects brought by the technical solutions of the above-mentioned embodiments, which will not be repeated here.

[0070] The above-described embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present application, and should all be included in the scope of protection of the present application.

Claims

1. A quasi-vertical power device, characterized in that: include: substrate; A buffer layer, a gallium nitride highly doped N+ layer, a gallium nitride low doped N- layer, a gallium nitride P-type substrate and a gallium nitride N-type active region are sequentially stacked on the substrate along a first direction; A first mesa region and a second mesa region are further provided on a side of the GaN high-doped N+ layer facing the GaN low-doped N- layer, formed by etching. The first mesa region and the second mesa region are provided at two ends of the GaN N-type active region along a second direction, and the first direction intersects the second direction. a first groove and a second groove arranged side by side along the second direction, the first groove and the second groove penetrating the gallium nitride N-type active region and the gallium nitride P-type substrate and extending to the gallium nitride low-doped N-layer; an insulating layer disposed on surfaces of the first groove and the second groove; an ohmic contact metal and a Schottky contact metal disposed on the surface of the insulating layer, wherein the ohmic contact metal is located in the first groove, and the Schottky contact metal is located in the second groove, wherein a portion of the Schottky contact metal located at the bottom of the groove is in direct contact with the gallium nitride low-doped N-layer; two drain electrodes respectively disposed on the first mesa region and the second mesa region; Two source electrodes are respectively arranged on the surface of the gallium nitride N-type active region, and the two source electrodes are arranged at two ends of the gallium nitride N-type active region along the second direction.

2. The quasi-vertical power device according to claim 1, wherein: The gallium nitride low-doped N-layer, the gallium nitride P-type substrate and the gallium nitride N-type active area are aligned at both ends along the second direction. Along the second direction, the size of the first mesa region is equal to the size of the second mesa region.

3. The quasi-vertical power device according to claim 1, wherein: The insulating layer is a SiO2 insulating layer formed by deposition.

4. The quasi-vertical power device according to claim 1, wherein: The ohmic contact metal is a Cr / Au double-layer metal film, and the Schottky contact metal is a Ni / Au double-layer metal film.

5. The quasi-vertical power device according to claim 1, wherein: The first groove and the second groove are V-shaped grooves.

6. The quasi-vertical power device according to claim 1, wherein: The gallium nitride N-type active region is provided with a third mesa region between the first groove and the second groove, and the third mesa region is provided with the insulating layer.

7. A method for manufacturing a quasi-vertical power device, characterized in that: include: A buffer layer, a gallium nitride highly doped N+ layer, a gallium nitride low doped N- layer, a gallium nitride P-type substrate and a gallium nitride N-type active region are sequentially grown on the substrate along a first direction; Etching a first mesa region and a second mesa region on a side of the GaN high-doped N+ layer facing the GaN low-doped N- layer, wherein the first mesa region and the second mesa region are arranged at two ends of the GaN N-type active region along a second direction, and the first direction intersects the second direction; Etching a first groove and a second groove side by side along the second direction, wherein the first groove and the second groove penetrate the gallium nitride N-type active area and the gallium nitride P-type substrate and extend to the gallium nitride low-doped N-layer; Depositing an insulating layer on the surfaces of the first groove and the second groove; forming an ohmic contact metal and a Schottky contact metal on the surface of the insulating layer, wherein the ohmic contact metal is located in the first groove, and the Schottky contact metal is located in the second groove, wherein a portion of the Schottky contact metal located at the bottom of the groove is in direct contact with the gallium nitride low-doped N-layer; Two drain electrodes are deposited on the first mesa region and the second mesa region respectively, and two source electrodes are deposited on the surface of the gallium nitride N-type active region respectively. The two source electrodes are arranged at both ends of the gallium nitride N-type active region along the second direction.

8. The method for manufacturing a quasi-vertical power device according to claim 7, wherein: The gallium nitride low-doped N-layer, the gallium nitride P-type substrate and the gallium nitride N-type active area are aligned at both ends along the second direction. Along the second direction, the size of the first mesa region is equal to the size of the second mesa region.

9. The method for manufacturing a quasi-vertical power device according to claim 7, wherein: The gallium nitride N-type active region is provided with a third mesa region between the first groove and the second groove. The method for manufacturing the quasi-vertical power device further includes: The insulating layer is deposited and formed in the third mesa region.

10. A chip, characterized in that: The device comprises at least one quasi-vertical power device according to any one of claims 1 to 6.

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