Semiconductor element and method for manufacturing the same

Abstract

A semiconductor device and a method of fabricating the same are disclosed. The method of fabricating the semiconductor device includes forming a fin structure on a substrate, forming a first gate structure and a second gate structure on the fin structure and an interlayer dielectric layer surrounding the first gate structure and the second gate structure, converting the first gate structure and the second gate structure into a first metal gate and a second metal gate, forming a hard mask on the first metal gate and the second metal gate, removing a portion of the hard mask, the second metal gate, and a portion of the fin structure to form an opening, and forming a dielectric layer in the opening to form a single diffusion isolation structure.

Description

[0001] This application is a divisional application of a Chinese patent application with the application number 201711262580.1 and the application date of 04 / 12 / 2017 for a semiconductor device and its manufacturing method. TECHNICAL FIELD

[0002] The present application relates to a method for manufacturing a semiconductor device, and in particular, to a method for separating a fin structure to form a single diffusion break (SDB) structure. BACKGROUND

[0003] In recent years, as the size of field effect transistors (FETs) continues to shrink, the development of existing planar FETs has reached the limit of manufacturing processes. In order to overcome the process limitations, non-planar FETs, such as fin field effect transistors (Fin FETs), have become the mainstream development trend to replace planar transistors. Because the three-dimensional structure of the fin FET can increase the contact area between the gate and the fin structure, it can further increase the control of the gate on the carrier channel region, thereby reducing the drain-induced barrier lowering (DIBL) effect faced by small-size devices and suppressing the short channel effect (SCE). Furthermore, the fin FET has a wider channel width under the same gate length, so it can double the drain drive current. Even the threshold voltage of the transistor can be adjusted by adjusting the work function of the gate.

[0004] In the current fin FET manufacturing process, after forming a shallow trench isolation around the fin structure, part of the fin structure and the shallow trench isolation are usually removed by etching to form a recess, and then the recess is filled with an insulating material to form a single diffusion break structure and separate the fin structure into two parts. However, there are still many problems in the current manufacturing process of the single diffusion break structure and the metal gate, so how to improve the existing fin FET manufacturing process and architecture is an important issue. SUMMARY

[0005] A method for fabricating a semiconductor device is disclosed. A fin structure is formed on a substrate. A first gate structure and a second gate structure are formed on the fin structure and an interlayer dielectric layer surrounds the first gate structure and the second gate structure. The first gate structure and the second gate structure are converted into a first metal gate and a second metal gate. A hard mask is formed on the first metal gate and the second metal gate. Part of the hard mask, the second metal gate and part of the fin structure are removed to form an opening. A dielectric layer is formed in the opening to form a single diffusion isolation structure.

[0006] A semiconductor device is disclosed. The semiconductor device includes a fin structure on a substrate, a gate structure on the fin structure, an interlayer dielectric layer surrounding the gate structure, and a single diffusion isolation structure in the interlayer dielectric layer and the fin structure. The single diffusion isolation structure includes a lower half and an upper half on the lower half. The upper half and the lower half have different widths. BRIEF DESCRIPTION OF DRAWINGS

[0007] Figure 1 A top view of a semiconductor device according to an embodiment of the present invention;

[0008] Figure 2 A cross-sectional view along the cutting line AA' of the semiconductor device according to an embodiment of the present invention; Figure 1

[0009] A cross-sectional view along the cutting line AA' of the semiconductor device according to an embodiment of the present invention; Figures 3 to 10 A cross-sectional view along the cutting line AA' of the semiconductor device according to an embodiment of the present invention; Figure 2 A method for fabricating a semiconductor device according to an embodiment of the present invention;

[0010] Figure 11 A structure of a semiconductor device according to an embodiment of the present invention.

[0011] LIST OF MAJOR ELEMENTS

[0012] 12 substrate 14 fin structure

[0013] 16 shallow trench isolation 18 gate structure

[0014] 20 gate structure 22 gate structure

[0015] 24 gate structure 26 gate dielectric layer

[0016] 28 gate material layer 30 spacer

[0017] 32 source / drain region 34 epitaxial layer

[0018] 36 contact hole etch stop layer 38 interlayer dielectric layer

[0019] 40 dielectric layer 42 high dielectric constant dielectric layer

[0020] 44 Work function metal layer 46 Low impedance metal layer

[0021] 48 Metal gate 50 Metal gate

[0022] 52 Metal gate 54 Metal gate

[0023] 56 Groove 58 Hard Mask

[0024] 60 Patterned photoresist 62 Opening

[0025] 64 Opening 66 Opening

[0026] 68 Padding layer 70 Dielectric layer

[0027] 72 Single-diffusion isolation structure; 74 Pores

[0028] 76 Lower Half 78 Upper Half Detailed Implementation

[0029] Please refer to Figures 1 to 10 ,in Figure 1 A top view of a semiconductor device according to an embodiment of the present invention. Figure 2 for Figure 1 A schematic diagram of a cross-section along the tangent AA'. Figures 3 to 10 This is a continuation. Figure 2 A schematic diagram illustrating a method for fabricating a semiconductor device. (Example) Figures 1 to 2 As shown, a substrate 12 is first provided, such as a silicon substrate or a silicon-on-insulator (SOI) substrate. Then, a plurality of fin structures 14 are formed on the substrate 12. In this embodiment, four fin structures 14 are provided on the substrate 12 as an example, but the number of fin structures can be adjusted arbitrarily according to product requirements and is not limited to this.

[0030] According to a preferred embodiment of the present invention, the fin structure 14 is preferably fabricated using techniques such as sidewall image transfer (SIT). The process generally includes: providing a layout pattern to a computer system and performing appropriate calculations to define the corresponding pattern in a photomask. Subsequently, multiple equidistant and equally wide patterned sacrificial layers are formed on the substrate using photolithography and etching processes, giving each layer a strip-like appearance. Then, deposition and etching processes are sequentially performed to form spacers on the sidewalls of the patterned sacrificial layers. The patterned sacrificial layers are then removed, and etching is performed under the cover of the spacers, transferring the pattern formed by the spacers into the substrate. Finally, a fin cut process is performed to obtain the desired patterned structure, such as a strip-shaped patterned fin structure.

[0031] In addition, the fin structure 14 can be formed by first forming a patterned mask (not shown) on the substrate 12, and then performing an etching process to transfer the pattern of the patterned mask to the substrate 12 to form the fin structure 14. Alternatively, the fin structure 14 can be formed by first forming a patterned hard mask layer (not shown) on the substrate 12, and then performing an epitaxial process to grow a semiconductor layer, such as a silicon germanium layer, on the substrate 12 exposed by the patterned hard mask layer, which can serve as the corresponding fin structure 14. These embodiments of forming the fin structure 14 are all within the scope of the present application.

[0032] A shallow trench isolation (STI) 16 is then formed around the fin structure 14. In this embodiment, the STI 16 can be formed by first forming a silicon oxide layer on the substrate 12 and completely covering the fin structure 14 using a flowable chemical vapor deposition (FCVD) process. Then, a chemical mechanical polishing (CMP) process is performed in combination with an etching process to remove part of the silicon oxide layer, so that the remaining silicon oxide layer is lower than the surface of the fin structure 14 to form the STI 16.

[0033] A gate structure 18, 20, 22, 24 or a dummy gate is then formed on the fin structure 14. In this embodiment, the gate structure 18, 20, 22, 24 can be formed by a gate first process, a high-k first process of a gate last process, or a high-k last process of a gate last process, depending on the process requirements. For example, in the high-k last process of a gate last process, a gate dielectric layer or a dielectric layer, a gate material layer composed of polysilicon, and a selective hard mask are sequentially formed on the substrate 12, and a patterned photoresist (not shown) is used as a mask to perform a pattern transfer process by a single etching or a sequential etching step to remove part of the gate material layer and part of the gate dielectric layer, and then the patterned photoresist is removed to form the gate structure 18, 20, 22, 24 on the fin structure 14, each of which is composed of a patterned gate dielectric layer 26 and a patterned gate material layer 28.

[0034] Then, at least one spacer wall 30 is formed on the sidewalls of gate structures 18, 20, 22, and 24, respectively. Next, source / drain regions 32 and / or epitaxial layers 34 are formed in the fin structures 14 and / or the substrate 12 on both sides of the spacer wall 30, and a metal silicide (not shown) is selectively formed on the surface of the source / drain regions 32 and / or the epitaxial layers 34. In this embodiment, the spacer wall 30 can be a single spacer wall or a composite spacer wall, for example, it may include a bias spacer wall and a main spacer wall. The bias spacer wall and the main spacer wall may contain the same or different materials, and both can be selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide nitride. The source / drain regions 32 may contain different dopants depending on the conductivity type of the transistor being disposed, for example, they may contain P-type dopants or N-type dopants.

[0035] Next, a contact hole etch stop layer 36 is formed and covers the surfaces of gate structures 18, 20, 22, 24 and shallow trench isolation 16. Then, an interlayer dielectric layer 38 is formed on the contact hole etch stop layer 36. Then, a planarization process is performed, for example, by using chemical mechanical polishing (CMP) to remove part of the interlayer dielectric layer 38 and part of the contact hole etch stop layer 36 and expose the gate material layer 28 made of polysilicon, so that the upper surface of the gate material layer 28 is flush with the upper surface of the interlayer dielectric layer 38.

[0036] like Figure 3 As shown, a metal gate replacement fabrication process is then performed to convert gate structures 18, 20, 22, and 24 into metal gates. For example, a selective dry or wet etching process can be performed first, such as using an etching solution such as ammonia hydroxide (NH4OH) or tetramethylammonium hydroxide (TMAH) to remove the gate material layer 28 and even the gate dielectric layer 26 in gate structures 18, 20, 22, and 24, so as to form a groove (not shown) in the interlayer dielectric layer 38.

[0037] A selective dielectric layer 40 or gate dielectric layer, a high-k dielectric layer 42, a work function metal layer 44, and a low impedance metal layer 46 are then formed in the recesses, followed by a planarization process, such as CMP, to remove portions of the low impedance metal layer 46, portions of the work function metal layer 44, and portions of the high-k dielectric layer 42 to form metal gates 48, 50, 52, 54. In this embodiment, the gate structures formed by the post high-k dielectric layer fabrication process include a dielectric layer 40 or gate dielectric layer, a U-shaped high-k dielectric layer 42, a U-shaped work function metal layer 44, and a low impedance metal layer 46.

[0038] In this embodiment, the high-k dielectric layer 42 includes a dielectric material having a dielectric constant greater than 4, such as selected from the group consisting of hafnium oxide (Hf02), hafnium silicon oxide (HfSi04), hafnium silicon oxynitride (HfSiON), aluminum oxide (AI2O3), lanthanum oxide (La203), tantalum oxide (Ta205), yttrium oxide (Y203), zirconium oxide (Zr02), strontium titanate oxide (SrTi03), zirconium silicon oxide (ZrSi04), hafnium zirconium oxide (HfZr04), strontium bismuth tantalate (SrBi2Ta20g, SBT), lead zirconate titanate (PbZrTi03, PZT), barium strontium titanate (BaSrTi03, BST), or combinations thereof. x Ti 1-x O3, PZT), barium strontium titanate (Ba x Sr 1- x TiO3, BST), or combinations thereof.

[0039] The work function metal layer 44 is preferably used to adjust the work function of the metal gate to be suitable for either an N-type transistor (NMOS) or a P-type transistor (PMOS). If the transistor is an N-type transistor, the work function metal layer 44 can be selected from a metal material having a work function of 3.9 electron volts (eV) to 4.3 eV, such as titanium aluminum (TiAl), zirconium aluminum (ZrAl), tungsten aluminum (WAl), tantalum aluminum (TaAl), hafnium aluminum (HfAl), or TiAlC (titanium aluminum carbide), but is not limited thereto. If the transistor is a P-type transistor, the work function metal layer 44 can be selected from a metal material having a work function of 4.8 eV to 5.2 eV, such as titanium nitride (TiN), tantalum nitride (TaN), or tantalum carbide (TaC), but is not limited thereto. Another barrier layer (not shown) can be included between the work function metal layer 44 and the low impedance metal layer 46, wherein the barrier layer can be made of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or the like. The low impedance metal layer 46 can be selected from a low resistance material such as copper (Cu), aluminum (Al), tungsten (W), titanium aluminum (TiAl), cobalt tungsten phosphide (CoWP), or a combination thereof.

[0040] Subsequently, as shown in FIG. 6, an etching process is performed to remove part of the low impedance metal layer 46, part of the work function metal layer 44, and part of the high dielectric constant dielectric layer 42 to form a recess 56. Figure 4

[0041] As shown in FIG. 7, a hard mask 58 is then formed in each recess 56, wherein the hard mask 58 is disposed on top of the contact hole etch stop layer 36 and the interlayer dielectric layer 38 in addition to filling each recess 56. In the present embodiment, the hard mask 58 is preferably made of silicon nitride, but is not limited thereto. Figure 5

[0042] Next, as shown in FIG. 8, a patterned mask, such as a patterned photoresist 60, is formed on the hard mask 58, wherein the patterned photoresist 60 preferably includes an opening 62 exposing part of the surface of the hard mask 58. Figure 6

[0043] As shown in FIG. 9, an etching process, or more specifically one or more etching processes, is then performed using the patterned photoresist 60 as a mask to sequentially remove part of the hard mask 58, part of the contact hole etch stop layer 36, part of the spacer 30, and part of the metal gate 52 to form an opening 64 in the interlayer dielectric layer 38 and the hard mask 58 directly above the metal gate 52, and then the patterned photoresist 60 is removed. In the present embodiment, the etching gas used to remove part of the hard mask 58 preferably includes carbon tetrafluoride (CF4), but is not limited thereto. Figure 7 ​​​​

[0044] like Figure 8 As shown, the remaining metal gate 52 and the fin structure 14 below it are then sequentially removed using a patterned hard mask 58 as a mask for another etching process, or more specifically, one or more etching processes, to form an approximately T-shaped opening 66 at the original location of the metal gate 52 and extend into the fin structure 14. In this embodiment, the etching gas used to remove the remaining metal gate 52 preferably includes sulfur hexafluoride (SF6), but is not limited to this.

[0045] It should be noted that, since the opening is preferably formed by removing the original metal gate 52, the extension direction of the formed opening 66 is preferably the same as the extension direction of the original gate structure 22 or the metal gate 52. In other words, compared to the fin structure 14, Figure 1 As shown, the opening 66 extends along a first direction (e.g., the X direction) and preferably extends along a second direction (e.g., the Y direction) perpendicular to the first direction.

[0046] Subsequently, as Figure 9 As shown, a pad layer 68 and a dielectric layer 70 are sequentially formed on the hard mask 58, filling the opening 66. In this embodiment, the pad layer 68 and the dielectric layer 70 are preferably made of different materials, and both can be selected from the group consisting of silicon oxide and silicon nitride. For example, in one embodiment of the present invention, a pad layer 68 made of silicon nitride and a dielectric layer 70 made of silicon oxide may be sequentially deposited in the opening 66, or a pad layer 68 made of silicon oxide and a dielectric layer 70 made of silicon nitride may be sequentially deposited in the opening 66; these variations are all within the scope of the present invention.

[0047] like Figure 10 As shown, a planarization process is then performed, such as CMP and / or etch-back processes, to remove part of the dielectric layer 70, part of the pad layer 68, and part of the hard mask 58, so that the upper surfaces of the remaining dielectric layer 70 and pad layer 68 are flush with the upper surfaces of the interlayer dielectric layer 38 and the remaining hard mask 58 to form a single-diffusion isolation structure 72. As in the direction extending from the aforementioned opening 66, compared to the fin structure 14... Figure 1 As shown, the monodiffusion isolation structure 72 formed in this stage extends along a first direction (e.g., the X direction) and preferably along a second direction (e.g., the Y direction) perpendicular to the first direction.

[0048] Please continue to refer to Figure 10 , Figure 10 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention. Figure 10As shown, the semiconductor device mainly includes a fin structure 14 disposed on a substrate, a gate structure or metal gates 48, 50, 54 disposed on the fin structure 14, an interlayer dielectric layer 38 surrounding the metal gates 48, 50, 54, a single-diffusion isolation structure 72 disposed in the interlayer dielectric layer 38 and the fin structure 14, a spacer wall 30 surrounding the metal gates 48, 50, 54 and the single-diffusion isolation structure 72, and a contact hole etch stop layer 36 disposed between the spacer walls 30.

[0049] In detail, the single-diffusion isolation structure 72 includes a lower half 76 and an upper half 78 disposed on the lower half 76. The upper half 78 and the lower half 76 have different widths, or more specifically, the width of the upper half 78 is preferably greater than the width of the lower half 76. In addition, the upper half 78 and the lower half 76 each include a padding layer 68 and a dielectric layer 70 disposed on the padding layer 68, and the padding layer 68 and the dielectric layer 70 preferably contain different materials.

[0050] It should be noted that, in this embodiment, the spacer walls 30 surrounding the metal gates 48, 50, 54 and the single-diffusion isolation structure 72 preferably have different heights. For example, the upper surface of the spacer wall 30 surrounding the metal gate 50 is preferably flush with the upper surface of the interlayer dielectric layer 38 and higher than the upper surface of the spacer wall 30 surrounding the single-diffusion isolation structure 72, while the upper surface of the spacer wall 30 surrounding the single-diffusion isolation structure 72 is preferably flush with the lower half 76 and the upper surface of the contact hole etch stop layer 36. In addition, although the contact hole etch stop layer 36 preferably includes a U-shape, in detail, the upper surface of the contact hole etch stop layer 36 located next to the single-diffusion isolation structure 72 is preferably lower than the upper surface of the contact hole etch stop layer 36 next to the metal gate 50.

[0051] Please continue to refer to Figure 11 , Figure 11 This is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention. Figure 11 As shown, the present invention can be used in Figure 10 A planarization process is performed, such as CMP and / or etch-back processes, to remove part of the dielectric layer 70, part of the pad layer 68, and part of the hard mask 58 to form a single-diffusion isolation structure 72, while simultaneously forming a pore 74 within the single-diffusion isolation structure 72. This embodiment is also within the scope of the present invention.

[0052] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall fall within the protection scope of the present invention.

Claims

1. A semiconductor element, characterized in that, Include: Fin-like structures are mounted on a base. A metal gate and an interlayer dielectric layer, wherein the metal gate is disposed on the fin structure and the interlayer dielectric layer surrounds the metal gate; A single-diffusion isolation structure is disposed within the interlayer dielectric layer and the fin structure and directly contacts the interlayer dielectric layer, wherein the single-diffusion isolation structure comprises: The lower half, wherein the upper surface of the lower half is flush with the upper surface of the metal gate; and The upper half is disposed on the lower half, wherein the upper half and the lower half have different widths and the upper surface of the lower half is higher than the upper surface of the fin structure.

2. The semiconductor device of claim 1, further comprising: A first gap wall surrounds the metal gate. A second spacer wall surrounds the mono-diffusion isolation structure; and A contact hole etching stop layer is disposed between the first gap wall and the second gap wall.

3. The semiconductor device of claim 2, wherein the first spacer wall and the second spacer wall have different heights.

4. The semiconductor device of claim 2, wherein the contact hole etch stop layer is U-shaped.

5. The semiconductor device of claim 2, wherein the upper surface of the contact hole etch stop layer next to the second gap wall is lower than the upper surface of the contact hole etch stop layer next to the first gap wall.

6. The semiconductor device of claim 1, wherein the single-diffusion isolation structure comprises: Padding layer; and A dielectric layer is disposed on the pad layer, wherein the pad layer and the dielectric layer contain different materials.

7. The semiconductor device of claim 1, further comprising a pore disposed within the single diffusion isolation structure.

8. The semiconductor device of claim 1, wherein the fin structure extends along a first direction and the monodiffusion isolation structure extends along a second direction.

9. The semiconductor element of claim 8, wherein the first direction is perpendicular to the second direction.

10. A semiconductor element, characterized in that, Include: Fin-like structures are mounted on a base. A metal gate and an interlayer dielectric layer, wherein the metal gate is disposed on the fin structure and the interlayer dielectric layer surrounds the metal gate; A single-diffusion isolation structure is disposed within the interlayer dielectric layer and the fin structure and directly contacts the interlayer dielectric layer, wherein the single-diffusion isolation structure comprises: lower half; as well as The upper half is disposed on the lower half, wherein the upper half and the lower half have different widths and the upper surface of the lower half is higher than the upper surface of the fin structure; as well as An air gap is provided in the single-diffusion isolation structure, wherein the upper surface of the air gap is higher than the upper surface of the metal gate.

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