A primary side feedback converter and a dynamic response optimization method and device thereof

Abstract

The present disclosure provides a primary side feedback converter and a dynamic response optimization method and device thereof. The device comprises a synchronous rectification driver, a synchronous rectification tube and a regulating circuit. The drain of the synchronous rectification tube is connected to the drain voltage input end of the regulating circuit. The source of the synchronous rectification tube is connected to the source voltage input end of the regulating circuit. The drain voltage output end of the regulating circuit is connected to the drain voltage input end of the synchronous rectification driver. The source voltage output end of the regulating circuit is connected to the source voltage input end of the synchronous rectification driver. The drain voltage and the source voltage of the synchronous rectification tube are input into the regulating circuit. The drain voltage and the source voltage are processed by the regulating circuit and output as regulated drain voltage and source voltage. The regulated drain voltage and source voltage are input into the synchronous rectification driver to trigger the synchronous rectification driver to output the driving control signal of the synchronous rectification tube.

Description

Technical Field

[0001] This disclosure relates to the field of voltage converter technology, and in particular to a primary-side feedback converter, and a method and apparatus for optimizing its dynamic response. Background Technology

[0002] Figure 1 The dual-clamp zero-voltage converter shown can achieve buck-boost power conversion. Compared with single-boost or single-buck circuits, it can achieve higher conversion efficiency over a wider voltage range, and its circuit structure is simple. Therefore, it is widely used in power supply fields such as new energy power generation, communications, and military industries. Figure 1 As shown, the converter mainly consists of the primary-side switching transistor S. P1 ~S P4 Power transformer T1 (including magnetizing inductor L) m Equivalent leakage inductance L of the original edge r Clamping capacitor C L Secondary-side synchronous rectifier tube S R1 and output filter capacitor C o Composition. The converter adopts primary-side feedback control, sampling the clamp capacitor voltage V. CL Used to achieve output voltage regulation control, V CL and output voltage reference V ref The difference is amplified by the output voltage regulator (OVR) and then output as a control signal v. err The primary-side drive signal generation unit generates the signal based on the control signal v. err Input voltage V in Midpoint voltage of bridge arm v A and v B When the primary-side switching transistor S is generated P1 ~S P4 drive control signal v GSP1 ~v GSP4 By adjusting S P1 ~S P4 The conduction time and timing relationship are used to achieve closed-loop control; synchronous rectification control is adopted on the secondary side, and the synchronous rectification driver detects the synchronous rectifier S. R1 The drain-source voltage is used to determine zero-voltage turn-on and zero-current turn-off to generate S. R1 drive control signal v GSR1 That is, when the drain-source voltage is lower than the turn-off threshold voltage V th_on At that time, S was opened R1 When the drain-source voltage is higher than the turn-off threshold voltage V th_off When, turn off S R1 .

[0003] Typical operating waveforms of the converter are as follows Figure 2a , 2bAs shown, the converter has mainly three working stages in a switching cycle, including input energy storage stage (t0~t1), power transmission stage (t1~t2) and current clamping stage (t2~t3). In the input energy storage stage (t0~t1), the primary side switch S P1 and S P4 are turned on, the input voltage V in is applied to the primary side of the power transformer T1, and since the leakage inductance L r is much smaller than the magnetizing inductance L m , the magnetizing inductance current i Lm increases linearly with a slope of V in / L m . At t1, S P1 and S P4 are turned off, the input energy storage stage ends, and then the primary side switch S P2 and S P3 and the secondary side synchronous rectifier S R1 are turned on, the converter enters the power transmission stage (t1~t2), the magnetizing inductance L m transfers energy to the load, and the magnetizing inductance current i Lm decreases linearly with a slope of -V CL / L m , since L r is much smaller than L m , there is V CL / n = V o , where n is the ratio of the number of turns of the primary side to the number of turns of the secondary side of the power transformer T1, i.e., the clamping capacitor voltage V CL of the converter is in proportional relationship with the output voltage V o , so the output voltage closed-loop control can be realized by sampling the clamping capacitor voltage V CL , without the need for a signal isolation circuit, which is simple to implement and helps to improve the power density of the converter; meanwhile, the clamping capacitor C L resonates with the leakage inductance L r and absorbs the energy thereof to avoid voltage spikes, since the leakage energy is not transferred to the secondary side, L r is designed to be much smaller than L m , and the resonant frequency of the clamping capacitor C L is much higher than the switching frequency of the converter (the clamping capacitor C L is also required to be relatively small), to realize high-precision output voltage control and high-efficiency power conversion. At t2, the magnetizing inductance current i Lm is zero, S P3 and S R1 are turned off, the power transmission stage ends, and then the primary side switch S P4 is turned on, the converter enters the current clamping stage (t2~t3), the voltage across the primary side of the transformer is zero, and the magnetizing inductance current i Lmremains unchanged, its negative current is supplied by S P3 , S P4 and S R1 The parasitic capacitance and excitation inductance L m of S 2a resonate to produce a Figure 2a t2~t L phase shown in the figure. Figure 2b is the working waveform of the secondary side synchronous rectification.

[0004] According to the above analysis, the clamping capacitor C o has a relatively small capacitance value, while in order to meet the load voltage stability, the output filter capacitor C o is usually very large, so when the load suddenly changes from full load or heavy load to no load, the phenomenon of disconnection between the primary and secondary sides of the converter shown in the figure will occur: the load current step decreases, resulting in an overshoot of the output voltage V CL and the clamping capacitor voltage V o Since the load current suddenly changes to zero and C L is much larger than C L , the decrease in capacitor voltage caused by the discharge of the clamping capacitor C o ( Figure 3 t a ~t b phase) is much faster than that of the output filter capacitor C ref When the clamping capacitor voltage is lower than the reference voltage V Lm , the duration of the input energy storage stage of the converter will be increased and the peak value of the excitation inductance current i L will be increased under the action of the closed-loop control system of the converter, because the primary and secondary sides are disconnected and C CL is small, the excitation inductance energy rapidly charges the clamping capacitor voltage V b ( Figure 3 t CL ~tc phase), and the upper limit value is clamped by the output voltage, and the closed-loop control system of the converter will reduce the duration of the input energy storage stage to reduce the clamping capacitor voltage, and then the clamping capacitor will discharge again and V o will decrease.

[0005] On the one hand, after the primary and secondary sides are disconnected, the output capacitor C o can only discharge slowly, resulting in a long time for the output voltage V L to recover to the closed-loop value, making the dynamic response performance of the converter not optimal. On the other hand, the disconnection of the primary and secondary sides may also cause oscillation of the clamping capacitor voltage, leading to protection and further worsening the dynamic response of the converter. Figure 4a The equivalent circuit of the converter after the primary and secondary sides are disconnected is shown, i.e. the four-switch buck-boost converter in no-load operation, at this time the control object of the closed-loop control system of the converter has changed greatly, and because the clamping capacitor C CLVery small, to meet the fast dynamic response design of high bandwidth closed loop control system parameters very easy to cause the clamping capacitor voltage V CL oscillation and cause protection, the experimental waveform is shown as Figure 4b Therefore, in order to ensure the stable operation of the system, the loop bandwidth of the closed loop system is usually sacrificed, resulting in poorer dynamic response performance of the converter.

[0006] In view of the above problems, the related art adopts the method of increasing the current loop to improve the dynamic response as shown in Figure 5 , which can reduce the voltage overshoot when the full load is cut off, reduce the time of disengagement of the primary and secondary sides and the recovery time of the output voltage by optimizing the dynamic response, but the loop acceleration may cause the clamping capacitor voltage oscillation to be more severe and trigger protection faster. Moreover, the method of increasing the current loop also needs to increase the current sampling circuit, such as the series current transformer of the primary side current sampling transformer, which is large in size, reduces the system power density, and increases the equivalent leakage inductance L r of the primary side of the power transformer T1, thereby reducing the efficiency of the converter and the output voltage control accuracy.

[0007] Another method in the related art can be to connect a suitable dead load in parallel across the output filter capacitor Co, to accelerate the discharge rate of the output filter capacitor after the primary and secondary sides are disengaged, so that the voltage is quickly restored to the closed loop point, reducing the recovery time of the dynamic response, and benefiting from the shortening of the disengagement time, the oscillation of the primary clamping capacitor voltage after disengagement can also be inhibited to a certain extent, but the additional loss caused by the dead load reduces the efficiency of the converter in the full load range. SUMMARY

[0008] The present disclosure provides a primary side feedback converter and a dynamic response optimization method and device thereof to at least solve the above technical problems existing in the prior art.

[0009] The present disclosure provides a dynamic response optimization device of a primary side feedback converter, comprising: a synchronous rectification driver, a synchronous rectification tube and a regulation circuit, the drain of the synchronous rectification tube is connected to the drain voltage input end of the regulation circuit, the source of the synchronous rectification tube is connected to the source voltage input end of the regulation circuit, the drain voltage output end of the regulation circuit is connected to the drain voltage input end of the synchronous rectification driver, and the source voltage output end of the regulation circuit is connected to the source voltage input end of the synchronous rectification driver.

[0010] The drain voltage and source voltage of the synchronous rectification tube are sent to the regulation circuit, and the regulated drain voltage and source voltage are output after being processed by the regulation circuit.

[0011] The adjusted drain voltage and source voltage are input to the synchronous rectifier driver to trigger the synchronous rectifier driver to output the drive control signal of the synchronous rectifier tube.

[0012] In one embodiment, the adjustment circuit includes: a first capacitor C 11 First resistor R 11 Second resistor R 12 ;

[0013] The first capacitor C 11 The first terminal is connected to the drain voltage input terminal of the regulating circuit, and the first capacitor C 11 The first end is also connected to the second resistor R 12 The first terminal; the first capacitor C 11 The second end is connected to the second resistor R 12 The second terminal and the first resistor R 11 The first terminal; the first resistor R 11 The second terminal is connected to the source voltage input terminal and the source voltage output terminal of the regulating circuit, respectively, and the second resistor R 12 The second terminal is connected to the drain voltage output terminal of the regulating circuit.

[0014] In one embodiment, the regulating circuit includes: a second capacitor C 21 Third resistor R 21 Fourth resistor R 22 Switching transistor Q 21 diode D 21 ;

[0015] The second capacitor C 21 The first terminal is connected to the source voltage input terminal of the regulating circuit, and the diode D 21 The first terminal of the diode D is connected to ground. 21 The second end is connected to the second capacitor C 21 The second terminal; the third resistor R 21 The first end is connected to the second capacitor C 21 The second terminal, the third resistor R 21 The second end is connected to the switching transistor Q. 21 The first terminal, the switch Q 21 The second terminal is connected to the source voltage output terminal of the regulating circuit, and the switching transistor Q... 21 The third terminal is connected to the drive control signal input terminal of the adjustment circuit, and the switching transistor Q 21 The third input signal is the drive control signal for the synchronous rectifier diode; the fourth resistor R 22 The first terminal is connected to the source voltage input terminal of the regulating circuit, and the fourth resistor R22 a second end of the switch S P1 is connected to a first end of the inductor L m , and a second end of the inductor L m is connected to a first end of the switch S P3 , and a second end of the switch S P3 is connected to a first end of the capacitor C L , and a second end of the capacitor C L is connected to an output of the output voltage regulator OVR.

[0016] a drain voltage input of the regulating circuit is directly connected to a drain voltage output of the regulating circuit.

[0017] In another aspect, the present disclosure provides a primary side feedback converter comprising the dynamic response optimization apparatus, the converter further comprising: primary side switches S P1 , S P2 , S P3 , and S P4 , a power transformer T1, a clamping capacitor C L , an output filter capacitor C o , synchronous rectifiers S R1 , and a primary side drive signal generation unit; the power transformer T1 comprises an excitation inductor L m and a primary side equivalent leakage inductor L r .

[0018] a first end of the switch S P1 is connected to a positive voltage input, a first end of the switch S P2 is connected to a negative voltage input, a second end of the switch S P1 and a second end of the switch S P2 are connected to a first end of the primary side equivalent leakage inductor L r , a second end of the primary side equivalent leakage inductor L r is connected to a first end of the excitation inductor L m , a second end of the excitation inductor L m is connected to a first end of the switches S P3 and S P4 , a second end of the switch S P3 is connected to a first end of the clamping capacitor C L , a second end of the switch S P4 is connected to a second end of the clamping capacitor C L ; a first end of the clamping capacitor C L is connected to an output voltage regulator OVR, an output of the output voltage regulator OVR is connected to the primary side drive signal generation unit; the primary side drive signal generation unit generates drive control signals of the switches S P1 , S P2 , S P3 , and S P4 according to a control signal v err , an input voltage V in , a bridge leg midpoint voltage v A , and v B .

[0019] The output filter capacitor C o One end of the synchronous rectifier S R1 The drain is grounded, and the source of the synchronous rectifier S R1 The secondary side of the power transformer T1 is connected.

[0020] In another aspect of the present disclosure, a dynamic response optimization method for a primary side feedback converter is provided, comprising:

[0021] The drain voltage and the source voltage of the synchronous rectifier are input into the regulation circuit, and the regulated drain voltage and the regulated source voltage are output after being processed by the regulation circuit;

[0022] The regulated drain voltage and the regulated source voltage are input into the synchronous rectifier driver to trigger the synchronous rectifier driver to output the driving control signal of the synchronous rectifier.

[0023] In an implementation manner, the method comprises:

[0024] In the input energy storage stage t0-t1, the primary side switch S P1 and S P4 are turned on, the input voltage V in is applied to the primary side of the power transformer T1, and the drain-source voltage of the synchronous rectifier S R1 is

[0025]

[0026] and

[0027]

[0028] At time t1, S P1 and S P4 are turned off, the input energy storage stage ends, and then the primary side switch S P2 and S P3 and the synchronous rectifier S R1 are turned on, and the converter enters the energy transmission stage t1-t2. During this process, the voltage across the primary side of the power transformer T1 changes from V in to -V CL . Since the voltage across the capacitor C 11 does not change abruptly, v D1 -v S1 changes to

[0029]

[0030] Then, the capacitor C 11 is discharged through resistors R 11 and R 12 , and at time t 2c , the capacitor C11 discharge is completed, v D1 -v S1 changes to

[0031]

[0032] wherein, v DS_on is S R1 the drain-source voltage difference when turned on; that is, t 2c after the moment, the synchronous rectifier driver still determines its turn-off moment according to S R1 the drain-source voltage, at no load and light load, the excitation inductor current i 2c at the moment t Lm is negative, S R1 the drain-source voltage v DSR1 >0, higher than the turn-off threshold voltage V th_off of the synchronous rectifier driver, S R1 is immediately turned off, and the conduction time is approximately fixed as t 2c -t1; while above light load, the excitation inductor current i 2c at the moment t Lm is still positive, and the synchronous rectifier driver still controls S R1 to turn off when i Lm is zero.

[0033] In an implementable manner, the method comprises:

[0034] The input energy storage stage t0-t1, the primary side switch S P1 and S P4 are turned on, the input voltage V in is applied to the primary side of the power transformer T1, the synchronous rectifier S R1 is in the turn-off state, the switch Q 21 is turned off, the diode D 21 is turned on, and the capacitor C 21 has a voltage v SG -v S =V in / n, and there is

[0035]

[0036] At the moment t1, S P1 and S P4 are turned off, the input energy storage stage ends, and then the primary side switch S P2 and S P3 and the synchronous rectifier S R1 are turned on, the converter enters the energy transmission stage t1-t2, the switch Q 21 is turned on, the diode D 21 is turned off, and the capacitor C 21By resistance R 21 and R 22 discharge, and at the beginning of the discharge, v S1 = [R 21 / (R 21 +R 22 )]x(V in / n), at the moment t 2d , the capacitor C 11 discharges completely, and v S1 =v S , after which v D1 -v S1 =v DS_on , that is, after the moment t 2d , the synchronous rectifier driver still determines its turn-off moment according to the drain-source voltage of S R1 , at no load and light load, the magnetizing inductor current i 2d at the moment t Lm is negative, the drain-source voltage v R1 of S DSR1 >0, which is higher than the turn-off threshold voltage V th_off of the synchronous rectifier driver, S R1 is immediately turned off, and the conduction time is approximately fixed as t 2d -t1; while above light load, the magnetizing inductor current i 2d at the moment t Lm is still positive, and the synchronous rectifier driver still controls S R1 to turn off when i Lm is zero;

[0037] At the moment t2, S R1 and S P3 are turned off, the power transmission stage ends, after which the primary switch S P4 is turned on, and the converter enters the current clamping stage t2-t3, the switch Q 21 is turned off, the diode D 21 is turned on, the voltage across the capacitor C 21 is zero, and v D1 -v S1 =v D -v S , that is, after which the synchronous rectifier driver still determines its turn-on moment according to the drain-source voltage of S R1 , and does not change the working state of the converter, and S R1 will not be mistakenly turned on; at the moment t3, S P2 is turned off, the current clamping stage ends, after which the primary switch S P1 is turned on, and the converter enters the input energy storage stage again.

[0038] Technical effects of the embodiments of the present disclosure:

[0039] The dynamic dead load effect is realized, the dynamic response of the converter is significantly optimized, the primary and secondary disconnection is effectively inhibited, and the efficiency of the converter above light load is not reduced.

[0040] The circuit is simple to implement, does not need to increase a current sampling circuit, and does not affect the equivalent leakage inductance of the primary side of the power transformer, which is beneficial to improving the efficiency and output voltage control accuracy.

[0041] It should be understood that the content described in this part is not intended to identify key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0042] The above and other objects, features and advantages of the exemplary embodiments of the present disclosure will be more apparent from the following detailed description read in conjunction with the accompanying drawings, in which several embodiments of the present disclosure are shown by way of example, and in which:

[0043] In the drawings, identical or corresponding reference numerals indicate identical or corresponding parts.

[0044] Figure 1 A circuit structure schematic diagram of a primary side feedback control double-clamp zero-voltage converter in the related art is shown;

[0045] Figure 2a 、 2b A schematic diagram of a typical working waveform of a converter in the related art is shown;

[0046] Figure 3 A typical waveform schematic diagram of a primary and secondary disconnection phenomenon of a converter in the related art is shown;

[0047] Figure 4a An equivalent circuit schematic diagram of a converter after primary and secondary disconnection in the related art is shown;

[0048] Figure 4b An experimental waveform schematic diagram of a primary and secondary disconnection phenomenon of a converter in the related art is shown;

[0049] Figure 5 A circuit structure schematic diagram of a double-clamp zero-voltage converter for improving dynamic response by adding a current loop in the related art is shown;

[0050] Figure 6 A structure schematic diagram of a dynamic response optimization device of a primary side feedback converter according to an embodiment of the present disclosure is shown;

[0051] Figure 7 A typical working waveform schematic diagram of a double-clamp zero-voltage converter under method control according to an embodiment of the present disclosure at no load and light load is shown;

[0052] Figure 8a Fig. 1 shows a circuit structure schematic diagram of the implementation mode one of the adjusting circuit of the embodiment of the present disclosure;

[0053] Figure 8b Fig. 2 shows a circuit structure schematic diagram of the implementation mode two of the adjusting circuit of the embodiment of the present disclosure;

[0054] Figure 9 Fig. 3 shows a key point working waveform schematic diagram corresponding to the implementation mode one of the adjusting circuit of the embodiment of the present disclosure;

[0055] Figure 10a Fig. 4 shows an equivalent circuit structure schematic diagram of the implementation mode two of the adjusting circuit of the embodiment of the present disclosure in the synchronous rectifier tube off stage;

[0056] Figure 10b Fig. 5 shows an equivalent circuit structure schematic diagram of the implementation mode two of the adjusting circuit of the embodiment of the present disclosure in the synchronous rectifier tube on stage;

[0057] Figure 11 Fig. 6 shows a key point working waveform schematic diagram corresponding to the implementation mode two of the adjusting circuit of the embodiment of the present disclosure;

[0058] Figure 12a Fig. 7 shows an experimental waveform schematic diagram before the implementation of the embodiment of the present disclosure;

[0059] Figure 12b Fig. 8 shows an experimental waveform schematic diagram after the implementation of the embodiment of the present disclosure;

[0060] Figure 13 Fig. 9 shows an experimental efficiency comparison schematic diagram before and after the implementation of the embodiment of the present disclosure. DETAILED DESCRIPTION

[0061] In order to make the purpose, features and advantages of the present disclosure more obvious and easy to understand, the technical solutions in the embodiments of the present disclosure will be described clearly and completely below with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, but not all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present disclosure.

[0062] The dynamic response optimization method and device of the primary feedback converter of the embodiment of the present disclosure mainly include: adjusting the minimum on time T R1 of the synchronous rectifier tube S on_min , the circuit structure of the implementation is shown in Fig. Figure 6 , the drain and source voltage (v D and v S ) of the synchronous rectifier tube S R1 is sent to T on_minThe regulating circuit, after processing, outputs a voltage signal v. D1 and v S1 Then trigger the synchronous rectifier driver to output S R1 drive control signal v GSR1 And achieve the following functions: synchronous rectifier tube S under no-load and light-load conditions R1 The fixed conduction time is T on_min This causes the magnetizing inductor current i to reach its maximum at the end of the energy transfer phase. Lm Negative direction, that is, realizing the transfer of energy from the secondary side to the primary side, the typical working waveform is as follows: Figure 7 As shown, similar to the method of increasing dead load at the output, it can achieve rapid recovery after the output voltage overshoots when switching from full load to no load, effectively suppressing the disconnection of the primary and secondary sides; while at light loads and above, S R1 On time greater than T on_min At the end of the energy transfer phase, the magnetizing inductor current i Lm To zero, typical operating waveform and Figure 2a As shown, the proposed method does not change the operating state of the converter under light loads and does not introduce additional losses.

[0063] The dynamic response optimization method for the primary-side feedback converter disclosed in this embodiment achieves the effect of dynamic dead load, that is, under no-load and light-load conditions, the output filter capacitor C is consumed by transferring energy from the secondary side to the primary side. o The energy on the primary and secondary sides is effectively suppressed to prevent the primary and secondary sides from separating and to optimize the dynamic response; while under light load and above, the equivalent dead load is zero, which will not bring additional losses and reduce the converter efficiency.

[0064] Figure 8 shows the T embodiment of this disclosure. on_min Two specific implementation circuits for the adjustment circuit. For example... Figure 8a As shown, the circuit for implementing method one consists of capacitor C. 11 and resistance R 11 ~R 12 Its components, and its key working waveforms are as follows: Figure 9 As shown, the basic principle is described as follows: During the input energy storage stage (t0~t1), the primary-side switch S... P1 and S P4 On, input voltage V in The synchronous rectifier S is applied to the primary side of the power transformer T1. R1 The voltage across the drain and source terminals is:

[0065]

[0066] And there are

[0067]

[0068] time t1 S P1and S P4 off, input energy storage stage ends, then primary switch S P2 and S P3 and synchronous rectifier S R1 on, converter enters energy transfer stage (t1-t2), in this process, power transformer T1 primary side voltage changes from V in to -V CL , since capacitor C 11 voltage will not jump, v D1 -v S1 changes to:

[0069]

[0070] then capacitor C 11 discharges through resistor R 11 and R 12 , at t 2c moment, capacitor C 11 discharge is completed, v D1 -v S1 changes to:

[0071]

[0072] where, v DS_on is the drain-source voltage of S R1 on. That is, after t 2c moment, the synchronous rectifier driver still determines its off time according to the drain-source voltage of S R1 , at no load and light load, t 2c moment excitation inductor current i Lm is negative, S R1 drain-source voltage v DSR1 >0, higher than the off threshold voltage V th_off of the synchronous rectifier driver, S R1 immediately off, the on time is approximately fixed as t 2c -t1; while above light load, t 2c moment excitation inductor current i Lm is still positive, the synchronous rectifier driver still controls S R1 off when i Lm to zero, will not change the working state of the converter.

[0073] t2 moment S R1 and S P3 off, power transfer stage ends, then primary switch S P4 on, converter enters current clamping stage (t2-t3), in this process, power transformer T1 primary side voltage changes from -V CL to zero, since capacitor C11 The voltage across the terminals will not change abruptly, v D1 -v S1 Change to V o Then capacitor C 11 Through resistor R 11 and R 12 Charging, v D1 -v S1 Change [R] 11 / (R 11 +R 12 )]×V o And it is always higher than the turn-on threshold voltage V. th_on S R1 It won't be activated by mistake.

[0074] time t3 S P2 After the turn-off and current clamping phase ends, the primary-side switch S... P1 When the circuit is turned on, the converter enters the input energy storage stage. During this process, the voltage across the primary side of the power transformer T1 changes from zero to V. in Due to capacitor C 11 The voltage across the terminals will not change abruptly, v D1 -v S1 Change to [R] 11 / (R 11 +R 12 )]×V o +V in / n, then capacitor C 11 Through resistor R 11 and R 12 Charging, v D1 -v S1 Change [R] 11 / (R 11 +R 12 )]×(V o +V in / n), and always higher than the turn-on threshold voltage V th_on S R1 It won't be activated by mistake.

[0075] like Figure 8b As shown, the circuit implementing method two consists of a switching transistor Q. 21 Capacitor C 21 diode D 21 and resistance R 21 ~R 22 The composition and equivalent circuits of its different operating stages are shown in Figure 10, and the key operating waveforms are as follows. Figure 11 As shown. The basic principle is described as follows: During the input energy storage stage (t0~t1), the primary-side switch S... P1 and S P4 On, input voltage Vin The synchronous rectifier S is applied to the primary side of the power transformer T1. R1 When in the off state, the equivalent circuit of the proposed implementation method two circuit is as follows: Figure 10a As shown, the switching transistor Q 21 Turn-off, diode D 21 On, capacitor C 21 The voltage across the terminals is v SG -v S =V in / n, and we have:

[0076]

[0077] time t1 S P1 and S P4 The input energy storage phase ends upon shutdown, after which the primary-side switch S... P2 and S P3 and synchronous rectifier S R1 When the circuit is turned on, the converter enters the energy transfer phase (t1~t2). At this time, the equivalent circuit of the proposed implementation method two is as follows: Figure 10b As shown, the switching transistor Q 21 Conducting diode D 21 Cut-off, capacitor C 21 Through resistor R 21 and R 22 Discharge, and at the start of discharge v S1 =[R 21 / (R 21 +R 22 )]×(V in / n), in t 2d Capacitor C at time 11 Discharge complete, with v S1 =v S After that, v D1 -v S1 =v DS_on , i.e. t 2d After a certain time, the synchronous rectifier driver still operates according to S. R1 The drain-source voltage determines its turn-off time; under no-load and light-load conditions, t 2d The excitation inductor current i at time t Lm If negative, S R1 drain-source voltage v DSR1 >0, higher than the turn-off threshold voltage V of the synchronous rectifier driver. th_off S R1 Immediate shutdown, with the conduction time approximately fixed at t. 2d -t1; while for light loads and above, t 2d The excitation inductor current i at time t Lm It remains positive; the synchronous rectifier driver still controls S.R1 in i Lm Turning off at zero time will not change the converter's operating state.

[0078] time t2 S R1 and S P3 Turn-off, the power transfer phase ends, and then the primary-side switch S... P4 When the circuit is turned on, the converter enters the current clamping stage (t2~t3). At this time, the equivalent circuit of the circuit implementing mode two is as follows: Figure 10a As shown, the switching transistor Q 21 Turn-off, diode D 21 On, capacitor C 21 The voltage across the terminals is zero, and v D1 -v S1 =v D -v S That is, the synchronous rectifier driver will still be based on S R1 The voltage across the drain and source terminals determines the turn-on time and does not change the operating state of the converter. R1 It won't be accidentally activated. (t3 time S) P2 After the turn-off and current clamping phase ends, the primary-side switch S... P1 Once the circuit is turned on, the converter re-enters the input energy storage stage.

[0079] Figure 12a , 12b Experimental waveform comparisons are provided. As can be seen from the figures, before adopting the embodiments of this disclosure, the output voltage overshoot of the converter when switching from full load to no load reached approximately 2V, with an excessively long recovery time. Furthermore, it was prone to triggering protection due to the primary and secondary sides separating, causing the system to shut down and unable to provide stable power to the load. After adopting the embodiments of this disclosure, the output voltage overshoot when switching from full load to no load was reduced to approximately 0.8V, and the recovery time was significantly shortened. Simultaneously, the voltage change trend of the clamping capacitor remained consistent with that of the output voltage, effectively suppressing the separation of the primary and secondary sides of the converter. Figure 13 Experimental efficiency comparison curves are provided. The embodiments disclosed herein do not introduce additional losses or reduce converter efficiency under light loads or above.

[0080] The advantages of this disclosed embodiment are: (1) It achieves dynamic dead load effect, significantly optimizes the dynamic response of the converter, effectively suppresses the disconnection of the primary and secondary sides, and does not reduce the efficiency of the converter above light load; (2) The circuit implementation is simple, no need to add current sampling circuit, and does not affect the equivalent leakage inductance of the primary side of the power transformer, which is conducive to improving efficiency and output voltage control accuracy.

[0081] It should be understood that the various forms of flow shown above can be used to reorder, add, or remove steps. For example, the steps described in the present disclosure can be performed in parallel, in series, or in a different order, as long as the desired results of the technology disclosed in the present disclosure are achieved, which is not limited herein.

[0082] In addition, the terms "first", "second", "third", etc. are used only for descriptive purposes and should not be construed as indicating or implying relative importance or an indicated number of technical features. Therefore, the features defined with "first", "second", etc. can explicitly or implicitly include at least one of the features. In the description of the present disclosure, the meaning of "a plurality of" is two or more, unless otherwise specifically limited.

[0083] The above description is merely a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A device for optimizing dynamic response of a primary side feedback converter, characterized in that, The method comprises: a synchronous rectification driver, a synchronous rectification tube and a regulating circuit, a drain of the synchronous rectification tube is connected to a drain voltage input of the regulating circuit, a source of the synchronous rectification tube is connected to a source voltage input of the regulating circuit, a drain voltage output of the regulating circuit is connected to a drain voltage input of the synchronous rectification driver, and a source voltage output of the regulating circuit is connected to a source voltage input of the synchronous rectification driver; the drain voltage and the source voltage of the synchronous rectification tube are input into the regulating circuit, and the drain voltage and the source voltage are output after being processed by the regulating circuit; the regulated drain voltage and source voltage are input into the synchronous rectification driver, and are used to trigger the synchronous rectification driver to output a driving control signal of the synchronous rectification tube; The adjusting circuit comprises: a second capacitor C 21 , a third resistor R 21 , a fourth resistor R 22 , a switch tube Q 21 , and a diode D 21 . The second capacitor C 21 The first end of the second capacitor C 21 The first end of the second capacitor C 21 The second end of the second capacitor C 21 The first end of the third resistor R 21 The second end of the third resistor R 21 The second end of the third resistor R 21 The first end of the third resistor R 21 The second end of the third resistor R 21 The second end of the third resistor R 21 The third end of the third resistor R 21 The third end of the third resistor R 22 The first end of the fourth resistor R 22 The second end of the fourth resistor R a drain voltage input of the regulating circuit is directly connected to a drain voltage output of the regulating circuit.

2. A primary side feedback converter, characterized by, The dynamic response optimization device of claim 1, wherein the transformer further comprises a primary side switch S P1 、 P2 、 P3 、 P4 , a power transformer T1, a clamping capacitor C L , an output filter capacitor C o , a synchronous rectifier S R1 , and a primary side drive signal generation unit; the power transformer T1 comprises an excitation inductance L m and a primary side equivalent leakage inductance L r ; The first end of the switch tube S P1 is connected with a voltage input positive pole, the first end of the switch tube S P2 is connected with a voltage input negative pole, the second end of the switch tube S P1 and the switch tube S P2 is connected with the first end of the primary side equivalent leakage inductance L r , the second end of the primary side equivalent leakage inductance L r is connected with the first end of the excitation inductance L m , the second end of the excitation inductance L m is connected with the first end of the primary side switch tube S P3 and S P4 , the second end of the primary side switch tube S P3 is connected with the first end of the clamping capacitor C L , the second end of the primary side switch tube S P4 is connected with the second end of the clamping capacitor C L ; the first end of the clamping capacitor C L is connected with an output voltage regulator OVR, the output end of the output voltage regulator OVR is connected with the primary side drive signal generation unit; the primary side drive signal generation unit generates drive control signals of the primary side switch tube S err , S in , S A and S B according to a control signal v P1 , an input voltage V P2 , a bridge arm midpoint voltage v P3 and v P4 . One end of the output filter capacitor C o is connected to the drain of the synchronous rectifier S R1 , and the other end is grounded; the source of the synchronous rectifier S R1 is connected to the secondary side of the power transformer T1.

3. The method for optimizing dynamic response of the primary side feedback converter according to claim 2, wherein, The method comprises: a synchronous rectification tube, a synchronous rectification driver and a regulating circuit, a drain voltage and a source voltage of the synchronous rectification tube are input into the regulating circuit, and the drain voltage and the source voltage are output after being processed by the regulating circuit; the regulated drain voltage and source voltage are input into the synchronous rectification driver, and are used to trigger the synchronous rectification driver to output a driving control signal of the synchronous rectification tube.

4. The method of claim 3, wherein, The method comprises: The input energy storage stage t0~t1, the original side switch tube S P1 and S P4 Conduct, input voltage V in Applied to the power transformer T1 original side, synchronous rectifier S R1 In the off state, switch tube Q 21 Off, diode D 21 Conduct, capacitor C 21 The voltage across both ends is v SG -v S =V in / n, and there are t1 time S P1 and S P4 off, input energy storage stage ends, then the primary side switch S P2 and S P3 and synchronous rectifier S R1 on, converter enters energy transmission stage t1-t2, switch Q 21 on, diode D 21 off, capacitor C 21 discharges through resistor R 21 and R 22 discharges, and at the beginning of discharge v S1 =[R 21 / (R 21 +R 22 )]×(V in / n), at t 2d time capacitor C 11 discharge is complete, v S1 =v S , then v D1 -v S1 =v DS_on , that is, after t 2d time, the synchronous rectifier driver still determines its turn-off time according to S R1 drain-source voltage, at no load and light load, t 2d time excitation inductor current i Lm is negative, S R1 drain-source voltage v DSR1 >0, higher than the synchronous rectifier driver turn-off threshold voltage V th_off , S R1 immediately off, the conduction time is approximately fixed as t 2d -t1; while above light load, t 2d time excitation inductor current i Lm is still positive, the synchronous rectifier driver still controls S R1 off when i Lm is zero; S is off at t2 R1 and S P3 is off, the power transfer stage ends, and then S P4 is on, the converter enters the current clamp stage t2~t3, Q 21 is off, diode D 21 is on, capacitor C 21 has zero voltage across, and has v D1 -v S1 = v D -v S , then the synchronous rectifier driver still determines its turn-on time according to S R1 voltage across drain and source, and does not change the working state of the converter, S R1 will not be turned on by mistake; S P2 is off at t3, the current clamp stage ends, and then S P1 is on, and the converter enters the input energy storage stage again.

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