Dual-path clock generation circuit and method, electronic device

Abstract

The present disclosure relates to a dual-path clock generation circuit and method, and an electronic device, and belongs to the technical field of integrated circuits. The dual-path clock generation circuit comprises: a first inverting module configured to input a first signal and output a first clock output signal; a second inverting module configured to input a second signal and output a second clock output signal, the first signal and the second signal being opposite clock signals; a first feed-forward buffer disposed between an input end of the first inverting module and an output end of the second inverting module, configured to transmit the first signal to compensate for the second clock output signal; and a second feed-forward buffer disposed between an input end of the second inverting module and an output end of the first inverting module, configured to transmit the second signal to delay the first clock output signal. The present disclosure provides a method for calibrating phase mismatch.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular, to a dual-path clock generation circuit and method, and an electronic device. BACKGROUND

[0002] With the continuous improvement of the sampling rate index, the number of analog-to-digital converters (ADCs) in the system is also increasing.

[0003] For a time-interleaved sampling system composed of two ADCs, theoretically, the sampling clock phases of the two ADCs need to be accurately different by 180 degrees.

[0004] However, due to the influence of clock generation circuit delay or temperature process deviation, as the input signal frequency increases, the sampling clock of the two ADCs will produce phase mismatch, it is difficult to achieve a phase difference of 180 degrees, which has a great impact on the system performance.

[0005] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0006] The purpose of the present disclosure is to provide a dual-path clock generation circuit, a dual-path clock generation method, and an electronic device to provide a method for calibrating phase mismatch.

[0007] Other characteristics and advantages of the present disclosure will become apparent from the following detailed description, or will be learned by practice of the present disclosure.

[0008] According to a first aspect of the present disclosure, a dual-path clock generation circuit is provided, comprising:

[0009] a first inverting module configured to access a first signal and output a first clock output signal;

[0010] a second inverting module configured to access a second signal and output a second clock output signal, the first signal and the second signal being opposite clock signals;

[0011] a first feed-forward buffer disposed between an input end of the first inverting module and an output end of the second inverting module, configured to transmit the first signal to compensate for the second clock output signal;

[0012] a second feed-forward buffer disposed between an input end of the second inverting module and an output end of the first inverting module, configured to transmit the second signal to delay the first clock output signal.

[0013] In an example embodiment of the present disclosure, the method further comprises:

[0014] a first switch disposed on a line of the first feed-forward buffer, for controlling on-off of the first feed-forward buffer;

[0015] a second switch disposed on a line of the second feed-forward buffer, for controlling on-off of the second feed-forward buffer.

[0016] In an example embodiment of the present disclosure, the first switch and the second switch are connected to a frequency control signal, for being turned on or turned off under control of the frequency control signal.

[0017] In an example embodiment of the present disclosure, when the frequency control signal is high frequency, the first switch and the second switch are turned on.

[0018] In an example embodiment of the present disclosure, the first switch and the second switch are CMOS analog switches.

[0019] In an example embodiment of the present disclosure, the first feed-forward buffer and the second feed-forward buffer are CMOS tubes composed of NMOS transistors and PMOS transistors.

[0020] In an example embodiment of the present disclosure, the first feed-forward buffer and the second feed-forward buffer are NMOS tubes composed of two NMOS transistors.

[0021] In an example embodiment of the present disclosure, the first feed-forward buffer and the second feed-forward buffer are PMOS tubes composed of two PMOS transistors.

[0022] In an example embodiment of the present disclosure, the first inverting module comprises a first inverter, and the second inverting module comprises a second inverter.

[0023] In an example embodiment of the present disclosure, the first inverter and the second inverter are CMOS tubes composed of NMOS transistors and PMOS transistors.

[0024] According to a second aspect of the present disclosure, a dual-path clock generation method is provided, which is applied to a dual-path clock generation circuit comprising a first inverting module for connecting a first signal, a second inverting module for connecting a second signal, a first feed-forward buffer and a second feed-forward buffer; the method comprises:

[0025] The first feedforward buffer is arranged between the input end of the first inverting module and the output end of the second inverting module, and is used for transmitting the first signal to compensate a second clock output signal output by the second inverting module.

[0026] The second feedforward buffer is arranged between the input end of the second inverting module and the output end of the first inverting module, and is used for transmitting the second signal to delay a first clock output signal output by the first inverting module.

[0027] In an example embodiment of the present disclosure, the method further comprises:

[0028] A first switch is arranged on the line of the first feedforward buffer, and is used for controlling the on-off of the first feedforward buffer.

[0029] A second switch is arranged on the line of the second feedforward buffer, and is used for controlling the on-off of the second feedforward buffer.

[0030] In an example embodiment of the present disclosure, the method further comprises:

[0031] A frequency control signal is connected to the first switch and the second switch respectively, and is used for controlling the first switch and the second switch to be turned on or turned off under the control of the frequency control signal.

[0032] In an example embodiment of the present disclosure, the method further comprises:

[0033] When the frequency control signal is a high frequency, the first switch and the second switch are controlled to be turned on.

[0034] In an example embodiment of the present disclosure, the method further comprises:

[0035] The first feedforward buffer and the second feedforward buffer are arranged as the same or different MOS tubes, and are used for phase calibration of the rising edge of the first signal and / or the falling edge of the first signal.

[0036] According to a third aspect of the present disclosure, an electronic device is provided, comprising the above-mentioned double-path clock generation circuit.

[0037] The technical solution provided by the present disclosure can have the following beneficial effects:

[0038] The double-path clock generating circuit provided by the exemplary embodiments of the present disclosure can advance the second clock output signal by setting a first feed-forward buffer between the input end of the first inverting module and the output end of the second inverting module, and transmitting the first signal to the output end of the second inverting module through the first feed-forward buffer to compensate the second clock output signal output by the second inverting module with the first signal. In addition, the double-path clock generating circuit can delay the first clock output signal output by the first inverting module by setting a second feed-forward buffer between the input end of the second inverting module and the output end of the first inverting module, and transmitting the second signal to the output end of the first inverting module through the second feed-forward buffer to delay the first clock output signal output by the first inverting module with the second signal. By delaying the end of the first clock output signal and advancing the start of the second clock output signal, the phase difference between the two output signals can be reduced, and the phase mismatch between the generated double-path clock signals can be reduced.

[0039] It should be understood that the general description above and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0040] The accompanying drawings, which are incorporated into and form part of the specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the disclosure. It is clear that the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained from these drawings without creative labor for those skilled in the art. In the drawings:

[0041] Figure 1 The structure of a double-path clock generating circuit for calibrating phase mismatch is schematically shown according to an exemplary embodiment of the present disclosure;

[0042] Figure 2 The structure of a double-path clock generating circuit for calibrating phase mismatch is schematically shown according to another exemplary embodiment of the present disclosure; Figure 1 The signal waveform of the double-path clock generating circuit shown is schematically shown;

[0043] Figure 3 The structure of a double-path clock generating circuit for calibrating phase mismatch is schematically shown according to another exemplary embodiment of the present disclosure;

[0044] Figure 4 The structure of a double-path clock generating circuit for calibrating phase mismatch is schematically shown according to another exemplary embodiment of the present disclosure; Figure 3 The signal waveform of the double-path clock generating circuit shown is schematically shown;

[0045] Figure 5 The structure of a double-path clock generating circuit for calibrating phase mismatch is schematically shown according to another exemplary embodiment of the present disclosure;

[0046] Figure 6 schematically illustrates Figure 5 schematically illustrates a signal waveform of the double-path clock generation circuit shown;

[0047] Figure 7 schematically illustrates a structure of another double-path clock generation circuit for calibrating phase mismatch in an exemplary embodiment according to the present disclosure;

[0048] Figure 8 schematically illustrates a structure of another double-path clock generation circuit for calibrating phase mismatch in an exemplary embodiment according to the present disclosure;

[0049] Figure 9 schematically illustrates a structure of another double-path clock generation circuit for calibrating phase mismatch in an exemplary embodiment according to the present disclosure;

[0050] Figure 10 schematically illustrates a flowchart of a double-path clock generation method in an exemplary embodiment according to the present disclosure. DETAILED DESCRIPTION

[0051] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings; however, these embodiments should not be construed as limiting all example embodiments. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the specification.

[0052] Moreover, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materials, and so forth. In other instances, well-known structures, materials, or operations are not shown or described in detail in order to avoid obscuring aspects of the disclosure.

[0053] The block diagrams in the drawings show only the functionality of the embodiments and do not imply that the functions must be implemented in a particular manner. For example, the functions of one or more of the illustrated components can be implemented in hardware, software, or a combination of both hardware and software. Further, the functions of the components can be combined or divided into other components not illustrated. The components of the embodiments can be implemented in software and / or firmware in addition to or instead of being implemented in hardware. The functions of the components can be combined or divided into other components not illustrated.

[0054] When multiple analog-to-digital converters (ADCs) are integrated on the same chip, due to the mismatch of device parameters between different chip regions, various mismatches of the synchronized clock between the multiple ADCs occur. The mismatches include a mismatch of a skew, a mismatch of a gain, and a phase mismatch of a sampling clock.

[0055] The dynamic performance of a sampling system using multiple ADCs is often limited by the above-mentioned various mismatches. The mismatch of the skew and the mismatch of the gain can generally be improved by using an external reference, etc. However, for the phase mismatch, a phase adjustment needs to be performed on the sampling clock. The adjustment accuracy is often affected by the time difference of the initial clock signal, which causes the effect of the phase mismatch improvement to gradually weaken as the frequency increases, and the problem of the phase mismatch to become more serious.

[0056] Reference Figure 1 provides a two-path clock generation circuit for calibrating a phase mismatch. For the two-path clock generation circuit, two signals, for example, CKT and CKB in Figure 1 , are generally needed to be input during signal transmission. Theoretically, the phase difference of the two clocks is 180 degrees. However, due to the above-mentioned various reasons, the two signals CKT and CKB actually input to the two-path clock generation circuit in Figure 1 have a time difference α, as shown in Figure 2 .

[0057] After the two signals CKT and CKB pass through the two-path clock generation circuit shown in Figure 1 , two output signals CKB_D and CKT_D shown in Figure 1 and Figure 2 are obtained. As can be calculated from the signal waveform diagram shown in Figure 2 , the two output signals CKB_D and CKT_D have a time difference Δ=(α+β) / 4, where β is the time needed for the rising of CKT or the time needed for the falling of CKB. That is, after the CKT and CKB signals with the phase mismatch α pass through the two-path clock generation circuit shown in Figure 1 , the two output signals CKB_D and CKT_D have a phase mismatch of (α+β) / 4.

[0058] As can be seen from the above results, the phase mismatch of (α+β) / 4 is still related to the phase mismatch α of the input signal. Therefore, when the sampling frequency is increased, Figure 1 the effect of the two-path clock generation circuit provided for calibrating and improving the phase mismatch gradually weakens, and the problem of the phase mismatch becomes more serious.

[0059] Therefore, after further research, reference is made to Figure 3The inventor of the present application proposes another dual-clock generation circuit for calibrating phase mismatch, and the output time difference of the calibrated dual-clock generation circuit is no longer related to the time difference a of the initial clock signal, thus weakening the influence of frequency on phase mismatch and providing a basis for further improvement of phase mismatch.

[0060] It should be noted that the above-mentioned dual-clock generation circuit can be used not only in ADC but also in any circuit that transmits dual-clock, for example, the transmission of dual-clock signals between a DRAM (Dynamic Random Access Memory) control unit and a DRAM.

[0061] As shown in FIG. 1, Figure 3 The dual-clock generation circuit includes a first inverting module 310, a second inverting module 330, a first feed-forward buffer 350, and a second feed-forward buffer 370, wherein

[0062] The first inverting module 310 is configured to input a first signal and output a first clock output signal, and the second inverting module 330 is configured to input a second signal opposite to the first signal and output a second clock output signal. To form a contrast, Figure 1 Figure 3 In the example shown in FIG. 1, the first signal is denoted as clock signal CKT, the second signal is denoted as clock signal CKB, the first clock output signal is denoted as CKB_D, and the second clock output signal is denoted as CKT_D. In theory, the first signal and the second signal have a phase difference of 180 degrees.

[0063] In the example shown in FIG. 1, the first feed-forward buffer 350 is arranged between the input end of the first inverting module 310 and the output end of the second inverting module 330, and is configured to transmit the first signal CKT to compensate the second clock output signal CKT_D; and the second feed-forward buffer 370 is arranged between the input end of the second inverting module 330 and the output end of the first inverting module 310, and is configured to transmit the second signal CKB to delay the first clock output signal CKB_D.

[0064] Taking the rising edge of the first signal CKT as an example, the dual-clock generation circuit provided by the example of the present disclosure can transmit the first signal CKT to the output end of the second inverting module 330 through the first feed-forward buffer 350 arranged between the input end of the first inverting module 310 and the output end of the second inverting module 330, so as to compensate the second clock output signal CKT_D using the first signal CKT, thereby Figure 4 ​The rising edge of the second clock output signal CKT_D is advanced. In addition, by setting the second feed-forward buffer 370 between the input end of the second inverting module 330 and the output end of the first inverting module 310, the second signal CKB can be transmitted to the output end of the first inverting module 310 through the second feed-forward buffer 370 to delay the arrival of the falling edge end of the first clock output signal CKB_D through the second signal CKB. By advancing the rising edge of the second clock output signal CKT_D and delaying the falling edge end of the first clock output signal CKB_D, the phase difference between the two first clock output signals CKB_D and CKT_D can be reduced, thereby reducing the phase mismatch between the generated double clock signals.

[0065] In the case of the time difference a of the initial clock signals CKT and CKB, the time length of the CKT rising delay is b, from Figure 4 The waveform diagram shown can be calculated. The first signal and the second signal pass through the exemplary embodiment of the present disclosure Figure 3 After the double clock generation circuit provided, the time difference a between the output edges of the two signals CKB_D and CKT_D becomes b / 4.

[0066] From the above results, it can be seen that the phase mismatch of b / 4 is no longer related to the phase mismatch a of the input signal, and is naturally not affected by the initial mismatch phase. In addition, by Figure 3 The phase mismatch correction improvement of the double clock generation circuit provided is naturally not affected by the frequency, and the improvement effect can be further improved by improving the rising or falling time b of the initial clock signal, thereby providing the possibility of eliminating the phase mismatch.

[0067] In the exemplary embodiment of the present disclosure, the first feed-forward buffer 350 and the second feed-forward buffer 370 can be composed of MOS tubes (Metal-Oxide-Semiconductor Field-Effect Transistor, Metal-Oxide-Semiconductor Field-Effect Transistor), and according to whether the rising edge or the falling edge of the input signal is required to be processed, the types of MOS tubes composing the first feed-forward buffer 350 and the second feed-forward buffer 370 are different.

[0068] Specifically, for Figure 3 The first feed-forward buffer 350 and the second feed-forward buffer 370 shown can improve both the rising edge of the input signal and the falling edge of the input signal, Figure 3 and Figure 4 The circuit diagram and the waveform diagram shown are for improving the rising edge of the input signal CKT, i.e., the first signal.

[0069] In Figure 3In the present embodiment, the first feed-forward buffer 350 and the second feed-forward buffer 370 are CMOS tubes (Complementary Metal Oxide Semiconductor) composed of NMOS tubes and PMOS tubes, i.e. MOS tubes composed of N-type MOS tubes and P-type MOS tubes. In the process of improving the rising edge of the input first signal CKT, from Figure 4 As can be seen, due to the existence of the initial phase mismatch a, the second signal CKB is always 1 during the entire rising process of the first signal CKT, and even after the first signal CKT is 1, the second signal CKB still has a period of time remaining at 1. However, before the first signal CKT rises over 1 / 2, the NMOS tube 312 of the first inverting module 310 is closed, and thus, although the second signal CKB is 1, the second signal CKB cannot control the first clock output signal CKB_D in advance through the NMOS tube 372 of the second feed-forward buffer 370, and the falling edge starting point of the first clock output signal CKB_D starts when the first signal CKT rises over 1 / 2 to open the NMOS tube 312. Secondly, after the NMOS tube 312 is opened and forms a loop with the NMOS tube 372, the falling edge ending point of the first clock output signal CKB_D does not come until the second signal CKB changes from 1 to 1 / 2.

[0070] From Figure 4 As can be seen, during the falling process of the second signal CKB, the first signal CKT always remains at 1, and then the first signal CKT opens the NMOS tube 352 of the first feed-forward buffer 350. The conducting NMOS tube 352 forms a loop with the NMOS tube 332 of the second inverting module 330, and the voltage VDD output from the NMOS tube 352 affects the process of gradually changing the signal CKT_D output from the second inverting module 330 from 0 to 1. Since VDD is usually 1, due to the existence of the initial phase mismatch a, the first signal CKT compensates for the process of gradually changing the second clock output signal CKT_D from 0 to 1 through the NMOS tube 352 of the first feed-forward buffer 350, thereby advancing the arrival of the rising edge starting point of the second clock output signal CKT_D.

[0071] Through the above-mentioned delay of the arrival of the falling edge ending point of the first clock output signal CKB_D and the advance of the arrival of the rising edge starting point of the second clock output signal CKT_D, the time difference between the first clock output signal CKB_D and the second clock output signal CKT_D is compensated, so that the calibrated phase mismatch is only related to the rising time β of the first signal CKT, and is no longer affected by the initial signal phase difference and the frequency.

[0072] Figure 5 And Figure 6The circuit diagram and waveform diagram for improving the falling edge of the input signal CKT, i.e. the first signal, are shown.

[0073] In Figure 5 the first feed-forward buffer 350 and the second feed-forward buffer 370 are also CMOS tubes composed of NMOS tubes and PMOS tubes, i.e. MOS tubes composed of N-type MOS tubes and P-type MOS tubes. In the process of improving the falling edge of the input first signal CKT, from Figure 5 It can be seen that due to the existence of the initial phase mismatch α, the second signal CKB is always 0 during the entire falling process of the first signal CKT, and even after the first signal CKT is 0, the second signal CKB still has a period of time remaining at 0. However, before the first signal CKT falls more than 1 / 2, the PMOS tube 311 of the first inverting module 310 is closed, so although the second signal CKB is 0, the second signal CKB cannot control the first clock output signal CKB_D in advance through the PMOS tube 371 of the second feed-forward buffer 370, and the rising edge of the first clock output signal CKB_D starts when the PMOS tube 311 is opened when the first signal CKT falls more than 1 / 2. Secondly, after the PMOS tube 311 is opened and forms a loop with the PMOS tube 371, the end of the rising edge of the first clock output signal CKB_D does not come until the second signal CKB changes from 0 to 1 / 2.

[0074] At the same time, the process of the first signal CKT falling is also the process of the second signal CKB rising. From Figure 6 It can be seen that during the process of the second signal CKB rising, the first signal CKT remains 0, and then the first signal CKT will open the PMOS tube 351 of the first feed-forward buffer 350. The conducting PMOS tube 351 will form a loop with the PMOS tube 331 of the second inverting module 330, and the signal 0 output from the PMOS tube 351 will affect the process of the second clock output signal CKT_D gradually changing from 1 to 0. Due to the existence of the initial phase mismatch α, the first signal CKT will compensate for the process of the second clock output signal CKT_D gradually changing from 1 to 0 through the PMOS tube 351 of the first feed-forward buffer 350, thereby advancing the arrival of the falling edge of the second clock output signal CKT_D.

[0075] Through the above-mentioned delay of the end of the rising edge of the first clock output signal CKB_D and the advance of the start of the falling edge of the second clock output signal CKT_D, the time difference between the first clock output signal CKB_D and CKT_D is compensated, so that the calibrated phase mismatch is only related to the falling time β of the first signal CKT, and is no longer affected by the initial signal phase difference and the frequency.

[0076] FromFigure 3 and Figure 5 As can be seen, the first feed-forward buffer 350 and the second feed-forward buffer 370 in both figures are composed of CMOS tubes, that is, the first feed-forward buffer 350 and the second feed-forward buffer 370 composed of CMOS tubes can not only improve the rising edge of the first signal CKT, but also improve the falling edge of the first signal CKT.

[0077] In addition, Figure 7 and Figure 8 Another two combination modes of the first feed-forward buffer 350 and the second feed-forward buffer 370 are shown: Figure 7 In the first feed-forward buffer 350 and the second feed-forward buffer 370 in the first combination mode, the first feed-forward buffer 350 and the second feed-forward buffer 370 are both NMOS tubes composed of two NMOS transistors; Figure 8 In the first feed-forward buffer 350 and the second feed-forward buffer 370 in the second combination mode, the first feed-forward buffer 350 and the second feed-forward buffer 370 are both PMOS tubes composed of two PMOS transistors.

[0078] From the above analysis of the working principle of Figure 3 and Figure 5 As can be seen from the analysis of the working principle of Figure 7 the first feed-forward buffer 350 and the second feed-forward buffer 370 in the first combination mode are mainly used to improve the rising edge of the first signal; Figure 8 the first feed-forward buffer 350 and the second feed-forward buffer 370 in the second combination mode are mainly used to improve the falling edge of the first signal. Figure 7 The working principle of the double-path clock generation circuit shown in Figure 3 can be analyzed with reference to the working principle of Figure 8 The working principle of the double-path clock generation circuit shown in Figure 5 can be analyzed with reference to the working principle of Figure 7 and Figure 8 The working principle of the double-path clock generation circuit shown in

[0079] In the exemplary embodiments of the present disclosure, the first inverting module 310 can include a first inverter, and the second inverting module 330 can include a second inverter. In Figure 3 , Figure 5 , Figure 7 and Figure 8 , the first inverter and the second inverter are both CMOS tubes composed of NMOS transistors and PMOS transistors. In actual applications, the first inverter and the second inverter can also be other types of inverters, and the exemplary embodiments of the present disclosure do not specially limit this.

[0080] Further, with reference to Figures 7-9As shown, the double-path clock generating circuit provided by the exemplary embodiment of the present disclosure further comprises a first switch 360 and a second switch 380, wherein the first switch 360 is arranged on the line of the first feed-forward buffer 350 for controlling the on-off of the first feed-forward buffer 350; the second switch 380 is arranged on the line of the second feed-forward buffer 370 for controlling the on-off of the second feed-forward buffer 370. Therefore, the on-off of the first feed-forward buffer 350 and the second feed-forward buffer 370 can be flexibly controlled as required, for example, the first feed-forward buffer 350 and the second feed-forward buffer 370 can be controlled to be turned on at the same time, or only the first feed-forward buffer 350 can be controlled to be turned on, or only the second feed-forward buffer 370 can be controlled to be turned on, or the first feed-forward buffer 350 and the second feed-forward buffer 370 can be both turned off as required, which is not specially limited in the exemplary embodiment of the present disclosure.

[0081] In the exemplary embodiment of the present disclosure, the first switch 360 and the second switch 380 arranged can be respectively connected to a frequency control signal, so as to control the first feed-forward buffer 350 and the second feed-forward buffer 370 to be turned on when the sampling frequency of the input signal is high, thereby the phase mismatch calibration of the input clock signal can be performed only in the case of high frequency, and the clock signal can be turned off in the case of low frequency, so as to save the current. Moreover, since the phase mismatch is usually more serious in the case of high frequency, the first feed-forward buffer 350 and the second feed-forward buffer 370 are turned on only in the case of high frequency, which has little influence on the accuracy of the phase mismatch calibration.

[0082] For example, the first frequency control signal can be connected to the first switch 360 for controlling the first feed-forward buffer 350 to be turned on when the sampling frequency of the first signal is high. The second frequency control signal can be connected to the second switch 380 for controlling the second feed-forward buffer 370 to be turned on when the sampling frequency of the second signal is high. Since the first signal and the second signal are two opposite signals with a phase difference of 180 degrees, the sampling frequencies of the first signal and the second signal are the same. Therefore, the same frequency control signal can be connected to the first switch 360 and the second switch 380, for example, the same first frequency control signal or the same second frequency control signal.

[0083] In actual application, the frequency control signal is a signal outputted for turning on the first switch 360 and the second switch 380 when the sampling frequency of the collected first signal or second signal is greater than a preset sampling rate. For example, when the first switch 360 and the second switch 380 are both CMOS analog switches, the first frequency control signal and the second frequency control signal are signals outputted for outputting high level 1 when the sampling frequency is greater than the preset sampling rate, so as to turn on the first switch 360 and the second switch 380.

[0084] In actual applications, the preset sampling rate can be set according to actual conditions, for example, the preset sampling rate can be 2666 MHz, 3200 MHz, etc., and the preset sampling rate is not specially limited in the example embodiments of the present disclosure.

[0085] It should be noted that, in actual applications, the first switch 360 and the second switch 380 can not only be opened when the frequency control signal is high frequency, but also can be set to other control opening modes according to actual needs. For example, the first switch 360 or the second switch 380 is opened when the frequency control signal is low frequency, or without the frequency control signal, it is always in the opened state. Any other opening mode is available, and the example embodiments of the present disclosure do not specially limit this.

[0086] It should be noted that the dual-path clock generation circuit provided by the example embodiments of the present disclosure is not only suitable for clock signals, but also suitable for phase mismatch calibration of any two opposite signals with a 180-degree phase difference.

[0087] The example embodiments of the present disclosure also provide a dual-path clock generation method applied to the dual-path clock generation circuit described above, which includes a first inverting module for accessing a first signal, a second inverting module for accessing a second signal, a first feed-forward buffer, and a second feed-forward buffer. Referring to Figure 10 , the dual-path clock generation method can specifically include the following steps:

[0088] Step S102, the first feed-forward buffer is arranged between the input end of the first inverting module and the output end of the second inverting module, and is used for transmitting the first signal to compensate the second clock output signal output by the second inverting module;

[0089] Step S104, the second feed-forward buffer is arranged between the input end of the second inverting module and the output end of the first inverting module, and is used for transmitting the second signal to delay the first clock output signal output by the first inverting module.

[0090] In some embodiments of the present disclosure, the method further includes: arranging a first switch on the line of the first feed-forward buffer for controlling the on-off of the first feed-forward buffer; and arranging a second switch on the line of the second feed-forward buffer for controlling the on-off of the second feed-forward buffer.

[0091] In some embodiments of the present disclosure, the method further includes: connecting a frequency control signal to the first switch and the second switch respectively, for controlling the first switch and the second switch to open or close under the control of the frequency control signal.

[0092] In some embodiments of the present disclosure, the method further comprises: controlling the first switch and the second switch to be open when the frequency control signal is high frequency.

[0093] In some embodiments of the present disclosure, the method further comprises: setting the first feedforward buffer and the second feedforward buffer to be composed of two same or different MOS transistors to perform phase calibration on the rising edge of the first signal and / or the falling edge of the first signal.

[0094] It should be noted that the two different MOS transistors mentioned above refer to the case of CMOS transistors composed of PMOS transistors and NMOS transistors as shown in FIG. 2B. Figure 3 and Figure 5 The two same MOS transistors mentioned above refer to the case of NMOS transistors as shown in FIG. 2A, or the case of PMOS transistors as shown in FIG. 2C. Figure 7 Figure 8

[0095] The double-path clock generation method provided by the exemplary embodiments of the present disclosure can transmit the first signal to the output end of the second inverting module through the first feedforward buffer by setting the first feedforward buffer between the input end of the first inverting module and the output end of the second inverting module, so as to compensate the second clock output signal output by the second inverting module using the first signal, thereby advancing the second clock output signal. In addition, the second signal can be transmitted to the output end of the first inverting module through the second feedforward buffer by setting the second feedforward buffer between the input end of the second inverting module and the output end of the first inverting module, so as to delay the first clock output signal output by the first inverting module through the second signal, thereby postponing the end point of the first clock output signal. By postponing the end point of the first clock output signal and advancing the start point of the second clock output signal, the phase difference between the two output signals can be reduced, thereby reducing the phase mismatch between the generated double-path clock signals.

[0096] The specific details of each step in the double-path clock generation method have been described in detail in the corresponding double-path clock generation circuit, and thus will not be described here again.

[0097] The exemplary embodiments of the present disclosure also provide an electronic device, which can include the double-path clock generation circuit described above. The specific structure and working principle of the double-path clock generation circuit have been described in detail in the foregoing embodiments, and thus will not be described here again.

[0098] ​​In the embodiments described above, all or part of the embodiments can be implemented by software, hardware, firmware or any combination thereof. When implemented by software, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded on a computer, all or part of the processes or functions described in the embodiments of the present disclosure are generated. The computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer readable storage medium or transferred from one computer readable storage medium to another computer readable storage medium. The computer readable storage medium can be any available medium accessible by a computer or data storage device such as a server, data center, etc. containing one or more media integrated with the medium. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid state disk (SSD)), etc. In the embodiments of the present disclosure, the computer can include the devices described above.

[0099] Although the present disclosure is described herein in conjunction with various embodiments, it is understood that other variations of the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed disclosure, from an inspection of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and the indefinite articles "a" or "an" do not exclude a plurality. A single processor or other unit can fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

[0100] Although the present disclosure is described herein in conjunction with specific features and embodiments thereof, it is understood that various modifications and combinations can be made thereto without departing from the spirit and scope of the disclosure. Accordingly, the description and drawings are to be regarded as illustrative in nature and are not to be taken as limiting the scope of the disclosure. It will be readily apparent to those skilled in the art that varying substitutions and modifications can be made to the disclosure without departing from the scope and spirit of the disclosure. Accordingly, it is intended that all such alterations and modifications be considered as within the scope of the disclosure.

Claims

1. A dual-channel clock generation circuit, characterized in that, include: The first inverting module is used to receive the first signal and output the first clock output signal; The second inverting module is used to receive the second signal and output the second clock output signal, wherein the first signal and the second signal are clock signals that are opposite to each other; A first feedforward buffer is disposed between the input terminal of the first inverting module and the output terminal of the second inverting module for transmitting the first signal to compensate the second clock output signal. The second feedforward buffer is disposed between the input terminal of the second inverting module and the output terminal of the first inverting module, and is used to transmit the second signal to delay the first clock output signal; The first switch is installed on the line of the first feedforward buffer and is used to control the on / off state of the first feedforward buffer. as well as The second switch is installed on the line of the second feedforward buffer and is used to control the on / off state of the second feedforward buffer. The first switch and the second switch are respectively connected to a frequency control signal, and are used to turn on or off under the control of the frequency control signal.

2. The circuit according to claim 1, characterized in that, When the frequency control signal is high frequency, the first switch and the second switch are turned on.

3. The circuit according to any one of claims 1-2, characterized in that, Both the first switch and the second switch are CMOS analog switches.

4. The circuit according to any one of claims 1-2, characterized in that, Both the first feedforward buffer and the second feedforward buffer are CMOS transistors composed of NMOS transistors and PMOS transistors.

5. The circuit according to any one of claims 1-2, characterized in that, Both the first feedforward buffer and the second feedforward buffer are NMOS transistors composed of two NMOS transistors.

6. The circuit according to any one of claims 1-2, characterized in that, Both the first feedforward buffer and the second feedforward buffer are PMOS transistors composed of two PMOS transistors.

7. The circuit according to any one of claims 1-2, characterized in that, The first inverting module includes a first inverter, and the second inverting module includes a second inverter.

8. The circuit according to claim 7, characterized in that, Both the first inverter and the second inverter are CMOS transistors composed of NMOS transistors and PMOS transistors.

9. A method for generating a dual-channel clock, characterized in that, The method is applied to a dual-channel clock generation circuit, which includes: a first inverting module for receiving a first signal, a second inverting module for receiving a second signal, a first feedforward buffer, and a second feedforward buffer. A first switch is set on the line of the first feedforward buffer to control the on / off state of the first feedforward buffer. A second switch is installed on the line of the second feedforward buffer to control the on / off state of the second feedforward buffer; The method includes: The first feedforward buffer is placed between the input terminal of the first inverting module and the output terminal of the second inverting module to transmit the first signal in order to compensate the second clock output signal output by the second inverting module. The second feedforward buffer is placed between the input terminal of the second inverting module and the output terminal of the first inverting module to transmit the second signal, thereby delaying the first clock output signal output by the first inverting module. Frequency control signals are respectively connected to the first switch and the second switch to control the first switch and the second switch to open or close under the control of the frequency control signals.

10. The method according to claim 9, characterized in that, The method further includes: When the frequency control signal is high frequency, the first switch and the second switch are controlled to turn on.

11. The method according to any one of claims 9-10, characterized in that, The method further includes: The first feedforward buffer and the first feedforward buffer are set to the same or different MOS transistors to perform phase calibration on the rising edge and / or falling edge of the first signal.

12. An electronic device, characterized in that, Includes a dual-channel clock generation circuit as described in any one of claims 1-8.

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